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pc: acpi: create Processor and Notify objects only for valid lapics
[qemu/ar7.git] / hw / i386 / acpi-build.c
blobe94f9fb99dea837a1ca3708014af3779dab4c01f
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "acpi-build.h"
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/acpi/bios-linker-loader.h"
38 #include "hw/loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45 #include "hw/timer/mc146818rtc_regs.h"
46
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/timer/hpet.h"
55
56 #include "hw/acpi/aml-build.h"
57
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
60
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
68
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
70
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75 #else
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
77 #endif
78
79 typedef struct AcpiCpuInfo {
80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
81 } AcpiCpuInfo;
82
83 typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86 } AcpiMcfgInfo;
87
88 typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
91 bool pcihp_bridge_en;
92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
99 uint16_t cpu_hp_io_base;
100 uint16_t cpu_hp_io_len;
101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static
125 int acpi_add_cpu_info(Object *o, void *opaque)
126 {
127 AcpiCpuInfo *cpu = opaque;
128 uint64_t apic_id;
129
130 if (object_dynamic_cast(o, TYPE_CPU)) {
131 apic_id = object_property_get_int(o, "apic-id", NULL);
132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
133
134 set_bit(apic_id, cpu->found_cpus);
135 }
136
137 object_child_foreach(o, acpi_add_cpu_info, opaque);
138 return 0;
139 }
140
141 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
142 {
143 Object *root = object_get_root();
144
145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
146 object_child_foreach(root, acpi_add_cpu_info, cpu);
147 }
148
149 static void acpi_get_pm_info(AcpiPmInfo *pm)
150 {
151 Object *piix = piix4_pm_find();
152 Object *lpc = ich9_lpc_find();
153 Object *obj = NULL;
154 QObject *o;
155
156 pm->cpu_hp_io_base = 0;
157 pm->pcihp_io_base = 0;
158 pm->pcihp_io_len = 0;
159 if (piix) {
160 obj = piix;
161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
162 pm->pcihp_io_base =
163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
164 pm->pcihp_io_len =
165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
166 }
167 if (lpc) {
168 obj = lpc;
169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
170 }
171 assert(obj);
172
173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
176
177 /* Fill in optional s3/s4 related properties */
178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
179 if (o) {
180 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
181 } else {
182 pm->s3_disabled = false;
183 }
184 qobject_decref(o);
185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
186 if (o) {
187 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
188 } else {
189 pm->s4_disabled = false;
190 }
191 qobject_decref(o);
192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
193 if (o) {
194 pm->s4_val = qint_get_int(qobject_to_qint(o));
195 } else {
196 pm->s4_val = false;
197 }
198 qobject_decref(o);
199
200 /* Fill in mandatory properties */
201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
202
203 pm->acpi_enable_cmd = object_property_get_int(obj,
204 ACPI_PM_PROP_ACPI_ENABLE_CMD,
205 NULL);
206 pm->acpi_disable_cmd = object_property_get_int(obj,
207 ACPI_PM_PROP_ACPI_DISABLE_CMD,
208 NULL);
209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
210 NULL);
211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
212 NULL);
213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
214 NULL);
215 pm->pcihp_bridge_en =
216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
217 NULL);
218 }
219
220 static void acpi_get_misc_info(AcpiMiscInfo *info)
221 {
222 Object *piix = piix4_pm_find();
223 Object *lpc = ich9_lpc_find();
224 assert(!!piix != !!lpc);
225
226 if (piix) {
227 info->is_piix4 = true;
228 }
229 if (lpc) {
230 info->is_piix4 = false;
231 }
232
233 info->has_hpet = hpet_find();
234 info->tpm_version = tpm_get_version();
235 info->pvpanic_port = pvpanic_port();
236 info->applesmc_io_base = applesmc_port();
237 }
238
239 /*
240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
241 * On i386 arch we only have two pci hosts, so we can look only for them.
242 */
243 static Object *acpi_get_i386_pci_host(void)
244 {
245 PCIHostState *host;
246
247 host = OBJECT_CHECK(PCIHostState,
248 object_resolve_path("/machine/i440fx", NULL),
249 TYPE_PCI_HOST_BRIDGE);
250 if (!host) {
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/q35", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 }
255
256 return OBJECT(host);
257 }
258
259 static void acpi_get_pci_info(PcPciInfo *info)
260 {
261 Object *pci_host;
262
263
264 pci_host = acpi_get_i386_pci_host();
265 g_assert(pci_host);
266
267 info->w32.begin = object_property_get_int(pci_host,
268 PCI_HOST_PROP_PCI_HOLE_START,
269 NULL);
270 info->w32.end = object_property_get_int(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_END,
272 NULL);
273 info->w64.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE64_START,
275 NULL);
276 info->w64.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_END,
278 NULL);
279 }
280
281 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
282
283 static void acpi_align_size(GArray *blob, unsigned align)
284 {
285 /* Align size to multiple of given size. This reduces the chance
286 * we need to change size in the future (breaking cross version migration).
287 */
288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
289 }
290
291 /* FACS */
292 static void
293 build_facs(GArray *table_data, GArray *linker)
294 {
295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
296 memcpy(&facs->signature, "FACS", 4);
297 facs->length = cpu_to_le32(sizeof(*facs));
298 }
299
300 /* Load chipset information in FADT */
301 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
302 {
303 fadt->model = 1;
304 fadt->reserved1 = 0;
305 fadt->sci_int = cpu_to_le16(pm->sci_int);
306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
307 fadt->acpi_enable = pm->acpi_enable_cmd;
308 fadt->acpi_disable = pm->acpi_disable_cmd;
309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
314 /* EVT, CNT, TMR length matches hw/acpi/core.c */
315 fadt->pm1_evt_len = 4;
316 fadt->pm1_cnt_len = 2;
317 fadt->pm_tmr_len = 4;
318 fadt->gpe0_blk_len = pm->gpe0_blk_len;
319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
322 (1 << ACPI_FADT_F_PROC_C1) |
323 (1 << ACPI_FADT_F_SLP_BUTTON) |
324 (1 << ACPI_FADT_F_RTC_S4));
325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
327 * For more than 8 CPUs, "Clustered Logical" mode has to be used
328 */
329 if (max_cpus > 8) {
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
331 }
332 fadt->century = RTC_CENTURY;
333 }
334
335
336 /* FADT */
337 static void
338 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
339 unsigned facs, unsigned dsdt,
340 const char *oem_id, const char *oem_table_id)
341 {
342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
343
344 fadt->firmware_ctrl = cpu_to_le32(facs);
345 /* FACS address to be filled by Guest linker */
346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
347 ACPI_BUILD_TABLE_FILE,
348 table_data, &fadt->firmware_ctrl,
349 sizeof fadt->firmware_ctrl);
350
351 fadt->dsdt = cpu_to_le32(dsdt);
352 /* DSDT address to be filled by Guest linker */
353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
354 ACPI_BUILD_TABLE_FILE,
355 table_data, &fadt->dsdt,
356 sizeof fadt->dsdt);
357
358 fadt_setup(fadt, pm);
359
360 build_header(linker, table_data,
361 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
362 }
363
364 static void
365 build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms)
366 {
367 MachineClass *mc = MACHINE_GET_CLASS(pcms);
368 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
369 int madt_start = table_data->len;
370
371 AcpiMultipleApicTable *madt;
372 AcpiMadtIoApic *io_apic;
373 AcpiMadtIntsrcovr *intsrcovr;
374 AcpiMadtLocalNmi *local_nmi;
375 int i;
376
377 madt = acpi_data_push(table_data, sizeof *madt);
378 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
379 madt->flags = cpu_to_le32(1);
380
381 for (i = 0; i < apic_ids->len; i++) {
382 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
383 int apic_id = apic_ids->cpus[i].arch_id;
384
385 apic->type = ACPI_APIC_PROCESSOR;
386 apic->length = sizeof(*apic);
387 apic->processor_id = apic_id;
388 apic->local_apic_id = apic_id;
389 if (apic_ids->cpus[i].cpu != NULL) {
390 apic->flags = cpu_to_le32(1);
391 } else {
392 apic->flags = cpu_to_le32(0);
393 }
394 }
395 g_free(apic_ids);
396
397 io_apic = acpi_data_push(table_data, sizeof *io_apic);
398 io_apic->type = ACPI_APIC_IO;
399 io_apic->length = sizeof(*io_apic);
400 #define ACPI_BUILD_IOAPIC_ID 0x0
401 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
402 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
403 io_apic->interrupt = cpu_to_le32(0);
404
405 if (pcms->apic_xrupt_override) {
406 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
407 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
408 intsrcovr->length = sizeof(*intsrcovr);
409 intsrcovr->source = 0;
410 intsrcovr->gsi = cpu_to_le32(2);
411 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
412 }
413 for (i = 1; i < 16; i++) {
414 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
415 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
416 /* No need for a INT source override structure. */
417 continue;
418 }
419 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
420 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
421 intsrcovr->length = sizeof(*intsrcovr);
422 intsrcovr->source = i;
423 intsrcovr->gsi = cpu_to_le32(i);
424 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
425 }
426
427 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
428 local_nmi->type = ACPI_APIC_LOCAL_NMI;
429 local_nmi->length = sizeof(*local_nmi);
430 local_nmi->processor_id = 0xff; /* all processors */
431 local_nmi->flags = cpu_to_le16(0);
432 local_nmi->lint = 1; /* ACPI_LINT1 */
433
434 build_header(linker, table_data,
435 (void *)(table_data->data + madt_start), "APIC",
436 table_data->len - madt_start, 1, NULL, NULL);
437 }
438
439 /* Assign BSEL property to all buses. In the future, this can be changed
440 * to only assign to buses that support hotplug.
441 */
442 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
443 {
444 unsigned *bsel_alloc = opaque;
445 unsigned *bus_bsel;
446
447 if (qbus_is_hotpluggable(BUS(bus))) {
448 bus_bsel = g_malloc(sizeof *bus_bsel);
449
450 *bus_bsel = (*bsel_alloc)++;
451 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
452 bus_bsel, NULL);
453 }
454
455 return bsel_alloc;
456 }
457
458 static void acpi_set_pci_info(void)
459 {
460 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
461 unsigned bsel_alloc = 0;
462
463 if (bus) {
464 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
465 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
466 }
467 }
468
469 static void build_append_pcihp_notify_entry(Aml *method, int slot)
470 {
471 Aml *if_ctx;
472 int32_t devfn = PCI_DEVFN(slot, 0);
473
474 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
475 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
476 aml_append(method, if_ctx);
477 }
478
479 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
480 bool pcihp_bridge_en)
481 {
482 Aml *dev, *notify_method, *method;
483 QObject *bsel;
484 PCIBus *sec;
485 int i;
486
487 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
488 if (bsel) {
489 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
490
491 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
492 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
493 }
494
495 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
496 DeviceClass *dc;
497 PCIDeviceClass *pc;
498 PCIDevice *pdev = bus->devices[i];
499 int slot = PCI_SLOT(i);
500 bool hotplug_enabled_dev;
501 bool bridge_in_acpi;
502
503 if (!pdev) {
504 if (bsel) { /* add hotplug slots for non present devices */
505 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
506 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
507 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
508 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
509 aml_append(method,
510 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
511 );
512 aml_append(dev, method);
513 aml_append(parent_scope, dev);
514
515 build_append_pcihp_notify_entry(notify_method, slot);
516 }
517 continue;
518 }
519
520 pc = PCI_DEVICE_GET_CLASS(pdev);
521 dc = DEVICE_GET_CLASS(pdev);
522
523 /* When hotplug for bridges is enabled, bridges are
524 * described in ACPI separately (see build_pci_bus_end).
525 * In this case they aren't themselves hot-pluggable.
526 * Hotplugged bridges *are* hot-pluggable.
527 */
528 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
529 !DEVICE(pdev)->hotplugged;
530
531 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
532
533 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
534 continue;
535 }
536
537 /* start to compose PCI slot descriptor */
538 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
539 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
540
541 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
542 /* add VGA specific AML methods */
543 int s3d;
544
545 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
546 s3d = 3;
547 } else {
548 s3d = 0;
549 }
550
551 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
552 aml_append(method, aml_return(aml_int(0)));
553 aml_append(dev, method);
554
555 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
556 aml_append(method, aml_return(aml_int(0)));
557 aml_append(dev, method);
558
559 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
560 aml_append(method, aml_return(aml_int(s3d)));
561 aml_append(dev, method);
562 } else if (hotplug_enabled_dev) {
563 /* add _SUN/_EJ0 to make slot hotpluggable */
564 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
565
566 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
567 aml_append(method,
568 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
569 );
570 aml_append(dev, method);
571
572 if (bsel) {
573 build_append_pcihp_notify_entry(notify_method, slot);
574 }
575 } else if (bridge_in_acpi) {
576 /*
577 * device is coldplugged bridge,
578 * add child device descriptions into its scope
579 */
580 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
581
582 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
583 }
584 /* slot descriptor has been composed, add it into parent context */
585 aml_append(parent_scope, dev);
586 }
587
588 if (bsel) {
589 aml_append(parent_scope, notify_method);
590 }
591
592 /* Append PCNT method to notify about events on local and child buses.
593 * Add unconditionally for root since DSDT expects it.
594 */
595 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
596
597 /* If bus supports hotplug select it and notify about local events */
598 if (bsel) {
599 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
600 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
601 aml_append(method,
602 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
603 );
604 aml_append(method,
605 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
606 );
607 }
608
609 /* Notify about child bus events in any case */
610 if (pcihp_bridge_en) {
611 QLIST_FOREACH(sec, &bus->child, sibling) {
612 int32_t devfn = sec->parent_dev->devfn;
613
614 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
615 }
616 }
617 aml_append(parent_scope, method);
618 qobject_decref(bsel);
619 }
620
621 /**
622 * build_prt_entry:
623 * @link_name: link name for PCI route entry
624 *
625 * build AML package containing a PCI route entry for @link_name
626 */
627 static Aml *build_prt_entry(const char *link_name)
628 {
629 Aml *a_zero = aml_int(0);
630 Aml *pkg = aml_package(4);
631 aml_append(pkg, a_zero);
632 aml_append(pkg, a_zero);
633 aml_append(pkg, aml_name("%s", link_name));
634 aml_append(pkg, a_zero);
635 return pkg;
636 }
637
638 /*
639 * initialize_route - Initialize the interrupt routing rule
640 * through a specific LINK:
641 * if (lnk_idx == idx)
642 * route using link 'link_name'
643 */
644 static Aml *initialize_route(Aml *route, const char *link_name,
645 Aml *lnk_idx, int idx)
646 {
647 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
648 Aml *pkg = build_prt_entry(link_name);
649
650 aml_append(if_ctx, aml_store(pkg, route));
651
652 return if_ctx;
653 }
654
655 /*
656 * build_prt - Define interrupt rounting rules
657 *
658 * Returns an array of 128 routes, one for each device,
659 * based on device location.
660 * The main goal is to equaly distribute the interrupts
661 * over the 4 existing ACPI links (works only for i440fx).
662 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
663 *
664 */
665 static Aml *build_prt(bool is_pci0_prt)
666 {
667 Aml *method, *while_ctx, *pin, *res;
668
669 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
670 res = aml_local(0);
671 pin = aml_local(1);
672 aml_append(method, aml_store(aml_package(128), res));
673 aml_append(method, aml_store(aml_int(0), pin));
674
675 /* while (pin < 128) */
676 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
677 {
678 Aml *slot = aml_local(2);
679 Aml *lnk_idx = aml_local(3);
680 Aml *route = aml_local(4);
681
682 /* slot = pin >> 2 */
683 aml_append(while_ctx,
684 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
685 /* lnk_idx = (slot + pin) & 3 */
686 aml_append(while_ctx,
687 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
688 lnk_idx));
689
690 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
691 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
692 if (is_pci0_prt) {
693 Aml *if_device_1, *if_pin_4, *else_pin_4;
694
695 /* device 1 is the power-management device, needs SCI */
696 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
697 {
698 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
699 {
700 aml_append(if_pin_4,
701 aml_store(build_prt_entry("LNKS"), route));
702 }
703 aml_append(if_device_1, if_pin_4);
704 else_pin_4 = aml_else();
705 {
706 aml_append(else_pin_4,
707 aml_store(build_prt_entry("LNKA"), route));
708 }
709 aml_append(if_device_1, else_pin_4);
710 }
711 aml_append(while_ctx, if_device_1);
712 } else {
713 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
714 }
715 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
716 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
717
718 /* route[0] = 0x[slot]FFFF */
719 aml_append(while_ctx,
720 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
721 NULL),
722 aml_index(route, aml_int(0))));
723 /* route[1] = pin & 3 */
724 aml_append(while_ctx,
725 aml_store(aml_and(pin, aml_int(3), NULL),
726 aml_index(route, aml_int(1))));
727 /* res[pin] = route */
728 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
729 /* pin++ */
730 aml_append(while_ctx, aml_increment(pin));
731 }
732 aml_append(method, while_ctx);
733 /* return res*/
734 aml_append(method, aml_return(res));
735
736 return method;
737 }
738
739 typedef struct CrsRangeEntry {
740 uint64_t base;
741 uint64_t limit;
742 } CrsRangeEntry;
743
744 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
745 {
746 CrsRangeEntry *entry;
747
748 entry = g_malloc(sizeof(*entry));
749 entry->base = base;
750 entry->limit = limit;
751
752 g_ptr_array_add(ranges, entry);
753 }
754
755 static void crs_range_free(gpointer data)
756 {
757 CrsRangeEntry *entry = (CrsRangeEntry *)data;
758 g_free(entry);
759 }
760
761 static gint crs_range_compare(gconstpointer a, gconstpointer b)
762 {
763 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
764 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
765
766 return (int64_t)entry_a->base - (int64_t)entry_b->base;
767 }
768
769 /*
770 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
771 * interval, computes the 'free' ranges from the same interval.
772 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
773 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
774 */
775 static void crs_replace_with_free_ranges(GPtrArray *ranges,
776 uint64_t start, uint64_t end)
777 {
778 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
779 uint64_t free_base = start;
780 int i;
781
782 g_ptr_array_sort(ranges, crs_range_compare);
783 for (i = 0; i < ranges->len; i++) {
784 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
785
786 if (free_base < used->base) {
787 crs_range_insert(free_ranges, free_base, used->base - 1);
788 }
789
790 free_base = used->limit + 1;
791 }
792
793 if (free_base < end) {
794 crs_range_insert(free_ranges, free_base, end);
795 }
796
797 g_ptr_array_set_size(ranges, 0);
798 for (i = 0; i < free_ranges->len; i++) {
799 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
800 }
801
802 g_ptr_array_free(free_ranges, false);
803 }
804
805 /*
806 * crs_range_merge - merges adjacent ranges in the given array.
807 * Array elements are deleted and replaced with the merged ranges.
808 */
809 static void crs_range_merge(GPtrArray *range)
810 {
811 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
812 CrsRangeEntry *entry;
813 uint64_t range_base, range_limit;
814 int i;
815
816 if (!range->len) {
817 return;
818 }
819
820 g_ptr_array_sort(range, crs_range_compare);
821
822 entry = g_ptr_array_index(range, 0);
823 range_base = entry->base;
824 range_limit = entry->limit;
825 for (i = 1; i < range->len; i++) {
826 entry = g_ptr_array_index(range, i);
827 if (entry->base - 1 == range_limit) {
828 range_limit = entry->limit;
829 } else {
830 crs_range_insert(tmp, range_base, range_limit);
831 range_base = entry->base;
832 range_limit = entry->limit;
833 }
834 }
835 crs_range_insert(tmp, range_base, range_limit);
836
837 g_ptr_array_set_size(range, 0);
838 for (i = 0; i < tmp->len; i++) {
839 entry = g_ptr_array_index(tmp, i);
840 crs_range_insert(range, entry->base, entry->limit);
841 }
842 g_ptr_array_free(tmp, true);
843 }
844
845 static Aml *build_crs(PCIHostState *host,
846 GPtrArray *io_ranges, GPtrArray *mem_ranges)
847 {
848 Aml *crs = aml_resource_template();
849 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
850 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
851 CrsRangeEntry *entry;
852 uint8_t max_bus = pci_bus_num(host->bus);
853 uint8_t type;
854 int devfn;
855 int i;
856
857 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
858 uint64_t range_base, range_limit;
859 PCIDevice *dev = host->bus->devices[devfn];
860
861 if (!dev) {
862 continue;
863 }
864
865 for (i = 0; i < PCI_NUM_REGIONS; i++) {
866 PCIIORegion *r = &dev->io_regions[i];
867
868 range_base = r->addr;
869 range_limit = r->addr + r->size - 1;
870
871 /*
872 * Work-around for old bioses
873 * that do not support multiple root buses
874 */
875 if (!range_base || range_base > range_limit) {
876 continue;
877 }
878
879 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
880 crs_range_insert(host_io_ranges, range_base, range_limit);
881 } else { /* "memory" */
882 crs_range_insert(host_mem_ranges, range_base, range_limit);
883 }
884 }
885
886 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
887 if (type == PCI_HEADER_TYPE_BRIDGE) {
888 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
889 if (subordinate > max_bus) {
890 max_bus = subordinate;
891 }
892
893 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
894 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
895
896 /*
897 * Work-around for old bioses
898 * that do not support multiple root buses
899 */
900 if (range_base && range_base <= range_limit) {
901 crs_range_insert(host_io_ranges, range_base, range_limit);
902 }
903
904 range_base =
905 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
906 range_limit =
907 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
908
909 /*
910 * Work-around for old bioses
911 * that do not support multiple root buses
912 */
913 if (range_base && range_base <= range_limit) {
914 crs_range_insert(host_mem_ranges, range_base, range_limit);
915 }
916
917 range_base =
918 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
919 range_limit =
920 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
921
922 /*
923 * Work-around for old bioses
924 * that do not support multiple root buses
925 */
926 if (range_base && range_base <= range_limit) {
927 crs_range_insert(host_mem_ranges, range_base, range_limit);
928 }
929 }
930 }
931
932 crs_range_merge(host_io_ranges);
933 for (i = 0; i < host_io_ranges->len; i++) {
934 entry = g_ptr_array_index(host_io_ranges, i);
935 aml_append(crs,
936 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
937 AML_POS_DECODE, AML_ENTIRE_RANGE,
938 0, entry->base, entry->limit, 0,
939 entry->limit - entry->base + 1));
940 crs_range_insert(io_ranges, entry->base, entry->limit);
941 }
942 g_ptr_array_free(host_io_ranges, true);
943
944 crs_range_merge(host_mem_ranges);
945 for (i = 0; i < host_mem_ranges->len; i++) {
946 entry = g_ptr_array_index(host_mem_ranges, i);
947 aml_append(crs,
948 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
949 AML_MAX_FIXED, AML_NON_CACHEABLE,
950 AML_READ_WRITE,
951 0, entry->base, entry->limit, 0,
952 entry->limit - entry->base + 1));
953 crs_range_insert(mem_ranges, entry->base, entry->limit);
954 }
955 g_ptr_array_free(host_mem_ranges, true);
956
957 aml_append(crs,
958 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
959 0,
960 pci_bus_num(host->bus),
961 max_bus,
962 0,
963 max_bus - pci_bus_num(host->bus) + 1));
964
965 return crs;
966 }
967
968 static void build_processor_devices(Aml *sb_scope, MachineState *machine,
969 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
970 {
971 int i;
972 Aml *dev;
973 Aml *crs;
974 Aml *pkg;
975 Aml *field;
976 Aml *ifctx;
977 Aml *method;
978 MachineClass *mc = MACHINE_GET_CLASS(machine);
979 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
980 PCMachineState *pcms = PC_MACHINE(machine);
981
982 /* The current AML generator can cover the APIC ID range [0..255],
983 * inclusive, for VCPU hotplug. */
984 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
985 g_assert(pcms->apic_id_limit <= ACPI_CPU_HOTPLUG_ID_LIMIT);
986
987 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
988 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
989 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
990 aml_append(dev,
991 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
992 );
993 /* device present, functioning, decoding, not shown in UI */
994 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
995 crs = aml_resource_template();
996 aml_append(crs,
997 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
998 pm->cpu_hp_io_len)
999 );
1000 aml_append(dev, aml_name_decl("_CRS", crs));
1001 aml_append(sb_scope, dev);
1002 /* declare CPU hotplug MMIO region and PRS field to access it */
1003 aml_append(sb_scope, aml_operation_region(
1004 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
1005 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1006 aml_append(field, aml_named_field("PRS", 256));
1007 aml_append(sb_scope, field);
1008
1009 /* build Processor object for each processor */
1010 for (i = 0; i < apic_ids->len; i++) {
1011 int apic_id = apic_ids->cpus[i].arch_id;
1012
1013 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
1014 dev = aml_processor(apic_id, 0, 0, "CP%.02X", apic_id);
1015
1016 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1017 aml_append(method,
1018 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(apic_id))));
1019 aml_append(dev, method);
1020
1021 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1022 aml_append(method,
1023 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(apic_id))));
1024 aml_append(dev, method);
1025
1026 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1027 aml_append(method,
1028 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(apic_id),
1029 aml_arg(0)))
1030 );
1031 aml_append(dev, method);
1032
1033 aml_append(sb_scope, dev);
1034 }
1035
1036 /* build this code:
1037 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1038 */
1039 /* Arg0 = Processor ID = APIC ID */
1040 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1041 for (i = 0; i < apic_ids->len; i++) {
1042 int apic_id = apic_ids->cpus[i].arch_id;
1043
1044 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(apic_id)));
1045 aml_append(ifctx,
1046 aml_notify(aml_name("CP%.02X", apic_id), aml_arg(1))
1047 );
1048 aml_append(method, ifctx);
1049 }
1050 aml_append(sb_scope, method);
1051
1052 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1053 *
1054 * Note: The ability to create variable-sized packages was first
1055 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1056 * ith up to 255 elements. Windows guests up to win2k8 fail when
1057 * VarPackageOp is used.
1058 */
1059 pkg = pcms->apic_id_limit <= 255 ? aml_package(pcms->apic_id_limit) :
1060 aml_varpackage(pcms->apic_id_limit);
1061
1062 for (i = 0; i < pcms->apic_id_limit; i++) {
1063 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1064 aml_append(pkg, aml_int(b));
1065 }
1066 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1067 g_free(apic_ids);
1068 }
1069
1070 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1071 uint16_t io_base, uint16_t io_len)
1072 {
1073 int i;
1074 Aml *scope;
1075 Aml *crs;
1076 Aml *field;
1077 Aml *dev;
1078 Aml *method;
1079 Aml *ifctx;
1080
1081 /* build memory devices */
1082 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1083 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1084 aml_append(scope,
1085 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1086 );
1087
1088 crs = aml_resource_template();
1089 aml_append(crs,
1090 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1091 );
1092 aml_append(scope, aml_name_decl("_CRS", crs));
1093
1094 aml_append(scope, aml_operation_region(
1095 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1096 aml_int(io_base), io_len)
1097 );
1098
1099 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1100 AML_NOLOCK, AML_PRESERVE);
1101 aml_append(field, /* read only */
1102 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1103 aml_append(field, /* read only */
1104 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1105 aml_append(field, /* read only */
1106 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1107 aml_append(field, /* read only */
1108 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1109 aml_append(field, /* read only */
1110 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1111 aml_append(scope, field);
1112
1113 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1114 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1115 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1116 aml_append(field, /* 1 if enabled, read only */
1117 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1118 aml_append(field,
1119 /*(read) 1 if has a insert event. (write) 1 to clear event */
1120 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1121 aml_append(field,
1122 /* (read) 1 if has a remove event. (write) 1 to clear event */
1123 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1124 aml_append(field,
1125 /* initiates device eject, write only */
1126 aml_named_field(MEMORY_SLOT_EJECT, 1));
1127 aml_append(scope, field);
1128
1129 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1130 AML_NOLOCK, AML_PRESERVE);
1131 aml_append(field, /* DIMM selector, write only */
1132 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1133 aml_append(field, /* _OST event code, write only */
1134 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1135 aml_append(field, /* _OST status code, write only */
1136 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1137 aml_append(scope, field);
1138 aml_append(sb_scope, scope);
1139
1140 for (i = 0; i < nr_mem; i++) {
1141 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1142 const char *s;
1143
1144 dev = aml_device("MP%02X", i);
1145 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1146 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1147
1148 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1149 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1150 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1151 aml_append(dev, method);
1152
1153 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1154 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1155 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1156 aml_append(dev, method);
1157
1158 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1159 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1160 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1161 aml_append(dev, method);
1162
1163 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1164 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1165
1166 aml_append(method, aml_return(aml_call4(
1167 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1168 )));
1169 aml_append(dev, method);
1170
1171 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1172 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1173 aml_append(method, aml_return(aml_call2(
1174 s, aml_name("_UID"), aml_arg(0))));
1175 aml_append(dev, method);
1176
1177 aml_append(sb_scope, dev);
1178 }
1179
1180 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1181 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1182 */
1183 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1184 for (i = 0; i < nr_mem; i++) {
1185 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1186 aml_append(ifctx,
1187 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1188 );
1189 aml_append(method, ifctx);
1190 }
1191 aml_append(sb_scope, method);
1192 }
1193
1194 static void build_hpet_aml(Aml *table)
1195 {
1196 Aml *crs;
1197 Aml *field;
1198 Aml *method;
1199 Aml *if_ctx;
1200 Aml *scope = aml_scope("_SB");
1201 Aml *dev = aml_device("HPET");
1202 Aml *zero = aml_int(0);
1203 Aml *id = aml_local(0);
1204 Aml *period = aml_local(1);
1205
1206 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1207 aml_append(dev, aml_name_decl("_UID", zero));
1208
1209 aml_append(dev,
1210 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1211 HPET_LEN));
1212 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1213 aml_append(field, aml_named_field("VEND", 32));
1214 aml_append(field, aml_named_field("PRD", 32));
1215 aml_append(dev, field);
1216
1217 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1218 aml_append(method, aml_store(aml_name("VEND"), id));
1219 aml_append(method, aml_store(aml_name("PRD"), period));
1220 aml_append(method, aml_shiftright(id, aml_int(16), id));
1221 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1222 aml_equal(id, aml_int(0xffff))));
1223 {
1224 aml_append(if_ctx, aml_return(zero));
1225 }
1226 aml_append(method, if_ctx);
1227
1228 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1229 aml_lgreater(period, aml_int(100000000))));
1230 {
1231 aml_append(if_ctx, aml_return(zero));
1232 }
1233 aml_append(method, if_ctx);
1234
1235 aml_append(method, aml_return(aml_int(0x0F)));
1236 aml_append(dev, method);
1237
1238 crs = aml_resource_template();
1239 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1240 aml_append(dev, aml_name_decl("_CRS", crs));
1241
1242 aml_append(scope, dev);
1243 aml_append(table, scope);
1244 }
1245
1246 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1247 {
1248 Aml *dev, *fdi;
1249 uint8_t maxc, maxh, maxs;
1250
1251 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1252
1253 dev = aml_device("FLP%c", 'A' + idx);
1254
1255 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1256
1257 fdi = aml_package(16);
1258 aml_append(fdi, aml_int(idx)); /* Drive Number */
1259 aml_append(fdi,
1260 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1261 /*
1262 * the values below are the limits of the drive, and are thus independent
1263 * of the inserted media
1264 */
1265 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1266 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1267 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1268 /*
1269 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1270 * the drive type, so shall we
1271 */
1272 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1273 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1274 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1275 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1276 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1277 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1278 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1279 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1280 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1281 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1282 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1283
1284 aml_append(dev, aml_name_decl("_FDI", fdi));
1285 return dev;
1286 }
1287
1288 static Aml *build_fdc_device_aml(ISADevice *fdc)
1289 {
1290 int i;
1291 Aml *dev;
1292 Aml *crs;
1293
1294 #define ACPI_FDE_MAX_FD 4
1295 uint32_t fde_buf[5] = {
1296 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1297 cpu_to_le32(2) /* tape presence (2 == never present) */
1298 };
1299
1300 dev = aml_device("FDC0");
1301 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1302
1303 crs = aml_resource_template();
1304 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1305 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1306 aml_append(crs, aml_irq_no_flags(6));
1307 aml_append(crs,
1308 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1309 aml_append(dev, aml_name_decl("_CRS", crs));
1310
1311 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1312 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1313
1314 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1315 fde_buf[i] = cpu_to_le32(1); /* drive present */
1316 aml_append(dev, build_fdinfo_aml(i, type));
1317 }
1318 }
1319 aml_append(dev, aml_name_decl("_FDE",
1320 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1321
1322 return dev;
1323 }
1324
1325 static Aml *build_rtc_device_aml(void)
1326 {
1327 Aml *dev;
1328 Aml *crs;
1329
1330 dev = aml_device("RTC");
1331 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1332 crs = aml_resource_template();
1333 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1334 aml_append(crs, aml_irq_no_flags(8));
1335 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1336 aml_append(dev, aml_name_decl("_CRS", crs));
1337
1338 return dev;
1339 }
1340
1341 static Aml *build_kbd_device_aml(void)
1342 {
1343 Aml *dev;
1344 Aml *crs;
1345 Aml *method;
1346
1347 dev = aml_device("KBD");
1348 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1349
1350 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1351 aml_append(method, aml_return(aml_int(0x0f)));
1352 aml_append(dev, method);
1353
1354 crs = aml_resource_template();
1355 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1356 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1357 aml_append(crs, aml_irq_no_flags(1));
1358 aml_append(dev, aml_name_decl("_CRS", crs));
1359
1360 return dev;
1361 }
1362
1363 static Aml *build_mouse_device_aml(void)
1364 {
1365 Aml *dev;
1366 Aml *crs;
1367 Aml *method;
1368
1369 dev = aml_device("MOU");
1370 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1371
1372 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1373 aml_append(method, aml_return(aml_int(0x0f)));
1374 aml_append(dev, method);
1375
1376 crs = aml_resource_template();
1377 aml_append(crs, aml_irq_no_flags(12));
1378 aml_append(dev, aml_name_decl("_CRS", crs));
1379
1380 return dev;
1381 }
1382
1383 static Aml *build_lpt_device_aml(void)
1384 {
1385 Aml *dev;
1386 Aml *crs;
1387 Aml *method;
1388 Aml *if_ctx;
1389 Aml *else_ctx;
1390 Aml *zero = aml_int(0);
1391 Aml *is_present = aml_local(0);
1392
1393 dev = aml_device("LPT");
1394 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1395
1396 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1397 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1398 if_ctx = aml_if(aml_equal(is_present, zero));
1399 {
1400 aml_append(if_ctx, aml_return(aml_int(0x00)));
1401 }
1402 aml_append(method, if_ctx);
1403 else_ctx = aml_else();
1404 {
1405 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1406 }
1407 aml_append(method, else_ctx);
1408 aml_append(dev, method);
1409
1410 crs = aml_resource_template();
1411 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1412 aml_append(crs, aml_irq_no_flags(7));
1413 aml_append(dev, aml_name_decl("_CRS", crs));
1414
1415 return dev;
1416 }
1417
1418 static Aml *build_com_device_aml(uint8_t uid)
1419 {
1420 Aml *dev;
1421 Aml *crs;
1422 Aml *method;
1423 Aml *if_ctx;
1424 Aml *else_ctx;
1425 Aml *zero = aml_int(0);
1426 Aml *is_present = aml_local(0);
1427 const char *enabled_field = "CAEN";
1428 uint8_t irq = 4;
1429 uint16_t io_port = 0x03F8;
1430
1431 assert(uid == 1 || uid == 2);
1432 if (uid == 2) {
1433 enabled_field = "CBEN";
1434 irq = 3;
1435 io_port = 0x02F8;
1436 }
1437
1438 dev = aml_device("COM%d", uid);
1439 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1440 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1441
1442 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1443 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1444 if_ctx = aml_if(aml_equal(is_present, zero));
1445 {
1446 aml_append(if_ctx, aml_return(aml_int(0x00)));
1447 }
1448 aml_append(method, if_ctx);
1449 else_ctx = aml_else();
1450 {
1451 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1452 }
1453 aml_append(method, else_ctx);
1454 aml_append(dev, method);
1455
1456 crs = aml_resource_template();
1457 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1458 aml_append(crs, aml_irq_no_flags(irq));
1459 aml_append(dev, aml_name_decl("_CRS", crs));
1460
1461 return dev;
1462 }
1463
1464 static void build_isa_devices_aml(Aml *table)
1465 {
1466 ISADevice *fdc = pc_find_fdc0();
1467
1468 Aml *scope = aml_scope("_SB.PCI0.ISA");
1469
1470 aml_append(scope, build_rtc_device_aml());
1471 aml_append(scope, build_kbd_device_aml());
1472 aml_append(scope, build_mouse_device_aml());
1473 if (fdc) {
1474 aml_append(scope, build_fdc_device_aml(fdc));
1475 }
1476 aml_append(scope, build_lpt_device_aml());
1477 aml_append(scope, build_com_device_aml(1));
1478 aml_append(scope, build_com_device_aml(2));
1479
1480 aml_append(table, scope);
1481 }
1482
1483 static void build_dbg_aml(Aml *table)
1484 {
1485 Aml *field;
1486 Aml *method;
1487 Aml *while_ctx;
1488 Aml *scope = aml_scope("\\");
1489 Aml *buf = aml_local(0);
1490 Aml *len = aml_local(1);
1491 Aml *idx = aml_local(2);
1492
1493 aml_append(scope,
1494 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1495 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1496 aml_append(field, aml_named_field("DBGB", 8));
1497 aml_append(scope, field);
1498
1499 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1500
1501 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1502 aml_append(method, aml_to_buffer(buf, buf));
1503 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1504 aml_append(method, aml_store(aml_int(0), idx));
1505
1506 while_ctx = aml_while(aml_lless(idx, len));
1507 aml_append(while_ctx,
1508 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1509 aml_append(while_ctx, aml_increment(idx));
1510 aml_append(method, while_ctx);
1511
1512 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1513 aml_append(scope, method);
1514
1515 aml_append(table, scope);
1516 }
1517
1518 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1519 {
1520 Aml *dev;
1521 Aml *crs;
1522 Aml *method;
1523 uint32_t irqs[] = {5, 10, 11};
1524
1525 dev = aml_device("%s", name);
1526 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1527 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1528
1529 crs = aml_resource_template();
1530 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1531 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1532 aml_append(dev, aml_name_decl("_PRS", crs));
1533
1534 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1535 aml_append(method, aml_return(aml_call1("IQST", reg)));
1536 aml_append(dev, method);
1537
1538 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1539 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1540 aml_append(dev, method);
1541
1542 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1543 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1544 aml_append(dev, method);
1545
1546 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1547 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1548 aml_append(method, aml_store(aml_name("PRRI"), reg));
1549 aml_append(dev, method);
1550
1551 return dev;
1552 }
1553
1554 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1555 {
1556 Aml *dev;
1557 Aml *crs;
1558 Aml *method;
1559 uint32_t irqs;
1560
1561 dev = aml_device("%s", name);
1562 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1563 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1564
1565 crs = aml_resource_template();
1566 irqs = gsi;
1567 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1568 AML_SHARED, &irqs, 1));
1569 aml_append(dev, aml_name_decl("_PRS", crs));
1570
1571 aml_append(dev, aml_name_decl("_CRS", crs));
1572
1573 /*
1574 * _DIS can be no-op because the interrupt cannot be disabled.
1575 */
1576 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1577 aml_append(dev, method);
1578
1579 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1580 aml_append(dev, method);
1581
1582 return dev;
1583 }
1584
1585 /* _CRS method - get current settings */
1586 static Aml *build_iqcr_method(bool is_piix4)
1587 {
1588 Aml *if_ctx;
1589 uint32_t irqs;
1590 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1591 Aml *crs = aml_resource_template();
1592
1593 irqs = 0;
1594 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1595 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1596 aml_append(method, aml_name_decl("PRR0", crs));
1597
1598 aml_append(method,
1599 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1600
1601 if (is_piix4) {
1602 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1603 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1604 aml_append(method, if_ctx);
1605 } else {
1606 aml_append(method,
1607 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1608 aml_name("PRRI")));
1609 }
1610
1611 aml_append(method, aml_return(aml_name("PRR0")));
1612 return method;
1613 }
1614
1615 /* _STA method - get status */
1616 static Aml *build_irq_status_method(void)
1617 {
1618 Aml *if_ctx;
1619 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1620
1621 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1622 aml_append(if_ctx, aml_return(aml_int(0x09)));
1623 aml_append(method, if_ctx);
1624 aml_append(method, aml_return(aml_int(0x0B)));
1625 return method;
1626 }
1627
1628 static void build_piix4_pci0_int(Aml *table)
1629 {
1630 Aml *dev;
1631 Aml *crs;
1632 Aml *field;
1633 Aml *method;
1634 uint32_t irqs;
1635 Aml *sb_scope = aml_scope("_SB");
1636 Aml *pci0_scope = aml_scope("PCI0");
1637
1638 aml_append(pci0_scope, build_prt(true));
1639 aml_append(sb_scope, pci0_scope);
1640
1641 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1642 aml_append(field, aml_named_field("PRQ0", 8));
1643 aml_append(field, aml_named_field("PRQ1", 8));
1644 aml_append(field, aml_named_field("PRQ2", 8));
1645 aml_append(field, aml_named_field("PRQ3", 8));
1646 aml_append(sb_scope, field);
1647
1648 aml_append(sb_scope, build_irq_status_method());
1649 aml_append(sb_scope, build_iqcr_method(true));
1650
1651 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1652 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1653 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1654 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1655
1656 dev = aml_device("LNKS");
1657 {
1658 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1659 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1660
1661 crs = aml_resource_template();
1662 irqs = 9;
1663 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1664 AML_ACTIVE_HIGH, AML_SHARED,
1665 &irqs, 1));
1666 aml_append(dev, aml_name_decl("_PRS", crs));
1667
1668 /* The SCI cannot be disabled and is always attached to GSI 9,
1669 * so these are no-ops. We only need this link to override the
1670 * polarity to active high and match the content of the MADT.
1671 */
1672 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1673 aml_append(method, aml_return(aml_int(0x0b)));
1674 aml_append(dev, method);
1675
1676 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1677 aml_append(dev, method);
1678
1679 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1680 aml_append(method, aml_return(aml_name("_PRS")));
1681 aml_append(dev, method);
1682
1683 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1684 aml_append(dev, method);
1685 }
1686 aml_append(sb_scope, dev);
1687
1688 aml_append(table, sb_scope);
1689 }
1690
1691 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1692 {
1693 int i;
1694 int head;
1695 Aml *pkg;
1696 char base = name[3] < 'E' ? 'A' : 'E';
1697 char *s = g_strdup(name);
1698 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1699
1700 assert(strlen(s) == 4);
1701
1702 head = name[3] - base;
1703 for (i = 0; i < 4; i++) {
1704 if (head + i > 3) {
1705 head = i * -1;
1706 }
1707 s[3] = base + head + i;
1708 pkg = aml_package(4);
1709 aml_append(pkg, a_nr);
1710 aml_append(pkg, aml_int(i));
1711 aml_append(pkg, aml_name("%s", s));
1712 aml_append(pkg, aml_int(0));
1713 aml_append(ctx, pkg);
1714 }
1715 g_free(s);
1716 }
1717
1718 static Aml *build_q35_routing_table(const char *str)
1719 {
1720 int i;
1721 Aml *pkg;
1722 char *name = g_strdup_printf("%s ", str);
1723
1724 pkg = aml_package(128);
1725 for (i = 0; i < 0x18; i++) {
1726 name[3] = 'E' + (i & 0x3);
1727 append_q35_prt_entry(pkg, i, name);
1728 }
1729
1730 name[3] = 'E';
1731 append_q35_prt_entry(pkg, 0x18, name);
1732
1733 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1734 for (i = 0x0019; i < 0x1e; i++) {
1735 name[3] = 'A';
1736 append_q35_prt_entry(pkg, i, name);
1737 }
1738
1739 /* PCIe->PCI bridge. use PIRQ[E-H] */
1740 name[3] = 'E';
1741 append_q35_prt_entry(pkg, 0x1e, name);
1742 name[3] = 'A';
1743 append_q35_prt_entry(pkg, 0x1f, name);
1744
1745 g_free(name);
1746 return pkg;
1747 }
1748
1749 static void build_q35_pci0_int(Aml *table)
1750 {
1751 Aml *field;
1752 Aml *method;
1753 Aml *sb_scope = aml_scope("_SB");
1754 Aml *pci0_scope = aml_scope("PCI0");
1755
1756 /* Zero => PIC mode, One => APIC Mode */
1757 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1758 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1759 {
1760 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1761 }
1762 aml_append(table, method);
1763
1764 aml_append(pci0_scope,
1765 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1766 aml_append(pci0_scope,
1767 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1768
1769 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1770 {
1771 Aml *if_ctx;
1772 Aml *else_ctx;
1773
1774 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1775 section 6.2.8.1 */
1776 /* Note: we provide the same info as the PCI routing
1777 table of the Bochs BIOS */
1778 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1779 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1780 aml_append(method, if_ctx);
1781 else_ctx = aml_else();
1782 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1783 aml_append(method, else_ctx);
1784 }
1785 aml_append(pci0_scope, method);
1786 aml_append(sb_scope, pci0_scope);
1787
1788 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1789 aml_append(field, aml_named_field("PRQA", 8));
1790 aml_append(field, aml_named_field("PRQB", 8));
1791 aml_append(field, aml_named_field("PRQC", 8));
1792 aml_append(field, aml_named_field("PRQD", 8));
1793 aml_append(field, aml_reserved_field(0x20));
1794 aml_append(field, aml_named_field("PRQE", 8));
1795 aml_append(field, aml_named_field("PRQF", 8));
1796 aml_append(field, aml_named_field("PRQG", 8));
1797 aml_append(field, aml_named_field("PRQH", 8));
1798 aml_append(sb_scope, field);
1799
1800 aml_append(sb_scope, build_irq_status_method());
1801 aml_append(sb_scope, build_iqcr_method(false));
1802
1803 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1804 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1805 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1806 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1807 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1808 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1809 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1810 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1811
1812 /*
1813 * TODO: UID probably shouldn't be the same for GSIx devices
1814 * but that's how it was in original ASL so keep it for now
1815 */
1816 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1817 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1818 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1819 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1820 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1821 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1822 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1823 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1824
1825 aml_append(table, sb_scope);
1826 }
1827
1828 static void build_q35_isa_bridge(Aml *table)
1829 {
1830 Aml *dev;
1831 Aml *scope;
1832 Aml *field;
1833
1834 scope = aml_scope("_SB.PCI0");
1835 dev = aml_device("ISA");
1836 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1837
1838 /* ICH9 PCI to ISA irq remapping */
1839 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1840 aml_int(0x60), 0x0C));
1841
1842 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1843 aml_int(0x80), 0x02));
1844 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1845 aml_append(field, aml_named_field("COMA", 3));
1846 aml_append(field, aml_reserved_field(1));
1847 aml_append(field, aml_named_field("COMB", 3));
1848 aml_append(field, aml_reserved_field(1));
1849 aml_append(field, aml_named_field("LPTD", 2));
1850 aml_append(dev, field);
1851
1852 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1853 aml_int(0x82), 0x02));
1854 /* enable bits */
1855 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1856 aml_append(field, aml_named_field("CAEN", 1));
1857 aml_append(field, aml_named_field("CBEN", 1));
1858 aml_append(field, aml_named_field("LPEN", 1));
1859 aml_append(dev, field);
1860
1861 aml_append(scope, dev);
1862 aml_append(table, scope);
1863 }
1864
1865 static void build_piix4_pm(Aml *table)
1866 {
1867 Aml *dev;
1868 Aml *scope;
1869
1870 scope = aml_scope("_SB.PCI0");
1871 dev = aml_device("PX13");
1872 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1873
1874 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1875 aml_int(0x00), 0xff));
1876 aml_append(scope, dev);
1877 aml_append(table, scope);
1878 }
1879
1880 static void build_piix4_isa_bridge(Aml *table)
1881 {
1882 Aml *dev;
1883 Aml *scope;
1884 Aml *field;
1885
1886 scope = aml_scope("_SB.PCI0");
1887 dev = aml_device("ISA");
1888 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1889
1890 /* PIIX PCI to ISA irq remapping */
1891 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1892 aml_int(0x60), 0x04));
1893 /* enable bits */
1894 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1895 /* Offset(0x5f),, 7, */
1896 aml_append(field, aml_reserved_field(0x2f8));
1897 aml_append(field, aml_reserved_field(7));
1898 aml_append(field, aml_named_field("LPEN", 1));
1899 /* Offset(0x67),, 3, */
1900 aml_append(field, aml_reserved_field(0x38));
1901 aml_append(field, aml_reserved_field(3));
1902 aml_append(field, aml_named_field("CAEN", 1));
1903 aml_append(field, aml_reserved_field(3));
1904 aml_append(field, aml_named_field("CBEN", 1));
1905 aml_append(dev, field);
1906
1907 aml_append(scope, dev);
1908 aml_append(table, scope);
1909 }
1910
1911 static void build_piix4_pci_hotplug(Aml *table)
1912 {
1913 Aml *scope;
1914 Aml *field;
1915 Aml *method;
1916
1917 scope = aml_scope("_SB.PCI0");
1918
1919 aml_append(scope,
1920 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1921 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1922 aml_append(field, aml_named_field("PCIU", 32));
1923 aml_append(field, aml_named_field("PCID", 32));
1924 aml_append(scope, field);
1925
1926 aml_append(scope,
1927 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1928 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1929 aml_append(field, aml_named_field("B0EJ", 32));
1930 aml_append(scope, field);
1931
1932 aml_append(scope,
1933 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1934 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1935 aml_append(field, aml_named_field("BNUM", 32));
1936 aml_append(scope, field);
1937
1938 aml_append(scope, aml_mutex("BLCK", 0));
1939
1940 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1941 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1942 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1943 aml_append(method,
1944 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1945 aml_append(method, aml_release(aml_name("BLCK")));
1946 aml_append(method, aml_return(aml_int(0)));
1947 aml_append(scope, method);
1948
1949 aml_append(table, scope);
1950 }
1951
1952 static Aml *build_q35_osc_method(void)
1953 {
1954 Aml *if_ctx;
1955 Aml *if_ctx2;
1956 Aml *else_ctx;
1957 Aml *method;
1958 Aml *a_cwd1 = aml_name("CDW1");
1959 Aml *a_ctrl = aml_name("CTRL");
1960
1961 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1962 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1963
1964 if_ctx = aml_if(aml_equal(
1965 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1966 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1967 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1968
1969 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1970 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1971
1972 /*
1973 * Always allow native PME, AER (no dependencies)
1974 * Never allow SHPC (no SHPC controller in this system)
1975 */
1976 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1977
1978 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1979 /* Unknown revision */
1980 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1981 aml_append(if_ctx, if_ctx2);
1982
1983 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1984 /* Capabilities bits were masked */
1985 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1986 aml_append(if_ctx, if_ctx2);
1987
1988 /* Update DWORD3 in the buffer */
1989 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1990 aml_append(method, if_ctx);
1991
1992 else_ctx = aml_else();
1993 /* Unrecognized UUID */
1994 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1995 aml_append(method, else_ctx);
1996
1997 aml_append(method, aml_return(aml_arg(3)));
1998 return method;
1999 }
2000
2001 static void
2002 build_dsdt(GArray *table_data, GArray *linker,
2003 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
2004 PcPciInfo *pci, MachineState *machine)
2005 {
2006 CrsRangeEntry *entry;
2007 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
2008 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
2009 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
2010 PCMachineState *pcms = PC_MACHINE(machine);
2011 uint32_t nr_mem = machine->ram_slots;
2012 int root_bus_limit = 0xFF;
2013 PCIBus *bus = NULL;
2014 int i;
2015
2016 dsdt = init_aml_allocator();
2017
2018 /* Reserve space for header */
2019 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
2020
2021 build_dbg_aml(dsdt);
2022 if (misc->is_piix4) {
2023 sb_scope = aml_scope("_SB");
2024 dev = aml_device("PCI0");
2025 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2026 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2027 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2028 aml_append(sb_scope, dev);
2029 aml_append(dsdt, sb_scope);
2030
2031 build_hpet_aml(dsdt);
2032 build_piix4_pm(dsdt);
2033 build_piix4_isa_bridge(dsdt);
2034 build_isa_devices_aml(dsdt);
2035 build_piix4_pci_hotplug(dsdt);
2036 build_piix4_pci0_int(dsdt);
2037 } else {
2038 sb_scope = aml_scope("_SB");
2039 aml_append(sb_scope,
2040 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
2041 aml_append(sb_scope,
2042 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
2043 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2044 aml_append(field, aml_named_field("PCIB", 8));
2045 aml_append(sb_scope, field);
2046 aml_append(dsdt, sb_scope);
2047
2048 sb_scope = aml_scope("_SB");
2049 dev = aml_device("PCI0");
2050 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2051 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2052 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2053 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2054 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2055 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2056 aml_append(dev, build_q35_osc_method());
2057 aml_append(sb_scope, dev);
2058 aml_append(dsdt, sb_scope);
2059
2060 build_hpet_aml(dsdt);
2061 build_q35_isa_bridge(dsdt);
2062 build_isa_devices_aml(dsdt);
2063 build_q35_pci0_int(dsdt);
2064 }
2065
2066 build_cpu_hotplug_aml(dsdt);
2067 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2068 pm->mem_hp_io_len);
2069
2070 scope = aml_scope("_GPE");
2071 {
2072 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2073
2074 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2075
2076 if (misc->is_piix4) {
2077 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2078 aml_append(method,
2079 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2080 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2081 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2082 aml_append(scope, method);
2083 } else {
2084 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2085 }
2086
2087 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2088 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2089 aml_append(scope, method);
2090
2091 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2092 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2093 aml_append(scope, method);
2094
2095 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2096 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2097 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2098 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2099 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2100 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2101 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2102 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2103 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2104 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2105 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2106 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2107 }
2108 aml_append(dsdt, scope);
2109
2110 bus = PC_MACHINE(machine)->bus;
2111 if (bus) {
2112 QLIST_FOREACH(bus, &bus->child, sibling) {
2113 uint8_t bus_num = pci_bus_num(bus);
2114 uint8_t numa_node = pci_bus_numa_node(bus);
2115
2116 /* look only for expander root buses */
2117 if (!pci_bus_is_root(bus)) {
2118 continue;
2119 }
2120
2121 if (bus_num < root_bus_limit) {
2122 root_bus_limit = bus_num - 1;
2123 }
2124
2125 scope = aml_scope("\\_SB");
2126 dev = aml_device("PC%.02X", bus_num);
2127 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2128 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2129 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2130
2131 if (numa_node != NUMA_NODE_UNASSIGNED) {
2132 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2133 }
2134
2135 aml_append(dev, build_prt(false));
2136 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2137 io_ranges, mem_ranges);
2138 aml_append(dev, aml_name_decl("_CRS", crs));
2139 aml_append(scope, dev);
2140 aml_append(dsdt, scope);
2141 }
2142 }
2143
2144 scope = aml_scope("\\_SB.PCI0");
2145 /* build PCI0._CRS */
2146 crs = aml_resource_template();
2147 aml_append(crs,
2148 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2149 0x0000, 0x0, root_bus_limit,
2150 0x0000, root_bus_limit + 1));
2151 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2152
2153 aml_append(crs,
2154 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2155 AML_POS_DECODE, AML_ENTIRE_RANGE,
2156 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2157
2158 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2159 for (i = 0; i < io_ranges->len; i++) {
2160 entry = g_ptr_array_index(io_ranges, i);
2161 aml_append(crs,
2162 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2163 AML_POS_DECODE, AML_ENTIRE_RANGE,
2164 0x0000, entry->base, entry->limit,
2165 0x0000, entry->limit - entry->base + 1));
2166 }
2167
2168 aml_append(crs,
2169 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2170 AML_CACHEABLE, AML_READ_WRITE,
2171 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2172
2173 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2174 for (i = 0; i < mem_ranges->len; i++) {
2175 entry = g_ptr_array_index(mem_ranges, i);
2176 aml_append(crs,
2177 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2178 AML_NON_CACHEABLE, AML_READ_WRITE,
2179 0, entry->base, entry->limit,
2180 0, entry->limit - entry->base + 1));
2181 }
2182
2183 if (pci->w64.begin) {
2184 aml_append(crs,
2185 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2186 AML_CACHEABLE, AML_READ_WRITE,
2187 0, pci->w64.begin, pci->w64.end - 1, 0,
2188 pci->w64.end - pci->w64.begin));
2189 }
2190 aml_append(scope, aml_name_decl("_CRS", crs));
2191
2192 /* reserve GPE0 block resources */
2193 dev = aml_device("GPE0");
2194 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2195 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2196 /* device present, functioning, decoding, not shown in UI */
2197 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2198 crs = aml_resource_template();
2199 aml_append(crs,
2200 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2201 );
2202 aml_append(dev, aml_name_decl("_CRS", crs));
2203 aml_append(scope, dev);
2204
2205 g_ptr_array_free(io_ranges, true);
2206 g_ptr_array_free(mem_ranges, true);
2207
2208 /* reserve PCIHP resources */
2209 if (pm->pcihp_io_len) {
2210 dev = aml_device("PHPR");
2211 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2212 aml_append(dev,
2213 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2214 /* device present, functioning, decoding, not shown in UI */
2215 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2216 crs = aml_resource_template();
2217 aml_append(crs,
2218 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2219 pm->pcihp_io_len)
2220 );
2221 aml_append(dev, aml_name_decl("_CRS", crs));
2222 aml_append(scope, dev);
2223 }
2224 aml_append(dsdt, scope);
2225
2226 /* create S3_ / S4_ / S5_ packages if necessary */
2227 scope = aml_scope("\\");
2228 if (!pm->s3_disabled) {
2229 pkg = aml_package(4);
2230 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2231 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2232 aml_append(pkg, aml_int(0)); /* reserved */
2233 aml_append(pkg, aml_int(0)); /* reserved */
2234 aml_append(scope, aml_name_decl("_S3", pkg));
2235 }
2236
2237 if (!pm->s4_disabled) {
2238 pkg = aml_package(4);
2239 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2240 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2241 aml_append(pkg, aml_int(pm->s4_val));
2242 aml_append(pkg, aml_int(0)); /* reserved */
2243 aml_append(pkg, aml_int(0)); /* reserved */
2244 aml_append(scope, aml_name_decl("_S4", pkg));
2245 }
2246
2247 pkg = aml_package(4);
2248 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2249 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2250 aml_append(pkg, aml_int(0)); /* reserved */
2251 aml_append(pkg, aml_int(0)); /* reserved */
2252 aml_append(scope, aml_name_decl("_S5", pkg));
2253 aml_append(dsdt, scope);
2254
2255 /* create fw_cfg node, unconditionally */
2256 {
2257 /* when using port i/o, the 8-bit data register *always* overlaps
2258 * with half of the 16-bit control register. Hence, the total size
2259 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2260 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2261 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2262 "dma_enabled", NULL) ?
2263 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2264 FW_CFG_CTL_SIZE;
2265
2266 scope = aml_scope("\\_SB.PCI0");
2267 dev = aml_device("FWCF");
2268
2269 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2270
2271 /* device present, functioning, decoding, not shown in UI */
2272 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2273
2274 crs = aml_resource_template();
2275 aml_append(crs,
2276 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2277 );
2278 aml_append(dev, aml_name_decl("_CRS", crs));
2279
2280 aml_append(scope, dev);
2281 aml_append(dsdt, scope);
2282 }
2283
2284 if (misc->applesmc_io_base) {
2285 scope = aml_scope("\\_SB.PCI0.ISA");
2286 dev = aml_device("SMC");
2287
2288 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2289 /* device present, functioning, decoding, not shown in UI */
2290 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2291
2292 crs = aml_resource_template();
2293 aml_append(crs,
2294 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2295 0x01, APPLESMC_MAX_DATA_LENGTH)
2296 );
2297 aml_append(crs, aml_irq_no_flags(6));
2298 aml_append(dev, aml_name_decl("_CRS", crs));
2299
2300 aml_append(scope, dev);
2301 aml_append(dsdt, scope);
2302 }
2303
2304 if (misc->pvpanic_port) {
2305 scope = aml_scope("\\_SB.PCI0.ISA");
2306
2307 dev = aml_device("PEVT");
2308 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2309
2310 crs = aml_resource_template();
2311 aml_append(crs,
2312 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2313 );
2314 aml_append(dev, aml_name_decl("_CRS", crs));
2315
2316 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2317 aml_int(misc->pvpanic_port), 1));
2318 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2319 aml_append(field, aml_named_field("PEPT", 8));
2320 aml_append(dev, field);
2321
2322 /* device present, functioning, decoding, shown in UI */
2323 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2324
2325 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2326 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2327 aml_append(method, aml_return(aml_local(0)));
2328 aml_append(dev, method);
2329
2330 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2331 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2332 aml_append(dev, method);
2333
2334 aml_append(scope, dev);
2335 aml_append(dsdt, scope);
2336 }
2337
2338 sb_scope = aml_scope("\\_SB");
2339 {
2340 build_processor_devices(sb_scope, machine, cpu, pm);
2341
2342 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2343 pm->mem_hp_io_len);
2344
2345 {
2346 Object *pci_host;
2347 PCIBus *bus = NULL;
2348
2349 pci_host = acpi_get_i386_pci_host();
2350 if (pci_host) {
2351 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2352 }
2353
2354 if (bus) {
2355 Aml *scope = aml_scope("PCI0");
2356 /* Scan all PCI buses. Generate tables to support hotplug. */
2357 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2358
2359 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2360 dev = aml_device("ISA.TPM");
2361 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2362 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2363 crs = aml_resource_template();
2364 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2365 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2366 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2367 aml_append(dev, aml_name_decl("_CRS", crs));
2368 aml_append(scope, dev);
2369 }
2370
2371 aml_append(sb_scope, scope);
2372 }
2373 }
2374 aml_append(dsdt, sb_scope);
2375 }
2376
2377 /* copy AML table into ACPI tables blob and patch header there */
2378 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2379 build_header(linker, table_data,
2380 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2381 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2382 free_aml_allocator();
2383 }
2384
2385 static void
2386 build_hpet(GArray *table_data, GArray *linker)
2387 {
2388 Acpi20Hpet *hpet;
2389
2390 hpet = acpi_data_push(table_data, sizeof(*hpet));
2391 /* Note timer_block_id value must be kept in sync with value advertised by
2392 * emulated hpet
2393 */
2394 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2395 hpet->addr.address = cpu_to_le64(HPET_BASE);
2396 build_header(linker, table_data,
2397 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2398 }
2399
2400 static void
2401 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
2402 {
2403 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2404 uint64_t log_area_start_address = acpi_data_len(tcpalog);
2405
2406 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2407 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2408 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2409
2410 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2411 false /* high memory */);
2412
2413 /* log area start address to be filled by Guest linker */
2414 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2415 ACPI_BUILD_TPMLOG_FILE,
2416 table_data, &tcpa->log_area_start_address,
2417 sizeof(tcpa->log_area_start_address));
2418
2419 build_header(linker, table_data,
2420 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2421
2422 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2423 }
2424
2425 static void
2426 build_tpm2(GArray *table_data, GArray *linker)
2427 {
2428 Acpi20TPM2 *tpm2_ptr;
2429
2430 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2431
2432 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2433 tpm2_ptr->control_area_address = cpu_to_le64(0);
2434 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2435
2436 build_header(linker, table_data,
2437 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2438 }
2439
2440 typedef enum {
2441 MEM_AFFINITY_NOFLAGS = 0,
2442 MEM_AFFINITY_ENABLED = (1 << 0),
2443 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2444 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2445 } MemoryAffinityFlags;
2446
2447 static void
2448 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2449 uint64_t len, int node, MemoryAffinityFlags flags)
2450 {
2451 numamem->type = ACPI_SRAT_MEMORY;
2452 numamem->length = sizeof(*numamem);
2453 memset(numamem->proximity, 0, 4);
2454 numamem->proximity[0] = node;
2455 numamem->flags = cpu_to_le32(flags);
2456 numamem->base_addr = cpu_to_le64(base);
2457 numamem->range_length = cpu_to_le64(len);
2458 }
2459
2460 static void
2461 build_srat(GArray *table_data, GArray *linker, MachineState *machine)
2462 {
2463 AcpiSystemResourceAffinityTable *srat;
2464 AcpiSratProcessorAffinity *core;
2465 AcpiSratMemoryAffinity *numamem;
2466
2467 int i;
2468 uint64_t curnode;
2469 int srat_start, numa_start, slots;
2470 uint64_t mem_len, mem_base, next_base;
2471 MachineClass *mc = MACHINE_GET_CLASS(machine);
2472 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2473 PCMachineState *pcms = PC_MACHINE(machine);
2474 ram_addr_t hotplugabble_address_space_size =
2475 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2476 NULL);
2477
2478 srat_start = table_data->len;
2479
2480 srat = acpi_data_push(table_data, sizeof *srat);
2481 srat->reserved1 = cpu_to_le32(1);
2482
2483 for (i = 0; i < apic_ids->len; i++) {
2484 int apic_id = apic_ids->cpus[i].arch_id;
2485
2486 core = acpi_data_push(table_data, sizeof *core);
2487 core->type = ACPI_SRAT_PROCESSOR;
2488 core->length = sizeof(*core);
2489 core->local_apic_id = apic_id;
2490 curnode = pcms->node_cpu[apic_id];
2491 core->proximity_lo = curnode;
2492 memset(core->proximity_hi, 0, 3);
2493 core->local_sapic_eid = 0;
2494 core->flags = cpu_to_le32(1);
2495 }
2496
2497
2498 /* the memory map is a bit tricky, it contains at least one hole
2499 * from 640k-1M and possibly another one from 3.5G-4G.
2500 */
2501 next_base = 0;
2502 numa_start = table_data->len;
2503
2504 numamem = acpi_data_push(table_data, sizeof *numamem);
2505 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2506 next_base = 1024 * 1024;
2507 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2508 mem_base = next_base;
2509 mem_len = pcms->node_mem[i - 1];
2510 if (i == 1) {
2511 mem_len -= 1024 * 1024;
2512 }
2513 next_base = mem_base + mem_len;
2514
2515 /* Cut out the ACPI_PCI hole */
2516 if (mem_base <= pcms->below_4g_mem_size &&
2517 next_base > pcms->below_4g_mem_size) {
2518 mem_len -= next_base - pcms->below_4g_mem_size;
2519 if (mem_len > 0) {
2520 numamem = acpi_data_push(table_data, sizeof *numamem);
2521 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2522 MEM_AFFINITY_ENABLED);
2523 }
2524 mem_base = 1ULL << 32;
2525 mem_len = next_base - pcms->below_4g_mem_size;
2526 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2527 }
2528 numamem = acpi_data_push(table_data, sizeof *numamem);
2529 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2530 MEM_AFFINITY_ENABLED);
2531 }
2532 slots = (table_data->len - numa_start) / sizeof *numamem;
2533 for (; slots < pcms->numa_nodes + 2; slots++) {
2534 numamem = acpi_data_push(table_data, sizeof *numamem);
2535 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2536 }
2537
2538 /*
2539 * Entry is required for Windows to enable memory hotplug in OS.
2540 * Memory devices may override proximity set by this entry,
2541 * providing _PXM method if necessary.
2542 */
2543 if (hotplugabble_address_space_size) {
2544 numamem = acpi_data_push(table_data, sizeof *numamem);
2545 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2546 hotplugabble_address_space_size, 0,
2547 MEM_AFFINITY_HOTPLUGGABLE |
2548 MEM_AFFINITY_ENABLED);
2549 }
2550
2551 build_header(linker, table_data,
2552 (void *)(table_data->data + srat_start),
2553 "SRAT",
2554 table_data->len - srat_start, 1, NULL, NULL);
2555 g_free(apic_ids);
2556 }
2557
2558 static void
2559 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2560 {
2561 AcpiTableMcfg *mcfg;
2562 const char *sig;
2563 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2564
2565 mcfg = acpi_data_push(table_data, len);
2566 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2567 /* Only a single allocation so no need to play with segments */
2568 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2569 mcfg->allocation[0].start_bus_number = 0;
2570 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2571
2572 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2573 * To avoid table size changes (which create migration issues),
2574 * always create the table even if there are no allocations,
2575 * but set the signature to a reserved value in this case.
2576 * ACPI spec requires OSPMs to ignore such tables.
2577 */
2578 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2579 /* Reserved signature: ignored by OSPM */
2580 sig = "QEMU";
2581 } else {
2582 sig = "MCFG";
2583 }
2584 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2585 }
2586
2587 static void
2588 build_dmar_q35(GArray *table_data, GArray *linker)
2589 {
2590 int dmar_start = table_data->len;
2591
2592 AcpiTableDmar *dmar;
2593 AcpiDmarHardwareUnit *drhd;
2594
2595 dmar = acpi_data_push(table_data, sizeof(*dmar));
2596 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2597 dmar->flags = 0; /* No intr_remap for now */
2598
2599 /* DMAR Remapping Hardware Unit Definition structure */
2600 drhd = acpi_data_push(table_data, sizeof(*drhd));
2601 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2602 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2603 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2604 drhd->pci_segment = cpu_to_le16(0);
2605 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2606
2607 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2608 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2609 }
2610
2611 static GArray *
2612 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2613 {
2614 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2615
2616 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2617 true /* fseg memory */);
2618
2619 memcpy(&rsdp->signature, "RSD PTR ", 8);
2620 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2621 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2622 /* Address to be filled by Guest linker */
2623 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2624 ACPI_BUILD_TABLE_FILE,
2625 rsdp_table, &rsdp->rsdt_physical_address,
2626 sizeof rsdp->rsdt_physical_address);
2627 rsdp->checksum = 0;
2628 /* Checksum to be filled by Guest linker */
2629 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2630 rsdp_table, rsdp, sizeof *rsdp,
2631 &rsdp->checksum);
2632
2633 return rsdp_table;
2634 }
2635
2636 typedef
2637 struct AcpiBuildState {
2638 /* Copy of table in RAM (for patching). */
2639 MemoryRegion *table_mr;
2640 /* Is table patched? */
2641 uint8_t patched;
2642 void *rsdp;
2643 MemoryRegion *rsdp_mr;
2644 MemoryRegion *linker_mr;
2645 } AcpiBuildState;
2646
2647 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2648 {
2649 Object *pci_host;
2650 QObject *o;
2651
2652 pci_host = acpi_get_i386_pci_host();
2653 g_assert(pci_host);
2654
2655 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2656 if (!o) {
2657 return false;
2658 }
2659 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2660 qobject_decref(o);
2661
2662 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2663 assert(o);
2664 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2665 qobject_decref(o);
2666 return true;
2667 }
2668
2669 static bool acpi_has_iommu(void)
2670 {
2671 bool ambiguous;
2672 Object *intel_iommu;
2673
2674 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2675 &ambiguous);
2676 return intel_iommu && !ambiguous;
2677 }
2678
2679 static
2680 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2681 {
2682 PCMachineState *pcms = PC_MACHINE(machine);
2683 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2684 GArray *table_offsets;
2685 unsigned facs, dsdt, rsdt, fadt;
2686 AcpiCpuInfo cpu;
2687 AcpiPmInfo pm;
2688 AcpiMiscInfo misc;
2689 AcpiMcfgInfo mcfg;
2690 PcPciInfo pci;
2691 uint8_t *u;
2692 size_t aml_len = 0;
2693 GArray *tables_blob = tables->table_data;
2694 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2695
2696 acpi_get_cpu_info(&cpu);
2697 acpi_get_pm_info(&pm);
2698 acpi_get_misc_info(&misc);
2699 acpi_get_pci_info(&pci);
2700 acpi_get_slic_oem(&slic_oem);
2701
2702 table_offsets = g_array_new(false, true /* clear */,
2703 sizeof(uint32_t));
2704 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2705
2706 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2707 64 /* Ensure FACS is aligned */,
2708 false /* high memory */);
2709
2710 /*
2711 * FACS is pointed to by FADT.
2712 * We place it first since it's the only table that has alignment
2713 * requirements.
2714 */
2715 facs = tables_blob->len;
2716 build_facs(tables_blob, tables->linker);
2717
2718 /* DSDT is pointed to by FADT */
2719 dsdt = tables_blob->len;
2720 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, machine);
2721
2722 /* Count the size of the DSDT and SSDT, we will need it for legacy
2723 * sizing of ACPI tables.
2724 */
2725 aml_len += tables_blob->len - dsdt;
2726
2727 /* ACPI tables pointed to by RSDT */
2728 fadt = tables_blob->len;
2729 acpi_add_table(table_offsets, tables_blob);
2730 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2731 slic_oem.id, slic_oem.table_id);
2732 aml_len += tables_blob->len - fadt;
2733
2734 acpi_add_table(table_offsets, tables_blob);
2735 build_madt(tables_blob, tables->linker, pcms);
2736
2737 if (misc.has_hpet) {
2738 acpi_add_table(table_offsets, tables_blob);
2739 build_hpet(tables_blob, tables->linker);
2740 }
2741 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2742 acpi_add_table(table_offsets, tables_blob);
2743 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2744
2745 if (misc.tpm_version == TPM_VERSION_2_0) {
2746 acpi_add_table(table_offsets, tables_blob);
2747 build_tpm2(tables_blob, tables->linker);
2748 }
2749 }
2750 if (pcms->numa_nodes) {
2751 acpi_add_table(table_offsets, tables_blob);
2752 build_srat(tables_blob, tables->linker, machine);
2753 }
2754 if (acpi_get_mcfg(&mcfg)) {
2755 acpi_add_table(table_offsets, tables_blob);
2756 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2757 }
2758 if (acpi_has_iommu()) {
2759 acpi_add_table(table_offsets, tables_blob);
2760 build_dmar_q35(tables_blob, tables->linker);
2761 }
2762 if (pcms->acpi_nvdimm_state.is_enabled) {
2763 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2764 }
2765
2766 /* Add tables supplied by user (if any) */
2767 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2768 unsigned len = acpi_table_len(u);
2769
2770 acpi_add_table(table_offsets, tables_blob);
2771 g_array_append_vals(tables_blob, u, len);
2772 }
2773
2774 /* RSDT is pointed to by RSDP */
2775 rsdt = tables_blob->len;
2776 build_rsdt(tables_blob, tables->linker, table_offsets,
2777 slic_oem.id, slic_oem.table_id);
2778
2779 /* RSDP is in FSEG memory, so allocate it separately */
2780 build_rsdp(tables->rsdp, tables->linker, rsdt);
2781
2782 /* We'll expose it all to Guest so we want to reduce
2783 * chance of size changes.
2784 *
2785 * We used to align the tables to 4k, but of course this would
2786 * too simple to be enough. 4k turned out to be too small an
2787 * alignment very soon, and in fact it is almost impossible to
2788 * keep the table size stable for all (max_cpus, max_memory_slots)
2789 * combinations. So the table size is always 64k for pc-i440fx-2.1
2790 * and we give an error if the table grows beyond that limit.
2791 *
2792 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2793 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2794 * than 2.0 and we can always pad the smaller tables with zeros. We can
2795 * then use the exact size of the 2.0 tables.
2796 *
2797 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2798 */
2799 if (pcmc->legacy_acpi_table_size) {
2800 /* Subtracting aml_len gives the size of fixed tables. Then add the
2801 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2802 */
2803 int legacy_aml_len =
2804 pcmc->legacy_acpi_table_size +
2805 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2806 int legacy_table_size =
2807 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2808 ACPI_BUILD_ALIGN_SIZE);
2809 if (tables_blob->len > legacy_table_size) {
2810 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2811 error_report("Warning: migration may not work.");
2812 }
2813 g_array_set_size(tables_blob, legacy_table_size);
2814 } else {
2815 /* Make sure we have a buffer in case we need to resize the tables. */
2816 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2817 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2818 error_report("Warning: ACPI tables are larger than 64k.");
2819 error_report("Warning: migration may not work.");
2820 error_report("Warning: please remove CPUs, NUMA nodes, "
2821 "memory slots or PCI bridges.");
2822 }
2823 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2824 }
2825
2826 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2827
2828 /* Cleanup memory that's no longer used. */
2829 g_array_free(table_offsets, true);
2830 }
2831
2832 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2833 {
2834 uint32_t size = acpi_data_len(data);
2835
2836 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2837 memory_region_ram_resize(mr, size, &error_abort);
2838
2839 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2840 memory_region_set_dirty(mr, 0, size);
2841 }
2842
2843 static void acpi_build_update(void *build_opaque)
2844 {
2845 AcpiBuildState *build_state = build_opaque;
2846 AcpiBuildTables tables;
2847
2848 /* No state to update or already patched? Nothing to do. */
2849 if (!build_state || build_state->patched) {
2850 return;
2851 }
2852 build_state->patched = 1;
2853
2854 acpi_build_tables_init(&tables);
2855
2856 acpi_build(&tables, MACHINE(qdev_get_machine()));
2857
2858 acpi_ram_update(build_state->table_mr, tables.table_data);
2859
2860 if (build_state->rsdp) {
2861 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2862 } else {
2863 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2864 }
2865
2866 acpi_ram_update(build_state->linker_mr, tables.linker);
2867 acpi_build_tables_cleanup(&tables, true);
2868 }
2869
2870 static void acpi_build_reset(void *build_opaque)
2871 {
2872 AcpiBuildState *build_state = build_opaque;
2873 build_state->patched = 0;
2874 }
2875
2876 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2877 GArray *blob, const char *name,
2878 uint64_t max_size)
2879 {
2880 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2881 name, acpi_build_update, build_state);
2882 }
2883
2884 static const VMStateDescription vmstate_acpi_build = {
2885 .name = "acpi_build",
2886 .version_id = 1,
2887 .minimum_version_id = 1,
2888 .fields = (VMStateField[]) {
2889 VMSTATE_UINT8(patched, AcpiBuildState),
2890 VMSTATE_END_OF_LIST()
2891 },
2892 };
2893
2894 void acpi_setup(void)
2895 {
2896 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2897 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2898 AcpiBuildTables tables;
2899 AcpiBuildState *build_state;
2900
2901 if (!pcms->fw_cfg) {
2902 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2903 return;
2904 }
2905
2906 if (!pcmc->has_acpi_build) {
2907 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2908 return;
2909 }
2910
2911 if (!acpi_enabled) {
2912 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2913 return;
2914 }
2915
2916 build_state = g_malloc0(sizeof *build_state);
2917
2918 acpi_set_pci_info();
2919
2920 acpi_build_tables_init(&tables);
2921 acpi_build(&tables, MACHINE(pcms));
2922
2923 /* Now expose it all to Guest */
2924 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2925 ACPI_BUILD_TABLE_FILE,
2926 ACPI_BUILD_TABLE_MAX_SIZE);
2927 assert(build_state->table_mr != NULL);
2928
2929 build_state->linker_mr =
2930 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2931
2932 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2933 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2934
2935 if (!pcmc->rsdp_in_ram) {
2936 /*
2937 * Keep for compatibility with old machine types.
2938 * Though RSDP is small, its contents isn't immutable, so
2939 * we'll update it along with the rest of tables on guest access.
2940 */
2941 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2942
2943 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2944 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2945 acpi_build_update, build_state,
2946 build_state->rsdp, rsdp_size);
2947 build_state->rsdp_mr = NULL;
2948 } else {
2949 build_state->rsdp = NULL;
2950 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2951 ACPI_BUILD_RSDP_FILE, 0);
2952 }
2953
2954 qemu_register_reset(acpi_build_reset, build_state);
2955 acpi_build_reset(build_state);
2956 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2957
2958 /* Cleanup tables but don't free the memory: we track it
2959 * in build_state.
2960 */
2961 acpi_build_tables_cleanup(&tables, false);
2962 }
AR7 emulation for QEMU