2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/bitops.h"
22 #include "hw/sysbus.h"
23 #include "migration/vmstate.h"
24 #include "hw/qdev-core.h"
25 #include "hw/pci/pci.h"
26 #include "exec/address-spaces.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
33 #include "hw/arm/smmuv3.h"
34 #include "smmuv3-internal.h"
35 #include "smmu-internal.h"
38 * smmuv3_trigger_irq - pulse @irq if enabled and update
39 * GERROR register in case of GERROR interrupt
42 * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
44 static void smmuv3_trigger_irq(SMMUv3State
*s
, SMMUIrq irq
,
52 pulse
= smmuv3_eventq_irq_enabled(s
);
55 qemu_log_mask(LOG_UNIMP
, "PRI not yet supported\n");
57 case SMMU_IRQ_CMD_SYNC
:
62 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
63 uint32_t new_gerrors
= ~pending
& gerror_mask
;
66 /* only toggle non pending errors */
69 s
->gerror
^= new_gerrors
;
70 trace_smmuv3_write_gerror(new_gerrors
, s
->gerror
);
72 pulse
= smmuv3_gerror_irq_enabled(s
);
77 trace_smmuv3_trigger_irq(irq
);
78 qemu_irq_pulse(s
->irq
[irq
]);
82 static void smmuv3_write_gerrorn(SMMUv3State
*s
, uint32_t new_gerrorn
)
84 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
85 uint32_t toggled
= s
->gerrorn
^ new_gerrorn
;
87 if (toggled
& ~pending
) {
88 qemu_log_mask(LOG_GUEST_ERROR
,
89 "guest toggles non pending errors = 0x%x\n",
94 * We do not raise any error in case guest toggles bits corresponding
95 * to not active IRQs (CONSTRAINED UNPREDICTABLE)
97 s
->gerrorn
= new_gerrorn
;
99 trace_smmuv3_write_gerrorn(toggled
& pending
, s
->gerrorn
);
102 static inline MemTxResult
queue_read(SMMUQueue
*q
, void *data
)
104 dma_addr_t addr
= Q_CONS_ENTRY(q
);
106 return dma_memory_read(&address_space_memory
, addr
, data
, q
->entry_size
);
109 static MemTxResult
queue_write(SMMUQueue
*q
, void *data
)
111 dma_addr_t addr
= Q_PROD_ENTRY(q
);
114 ret
= dma_memory_write(&address_space_memory
, addr
, data
, q
->entry_size
);
115 if (ret
!= MEMTX_OK
) {
123 static MemTxResult
smmuv3_write_eventq(SMMUv3State
*s
, Evt
*evt
)
125 SMMUQueue
*q
= &s
->eventq
;
128 if (!smmuv3_eventq_enabled(s
)) {
132 if (smmuv3_q_full(q
)) {
136 r
= queue_write(q
, evt
);
141 if (!smmuv3_q_empty(q
)) {
142 smmuv3_trigger_irq(s
, SMMU_IRQ_EVTQ
, 0);
147 void smmuv3_record_event(SMMUv3State
*s
, SMMUEventInfo
*info
)
152 if (!smmuv3_eventq_enabled(s
)) {
156 EVT_SET_TYPE(&evt
, info
->type
);
157 EVT_SET_SID(&evt
, info
->sid
);
159 switch (info
->type
) {
163 EVT_SET_SSID(&evt
, info
->u
.f_uut
.ssid
);
164 EVT_SET_SSV(&evt
, info
->u
.f_uut
.ssv
);
165 EVT_SET_ADDR(&evt
, info
->u
.f_uut
.addr
);
166 EVT_SET_RNW(&evt
, info
->u
.f_uut
.rnw
);
167 EVT_SET_PNU(&evt
, info
->u
.f_uut
.pnu
);
168 EVT_SET_IND(&evt
, info
->u
.f_uut
.ind
);
170 case SMMU_EVT_C_BAD_STREAMID
:
171 EVT_SET_SSID(&evt
, info
->u
.c_bad_streamid
.ssid
);
172 EVT_SET_SSV(&evt
, info
->u
.c_bad_streamid
.ssv
);
174 case SMMU_EVT_F_STE_FETCH
:
175 EVT_SET_SSID(&evt
, info
->u
.f_ste_fetch
.ssid
);
176 EVT_SET_SSV(&evt
, info
->u
.f_ste_fetch
.ssv
);
177 EVT_SET_ADDR2(&evt
, info
->u
.f_ste_fetch
.addr
);
179 case SMMU_EVT_C_BAD_STE
:
180 EVT_SET_SSID(&evt
, info
->u
.c_bad_ste
.ssid
);
181 EVT_SET_SSV(&evt
, info
->u
.c_bad_ste
.ssv
);
183 case SMMU_EVT_F_STREAM_DISABLED
:
185 case SMMU_EVT_F_TRANS_FORBIDDEN
:
186 EVT_SET_ADDR(&evt
, info
->u
.f_transl_forbidden
.addr
);
187 EVT_SET_RNW(&evt
, info
->u
.f_transl_forbidden
.rnw
);
189 case SMMU_EVT_C_BAD_SUBSTREAMID
:
190 EVT_SET_SSID(&evt
, info
->u
.c_bad_substream
.ssid
);
192 case SMMU_EVT_F_CD_FETCH
:
193 EVT_SET_SSID(&evt
, info
->u
.f_cd_fetch
.ssid
);
194 EVT_SET_SSV(&evt
, info
->u
.f_cd_fetch
.ssv
);
195 EVT_SET_ADDR(&evt
, info
->u
.f_cd_fetch
.addr
);
197 case SMMU_EVT_C_BAD_CD
:
198 EVT_SET_SSID(&evt
, info
->u
.c_bad_cd
.ssid
);
199 EVT_SET_SSV(&evt
, info
->u
.c_bad_cd
.ssv
);
201 case SMMU_EVT_F_WALK_EABT
:
202 case SMMU_EVT_F_TRANSLATION
:
203 case SMMU_EVT_F_ADDR_SIZE
:
204 case SMMU_EVT_F_ACCESS
:
205 case SMMU_EVT_F_PERMISSION
:
206 EVT_SET_STALL(&evt
, info
->u
.f_walk_eabt
.stall
);
207 EVT_SET_STAG(&evt
, info
->u
.f_walk_eabt
.stag
);
208 EVT_SET_SSID(&evt
, info
->u
.f_walk_eabt
.ssid
);
209 EVT_SET_SSV(&evt
, info
->u
.f_walk_eabt
.ssv
);
210 EVT_SET_S2(&evt
, info
->u
.f_walk_eabt
.s2
);
211 EVT_SET_ADDR(&evt
, info
->u
.f_walk_eabt
.addr
);
212 EVT_SET_RNW(&evt
, info
->u
.f_walk_eabt
.rnw
);
213 EVT_SET_PNU(&evt
, info
->u
.f_walk_eabt
.pnu
);
214 EVT_SET_IND(&evt
, info
->u
.f_walk_eabt
.ind
);
215 EVT_SET_CLASS(&evt
, info
->u
.f_walk_eabt
.class);
216 EVT_SET_ADDR2(&evt
, info
->u
.f_walk_eabt
.addr2
);
218 case SMMU_EVT_F_CFG_CONFLICT
:
219 EVT_SET_SSID(&evt
, info
->u
.f_cfg_conflict
.ssid
);
220 EVT_SET_SSV(&evt
, info
->u
.f_cfg_conflict
.ssv
);
222 /* rest is not implemented */
223 case SMMU_EVT_F_BAD_ATS_TREQ
:
224 case SMMU_EVT_F_TLB_CONFLICT
:
225 case SMMU_EVT_E_PAGE_REQ
:
227 g_assert_not_reached();
230 trace_smmuv3_record_event(smmu_event_string(info
->type
), info
->sid
);
231 r
= smmuv3_write_eventq(s
, &evt
);
233 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_EVENTQ_ABT_ERR_MASK
);
235 info
->recorded
= true;
238 static void smmuv3_init_regs(SMMUv3State
*s
)
241 * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
242 * multi-level stream table
244 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, S1P
, 1); /* stage 1 supported */
245 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTF
, 2); /* AArch64 PTW only */
246 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, COHACC
, 1); /* IO coherent */
247 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, ASID16
, 1); /* 16-bit ASID */
248 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTENDIAN
, 2); /* little endian */
249 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STALL_MODEL
, 1); /* No stall */
250 /* terminated transaction will always be aborted/error returned */
251 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TERM_MODEL
, 1);
252 /* 2-level stream table supported */
253 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STLEVEL
, 1);
255 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, SIDSIZE
, SMMU_IDR1_SIDSIZE
);
256 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, EVENTQS
, SMMU_EVENTQS
);
257 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, CMDQS
, SMMU_CMDQS
);
259 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, RIL
, 1);
260 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, HAD
, 1);
262 /* 4K and 64K granule support */
263 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN4K
, 1);
264 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN64K
, 1);
265 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, OAS
, SMMU_IDR5_OAS
); /* 44 bits */
267 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 5, SMMU_CMDQS
);
270 s
->cmdq
.entry_size
= sizeof(struct Cmd
);
271 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 5, SMMU_EVENTQS
);
274 s
->eventq
.entry_size
= sizeof(struct Evt
);
281 static int smmu_get_ste(SMMUv3State
*s
, dma_addr_t addr
, STE
*buf
,
282 SMMUEventInfo
*event
)
286 trace_smmuv3_get_ste(addr
);
287 /* TODO: guarantee 64-bit single-copy atomicity */
288 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
));
289 if (ret
!= MEMTX_OK
) {
290 qemu_log_mask(LOG_GUEST_ERROR
,
291 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
292 event
->type
= SMMU_EVT_F_STE_FETCH
;
293 event
->u
.f_ste_fetch
.addr
= addr
;
300 /* @ssid > 0 not supported yet */
301 static int smmu_get_cd(SMMUv3State
*s
, STE
*ste
, uint32_t ssid
,
302 CD
*buf
, SMMUEventInfo
*event
)
304 dma_addr_t addr
= STE_CTXPTR(ste
);
307 trace_smmuv3_get_cd(addr
);
308 /* TODO: guarantee 64-bit single-copy atomicity */
309 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
));
310 if (ret
!= MEMTX_OK
) {
311 qemu_log_mask(LOG_GUEST_ERROR
,
312 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
313 event
->type
= SMMU_EVT_F_CD_FETCH
;
314 event
->u
.f_ste_fetch
.addr
= addr
;
320 /* Returns < 0 in case of invalid STE, 0 otherwise */
321 static int decode_ste(SMMUv3State
*s
, SMMUTransCfg
*cfg
,
322 STE
*ste
, SMMUEventInfo
*event
)
326 if (!STE_VALID(ste
)) {
327 if (!event
->inval_ste_allowed
) {
328 qemu_log_mask(LOG_GUEST_ERROR
, "invalid STE\n");
333 config
= STE_CONFIG(ste
);
335 if (STE_CFG_ABORT(config
)) {
340 if (STE_CFG_BYPASS(config
)) {
341 cfg
->bypassed
= true;
345 if (STE_CFG_S2_ENABLED(config
)) {
346 qemu_log_mask(LOG_UNIMP
, "SMMUv3 does not support stage 2 yet\n");
350 if (STE_S1CDMAX(ste
) != 0) {
351 qemu_log_mask(LOG_UNIMP
,
352 "SMMUv3 does not support multiple context descriptors yet\n");
356 if (STE_S1STALLD(ste
)) {
357 qemu_log_mask(LOG_UNIMP
,
358 "SMMUv3 S1 stalling fault model not allowed yet\n");
364 event
->type
= SMMU_EVT_C_BAD_STE
;
369 * smmu_find_ste - Return the stream table entry associated
374 * @ste: returned stream table entry
375 * @event: handle to an event info
377 * Supports linear and 2-level stream table
378 * Return 0 on success, -EINVAL otherwise
380 static int smmu_find_ste(SMMUv3State
*s
, uint32_t sid
, STE
*ste
,
381 SMMUEventInfo
*event
)
383 dma_addr_t addr
, strtab_base
;
385 int strtab_size_shift
;
388 trace_smmuv3_find_ste(sid
, s
->features
, s
->sid_split
);
389 log2size
= FIELD_EX32(s
->strtab_base_cfg
, STRTAB_BASE_CFG
, LOG2SIZE
);
391 * Check SID range against both guest-configured and implementation limits
393 if (sid
>= (1 << MIN(log2size
, SMMU_IDR1_SIDSIZE
))) {
394 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
397 if (s
->features
& SMMU_FEATURE_2LVL_STE
) {
398 int l1_ste_offset
, l2_ste_offset
, max_l2_ste
, span
;
399 dma_addr_t l1ptr
, l2ptr
;
403 * Align strtab base address to table size. For this purpose, assume it
404 * is not bounded by SMMU_IDR1_SIDSIZE.
406 strtab_size_shift
= MAX(5, (int)log2size
- s
->sid_split
- 1 + 3);
407 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
408 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
409 l1_ste_offset
= sid
>> s
->sid_split
;
410 l2_ste_offset
= sid
& ((1 << s
->sid_split
) - 1);
411 l1ptr
= (dma_addr_t
)(strtab_base
+ l1_ste_offset
* sizeof(l1std
));
412 /* TODO: guarantee 64-bit single-copy atomicity */
413 ret
= dma_memory_read(&address_space_memory
, l1ptr
, &l1std
,
415 if (ret
!= MEMTX_OK
) {
416 qemu_log_mask(LOG_GUEST_ERROR
,
417 "Could not read L1PTR at 0X%"PRIx64
"\n", l1ptr
);
418 event
->type
= SMMU_EVT_F_STE_FETCH
;
419 event
->u
.f_ste_fetch
.addr
= l1ptr
;
423 span
= L1STD_SPAN(&l1std
);
426 /* l2ptr is not valid */
427 if (!event
->inval_ste_allowed
) {
428 qemu_log_mask(LOG_GUEST_ERROR
,
429 "invalid sid=%d (L1STD span=0)\n", sid
);
431 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
434 max_l2_ste
= (1 << span
) - 1;
435 l2ptr
= l1std_l2ptr(&l1std
);
436 trace_smmuv3_find_ste_2lvl(s
->strtab_base
, l1ptr
, l1_ste_offset
,
437 l2ptr
, l2_ste_offset
, max_l2_ste
);
438 if (l2_ste_offset
> max_l2_ste
) {
439 qemu_log_mask(LOG_GUEST_ERROR
,
440 "l2_ste_offset=%d > max_l2_ste=%d\n",
441 l2_ste_offset
, max_l2_ste
);
442 event
->type
= SMMU_EVT_C_BAD_STE
;
445 addr
= l2ptr
+ l2_ste_offset
* sizeof(*ste
);
447 strtab_size_shift
= log2size
+ 5;
448 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
449 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
450 addr
= strtab_base
+ sid
* sizeof(*ste
);
453 if (smmu_get_ste(s
, addr
, ste
, event
)) {
460 static int decode_cd(SMMUTransCfg
*cfg
, CD
*cd
, SMMUEventInfo
*event
)
465 if (!CD_VALID(cd
) || !CD_AARCH64(cd
)) {
469 goto bad_cd
; /* SMMU_IDR0.TERM_MODEL == 1 */
472 goto bad_cd
; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
474 if (CD_HA(cd
) || CD_HD(cd
)) {
475 goto bad_cd
; /* HTTU = 0 */
478 /* we support only those at the moment */
482 cfg
->oas
= oas2bits(CD_IPS(cd
));
483 cfg
->oas
= MIN(oas2bits(SMMU_IDR5_OAS
), cfg
->oas
);
484 cfg
->tbi
= CD_TBI(cd
);
485 cfg
->asid
= CD_ASID(cd
);
487 trace_smmuv3_decode_cd(cfg
->oas
);
489 /* decode data dependent on TT */
490 for (i
= 0; i
<= 1; i
++) {
492 SMMUTransTableInfo
*tt
= &cfg
->tt
[i
];
494 cfg
->tt
[i
].disabled
= CD_EPD(cd
, i
);
495 if (cfg
->tt
[i
].disabled
) {
500 if (tsz
< 16 || tsz
> 39) {
505 tt
->granule_sz
= tg2granule(tg
, i
);
506 if ((tt
->granule_sz
!= 12 && tt
->granule_sz
!= 16) || CD_ENDI(cd
)) {
511 tt
->ttb
= CD_TTB(cd
, i
);
512 if (tt
->ttb
& ~(MAKE_64BIT_MASK(0, cfg
->oas
))) {
515 tt
->had
= CD_HAD(cd
, i
);
516 trace_smmuv3_decode_cd_tt(i
, tt
->tsz
, tt
->ttb
, tt
->granule_sz
, tt
->had
);
519 event
->record_trans_faults
= CD_R(cd
);
524 event
->type
= SMMU_EVT_C_BAD_CD
;
529 * smmuv3_decode_config - Prepare the translation configuration
530 * for the @mr iommu region
531 * @mr: iommu memory region the translation config must be prepared for
532 * @cfg: output translation configuration which is populated through
533 * the different configuration decoding steps
534 * @event: must be zero'ed by the caller
536 * return < 0 in case of config decoding error (@event is filled
537 * accordingly). Return 0 otherwise.
539 static int smmuv3_decode_config(IOMMUMemoryRegion
*mr
, SMMUTransCfg
*cfg
,
540 SMMUEventInfo
*event
)
542 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
543 uint32_t sid
= smmu_get_sid(sdev
);
544 SMMUv3State
*s
= sdev
->smmu
;
549 ret
= smmu_find_ste(s
, sid
, &ste
, event
);
554 ret
= decode_ste(s
, cfg
, &ste
, event
);
559 if (cfg
->aborted
|| cfg
->bypassed
) {
563 ret
= smmu_get_cd(s
, &ste
, 0 /* ssid */, &cd
, event
);
568 return decode_cd(cfg
, &cd
, event
);
572 * smmuv3_get_config - Look up for a cached copy of configuration data for
573 * @sdev and on cache miss performs a configuration structure decoding from
576 * @sdev: SMMUDevice handle
577 * @event: output event info
579 * The configuration cache contains data resulting from both STE and CD
580 * decoding under the form of an SMMUTransCfg struct. The hash table is indexed
581 * by the SMMUDevice handle.
583 static SMMUTransCfg
*smmuv3_get_config(SMMUDevice
*sdev
, SMMUEventInfo
*event
)
585 SMMUv3State
*s
= sdev
->smmu
;
586 SMMUState
*bc
= &s
->smmu_state
;
589 cfg
= g_hash_table_lookup(bc
->configs
, sdev
);
591 sdev
->cfg_cache_hits
++;
592 trace_smmuv3_config_cache_hit(smmu_get_sid(sdev
),
593 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
594 100 * sdev
->cfg_cache_hits
/
595 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
597 sdev
->cfg_cache_misses
++;
598 trace_smmuv3_config_cache_miss(smmu_get_sid(sdev
),
599 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
600 100 * sdev
->cfg_cache_hits
/
601 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
602 cfg
= g_new0(SMMUTransCfg
, 1);
604 if (!smmuv3_decode_config(&sdev
->iommu
, cfg
, event
)) {
605 g_hash_table_insert(bc
->configs
, sdev
, cfg
);
614 static void smmuv3_flush_config(SMMUDevice
*sdev
)
616 SMMUv3State
*s
= sdev
->smmu
;
617 SMMUState
*bc
= &s
->smmu_state
;
619 trace_smmuv3_config_cache_inv(smmu_get_sid(sdev
));
620 g_hash_table_remove(bc
->configs
, sdev
);
623 static IOMMUTLBEntry
smmuv3_translate(IOMMUMemoryRegion
*mr
, hwaddr addr
,
624 IOMMUAccessFlags flag
, int iommu_idx
)
626 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
627 SMMUv3State
*s
= sdev
->smmu
;
628 uint32_t sid
= smmu_get_sid(sdev
);
629 SMMUEventInfo event
= {.type
= SMMU_EVT_NONE
,
631 .inval_ste_allowed
= false};
632 SMMUPTWEventInfo ptw_info
= {};
633 SMMUTranslationStatus status
;
634 SMMUState
*bs
= ARM_SMMU(s
);
635 uint64_t page_mask
, aligned_addr
;
636 SMMUTLBEntry
*cached_entry
= NULL
;
637 SMMUTransTableInfo
*tt
;
638 SMMUTransCfg
*cfg
= NULL
;
639 IOMMUTLBEntry entry
= {
640 .target_as
= &address_space_memory
,
642 .translated_addr
= addr
,
643 .addr_mask
= ~(hwaddr
)0,
647 qemu_mutex_lock(&s
->mutex
);
649 if (!smmu_enabled(s
)) {
650 status
= SMMU_TRANS_DISABLE
;
654 cfg
= smmuv3_get_config(sdev
, &event
);
656 status
= SMMU_TRANS_ERROR
;
661 status
= SMMU_TRANS_ABORT
;
666 status
= SMMU_TRANS_BYPASS
;
670 tt
= select_tt(cfg
, addr
);
672 if (event
.record_trans_faults
) {
673 event
.type
= SMMU_EVT_F_TRANSLATION
;
674 event
.u
.f_translation
.addr
= addr
;
675 event
.u
.f_translation
.rnw
= flag
& 0x1;
677 status
= SMMU_TRANS_ERROR
;
681 page_mask
= (1ULL << (tt
->granule_sz
)) - 1;
682 aligned_addr
= addr
& ~page_mask
;
684 cached_entry
= smmu_iotlb_lookup(bs
, cfg
, tt
, aligned_addr
);
686 if ((flag
& IOMMU_WO
) && !(cached_entry
->entry
.perm
& IOMMU_WO
)) {
687 status
= SMMU_TRANS_ERROR
;
688 if (event
.record_trans_faults
) {
689 event
.type
= SMMU_EVT_F_PERMISSION
;
690 event
.u
.f_permission
.addr
= addr
;
691 event
.u
.f_permission
.rnw
= flag
& 0x1;
694 status
= SMMU_TRANS_SUCCESS
;
699 cached_entry
= g_new0(SMMUTLBEntry
, 1);
701 if (smmu_ptw(cfg
, aligned_addr
, flag
, cached_entry
, &ptw_info
)) {
702 g_free(cached_entry
);
703 switch (ptw_info
.type
) {
704 case SMMU_PTW_ERR_WALK_EABT
:
705 event
.type
= SMMU_EVT_F_WALK_EABT
;
706 event
.u
.f_walk_eabt
.addr
= addr
;
707 event
.u
.f_walk_eabt
.rnw
= flag
& 0x1;
708 event
.u
.f_walk_eabt
.class = 0x1;
709 event
.u
.f_walk_eabt
.addr2
= ptw_info
.addr
;
711 case SMMU_PTW_ERR_TRANSLATION
:
712 if (event
.record_trans_faults
) {
713 event
.type
= SMMU_EVT_F_TRANSLATION
;
714 event
.u
.f_translation
.addr
= addr
;
715 event
.u
.f_translation
.rnw
= flag
& 0x1;
718 case SMMU_PTW_ERR_ADDR_SIZE
:
719 if (event
.record_trans_faults
) {
720 event
.type
= SMMU_EVT_F_ADDR_SIZE
;
721 event
.u
.f_addr_size
.addr
= addr
;
722 event
.u
.f_addr_size
.rnw
= flag
& 0x1;
725 case SMMU_PTW_ERR_ACCESS
:
726 if (event
.record_trans_faults
) {
727 event
.type
= SMMU_EVT_F_ACCESS
;
728 event
.u
.f_access
.addr
= addr
;
729 event
.u
.f_access
.rnw
= flag
& 0x1;
732 case SMMU_PTW_ERR_PERMISSION
:
733 if (event
.record_trans_faults
) {
734 event
.type
= SMMU_EVT_F_PERMISSION
;
735 event
.u
.f_permission
.addr
= addr
;
736 event
.u
.f_permission
.rnw
= flag
& 0x1;
740 g_assert_not_reached();
742 status
= SMMU_TRANS_ERROR
;
744 smmu_iotlb_insert(bs
, cfg
, cached_entry
);
745 status
= SMMU_TRANS_SUCCESS
;
749 qemu_mutex_unlock(&s
->mutex
);
751 case SMMU_TRANS_SUCCESS
:
753 entry
.translated_addr
= cached_entry
->entry
.translated_addr
+
754 (addr
& cached_entry
->entry
.addr_mask
);
755 entry
.addr_mask
= cached_entry
->entry
.addr_mask
;
756 trace_smmuv3_translate_success(mr
->parent_obj
.name
, sid
, addr
,
757 entry
.translated_addr
, entry
.perm
);
759 case SMMU_TRANS_DISABLE
:
761 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
762 trace_smmuv3_translate_disable(mr
->parent_obj
.name
, sid
, addr
,
765 case SMMU_TRANS_BYPASS
:
767 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
768 trace_smmuv3_translate_bypass(mr
->parent_obj
.name
, sid
, addr
,
771 case SMMU_TRANS_ABORT
:
772 /* no event is recorded on abort */
773 trace_smmuv3_translate_abort(mr
->parent_obj
.name
, sid
, addr
,
776 case SMMU_TRANS_ERROR
:
777 qemu_log_mask(LOG_GUEST_ERROR
,
778 "%s translation failed for iova=0x%"PRIx64
"(%s)\n",
779 mr
->parent_obj
.name
, addr
, smmu_event_string(event
.type
));
780 smmuv3_record_event(s
, &event
);
788 * smmuv3_notify_iova - call the notifier @n for a given
789 * @asid and @iova tuple.
791 * @mr: IOMMU mr region handle
792 * @n: notifier to be called
793 * @asid: address space ID or negative value if we don't care
795 * @tg: translation granule (if communicated through range invalidation)
796 * @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
798 static void smmuv3_notify_iova(IOMMUMemoryRegion
*mr
,
800 int asid
, dma_addr_t iova
,
801 uint8_t tg
, uint64_t num_pages
)
803 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
808 SMMUEventInfo event
= {.inval_ste_allowed
= true};
809 SMMUTransCfg
*cfg
= smmuv3_get_config(sdev
, &event
);
810 SMMUTransTableInfo
*tt
;
816 if (asid
>= 0 && cfg
->asid
!= asid
) {
820 tt
= select_tt(cfg
, iova
);
824 granule
= tt
->granule_sz
;
826 granule
= tg
* 2 + 10;
829 event
.type
= IOMMU_NOTIFIER_UNMAP
;
830 event
.entry
.target_as
= &address_space_memory
;
831 event
.entry
.iova
= iova
;
832 event
.entry
.addr_mask
= num_pages
* (1 << granule
) - 1;
833 event
.entry
.perm
= IOMMU_NONE
;
835 memory_region_notify_iommu_one(n
, &event
);
838 /* invalidate an asid/iova range tuple in all mr's */
839 static void smmuv3_inv_notifiers_iova(SMMUState
*s
, int asid
, dma_addr_t iova
,
840 uint8_t tg
, uint64_t num_pages
)
844 QLIST_FOREACH(sdev
, &s
->devices_with_notifiers
, next
) {
845 IOMMUMemoryRegion
*mr
= &sdev
->iommu
;
848 trace_smmuv3_inv_notifiers_iova(mr
->parent_obj
.name
, asid
, iova
,
851 IOMMU_NOTIFIER_FOREACH(n
, mr
) {
852 smmuv3_notify_iova(mr
, n
, asid
, iova
, tg
, num_pages
);
857 static void smmuv3_s1_range_inval(SMMUState
*s
, Cmd
*cmd
)
859 uint8_t scale
= 0, num
= 0, ttl
= 0;
860 dma_addr_t addr
= CMD_ADDR(cmd
);
861 uint8_t type
= CMD_TYPE(cmd
);
862 uint16_t vmid
= CMD_VMID(cmd
);
863 bool leaf
= CMD_LEAF(cmd
);
864 uint8_t tg
= CMD_TG(cmd
);
865 uint64_t first_page
= 0, last_page
;
866 uint64_t num_pages
= 1;
870 scale
= CMD_SCALE(cmd
);
873 num_pages
= (num
+ 1) * BIT_ULL(scale
);
876 if (type
== SMMU_CMD_TLBI_NH_VA
) {
877 asid
= CMD_ASID(cmd
);
880 /* Split invalidations into ^2 range invalidations */
881 last_page
= num_pages
- 1;
883 uint8_t granule
= tg
* 2 + 10;
884 uint64_t mask
, count
;
886 mask
= dma_aligned_pow2_mask(first_page
, last_page
, 64 - granule
);
889 trace_smmuv3_s1_range_inval(vmid
, asid
, addr
, tg
, count
, ttl
, leaf
);
890 smmuv3_inv_notifiers_iova(s
, asid
, addr
, tg
, count
);
891 smmu_iotlb_inv_iova(s
, asid
, addr
, tg
, count
, ttl
);
895 addr
+= count
* BIT_ULL(granule
);
900 smmuv3_invalidate_ste(gpointer key
, gpointer value
, gpointer user_data
)
902 SMMUDevice
*sdev
= (SMMUDevice
*)key
;
903 uint32_t sid
= smmu_get_sid(sdev
);
904 SMMUSIDRange
*sid_range
= (SMMUSIDRange
*)user_data
;
906 if (sid
< sid_range
->start
|| sid
> sid_range
->end
) {
909 trace_smmuv3_config_cache_inv(sid
);
913 static int smmuv3_cmdq_consume(SMMUv3State
*s
)
915 SMMUState
*bs
= ARM_SMMU(s
);
916 SMMUCmdError cmd_error
= SMMU_CERROR_NONE
;
917 SMMUQueue
*q
= &s
->cmdq
;
918 SMMUCommandType type
= 0;
920 if (!smmuv3_cmdq_enabled(s
)) {
924 * some commands depend on register values, typically CR0. In case those
925 * register values change while handling the command, spec says it
926 * is UNPREDICTABLE whether the command is interpreted under the new
930 while (!smmuv3_q_empty(q
)) {
931 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
934 trace_smmuv3_cmdq_consume(Q_PROD(q
), Q_CONS(q
),
935 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
937 if (FIELD_EX32(pending
, GERROR
, CMDQ_ERR
)) {
941 if (queue_read(q
, &cmd
) != MEMTX_OK
) {
942 cmd_error
= SMMU_CERROR_ABT
;
946 type
= CMD_TYPE(&cmd
);
948 trace_smmuv3_cmdq_opcode(smmu_cmd_string(type
));
950 qemu_mutex_lock(&s
->mutex
);
953 if (CMD_SYNC_CS(&cmd
) & CMD_SYNC_SIG_IRQ
) {
954 smmuv3_trigger_irq(s
, SMMU_IRQ_CMD_SYNC
, 0);
957 case SMMU_CMD_PREFETCH_CONFIG
:
958 case SMMU_CMD_PREFETCH_ADDR
:
960 case SMMU_CMD_CFGI_STE
:
962 uint32_t sid
= CMD_SID(&cmd
);
963 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
966 if (CMD_SSEC(&cmd
)) {
967 cmd_error
= SMMU_CERROR_ILL
;
975 trace_smmuv3_cmdq_cfgi_ste(sid
);
976 sdev
= container_of(mr
, SMMUDevice
, iommu
);
977 smmuv3_flush_config(sdev
);
981 case SMMU_CMD_CFGI_STE_RANGE
: /* same as SMMU_CMD_CFGI_ALL */
983 uint32_t start
= CMD_SID(&cmd
);
984 uint8_t range
= CMD_STE_RANGE(&cmd
);
985 uint64_t end
= start
+ (1ULL << (range
+ 1)) - 1;
986 SMMUSIDRange sid_range
= {start
, end
};
988 if (CMD_SSEC(&cmd
)) {
989 cmd_error
= SMMU_CERROR_ILL
;
992 trace_smmuv3_cmdq_cfgi_ste_range(start
, end
);
993 g_hash_table_foreach_remove(bs
->configs
, smmuv3_invalidate_ste
,
997 case SMMU_CMD_CFGI_CD
:
998 case SMMU_CMD_CFGI_CD_ALL
:
1000 uint32_t sid
= CMD_SID(&cmd
);
1001 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
1004 if (CMD_SSEC(&cmd
)) {
1005 cmd_error
= SMMU_CERROR_ILL
;
1013 trace_smmuv3_cmdq_cfgi_cd(sid
);
1014 sdev
= container_of(mr
, SMMUDevice
, iommu
);
1015 smmuv3_flush_config(sdev
);
1018 case SMMU_CMD_TLBI_NH_ASID
:
1020 uint16_t asid
= CMD_ASID(&cmd
);
1022 trace_smmuv3_cmdq_tlbi_nh_asid(asid
);
1023 smmu_inv_notifiers_all(&s
->smmu_state
);
1024 smmu_iotlb_inv_asid(bs
, asid
);
1027 case SMMU_CMD_TLBI_NH_ALL
:
1028 case SMMU_CMD_TLBI_NSNH_ALL
:
1029 trace_smmuv3_cmdq_tlbi_nh();
1030 smmu_inv_notifiers_all(&s
->smmu_state
);
1031 smmu_iotlb_inv_all(bs
);
1033 case SMMU_CMD_TLBI_NH_VAA
:
1034 case SMMU_CMD_TLBI_NH_VA
:
1035 smmuv3_s1_range_inval(bs
, &cmd
);
1037 case SMMU_CMD_TLBI_EL3_ALL
:
1038 case SMMU_CMD_TLBI_EL3_VA
:
1039 case SMMU_CMD_TLBI_EL2_ALL
:
1040 case SMMU_CMD_TLBI_EL2_ASID
:
1041 case SMMU_CMD_TLBI_EL2_VA
:
1042 case SMMU_CMD_TLBI_EL2_VAA
:
1043 case SMMU_CMD_TLBI_S12_VMALL
:
1044 case SMMU_CMD_TLBI_S2_IPA
:
1045 case SMMU_CMD_ATC_INV
:
1046 case SMMU_CMD_PRI_RESP
:
1047 case SMMU_CMD_RESUME
:
1048 case SMMU_CMD_STALL_TERM
:
1049 trace_smmuv3_unhandled_cmd(type
);
1052 cmd_error
= SMMU_CERROR_ILL
;
1053 qemu_log_mask(LOG_GUEST_ERROR
,
1054 "Illegal command type: %d\n", CMD_TYPE(&cmd
));
1057 qemu_mutex_unlock(&s
->mutex
);
1062 * We only increment the cons index after the completion of
1063 * the command. We do that because the SYNC returns immediately
1064 * and does not check the completion of previous commands
1070 trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type
), cmd_error
);
1071 smmu_write_cmdq_err(s
, cmd_error
);
1072 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_CMDQ_ERR_MASK
);
1075 trace_smmuv3_cmdq_consume_out(Q_PROD(q
), Q_CONS(q
),
1076 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
1081 static MemTxResult
smmu_writell(SMMUv3State
*s
, hwaddr offset
,
1082 uint64_t data
, MemTxAttrs attrs
)
1085 case A_GERROR_IRQ_CFG0
:
1086 s
->gerror_irq_cfg0
= data
;
1089 s
->strtab_base
= data
;
1092 s
->cmdq
.base
= data
;
1093 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1094 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1095 s
->cmdq
.log2size
= SMMU_CMDQS
;
1099 s
->eventq
.base
= data
;
1100 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1101 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1102 s
->eventq
.log2size
= SMMU_EVENTQS
;
1105 case A_EVENTQ_IRQ_CFG0
:
1106 s
->eventq_irq_cfg0
= data
;
1109 qemu_log_mask(LOG_UNIMP
,
1110 "%s Unexpected 64-bit access to 0x%"PRIx64
" (WI)\n",
1116 static MemTxResult
smmu_writel(SMMUv3State
*s
, hwaddr offset
,
1117 uint64_t data
, MemTxAttrs attrs
)
1122 s
->cr0ack
= data
& ~SMMU_CR0_RESERVED
;
1123 /* in case the command queue has been enabled */
1124 smmuv3_cmdq_consume(s
);
1136 smmuv3_write_gerrorn(s
, data
);
1138 * By acknowledging the CMDQ_ERR, SW may notify cmds can
1139 * be processed again
1141 smmuv3_cmdq_consume(s
);
1143 case A_GERROR_IRQ_CFG0
: /* 64b */
1144 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 0, 32, data
);
1146 case A_GERROR_IRQ_CFG0
+ 4:
1147 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 32, 32, data
);
1149 case A_GERROR_IRQ_CFG1
:
1150 s
->gerror_irq_cfg1
= data
;
1152 case A_GERROR_IRQ_CFG2
:
1153 s
->gerror_irq_cfg2
= data
;
1155 case A_STRTAB_BASE
: /* 64b */
1156 s
->strtab_base
= deposit64(s
->strtab_base
, 0, 32, data
);
1158 case A_STRTAB_BASE
+ 4:
1159 s
->strtab_base
= deposit64(s
->strtab_base
, 32, 32, data
);
1161 case A_STRTAB_BASE_CFG
:
1162 s
->strtab_base_cfg
= data
;
1163 if (FIELD_EX32(data
, STRTAB_BASE_CFG
, FMT
) == 1) {
1164 s
->sid_split
= FIELD_EX32(data
, STRTAB_BASE_CFG
, SPLIT
);
1165 s
->features
|= SMMU_FEATURE_2LVL_STE
;
1168 case A_CMDQ_BASE
: /* 64b */
1169 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 32, data
);
1170 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1171 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1172 s
->cmdq
.log2size
= SMMU_CMDQS
;
1175 case A_CMDQ_BASE
+ 4: /* 64b */
1176 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 32, 32, data
);
1179 s
->cmdq
.prod
= data
;
1180 smmuv3_cmdq_consume(s
);
1183 s
->cmdq
.cons
= data
;
1185 case A_EVENTQ_BASE
: /* 64b */
1186 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 32, data
);
1187 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1188 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1189 s
->eventq
.log2size
= SMMU_EVENTQS
;
1192 case A_EVENTQ_BASE
+ 4:
1193 s
->eventq
.base
= deposit64(s
->eventq
.base
, 32, 32, data
);
1196 s
->eventq
.prod
= data
;
1199 s
->eventq
.cons
= data
;
1201 case A_EVENTQ_IRQ_CFG0
: /* 64b */
1202 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 0, 32, data
);
1204 case A_EVENTQ_IRQ_CFG0
+ 4:
1205 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 32, 32, data
);
1207 case A_EVENTQ_IRQ_CFG1
:
1208 s
->eventq_irq_cfg1
= data
;
1210 case A_EVENTQ_IRQ_CFG2
:
1211 s
->eventq_irq_cfg2
= data
;
1214 qemu_log_mask(LOG_UNIMP
,
1215 "%s Unexpected 32-bit access to 0x%"PRIx64
" (WI)\n",
1221 static MemTxResult
smmu_write_mmio(void *opaque
, hwaddr offset
, uint64_t data
,
1222 unsigned size
, MemTxAttrs attrs
)
1224 SMMUState
*sys
= opaque
;
1225 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1228 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1233 r
= smmu_writell(s
, offset
, data
, attrs
);
1236 r
= smmu_writel(s
, offset
, data
, attrs
);
1243 trace_smmuv3_write_mmio(offset
, data
, size
, r
);
1247 static MemTxResult
smmu_readll(SMMUv3State
*s
, hwaddr offset
,
1248 uint64_t *data
, MemTxAttrs attrs
)
1251 case A_GERROR_IRQ_CFG0
:
1252 *data
= s
->gerror_irq_cfg0
;
1255 *data
= s
->strtab_base
;
1258 *data
= s
->cmdq
.base
;
1261 *data
= s
->eventq
.base
;
1265 qemu_log_mask(LOG_UNIMP
,
1266 "%s Unexpected 64-bit access to 0x%"PRIx64
" (RAZ)\n",
1272 static MemTxResult
smmu_readl(SMMUv3State
*s
, hwaddr offset
,
1273 uint64_t *data
, MemTxAttrs attrs
)
1276 case A_IDREGS
... A_IDREGS
+ 0x2f:
1277 *data
= smmuv3_idreg(offset
- A_IDREGS
);
1279 case A_IDR0
... A_IDR5
:
1280 *data
= s
->idr
[(offset
- A_IDR0
) / 4];
1304 case A_IRQ_CTRL_ACK
:
1305 *data
= s
->irq_ctrl
;
1313 case A_GERROR_IRQ_CFG0
: /* 64b */
1314 *data
= extract64(s
->gerror_irq_cfg0
, 0, 32);
1316 case A_GERROR_IRQ_CFG0
+ 4:
1317 *data
= extract64(s
->gerror_irq_cfg0
, 32, 32);
1319 case A_GERROR_IRQ_CFG1
:
1320 *data
= s
->gerror_irq_cfg1
;
1322 case A_GERROR_IRQ_CFG2
:
1323 *data
= s
->gerror_irq_cfg2
;
1325 case A_STRTAB_BASE
: /* 64b */
1326 *data
= extract64(s
->strtab_base
, 0, 32);
1328 case A_STRTAB_BASE
+ 4: /* 64b */
1329 *data
= extract64(s
->strtab_base
, 32, 32);
1331 case A_STRTAB_BASE_CFG
:
1332 *data
= s
->strtab_base_cfg
;
1334 case A_CMDQ_BASE
: /* 64b */
1335 *data
= extract64(s
->cmdq
.base
, 0, 32);
1337 case A_CMDQ_BASE
+ 4:
1338 *data
= extract64(s
->cmdq
.base
, 32, 32);
1341 *data
= s
->cmdq
.prod
;
1344 *data
= s
->cmdq
.cons
;
1346 case A_EVENTQ_BASE
: /* 64b */
1347 *data
= extract64(s
->eventq
.base
, 0, 32);
1349 case A_EVENTQ_BASE
+ 4: /* 64b */
1350 *data
= extract64(s
->eventq
.base
, 32, 32);
1353 *data
= s
->eventq
.prod
;
1356 *data
= s
->eventq
.cons
;
1360 qemu_log_mask(LOG_UNIMP
,
1361 "%s unhandled 32-bit access at 0x%"PRIx64
" (RAZ)\n",
1367 static MemTxResult
smmu_read_mmio(void *opaque
, hwaddr offset
, uint64_t *data
,
1368 unsigned size
, MemTxAttrs attrs
)
1370 SMMUState
*sys
= opaque
;
1371 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1374 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1379 r
= smmu_readll(s
, offset
, data
, attrs
);
1382 r
= smmu_readl(s
, offset
, data
, attrs
);
1389 trace_smmuv3_read_mmio(offset
, *data
, size
, r
);
1393 static const MemoryRegionOps smmu_mem_ops
= {
1394 .read_with_attrs
= smmu_read_mmio
,
1395 .write_with_attrs
= smmu_write_mmio
,
1396 .endianness
= DEVICE_LITTLE_ENDIAN
,
1398 .min_access_size
= 4,
1399 .max_access_size
= 8,
1402 .min_access_size
= 4,
1403 .max_access_size
= 8,
1407 static void smmu_init_irq(SMMUv3State
*s
, SysBusDevice
*dev
)
1411 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
1412 sysbus_init_irq(dev
, &s
->irq
[i
]);
1416 static void smmu_reset(DeviceState
*dev
)
1418 SMMUv3State
*s
= ARM_SMMUV3(dev
);
1419 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1421 c
->parent_reset(dev
);
1423 smmuv3_init_regs(s
);
1426 static void smmu_realize(DeviceState
*d
, Error
**errp
)
1428 SMMUState
*sys
= ARM_SMMU(d
);
1429 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1430 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1431 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
1432 Error
*local_err
= NULL
;
1434 c
->parent_realize(d
, &local_err
);
1436 error_propagate(errp
, local_err
);
1440 qemu_mutex_init(&s
->mutex
);
1442 memory_region_init_io(&sys
->iomem
, OBJECT(s
),
1443 &smmu_mem_ops
, sys
, TYPE_ARM_SMMUV3
, 0x20000);
1445 sys
->mrtypename
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
;
1447 sysbus_init_mmio(dev
, &sys
->iomem
);
1449 smmu_init_irq(s
, dev
);
1452 static const VMStateDescription vmstate_smmuv3_queue
= {
1453 .name
= "smmuv3_queue",
1455 .minimum_version_id
= 1,
1456 .fields
= (VMStateField
[]) {
1457 VMSTATE_UINT64(base
, SMMUQueue
),
1458 VMSTATE_UINT32(prod
, SMMUQueue
),
1459 VMSTATE_UINT32(cons
, SMMUQueue
),
1460 VMSTATE_UINT8(log2size
, SMMUQueue
),
1461 VMSTATE_END_OF_LIST(),
1465 static const VMStateDescription vmstate_smmuv3
= {
1468 .minimum_version_id
= 1,
1469 .priority
= MIG_PRI_IOMMU
,
1470 .fields
= (VMStateField
[]) {
1471 VMSTATE_UINT32(features
, SMMUv3State
),
1472 VMSTATE_UINT8(sid_size
, SMMUv3State
),
1473 VMSTATE_UINT8(sid_split
, SMMUv3State
),
1475 VMSTATE_UINT32_ARRAY(cr
, SMMUv3State
, 3),
1476 VMSTATE_UINT32(cr0ack
, SMMUv3State
),
1477 VMSTATE_UINT32(statusr
, SMMUv3State
),
1478 VMSTATE_UINT32(irq_ctrl
, SMMUv3State
),
1479 VMSTATE_UINT32(gerror
, SMMUv3State
),
1480 VMSTATE_UINT32(gerrorn
, SMMUv3State
),
1481 VMSTATE_UINT64(gerror_irq_cfg0
, SMMUv3State
),
1482 VMSTATE_UINT32(gerror_irq_cfg1
, SMMUv3State
),
1483 VMSTATE_UINT32(gerror_irq_cfg2
, SMMUv3State
),
1484 VMSTATE_UINT64(strtab_base
, SMMUv3State
),
1485 VMSTATE_UINT32(strtab_base_cfg
, SMMUv3State
),
1486 VMSTATE_UINT64(eventq_irq_cfg0
, SMMUv3State
),
1487 VMSTATE_UINT32(eventq_irq_cfg1
, SMMUv3State
),
1488 VMSTATE_UINT32(eventq_irq_cfg2
, SMMUv3State
),
1490 VMSTATE_STRUCT(cmdq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1491 VMSTATE_STRUCT(eventq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1493 VMSTATE_END_OF_LIST(),
1497 static void smmuv3_instance_init(Object
*obj
)
1499 /* Nothing much to do here as of now */
1502 static void smmuv3_class_init(ObjectClass
*klass
, void *data
)
1504 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1505 SMMUv3Class
*c
= ARM_SMMUV3_CLASS(klass
);
1507 dc
->vmsd
= &vmstate_smmuv3
;
1508 device_class_set_parent_reset(dc
, smmu_reset
, &c
->parent_reset
);
1509 c
->parent_realize
= dc
->realize
;
1510 dc
->realize
= smmu_realize
;
1513 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
1514 IOMMUNotifierFlag old
,
1515 IOMMUNotifierFlag
new,
1518 SMMUDevice
*sdev
= container_of(iommu
, SMMUDevice
, iommu
);
1519 SMMUv3State
*s3
= sdev
->smmu
;
1520 SMMUState
*s
= &(s3
->smmu_state
);
1522 if (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP
) {
1523 error_setg(errp
, "SMMUv3 does not support dev-iotlb yet");
1527 if (new & IOMMU_NOTIFIER_MAP
) {
1529 "device %02x.%02x.%x requires iommu MAP notifier which is "
1530 "not currently supported", pci_bus_num(sdev
->bus
),
1531 PCI_SLOT(sdev
->devfn
), PCI_FUNC(sdev
->devfn
));
1535 if (old
== IOMMU_NOTIFIER_NONE
) {
1536 trace_smmuv3_notify_flag_add(iommu
->parent_obj
.name
);
1537 QLIST_INSERT_HEAD(&s
->devices_with_notifiers
, sdev
, next
);
1538 } else if (new == IOMMU_NOTIFIER_NONE
) {
1539 trace_smmuv3_notify_flag_del(iommu
->parent_obj
.name
);
1540 QLIST_REMOVE(sdev
, next
);
1545 static void smmuv3_iommu_memory_region_class_init(ObjectClass
*klass
,
1548 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
1550 imrc
->translate
= smmuv3_translate
;
1551 imrc
->notify_flag_changed
= smmuv3_notify_flag_changed
;
1554 static const TypeInfo smmuv3_type_info
= {
1555 .name
= TYPE_ARM_SMMUV3
,
1556 .parent
= TYPE_ARM_SMMU
,
1557 .instance_size
= sizeof(SMMUv3State
),
1558 .instance_init
= smmuv3_instance_init
,
1559 .class_size
= sizeof(SMMUv3Class
),
1560 .class_init
= smmuv3_class_init
,
1563 static const TypeInfo smmuv3_iommu_memory_region_info
= {
1564 .parent
= TYPE_IOMMU_MEMORY_REGION
,
1565 .name
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
,
1566 .class_init
= smmuv3_iommu_memory_region_class_init
,
1569 static void smmuv3_register_types(void)
1571 type_register(&smmuv3_type_info
);
1572 type_register(&smmuv3_iommu_memory_region_info
);
1575 type_init(smmuv3_register_types
)