target/openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "exception.h"
  26 #include "sysemu/sysemu.h"
  27
  28 #define TO_SPR(group, number) (((group) << 11) + (number))
  29
  30 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
  31 {
  32 #ifndef CONFIG_USER_ONLY
  33     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  34     CPUState *cs = CPU(cpu);
  35     int idx;
  36
  37     switch (spr) {
  38     case TO_SPR(0, 0): /* VR */
  39         env->vr = rb;
  40         break;
  41
  42     case TO_SPR(0, 11): /* EVBAR */
  43         env->evbar = rb;
  44         break;
  45
  46     case TO_SPR(0, 16): /* NPC */
  47         cpu_restore_state(cs, GETPC(), true);
  48         /* ??? Mirror or1ksim in not trashing delayed branch state
  49            when "jumping" to the current instruction.  */
  50         if (env->pc != rb) {
  51             env->pc = rb;
  52             env->dflag = 0;
  53             cpu_loop_exit(cs);
  54         }
  55         break;
  56
  57     case TO_SPR(0, 17): /* SR */
  58         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  59             (rb & (SR_IME | SR_DME | SR_SM))) {
  60             tlb_flush(cs);
  61         }
  62         cpu_set_sr(env, rb);
  63         break;
  64
  65     case TO_SPR(0, 18): /* PPC */
  66         env->ppc = rb;
  67         break;
  68
  69     case TO_SPR(0, 32): /* EPCR */
  70         env->epcr = rb;
  71         break;
  72
  73     case TO_SPR(0, 48): /* EEAR */
  74         env->eear = rb;
  75         break;
  76
  77     case TO_SPR(0, 64): /* ESR */
  78         env->esr = rb;
  79         break;
  80
  81     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
  82         idx = (spr - 1024);
  83         env->shadow_gpr[idx / 32][idx % 32] = rb;
  84         break;
  85
  86     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
  87         idx = spr - TO_SPR(1, 512);
  88         if (!(rb & 1)) {
  89             tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK);
  90         }
  91         env->tlb.dtlb[idx].mr = rb;
  92         break;
  93
  94     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
  95         idx = spr - TO_SPR(1, 640);
  96         env->tlb.dtlb[idx].tr = rb;
  97         break;
  98     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
  99     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 100     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 101     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 102     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 103     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 104         break;
 105     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 106         idx = spr - TO_SPR(2, 512);
 107         if (!(rb & 1)) {
 108             tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK);
 109         }
 110         env->tlb.itlb[idx].mr = rb;
 111         break;
 112
 113     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 114         idx = spr - TO_SPR(2, 640);
 115         env->tlb.itlb[idx].tr = rb;
 116         break;
 117     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 118     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 119     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 120     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 121     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 122     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 123         break;
 124     case TO_SPR(5, 1):  /* MACLO */
 125         env->mac = deposit64(env->mac, 0, 32, rb);
 126         break;
 127     case TO_SPR(5, 2):  /* MACHI */
 128         env->mac = deposit64(env->mac, 32, 32, rb);
 129         break;
 130     case TO_SPR(8, 0):  /* PMR */
 131         env->pmr = rb;
 132         if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
 133             cpu_restore_state(cs, GETPC(), true);
 134             env->pc += 4;
 135             cs->halted = 1;
 136             raise_exception(cpu, EXCP_HALTED);
 137         }
 138         break;
 139     case TO_SPR(9, 0):  /* PICMR */
 140         env->picmr |= rb;
 141         break;
 142     case TO_SPR(9, 2):  /* PICSR */
 143         env->picsr &= ~rb;
 144         break;
 145     case TO_SPR(10, 0): /* TTMR */
 146         {
 147             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 148                 switch (rb & TTMR_M) {
 149                 case TIMER_NONE:
 150                     cpu_openrisc_count_stop(cpu);
 151                     break;
 152                 case TIMER_INTR:
 153                 case TIMER_SHOT:
 154                 case TIMER_CONT:
 155                     cpu_openrisc_count_start(cpu);
 156                     break;
 157                 default:
 158                     break;
 159                 }
 160             }
 161
 162             int ip = env->ttmr & TTMR_IP;
 163
 164             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 165                 env->ttmr = (rb & ~TTMR_IP) | ip;
 166             } else {    /* Clear IP bit.  */
 167                 env->ttmr = rb & ~TTMR_IP;
 168                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 169             }
 170
 171             cpu_openrisc_timer_update(cpu);
 172         }
 173         break;
 174
 175     case TO_SPR(10, 1): /* TTCR */
 176         cpu_openrisc_count_set(cpu, rb);
 177         if (env->ttmr & TIMER_NONE) {
 178             return;
 179         }
 180         cpu_openrisc_timer_update(cpu);
 181         break;
 182     default:
 183         break;
 184     }
 185 #endif
 186 }
 187
 188 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
 189                            target_ulong spr)
 190 {
 191 #ifndef CONFIG_USER_ONLY
 192     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 193     CPUState *cs = CPU(cpu);
 194     int idx;
 195
 196     switch (spr) {
 197     case TO_SPR(0, 0): /* VR */
 198         return env->vr & SPR_VR;
 199
 200     case TO_SPR(0, 1): /* UPR */
 201         return env->upr;    /* TT, DM, IM, UP present */
 202
 203     case TO_SPR(0, 2): /* CPUCFGR */
 204         return env->cpucfgr;
 205
 206     case TO_SPR(0, 3): /* DMMUCFGR */
 207         return env->dmmucfgr;    /* 1Way, 64 entries */
 208
 209     case TO_SPR(0, 4): /* IMMUCFGR */
 210         return env->immucfgr;
 211
 212     case TO_SPR(0, 11): /* EVBAR */
 213         return env->evbar;
 214
 215     case TO_SPR(0, 16): /* NPC (equals PC) */
 216         cpu_restore_state(cs, GETPC(), false);
 217         return env->pc;
 218
 219     case TO_SPR(0, 17): /* SR */
 220         return cpu_get_sr(env);
 221
 222     case TO_SPR(0, 18): /* PPC */
 223         cpu_restore_state(cs, GETPC(), false);
 224         return env->ppc;
 225
 226     case TO_SPR(0, 32): /* EPCR */
 227         return env->epcr;
 228
 229     case TO_SPR(0, 48): /* EEAR */
 230         return env->eear;
 231
 232     case TO_SPR(0, 64): /* ESR */
 233         return env->esr;
 234
 235     case TO_SPR(0, 128): /* COREID */
 236         return cpu->parent_obj.cpu_index;
 237
 238     case TO_SPR(0, 129): /* NUMCORES */
 239         return max_cpus;
 240
 241     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
 242         idx = (spr - 1024);
 243         return env->shadow_gpr[idx / 32][idx % 32];
 244
 245     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 246         idx = spr - TO_SPR(1, 512);
 247         return env->tlb.dtlb[idx].mr;
 248
 249     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 250         idx = spr - TO_SPR(1, 640);
 251         return env->tlb.dtlb[idx].tr;
 252
 253     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 254     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 255     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 256     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 257     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 258     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 259         break;
 260
 261     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 262         idx = spr - TO_SPR(2, 512);
 263         return env->tlb.itlb[idx].mr;
 264
 265     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 266         idx = spr - TO_SPR(2, 640);
 267         return env->tlb.itlb[idx].tr;
 268
 269     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 270     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 271     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 272     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 273     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 274     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 275         break;
 276
 277     case TO_SPR(5, 1):  /* MACLO */
 278         return (uint32_t)env->mac;
 279         break;
 280     case TO_SPR(5, 2):  /* MACHI */
 281         return env->mac >> 32;
 282         break;
 283
 284     case TO_SPR(8, 0):  /* PMR */
 285         return env->pmr;
 286
 287     case TO_SPR(9, 0):  /* PICMR */
 288         return env->picmr;
 289
 290     case TO_SPR(9, 2):  /* PICSR */
 291         return env->picsr;
 292
 293     case TO_SPR(10, 0): /* TTMR */
 294         return env->ttmr;
 295
 296     case TO_SPR(10, 1): /* TTCR */
 297         cpu_openrisc_count_update(cpu);
 298         return cpu_openrisc_count_get(cpu);
 299
 300     default:
 301         break;
 302     }
 303 #endif
 304
 305     /* for rd is passed in, if rd unchanged, just keep it back.  */
 306     return rd;
 307 }