include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef XICS_H
  29 #define XICS_H
  30
  31 #include "hw/qdev.h"
  32 #include "target/ppc/cpu-qom.h"
  33
  34 #define XICS_IPI        0x2
  35 #define XICS_BUID       0x1
  36 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  37
  38 /*
  39  * We currently only support one BUID which is our interrupt base
  40  * (the kernel implementation supports more but we don't exploit
  41  *  that yet)
  42  */
  43 typedef struct ICPStateClass ICPStateClass;
  44 typedef struct ICPState ICPState;
  45 typedef struct PnvICPState PnvICPState;
  46 typedef struct ICSStateClass ICSStateClass;
  47 typedef struct ICSState ICSState;
  48 typedef struct ICSIRQState ICSIRQState;
  49 typedef struct XICSFabric XICSFabric;
  50
  51 #define TYPE_ICP "icp"
  52 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  53
  54 #define TYPE_KVM_ICP "icp-kvm"
  55 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
  56
  57 #define TYPE_PNV_ICP "pnv-icp"
  58 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
  59
  60 #define ICP_CLASS(klass) \
  61      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  62 #define ICP_GET_CLASS(obj) \
  63      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
  64
  65 struct ICPStateClass {
  66     DeviceClass parent_class;
  67
  68     void (*realize)(ICPState *icp, Error **errp);
  69     void (*pre_save)(ICPState *icp);
  70     int (*post_load)(ICPState *icp, int version_id);
  71     void (*reset)(ICPState *icp);
  72     void (*synchronize_state)(ICPState *icp);
  73 };
  74
  75 struct ICPState {
  76     /*< private >*/
  77     DeviceState parent_obj;
  78     /*< public >*/
  79     CPUState *cs;
  80     ICSState *xirr_owner;
  81     uint32_t xirr;
  82     uint8_t pending_priority;
  83     uint8_t mfrr;
  84     qemu_irq output;
  85
  86     XICSFabric *xics;
  87 };
  88
  89 #define ICP_PROP_XICS "xics"
  90 #define ICP_PROP_CPU "cpu"
  91
  92 struct PnvICPState {
  93     ICPState parent_obj;
  94
  95     MemoryRegion mmio;
  96     uint32_t links[3];
  97 };
  98
  99 #define TYPE_ICS_BASE "ics-base"
 100 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
 101
 102 /* Retain ics for sPAPR for migration from existing sPAPR guests */
 103 #define TYPE_ICS_SIMPLE "ics"
 104 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
 105
 106 #define TYPE_ICS_KVM "icskvm"
 107 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
 108
 109 #define ICS_BASE_CLASS(klass) \
 110      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
 111 #define ICS_BASE_GET_CLASS(obj) \
 112      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
 113
 114 struct ICSStateClass {
 115     DeviceClass parent_class;
 116
 117     void (*realize)(ICSState *s, Error **errp);
 118     void (*pre_save)(ICSState *s);
 119     int (*post_load)(ICSState *s, int version_id);
 120     void (*reject)(ICSState *s, uint32_t irq);
 121     void (*resend)(ICSState *s);
 122     void (*eoi)(ICSState *s, uint32_t irq);
 123     void (*synchronize_state)(ICSState *s);
 124 };
 125
 126 struct ICSState {
 127     /*< private >*/
 128     DeviceState parent_obj;
 129     /*< public >*/
 130     uint32_t nr_irqs;
 131     uint32_t offset;
 132     qemu_irq *qirqs;
 133     ICSIRQState *irqs;
 134     XICSFabric *xics;
 135 };
 136
 137 #define ICS_PROP_XICS "xics"
 138
 139 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 140 {
 141     return (ics->offset != 0) && (nr >= ics->offset)
 142         && (nr < (ics->offset + ics->nr_irqs));
 143 }
 144
 145 struct ICSIRQState {
 146     uint32_t server;
 147     uint8_t priority;
 148     uint8_t saved_priority;
 149 #define XICS_STATUS_ASSERTED           0x1
 150 #define XICS_STATUS_SENT               0x2
 151 #define XICS_STATUS_REJECTED           0x4
 152 #define XICS_STATUS_MASKED_PENDING     0x8
 153 #define XICS_STATUS_PRESENTED          0x10
 154 #define XICS_STATUS_QUEUED             0x20
 155     uint8_t status;
 156 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 157 #define XICS_FLAGS_IRQ_LSI             0x1
 158 #define XICS_FLAGS_IRQ_MSI             0x2
 159 #define XICS_FLAGS_IRQ_MASK            0x3
 160     uint8_t flags;
 161 };
 162
 163 struct XICSFabric {
 164     Object parent;
 165 };
 166
 167 #define TYPE_XICS_FABRIC "xics-fabric"
 168 #define XICS_FABRIC(obj)                                     \
 169     OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
 170 #define XICS_FABRIC_CLASS(klass)                                     \
 171     OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
 172 #define XICS_FABRIC_GET_CLASS(obj)                                   \
 173     OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
 174
 175 typedef struct XICSFabricClass {
 176     InterfaceClass parent;
 177     ICSState *(*ics_get)(XICSFabric *xi, int irq);
 178     void (*ics_resend)(XICSFabric *xi);
 179     ICPState *(*icp_get)(XICSFabric *xi, int server);
 180 } XICSFabricClass;
 181
 182 #define XICS_IRQS_SPAPR               1024
 183
 184 void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle);
 185
 186 ICPState *xics_icp_get(XICSFabric *xi, int server);
 187
 188 /* Internal XICS interfaces */
 189 void icp_set_cppr(ICPState *icp, uint8_t cppr);
 190 void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
 191 uint32_t icp_accept(ICPState *ss);
 192 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 193 void icp_eoi(ICPState *icp, uint32_t xirr);
 194
 195 void ics_simple_write_xive(ICSState *ics, int nr, int server,
 196                            uint8_t priority, uint8_t saved_priority);
 197
 198 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 199 void icp_pic_print_info(ICPState *icp, Monitor *mon);
 200 void ics_pic_print_info(ICSState *ics, Monitor *mon);
 201
 202 void ics_resend(ICSState *ics);
 203 void icp_resend(ICPState *ss);
 204
 205 typedef struct sPAPRMachineState sPAPRMachineState;
 206
 207 int xics_kvm_init(sPAPRMachineState *spapr, Error **errp);
 208 void xics_spapr_init(sPAPRMachineState *spapr);
 209
 210 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
 211                    Error **errp);
 212
 213 #endif /* XICS_H */