Remove empty dummy file "loaders.cache" during uninstall (bug #1766841)
[qemu/ar7.git] / include / hw / pci / pci.h
bloba9c3ee5aa2824cca6be0cc1570f66fee53ede049
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
4 #include "hw/qdev.h"
5 #include "exec/memory.h"
6 #include "sysemu/dma.h"
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
11 #include "hw/pci/pcie.h"
13 extern bool pci_available;
15 /* PCI bus */
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20 #define PCI_FUNC(devfn) ((devfn) & 0x07)
21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22 #define PCI_BUS_MAX 256
23 #define PCI_DEVFN_MAX 256
24 #define PCI_SLOT_MAX 32
25 #define PCI_FUNC_MAX 8
27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
28 #include "hw/pci/pci_ids.h"
30 /* QEMU-specific Vendor and Device ID definitions */
32 /* IBM (0x1014) */
33 #define PCI_DEVICE_ID_IBM_440GX 0x027f
34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
36 /* Hitachi (0x1054) */
37 #define PCI_VENDOR_ID_HITACHI 0x1054
38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
40 /* Apple (0x106b) */
41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
47 /* Realtek (0x10ec) */
48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
50 /* Xilinx (0x10ee) */
51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
53 /* Marvell (0x11ab) */
54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
56 /* QEMU/Bochs VGA (0x1234) */
57 #define PCI_VENDOR_ID_QEMU 0x1234
58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
60 /* VMWare (0x15ad) */
61 #define PCI_VENDOR_ID_VMWARE 0x15ad
62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
70 /* Intel (0x8086) */
71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72 #define PCI_DEVICE_ID_INTEL_82557 0x1229
73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78 #define PCI_SUBDEVICE_ID_QEMU 0x1100
80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
89 #define PCI_VENDOR_ID_REDHAT 0x1b36
90 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
91 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
92 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
93 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
94 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
95 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
96 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
97 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
98 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
99 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
100 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
101 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
102 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
103 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
104 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
106 #define FMT_PCIBUS PRIx64
108 typedef uint64_t pcibus_t;
110 struct PCIHostDeviceAddress {
111 unsigned int domain;
112 unsigned int bus;
113 unsigned int slot;
114 unsigned int function;
117 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
118 uint32_t address, uint32_t data, int len);
119 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
120 uint32_t address, int len);
121 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
122 pcibus_t addr, pcibus_t size, int type);
123 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
125 typedef struct PCIIORegion {
126 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
127 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
128 pcibus_t size;
129 uint8_t type;
130 MemoryRegion *memory;
131 MemoryRegion *address_space;
132 } PCIIORegion;
134 #define PCI_ROM_SLOT 6
135 #define PCI_NUM_REGIONS 7
137 enum {
138 QEMU_PCI_VGA_MEM,
139 QEMU_PCI_VGA_IO_LO,
140 QEMU_PCI_VGA_IO_HI,
141 QEMU_PCI_VGA_NUM_REGIONS,
144 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
145 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
146 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
147 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
148 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
149 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
151 #include "hw/pci/pci_regs.h"
153 /* PCI HEADER_TYPE */
154 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
156 /* Size of the standard PCI config header */
157 #define PCI_CONFIG_HEADER_SIZE 0x40
158 /* Size of the standard PCI config space */
159 #define PCI_CONFIG_SPACE_SIZE 0x100
160 /* Size of the standard PCIe config space: 4KB */
161 #define PCIE_CONFIG_SPACE_SIZE 0x1000
163 #define PCI_NUM_PINS 4 /* A-D */
165 /* Bits in cap_present field. */
166 enum {
167 QEMU_PCI_CAP_MSI = 0x1,
168 QEMU_PCI_CAP_MSIX = 0x2,
169 QEMU_PCI_CAP_EXPRESS = 0x4,
171 /* multifunction capable device */
172 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
173 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
175 /* command register SERR bit enabled */
176 #define QEMU_PCI_CAP_SERR_BITNR 4
177 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
178 /* Standard hot plug controller. */
179 #define QEMU_PCI_SHPC_BITNR 5
180 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
181 #define QEMU_PCI_SLOTID_BITNR 6
182 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
183 /* PCI Express capability - Power Controller Present */
184 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
185 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
186 /* Link active status in endpoint capability is always set */
187 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
188 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
189 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
190 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
193 #define TYPE_PCI_DEVICE "pci-device"
194 #define PCI_DEVICE(obj) \
195 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
196 #define PCI_DEVICE_CLASS(klass) \
197 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
198 #define PCI_DEVICE_GET_CLASS(obj) \
199 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
201 /* Implemented by devices that can be plugged on PCI Express buses */
202 #define INTERFACE_PCIE_DEVICE "pci-express-device"
204 /* Implemented by devices that can be plugged on Conventional PCI buses */
205 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
207 typedef struct PCIINTxRoute {
208 enum {
209 PCI_INTX_ENABLED,
210 PCI_INTX_INVERTED,
211 PCI_INTX_DISABLED,
212 } mode;
213 int irq;
214 } PCIINTxRoute;
216 typedef struct PCIDeviceClass {
217 DeviceClass parent_class;
219 void (*realize)(PCIDevice *dev, Error **errp);
220 PCIUnregisterFunc *exit;
221 PCIConfigReadFunc *config_read;
222 PCIConfigWriteFunc *config_write;
224 uint16_t vendor_id;
225 uint16_t device_id;
226 uint8_t revision;
227 uint16_t class_id;
228 uint16_t subsystem_vendor_id; /* only for header type = 0 */
229 uint16_t subsystem_id; /* only for header type = 0 */
232 * pci-to-pci bridge or normal device.
233 * This doesn't mean pci host switch.
234 * When card bus bridge is supported, this would be enhanced.
236 int is_bridge;
238 /* rom bar */
239 const char *romfile;
240 } PCIDeviceClass;
242 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
243 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
244 MSIMessage msg);
245 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
246 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
247 unsigned int vector_start,
248 unsigned int vector_end);
250 enum PCIReqIDType {
251 PCI_REQ_ID_INVALID = 0,
252 PCI_REQ_ID_BDF,
253 PCI_REQ_ID_SECONDARY_BUS,
254 PCI_REQ_ID_MAX,
256 typedef enum PCIReqIDType PCIReqIDType;
258 struct PCIReqIDCache {
259 PCIDevice *dev;
260 PCIReqIDType type;
262 typedef struct PCIReqIDCache PCIReqIDCache;
264 struct PCIDevice {
265 DeviceState qdev;
267 /* PCI config space */
268 uint8_t *config;
270 /* Used to enable config checks on load. Note that writable bits are
271 * never checked even if set in cmask. */
272 uint8_t *cmask;
274 /* Used to implement R/W bytes */
275 uint8_t *wmask;
277 /* Used to implement RW1C(Write 1 to Clear) bytes */
278 uint8_t *w1cmask;
280 /* Used to allocate config space for capabilities. */
281 uint8_t *used;
283 /* the following fields are read only */
284 int32_t devfn;
285 /* Cached device to fetch requester ID from, to avoid the PCI
286 * tree walking every time we invoke PCI request (e.g.,
287 * MSI). For conventional PCI root complex, this field is
288 * meaningless. */
289 PCIReqIDCache requester_id_cache;
290 char name[64];
291 PCIIORegion io_regions[PCI_NUM_REGIONS];
292 AddressSpace bus_master_as;
293 MemoryRegion bus_master_container_region;
294 MemoryRegion bus_master_enable_region;
296 /* do not access the following fields */
297 PCIConfigReadFunc *config_read;
298 PCIConfigWriteFunc *config_write;
300 /* Legacy PCI VGA regions */
301 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
302 bool has_vga;
304 /* Current IRQ levels. Used internally by the generic PCI code. */
305 uint8_t irq_state;
307 /* Capability bits */
308 uint32_t cap_present;
310 /* Offset of MSI-X capability in config space */
311 uint8_t msix_cap;
313 /* MSI-X entries */
314 int msix_entries_nr;
316 /* Space to store MSIX table & pending bit array */
317 uint8_t *msix_table;
318 uint8_t *msix_pba;
319 /* MemoryRegion container for msix exclusive BAR setup */
320 MemoryRegion msix_exclusive_bar;
321 /* Memory Regions for MSIX table and pending bit entries. */
322 MemoryRegion msix_table_mmio;
323 MemoryRegion msix_pba_mmio;
324 /* Reference-count for entries actually in use by driver. */
325 unsigned *msix_entry_used;
326 /* MSIX function mask set or MSIX disabled */
327 bool msix_function_masked;
328 /* Version id needed for VMState */
329 int32_t version_id;
331 /* Offset of MSI capability in config space */
332 uint8_t msi_cap;
334 /* PCI Express */
335 PCIExpressDevice exp;
337 /* SHPC */
338 SHPCDevice *shpc;
340 /* Location of option rom */
341 char *romfile;
342 bool has_rom;
343 MemoryRegion rom;
344 uint32_t rom_bar;
346 /* INTx routing notifier */
347 PCIINTxRoutingNotifier intx_routing_notifier;
349 /* MSI-X notifiers */
350 MSIVectorUseNotifier msix_vector_use_notifier;
351 MSIVectorReleaseNotifier msix_vector_release_notifier;
352 MSIVectorPollNotifier msix_vector_poll_notifier;
355 void pci_register_bar(PCIDevice *pci_dev, int region_num,
356 uint8_t attr, MemoryRegion *memory);
357 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
358 MemoryRegion *io_lo, MemoryRegion *io_hi);
359 void pci_unregister_vga(PCIDevice *pci_dev);
360 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
362 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
363 uint8_t offset, uint8_t size,
364 Error **errp);
366 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
368 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
371 uint32_t pci_default_read_config(PCIDevice *d,
372 uint32_t address, int len);
373 void pci_default_write_config(PCIDevice *d,
374 uint32_t address, uint32_t val, int len);
375 void pci_device_save(PCIDevice *s, QEMUFile *f);
376 int pci_device_load(PCIDevice *s, QEMUFile *f);
377 MemoryRegion *pci_address_space(PCIDevice *dev);
378 MemoryRegion *pci_address_space_io(PCIDevice *dev);
381 * Should not normally be used by devices. For use by sPAPR target
382 * where QEMU emulates firmware.
384 int pci_bar(PCIDevice *d, int reg);
386 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
387 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
388 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
390 #define TYPE_PCI_BUS "PCI"
391 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
392 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
393 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
394 #define TYPE_PCIE_BUS "PCIE"
396 bool pci_bus_is_express(PCIBus *bus);
397 bool pci_bus_is_root(PCIBus *bus);
398 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
399 const char *name,
400 MemoryRegion *address_space_mem,
401 MemoryRegion *address_space_io,
402 uint8_t devfn_min, const char *typename);
403 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename);
407 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
408 void *irq_opaque, int nirq);
409 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
410 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
411 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
412 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
413 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
414 void *irq_opaque,
415 MemoryRegion *address_space_mem,
416 MemoryRegion *address_space_io,
417 uint8_t devfn_min, int nirq,
418 const char *typename);
419 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
420 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
421 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
422 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
423 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
424 PCIINTxRoutingNotifier notifier);
425 void pci_device_reset(PCIDevice *dev);
427 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
428 const char *default_model,
429 const char *default_devaddr);
431 PCIDevice *pci_vga_init(PCIBus *bus);
433 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
435 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
437 int pci_bus_num(PCIBus *s);
438 static inline int pci_dev_bus_num(const PCIDevice *dev)
440 return pci_bus_num(pci_get_bus(dev));
443 int pci_bus_numa_node(PCIBus *bus);
444 void pci_for_each_device(PCIBus *bus, int bus_num,
445 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
446 void *opaque);
447 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
448 void (*fn)(PCIBus *bus, PCIDevice *d,
449 void *opaque),
450 void *opaque);
451 void pci_for_each_bus_depth_first(PCIBus *bus,
452 void *(*begin)(PCIBus *bus, void *parent_state),
453 void (*end)(PCIBus *bus, void *state),
454 void *parent_state);
455 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
457 /* Use this wrapper when specific scan order is not required. */
458 static inline
459 void pci_for_each_bus(PCIBus *bus,
460 void (*fn)(PCIBus *bus, void *opaque),
461 void *opaque)
463 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
466 PCIBus *pci_device_root_bus(const PCIDevice *d);
467 const char *pci_root_bus_path(PCIDevice *dev);
468 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
469 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
470 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
472 void pci_device_deassert_intx(PCIDevice *dev);
474 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
476 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
477 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
479 static inline void
480 pci_set_byte(uint8_t *config, uint8_t val)
482 *config = val;
485 static inline uint8_t
486 pci_get_byte(const uint8_t *config)
488 return *config;
491 static inline void
492 pci_set_word(uint8_t *config, uint16_t val)
494 stw_le_p(config, val);
497 static inline uint16_t
498 pci_get_word(const uint8_t *config)
500 return lduw_le_p(config);
503 static inline void
504 pci_set_long(uint8_t *config, uint32_t val)
506 stl_le_p(config, val);
509 static inline uint32_t
510 pci_get_long(const uint8_t *config)
512 return ldl_le_p(config);
516 * PCI capabilities and/or their fields
517 * are generally DWORD aligned only so
518 * mechanism used by pci_set/get_quad()
519 * must be tolerant to unaligned pointers
522 static inline void
523 pci_set_quad(uint8_t *config, uint64_t val)
525 stq_le_p(config, val);
528 static inline uint64_t
529 pci_get_quad(const uint8_t *config)
531 return ldq_le_p(config);
534 static inline void
535 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
537 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
540 static inline void
541 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
543 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
546 static inline void
547 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
549 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
552 static inline void
553 pci_config_set_class(uint8_t *pci_config, uint16_t val)
555 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
558 static inline void
559 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
561 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
564 static inline void
565 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
567 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
571 * helper functions to do bit mask operation on configuration space.
572 * Just to set bit, use test-and-set and discard returned value.
573 * Just to clear bit, use test-and-clear and discard returned value.
574 * NOTE: They aren't atomic.
576 static inline uint8_t
577 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
579 uint8_t val = pci_get_byte(config);
580 pci_set_byte(config, val & ~mask);
581 return val & mask;
584 static inline uint8_t
585 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
587 uint8_t val = pci_get_byte(config);
588 pci_set_byte(config, val | mask);
589 return val & mask;
592 static inline uint16_t
593 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
595 uint16_t val = pci_get_word(config);
596 pci_set_word(config, val & ~mask);
597 return val & mask;
600 static inline uint16_t
601 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
603 uint16_t val = pci_get_word(config);
604 pci_set_word(config, val | mask);
605 return val & mask;
608 static inline uint32_t
609 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
611 uint32_t val = pci_get_long(config);
612 pci_set_long(config, val & ~mask);
613 return val & mask;
616 static inline uint32_t
617 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
619 uint32_t val = pci_get_long(config);
620 pci_set_long(config, val | mask);
621 return val & mask;
624 static inline uint64_t
625 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
627 uint64_t val = pci_get_quad(config);
628 pci_set_quad(config, val & ~mask);
629 return val & mask;
632 static inline uint64_t
633 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
635 uint64_t val = pci_get_quad(config);
636 pci_set_quad(config, val | mask);
637 return val & mask;
640 /* Access a register specified by a mask */
641 static inline void
642 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
644 uint8_t val = pci_get_byte(config);
645 uint8_t rval = reg << ctz32(mask);
646 pci_set_byte(config, (~mask & val) | (mask & rval));
649 static inline uint8_t
650 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
652 uint8_t val = pci_get_byte(config);
653 return (val & mask) >> ctz32(mask);
656 static inline void
657 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
659 uint16_t val = pci_get_word(config);
660 uint16_t rval = reg << ctz32(mask);
661 pci_set_word(config, (~mask & val) | (mask & rval));
664 static inline uint16_t
665 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
667 uint16_t val = pci_get_word(config);
668 return (val & mask) >> ctz32(mask);
671 static inline void
672 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
674 uint32_t val = pci_get_long(config);
675 uint32_t rval = reg << ctz32(mask);
676 pci_set_long(config, (~mask & val) | (mask & rval));
679 static inline uint32_t
680 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
682 uint32_t val = pci_get_long(config);
683 return (val & mask) >> ctz32(mask);
686 static inline void
687 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
689 uint64_t val = pci_get_quad(config);
690 uint64_t rval = reg << ctz32(mask);
691 pci_set_quad(config, (~mask & val) | (mask & rval));
694 static inline uint64_t
695 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
697 uint64_t val = pci_get_quad(config);
698 return (val & mask) >> ctz32(mask);
701 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
702 const char *name);
703 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
704 bool multifunction,
705 const char *name);
706 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
707 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
709 void lsi53c895a_create(PCIBus *bus);
710 void lsi53c810_create(PCIBus *bus, int devfn);
712 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
713 void pci_set_irq(PCIDevice *pci_dev, int level);
715 static inline void pci_irq_assert(PCIDevice *pci_dev)
717 pci_set_irq(pci_dev, 1);
720 static inline void pci_irq_deassert(PCIDevice *pci_dev)
722 pci_set_irq(pci_dev, 0);
726 * FIXME: PCI does not work this way.
727 * All the callers to this method should be fixed.
729 static inline void pci_irq_pulse(PCIDevice *pci_dev)
731 pci_irq_assert(pci_dev);
732 pci_irq_deassert(pci_dev);
735 static inline int pci_is_express(const PCIDevice *d)
737 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
740 static inline uint32_t pci_config_size(const PCIDevice *d)
742 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
745 static inline uint16_t pci_get_bdf(PCIDevice *dev)
747 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
750 uint16_t pci_requester_id(PCIDevice *dev);
752 /* DMA access functions */
753 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
755 return &dev->bus_master_as;
758 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
759 void *buf, dma_addr_t len, DMADirection dir)
761 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
762 return 0;
765 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
766 void *buf, dma_addr_t len)
768 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
771 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
772 const void *buf, dma_addr_t len)
774 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
777 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
778 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
779 dma_addr_t addr) \
781 return ld##_l##_dma(pci_get_address_space(dev), addr); \
783 static inline void st##_s##_pci_dma(PCIDevice *dev, \
784 dma_addr_t addr, uint##_bits##_t val) \
786 st##_s##_dma(pci_get_address_space(dev), addr, val); \
789 PCI_DMA_DEFINE_LDST(ub, b, 8);
790 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
791 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
792 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
793 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
794 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
795 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
797 #undef PCI_DMA_DEFINE_LDST
799 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
800 dma_addr_t *plen, DMADirection dir)
802 void *buf;
804 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
805 return buf;
808 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
809 DMADirection dir, dma_addr_t access_len)
811 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
814 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
815 int alloc_hint)
817 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
820 extern const VMStateDescription vmstate_pci_device;
822 #define VMSTATE_PCI_DEVICE(_field, _state) { \
823 .name = (stringify(_field)), \
824 .size = sizeof(PCIDevice), \
825 .vmsd = &vmstate_pci_device, \
826 .flags = VMS_STRUCT, \
827 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
830 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
831 .name = (stringify(_field)), \
832 .size = sizeof(PCIDevice), \
833 .vmsd = &vmstate_pci_device, \
834 .flags = VMS_STRUCT|VMS_POINTER, \
835 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
838 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
840 #endif