include/hw/acpi/tpm.h

   1 /*
   2  * tpm.h - TPM ACPI definitions
   3  *
   4  * Copyright (C) 2014 IBM Corporation
   5  *
   6  * Authors:
   7  *  Stefan Berger <stefanb@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  * Implementation of the TIS interface according to specs found at
  13  * http://www.trustedcomputinggroup.org
  14  *
  15  */
  16 #ifndef HW_ACPI_TPM_H
  17 #define HW_ACPI_TPM_H
  18
  19 #include "hw/registerfields.h"
  20
  21 #define TPM_TIS_ADDR_BASE           0xFED40000
  22 #define TPM_TIS_ADDR_SIZE           0x5000
  23
  24 #define TPM_TIS_IRQ                 5
  25
  26 #define TPM_TIS_NUM_LOCALITIES      5     /* per spec */
  27 #define TPM_TIS_LOCALITY_SHIFT      12
  28
  29 /* tis registers */
  30 #define TPM_TIS_REG_ACCESS                0x00
  31 #define TPM_TIS_REG_INT_ENABLE            0x08
  32 #define TPM_TIS_REG_INT_VECTOR            0x0c
  33 #define TPM_TIS_REG_INT_STATUS            0x10
  34 #define TPM_TIS_REG_INTF_CAPABILITY       0x14
  35 #define TPM_TIS_REG_STS                   0x18
  36 #define TPM_TIS_REG_DATA_FIFO             0x24
  37 #define TPM_TIS_REG_INTERFACE_ID          0x30
  38 #define TPM_TIS_REG_DATA_XFIFO            0x80
  39 #define TPM_TIS_REG_DATA_XFIFO_END        0xbc
  40 #define TPM_TIS_REG_DID_VID               0xf00
  41 #define TPM_TIS_REG_RID                   0xf04
  42
  43 /* vendor-specific registers */
  44 #define TPM_TIS_REG_DEBUG                 0xf90
  45
  46 #define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */
  47 #define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */
  48 #define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */
  49 #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */
  50 #define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */
  51
  52 #define TPM_TIS_STS_VALID                 (1 << 7)
  53 #define TPM_TIS_STS_COMMAND_READY         (1 << 6)
  54 #define TPM_TIS_STS_TPM_GO                (1 << 5)
  55 #define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)
  56 #define TPM_TIS_STS_EXPECT                (1 << 3)
  57 #define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)
  58 #define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)
  59
  60 #define TPM_TIS_BURST_COUNT_SHIFT         8
  61 #define TPM_TIS_BURST_COUNT(X) \
  62     ((X) << TPM_TIS_BURST_COUNT_SHIFT)
  63
  64 #define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)
  65 #define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)
  66 #define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)
  67 #define TPM_TIS_ACCESS_SEIZE              (1 << 3)
  68 #define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)
  69 #define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)
  70 #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)
  71
  72 #define TPM_TIS_INT_ENABLED               (1 << 31)
  73 #define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)
  74 #define TPM_TIS_INT_STS_VALID             (1 << 1)
  75 #define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)
  76 #define TPM_TIS_INT_COMMAND_READY         (1 << 7)
  77
  78 #define TPM_TIS_INT_POLARITY_MASK         (3 << 3)
  79 #define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)
  80
  81 #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \
  82                                       TPM_TIS_INT_DATA_AVAILABLE   | \
  83                                       TPM_TIS_INT_STS_VALID | \
  84                                       TPM_TIS_INT_COMMAND_READY)
  85
  86 #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)
  87 #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)
  88 #define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)
  89 #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
  90 #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)
  91 #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */
  92 #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \
  93     (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
  94      TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
  95      TPM_TIS_CAP_DATA_TRANSFER_64B | \
  96      TPM_TIS_CAP_INTERFACE_VERSION1_3 | \
  97      TPM_TIS_INTERRUPTS_SUPPORTED)
  98
  99 #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \
 100     (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
 101      TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
 102      TPM_TIS_CAP_DATA_TRANSFER_64B | \
 103      TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \
 104      TPM_TIS_INTERRUPTS_SUPPORTED)
 105
 106 #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */
 107 #define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */
 108 #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */
 109 #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */
 110 #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */
 111 #define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */
 112
 113 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \
 114     (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \
 115      (~0u << 4)/* all of it is don't care */)
 116
 117 /* if backend was a TPM 2.0: */
 118 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \
 119     (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \
 120      TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \
 121      TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \
 122      TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)
 123
 124 #define TPM_TIS_TPM_DID       0x0001
 125 #define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM
 126 #define TPM_TIS_TPM_RID       0x0001
 127
 128 #define TPM_TIS_NO_DATA_BYTE  0xff
 129
 130
 131 REG32(CRB_LOC_STATE, 0x00)
 132   FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
 133   FIELD(CRB_LOC_STATE, locAssigned, 1, 1)
 134   FIELD(CRB_LOC_STATE, activeLocality, 2, 3)
 135   FIELD(CRB_LOC_STATE, reserved, 5, 2)
 136   FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1)
 137 REG32(CRB_LOC_CTRL, 0x08)
 138 REG32(CRB_LOC_STS, 0x0C)
 139   FIELD(CRB_LOC_STS, Granted, 0, 1)
 140   FIELD(CRB_LOC_STS, beenSeized, 1, 1)
 141 REG32(CRB_INTF_ID, 0x30)
 142   FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
 143   FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4)
 144   FIELD(CRB_INTF_ID, CapLocality, 8, 1)
 145   FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1)
 146   FIELD(CRB_INTF_ID, Reserved1, 10, 1)
 147   FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2)
 148   FIELD(CRB_INTF_ID, CapFIFO, 13, 1)
 149   FIELD(CRB_INTF_ID, CapCRB, 14, 1)
 150   FIELD(CRB_INTF_ID, CapIFRes, 15, 2)
 151   FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2)
 152   FIELD(CRB_INTF_ID, IntfSelLock, 19, 1)
 153   FIELD(CRB_INTF_ID, Reserved2, 20, 4)
 154   FIELD(CRB_INTF_ID, RID, 24, 8)
 155 REG32(CRB_INTF_ID2, 0x34)
 156   FIELD(CRB_INTF_ID2, VID, 0, 16)
 157   FIELD(CRB_INTF_ID2, DID, 16, 16)
 158 REG32(CRB_CTRL_EXT, 0x38)
 159 REG32(CRB_CTRL_REQ, 0x40)
 160 REG32(CRB_CTRL_STS, 0x44)
 161   FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
 162   FIELD(CRB_CTRL_STS, tpmIdle, 1, 1)
 163 REG32(CRB_CTRL_CANCEL, 0x48)
 164 REG32(CRB_CTRL_START, 0x4C)
 165 REG32(CRB_INT_ENABLED, 0x50)
 166 REG32(CRB_INT_STS, 0x54)
 167 REG32(CRB_CTRL_CMD_SIZE, 0x58)
 168 REG32(CRB_CTRL_CMD_LADDR, 0x5C)
 169 REG32(CRB_CTRL_CMD_HADDR, 0x60)
 170 REG32(CRB_CTRL_RSP_SIZE, 0x64)
 171 REG32(CRB_CTRL_RSP_ADDR, 0x68)
 172 REG32(CRB_DATA_BUFFER, 0x80)
 173
 174 #define TPM_CRB_ADDR_BASE           0xFED40000
 175 #define TPM_CRB_ADDR_SIZE           0x1000
 176 #define TPM_CRB_ADDR_CTRL           (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
 177 #define TPM_CRB_R_MAX               R_CRB_DATA_BUFFER
 178
 179 #define TPM_LOG_AREA_MINIMUM_SIZE   (64 * 1024)
 180
 181 #define TPM_TCPA_ACPI_CLASS_CLIENT  0
 182 #define TPM_TCPA_ACPI_CLASS_SERVER  1
 183
 184 #define TPM2_ACPI_CLASS_CLIENT      0
 185 #define TPM2_ACPI_CLASS_SERVER      1
 186
 187 #define TPM2_START_METHOD_MMIO      6
 188 #define TPM2_START_METHOD_CRB       7
 189
 190 #endif /* HW_ACPI_TPM_H */