hw/rdma/vmw/pvrdma_main.c

   1 /*
   2  * QEMU paravirtual RDMA
   3  *
   4  * Copyright (C) 2018 Oracle
   5  * Copyright (C) 2018 Red Hat Inc
   6  *
   7  * Authors:
   8  *     Yuval Shaia <yuval.shaia@oracle.com>
   9  *     Marcel Apfelbaum <marcel@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  *
  14  */
  15
  16 #include "qemu/osdep.h"
  17 #include "qapi/error.h"
  18 #include "hw/hw.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_ids.h"
  21 #include "hw/pci/msi.h"
  22 #include "hw/pci/msix.h"
  23 #include "hw/qdev-core.h"
  24 #include "hw/qdev-properties.h"
  25 #include "cpu.h"
  26 #include "trace.h"
  27 #include "sysemu/sysemu.h"
  28
  29 #include "../rdma_rm.h"
  30 #include "../rdma_backend.h"
  31 #include "../rdma_utils.h"
  32
  33 #include <infiniband/verbs.h>
  34 #include "pvrdma.h"
  35 #include "standard-headers/rdma/vmw_pvrdma-abi.h"
  36 #include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
  37 #include "pvrdma_qp_ops.h"
  38
  39 static Property pvrdma_dev_properties[] = {
  40     DEFINE_PROP_STRING("netdev", PVRDMADev, backend_eth_device_name),
  41     DEFINE_PROP_STRING("ibdev", PVRDMADev, backend_device_name),
  42     DEFINE_PROP_UINT8("ibport", PVRDMADev, backend_port_num, 1),
  43     DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
  44                        MAX_MR_SIZE),
  45     DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
  46     DEFINE_PROP_INT32("dev-caps-max-sge", PVRDMADev, dev_attr.max_sge, MAX_SGE),
  47     DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
  48     DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
  49     DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
  50     DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
  51                       MAX_QP_RD_ATOM),
  52     DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
  53                       dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
  54     DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
  55     DEFINE_PROP_CHR("mad-chardev", PVRDMADev, mad_chr),
  56     DEFINE_PROP_END_OF_LIST(),
  57 };
  58
  59 static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
  60                           void *ring_state)
  61 {
  62     pvrdma_ring_free(ring);
  63     rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
  64 }
  65
  66 static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
  67                          const char *name, PCIDevice *pci_dev,
  68                          dma_addr_t dir_addr, uint32_t num_pages)
  69 {
  70     uint64_t *dir, *tbl;
  71     int rc = 0;
  72
  73     pr_dbg("Initializing device ring %s\n", name);
  74     pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)dir_addr);
  75     pr_dbg("num_pages=%d\n", num_pages);
  76     dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
  77     if (!dir) {
  78         pr_err("Failed to map to page directory\n");
  79         rc = -ENOMEM;
  80         goto out;
  81     }
  82     tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
  83     if (!tbl) {
  84         pr_err("Failed to map to page table\n");
  85         rc = -ENOMEM;
  86         goto out_free_dir;
  87     }
  88
  89     *ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
  90     if (!*ring_state) {
  91         pr_err("Failed to map to ring state\n");
  92         rc = -ENOMEM;
  93         goto out_free_tbl;
  94     }
  95     /* RX ring is the second */
  96     (*ring_state)++;
  97     rc = pvrdma_ring_init(ring, name, pci_dev,
  98                           (struct pvrdma_ring *)*ring_state,
  99                           (num_pages - 1) * TARGET_PAGE_SIZE /
 100                           sizeof(struct pvrdma_cqne),
 101                           sizeof(struct pvrdma_cqne),
 102                           (dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
 103     if (rc) {
 104         pr_err("Failed to initialize ring\n");
 105         rc = -ENOMEM;
 106         goto out_free_ring_state;
 107     }
 108
 109     goto out_free_tbl;
 110
 111 out_free_ring_state:
 112     rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
 113
 114 out_free_tbl:
 115     rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
 116
 117 out_free_dir:
 118     rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
 119
 120 out:
 121     return rc;
 122 }
 123
 124 static void free_dsr(PVRDMADev *dev)
 125 {
 126     PCIDevice *pci_dev = PCI_DEVICE(dev);
 127
 128     if (!dev->dsr_info.dsr) {
 129         return;
 130     }
 131
 132     free_dev_ring(pci_dev, &dev->dsr_info.async,
 133                   dev->dsr_info.async_ring_state);
 134
 135     free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
 136
 137     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
 138                          sizeof(union pvrdma_cmd_req));
 139
 140     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
 141                          sizeof(union pvrdma_cmd_resp));
 142
 143     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
 144                          sizeof(struct pvrdma_device_shared_region));
 145
 146     dev->dsr_info.dsr = NULL;
 147 }
 148
 149 static int load_dsr(PVRDMADev *dev)
 150 {
 151     int rc = 0;
 152     PCIDevice *pci_dev = PCI_DEVICE(dev);
 153     DSRInfo *dsr_info;
 154     struct pvrdma_device_shared_region *dsr;
 155
 156     free_dsr(dev);
 157
 158     /* Map to DSR */
 159     pr_dbg("dsr_dma=0x%llx\n", (long long unsigned int)dev->dsr_info.dma);
 160     dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
 161                               sizeof(struct pvrdma_device_shared_region));
 162     if (!dev->dsr_info.dsr) {
 163         pr_err("Failed to map to DSR\n");
 164         rc = -ENOMEM;
 165         goto out;
 166     }
 167
 168     /* Shortcuts */
 169     dsr_info = &dev->dsr_info;
 170     dsr = dsr_info->dsr;
 171
 172     /* Map to command slot */
 173     pr_dbg("cmd_dma=0x%llx\n", (long long unsigned int)dsr->cmd_slot_dma);
 174     dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
 175                                      sizeof(union pvrdma_cmd_req));
 176     if (!dsr_info->req) {
 177         pr_err("Failed to map to command slot address\n");
 178         rc = -ENOMEM;
 179         goto out_free_dsr;
 180     }
 181
 182     /* Map to response slot */
 183     pr_dbg("rsp_dma=0x%llx\n", (long long unsigned int)dsr->resp_slot_dma);
 184     dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
 185                                      sizeof(union pvrdma_cmd_resp));
 186     if (!dsr_info->rsp) {
 187         pr_err("Failed to map to response slot address\n");
 188         rc = -ENOMEM;
 189         goto out_free_req;
 190     }
 191
 192     /* Map to CQ notification ring */
 193     rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
 194                        pci_dev, dsr->cq_ring_pages.pdir_dma,
 195                        dsr->cq_ring_pages.num_pages);
 196     if (rc) {
 197         pr_err("Failed to map to initialize CQ ring\n");
 198         rc = -ENOMEM;
 199         goto out_free_rsp;
 200     }
 201
 202     /* Map to event notification ring */
 203     rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
 204                        "dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
 205                        dsr->async_ring_pages.num_pages);
 206     if (rc) {
 207         pr_err("Failed to map to initialize event ring\n");
 208         rc = -ENOMEM;
 209         goto out_free_rsp;
 210     }
 211
 212     goto out;
 213
 214 out_free_rsp:
 215     rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
 216
 217 out_free_req:
 218     rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
 219
 220 out_free_dsr:
 221     rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
 222                        sizeof(struct pvrdma_device_shared_region));
 223     dsr_info->dsr = NULL;
 224
 225 out:
 226     return rc;
 227 }
 228
 229 static void init_dsr_dev_caps(PVRDMADev *dev)
 230 {
 231     struct pvrdma_device_shared_region *dsr;
 232
 233     if (dev->dsr_info.dsr == NULL) {
 234         pr_err("Can't initialized DSR\n");
 235         return;
 236     }
 237
 238     dsr = dev->dsr_info.dsr;
 239
 240     dsr->caps.fw_ver = PVRDMA_FW_VERSION;
 241     pr_dbg("fw_ver=0x%" PRIx64 "\n", dsr->caps.fw_ver);
 242
 243     dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
 244     pr_dbg("mode=%d\n", dsr->caps.mode);
 245
 246     dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
 247     pr_dbg("gid_types=0x%x\n", dsr->caps.gid_types);
 248
 249     dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
 250     pr_dbg("max_uar=%d\n", dsr->caps.max_uar);
 251
 252     dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
 253     dsr->caps.max_qp = dev->dev_attr.max_qp;
 254     dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
 255     dsr->caps.max_sge = dev->dev_attr.max_sge;
 256     dsr->caps.max_cq = dev->dev_attr.max_cq;
 257     dsr->caps.max_cqe = dev->dev_attr.max_cqe;
 258     dsr->caps.max_mr = dev->dev_attr.max_mr;
 259     dsr->caps.max_pd = dev->dev_attr.max_pd;
 260     dsr->caps.max_ah = dev->dev_attr.max_ah;
 261
 262     dsr->caps.gid_tbl_len = MAX_GIDS;
 263     pr_dbg("gid_tbl_len=%d\n", dsr->caps.gid_tbl_len);
 264
 265     dsr->caps.sys_image_guid = 0;
 266     pr_dbg("sys_image_guid=%" PRIx64 "\n", dsr->caps.sys_image_guid);
 267
 268     dsr->caps.node_guid = dev->node_guid;
 269     pr_dbg("node_guid=%" PRIx64 "\n", be64_to_cpu(dsr->caps.node_guid));
 270
 271     dsr->caps.phys_port_cnt = MAX_PORTS;
 272     pr_dbg("phys_port_cnt=%d\n", dsr->caps.phys_port_cnt);
 273
 274     dsr->caps.max_pkeys = MAX_PKEYS;
 275     pr_dbg("max_pkeys=%d\n", dsr->caps.max_pkeys);
 276
 277     pr_dbg("Initialized\n");
 278 }
 279
 280 static void uninit_msix(PCIDevice *pdev, int used_vectors)
 281 {
 282     PVRDMADev *dev = PVRDMA_DEV(pdev);
 283     int i;
 284
 285     for (i = 0; i < used_vectors; i++) {
 286         msix_vector_unuse(pdev, i);
 287     }
 288
 289     msix_uninit(pdev, &dev->msix, &dev->msix);
 290 }
 291
 292 static int init_msix(PCIDevice *pdev, Error **errp)
 293 {
 294     PVRDMADev *dev = PVRDMA_DEV(pdev);
 295     int i;
 296     int rc;
 297
 298     rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
 299                    RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
 300                    RDMA_MSIX_PBA, 0, NULL);
 301
 302     if (rc < 0) {
 303         error_setg(errp, "Failed to initialize MSI-X");
 304         return rc;
 305     }
 306
 307     for (i = 0; i < RDMA_MAX_INTRS; i++) {
 308         rc = msix_vector_use(PCI_DEVICE(dev), i);
 309         if (rc < 0) {
 310             error_setg(errp, "Fail mark MSI-X vector %d", i);
 311             uninit_msix(pdev, i);
 312             return rc;
 313         }
 314     }
 315
 316     return 0;
 317 }
 318
 319 static void pvrdma_fini(PCIDevice *pdev)
 320 {
 321     PVRDMADev *dev = PVRDMA_DEV(pdev);
 322
 323     pr_dbg("Closing device %s %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
 324            PCI_FUNC(pdev->devfn));
 325
 326     pvrdma_qp_ops_fini();
 327
 328     rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
 329                  dev->backend_eth_device_name);
 330
 331     rdma_backend_fini(&dev->backend_dev);
 332
 333     free_dsr(dev);
 334
 335     if (msix_enabled(pdev)) {
 336         uninit_msix(pdev, RDMA_MAX_INTRS);
 337     }
 338
 339     pr_dbg("Device %s %x.%x is down\n", pdev->name, PCI_SLOT(pdev->devfn),
 340            PCI_FUNC(pdev->devfn));
 341 }
 342
 343 static void pvrdma_stop(PVRDMADev *dev)
 344 {
 345     rdma_backend_stop(&dev->backend_dev);
 346 }
 347
 348 static void pvrdma_start(PVRDMADev *dev)
 349 {
 350     rdma_backend_start(&dev->backend_dev);
 351 }
 352
 353 static void activate_device(PVRDMADev *dev)
 354 {
 355     pvrdma_start(dev);
 356     set_reg_val(dev, PVRDMA_REG_ERR, 0);
 357     pr_dbg("Device activated\n");
 358 }
 359
 360 static int unquiesce_device(PVRDMADev *dev)
 361 {
 362     pr_dbg("Device unquiesced\n");
 363     return 0;
 364 }
 365
 366 static void reset_device(PVRDMADev *dev)
 367 {
 368     pvrdma_stop(dev);
 369
 370     pr_dbg("Device reset complete\n");
 371 }
 372
 373 static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
 374 {
 375     PVRDMADev *dev = opaque;
 376     uint32_t val;
 377
 378     /* pr_dbg("addr=0x%lx, size=%d\n", addr, size); */
 379
 380     if (get_reg_val(dev, addr, &val)) {
 381         pr_dbg("Error trying to read REG value from address 0x%x\n",
 382                (uint32_t)addr);
 383         return -EINVAL;
 384     }
 385
 386     trace_pvrdma_regs_read(addr, val);
 387
 388     return val;
 389 }
 390
 391 static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 392 {
 393     PVRDMADev *dev = opaque;
 394
 395     /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
 396
 397     if (set_reg_val(dev, addr, val)) {
 398         pr_err("Fail to set REG value, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 399                addr, val);
 400         return;
 401     }
 402
 403     trace_pvrdma_regs_write(addr, val);
 404
 405     switch (addr) {
 406     case PVRDMA_REG_DSRLOW:
 407         dev->dsr_info.dma = val;
 408         break;
 409     case PVRDMA_REG_DSRHIGH:
 410         dev->dsr_info.dma |= val << 32;
 411         load_dsr(dev);
 412         init_dsr_dev_caps(dev);
 413         break;
 414     case PVRDMA_REG_CTL:
 415         switch (val) {
 416         case PVRDMA_DEVICE_CTL_ACTIVATE:
 417             activate_device(dev);
 418             break;
 419         case PVRDMA_DEVICE_CTL_UNQUIESCE:
 420             unquiesce_device(dev);
 421             break;
 422         case PVRDMA_DEVICE_CTL_RESET:
 423             reset_device(dev);
 424             break;
 425         }
 426         break;
 427     case PVRDMA_REG_IMR:
 428         pr_dbg("Interrupt mask=0x%" PRIx64 "\n", val);
 429         dev->interrupt_mask = val;
 430         break;
 431     case PVRDMA_REG_REQUEST:
 432         if (val == 0) {
 433             execute_command(dev);
 434         }
 435         break;
 436     default:
 437         break;
 438     }
 439 }
 440
 441 static const MemoryRegionOps regs_ops = {
 442     .read = regs_read,
 443     .write = regs_write,
 444     .endianness = DEVICE_LITTLE_ENDIAN,
 445     .impl = {
 446         .min_access_size = sizeof(uint32_t),
 447         .max_access_size = sizeof(uint32_t),
 448     },
 449 };
 450
 451 static uint64_t uar_read(void *opaque, hwaddr addr, unsigned size)
 452 {
 453     return 0xffffffff;
 454 }
 455
 456 static void uar_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 457 {
 458     PVRDMADev *dev = opaque;
 459
 460     /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
 461
 462     switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
 463     case PVRDMA_UAR_QP_OFFSET:
 464         pr_dbg("UAR QP command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 465                (uint64_t)addr, val);
 466         if (val & PVRDMA_UAR_QP_SEND) {
 467             pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
 468         }
 469         if (val & PVRDMA_UAR_QP_RECV) {
 470             pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
 471         }
 472         break;
 473     case PVRDMA_UAR_CQ_OFFSET:
 474         /* pr_dbg("UAR CQ cmd, addr=0x%x, val=0x%lx\n", (uint32_t)addr, val); */
 475         if (val & PVRDMA_UAR_CQ_ARM) {
 476             rdma_rm_req_notify_cq(&dev->rdma_dev_res,
 477                                   val & PVRDMA_UAR_HANDLE_MASK,
 478                                   !!(val & PVRDMA_UAR_CQ_ARM_SOL));
 479         }
 480         if (val & PVRDMA_UAR_CQ_ARM_SOL) {
 481             pr_dbg("UAR_CQ_ARM_SOL (%" PRIx64 ")\n",
 482                    val & PVRDMA_UAR_HANDLE_MASK);
 483         }
 484         if (val & PVRDMA_UAR_CQ_POLL) {
 485             pr_dbg("UAR_CQ_POLL (%" PRIx64 ")\n", val & PVRDMA_UAR_HANDLE_MASK);
 486             pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
 487         }
 488         break;
 489     default:
 490         pr_err("Unsupported command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 491                addr, val);
 492         break;
 493     }
 494 }
 495
 496 static const MemoryRegionOps uar_ops = {
 497     .read = uar_read,
 498     .write = uar_write,
 499     .endianness = DEVICE_LITTLE_ENDIAN,
 500     .impl = {
 501         .min_access_size = sizeof(uint32_t),
 502         .max_access_size = sizeof(uint32_t),
 503     },
 504 };
 505
 506 static void init_pci_config(PCIDevice *pdev)
 507 {
 508     pdev->config[PCI_INTERRUPT_PIN] = 1;
 509 }
 510
 511 static void init_bars(PCIDevice *pdev)
 512 {
 513     PVRDMADev *dev = PVRDMA_DEV(pdev);
 514
 515     /* BAR 0 - MSI-X */
 516     memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
 517                        RDMA_BAR0_MSIX_SIZE);
 518     pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 519                      &dev->msix);
 520
 521     /* BAR 1 - Registers */
 522     memset(&dev->regs_data, 0, sizeof(dev->regs_data));
 523     memory_region_init_io(&dev->regs, OBJECT(dev), &regs_ops, dev,
 524                           "pvrdma-regs", sizeof(dev->regs_data));
 525     pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 526                      &dev->regs);
 527
 528     /* BAR 2 - UAR */
 529     memset(&dev->uar_data, 0, sizeof(dev->uar_data));
 530     memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
 531                           sizeof(dev->uar_data));
 532     pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 533                      &dev->uar);
 534 }
 535
 536 static void init_regs(PCIDevice *pdev)
 537 {
 538     PVRDMADev *dev = PVRDMA_DEV(pdev);
 539
 540     set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
 541     set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
 542 }
 543
 544 static void init_dev_caps(PVRDMADev *dev)
 545 {
 546     size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
 547                           (TARGET_PAGE_SIZE / sizeof(uint64_t));
 548     size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
 549                        sizeof(struct pvrdma_rq_wqe_hdr));
 550
 551     dev->dev_attr.max_qp_wr = pg_tbl_bytes /
 552                               (wr_sz + sizeof(struct pvrdma_sge) * MAX_SGE) -
 553                               TARGET_PAGE_SIZE; /* First page is ring state */
 554     pr_dbg("max_qp_wr=%d\n", dev->dev_attr.max_qp_wr);
 555
 556     dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
 557                             TARGET_PAGE_SIZE; /* First page is ring state */
 558     pr_dbg("max_cqe=%d\n", dev->dev_attr.max_cqe);
 559 }
 560
 561 static int pvrdma_check_ram_shared(Object *obj, void *opaque)
 562 {
 563     bool *shared = opaque;
 564
 565     if (object_dynamic_cast(obj, "memory-backend-ram")) {
 566         *shared = object_property_get_bool(obj, "share", NULL);
 567     }
 568
 569     return 0;
 570 }
 571
 572 static void pvrdma_shutdown_notifier(Notifier *n, void *opaque)
 573 {
 574     PVRDMADev *dev = container_of(n, PVRDMADev, shutdown_notifier);
 575     PCIDevice *pci_dev = PCI_DEVICE(dev);
 576
 577     pvrdma_fini(pci_dev);
 578 }
 579
 580 static void pvrdma_realize(PCIDevice *pdev, Error **errp)
 581 {
 582     int rc = 0;
 583     PVRDMADev *dev = PVRDMA_DEV(pdev);
 584     Object *memdev_root;
 585     bool ram_shared = false;
 586     PCIDevice *func0;
 587
 588     init_pr_dbg();
 589
 590     pr_dbg("Initializing device %s %x.%x\n", pdev->name,
 591            PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 592
 593     if (TARGET_PAGE_SIZE != getpagesize()) {
 594         error_setg(errp, "Target page size must be the same as host page size");
 595         return;
 596     }
 597
 598     func0 = pci_get_function_0(pdev);
 599     /* Break if not vmxnet3 device in slot 0 */
 600     if (strcmp(object_get_typename(&func0->qdev.parent_obj), TYPE_VMXNET3)) {
 601         pr_dbg("func0 type is %s\n",
 602                object_get_typename(&func0->qdev.parent_obj));
 603         error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
 604                    TYPE_VMXNET3);
 605         return;
 606     }
 607     dev->func0 = VMXNET3(func0);
 608
 609     addrconf_addr_eui48((unsigned char *)&dev->node_guid,
 610                         (const char *)&dev->func0->conf.macaddr.a);
 611
 612     memdev_root = object_resolve_path("/objects", NULL);
 613     if (memdev_root) {
 614         object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
 615     }
 616     if (!ram_shared) {
 617         error_setg(errp, "Only shared memory backed ram is supported");
 618         return;
 619     }
 620
 621     dev->dsr_info.dsr = NULL;
 622
 623     init_pci_config(pdev);
 624
 625     init_bars(pdev);
 626
 627     init_regs(pdev);
 628
 629     init_dev_caps(dev);
 630
 631     rc = init_msix(pdev, errp);
 632     if (rc) {
 633         goto out;
 634     }
 635
 636     rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
 637                            dev->backend_device_name, dev->backend_port_num,
 638                            &dev->dev_attr, &dev->mad_chr, errp);
 639     if (rc) {
 640         goto out;
 641     }
 642
 643     rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr, errp);
 644     if (rc) {
 645         goto out;
 646     }
 647
 648     rc = pvrdma_qp_ops_init();
 649     if (rc) {
 650         goto out;
 651     }
 652
 653     dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
 654     qemu_register_shutdown_notifier(&dev->shutdown_notifier);
 655
 656 out:
 657     if (rc) {
 658         pvrdma_fini(pdev);
 659         error_append_hint(errp, "Device fail to load\n");
 660     }
 661 }
 662
 663 static void pvrdma_exit(PCIDevice *pdev)
 664 {
 665     pvrdma_fini(pdev);
 666 }
 667
 668 static void pvrdma_class_init(ObjectClass *klass, void *data)
 669 {
 670     DeviceClass *dc = DEVICE_CLASS(klass);
 671     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 672
 673     k->realize = pvrdma_realize;
 674     k->exit = pvrdma_exit;
 675     k->vendor_id = PCI_VENDOR_ID_VMWARE;
 676     k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
 677     k->revision = 0x00;
 678     k->class_id = PCI_CLASS_NETWORK_OTHER;
 679
 680     dc->desc = "RDMA Device";
 681     dc->props = pvrdma_dev_properties;
 682     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 683 }
 684
 685 static const TypeInfo pvrdma_info = {
 686     .name = PVRDMA_HW_NAME,
 687     .parent = TYPE_PCI_DEVICE,
 688     .instance_size = sizeof(PVRDMADev),
 689     .class_init = pvrdma_class_init,
 690     .interfaces = (InterfaceInfo[]) {
 691         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 692         { }
 693     }
 694 };
 695
 696 static void register_types(void)
 697 {
 698     type_register_static(&pvrdma_info);
 699 }
 700
 701 type_init(register_types)