hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  *
   7  * Provides a board compatible with the SiFive Freedom U SDK:
   8  *
   9  * 0) UART
  10  * 1) CLINT (Core Level Interruptor)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This board currently uses a hardcoded devicetree that indicates one hart.
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms and conditions of the GNU General Public License,
  17  * version 2 or later, as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope it will be useful, but WITHOUT
  20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  22  * more details.
  23  *
  24  * You should have received a copy of the GNU General Public License along with
  25  * this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/log.h"
  30 #include "qemu/error-report.h"
  31 #include "qapi/error.h"
  32 #include "hw/hw.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/char/serial.h"
  37 #include "target/riscv/cpu.h"
  38 #include "hw/riscv/riscv_hart.h"
  39 #include "hw/riscv/sifive_plic.h"
  40 #include "hw/riscv/sifive_clint.h"
  41 #include "hw/riscv/sifive_uart.h"
  42 #include "hw/riscv/sifive_prci.h"
  43 #include "hw/riscv/sifive_u.h"
  44 #include "chardev/char.h"
  45 #include "sysemu/arch_init.h"
  46 #include "sysemu/device_tree.h"
  47 #include "exec/address-spaces.h"
  48 #include "elf.h"
  49
  50 static const struct MemmapEntry {
  51     hwaddr base;
  52     hwaddr size;
  53 } sifive_u_memmap[] = {
  54     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  55     [SIFIVE_U_MROM] =     {     0x1000,     0x2000 },
  56     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  57     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  58     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
  59     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
  60     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  61 };
  62
  63 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
  64 {
  65     int i;
  66     for (i = 0; i < (len >> 2); i++) {
  67         stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
  68     }
  69 }
  70
  71 static uint64_t identity_translate(void *opaque, uint64_t addr)
  72 {
  73     return addr;
  74 }
  75
  76 static uint64_t load_kernel(const char *kernel_filename)
  77 {
  78     uint64_t kernel_entry, kernel_high;
  79
  80     if (load_elf(kernel_filename, identity_translate, NULL,
  81                  &kernel_entry, NULL, &kernel_high,
  82                  0, ELF_MACHINE, 1, 0) < 0) {
  83         error_report("qemu: could not load kernel '%s'", kernel_filename);
  84         exit(1);
  85     }
  86     return kernel_entry;
  87 }
  88
  89 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  90     uint64_t mem_size, const char *cmdline)
  91 {
  92     void *fdt;
  93     int cpu;
  94     uint32_t *cells;
  95     char *nodename;
  96     uint32_t plic_phandle;
  97
  98     fdt = s->fdt = create_device_tree(&s->fdt_size);
  99     if (!fdt) {
 100         error_report("create_device_tree() failed");
 101         exit(1);
 102     }
 103
 104     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
 105     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
 106     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 107     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 108
 109     qemu_fdt_add_subnode(fdt, "/soc");
 110     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 111     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
 112     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 113     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 114
 115     nodename = g_strdup_printf("/memory@%lx",
 116         (long)memmap[SIFIVE_U_DRAM].base);
 117     qemu_fdt_add_subnode(fdt, nodename);
 118     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 119         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 120         mem_size >> 32, mem_size);
 121     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 122     g_free(nodename);
 123
 124     qemu_fdt_add_subnode(fdt, "/cpus");
 125     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 126         SIFIVE_CLINT_TIMEBASE_FREQ);
 127     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 128     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 129
 130     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 131         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 132         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 133         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 134         qemu_fdt_add_subnode(fdt, nodename);
 135         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 136                               SIFIVE_U_CLOCK_FREQ);
 137         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 138         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 139         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 140         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 141         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 142         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 143         qemu_fdt_add_subnode(fdt, intc);
 144         qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 145         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
 146         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 147         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 148         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 149         g_free(isa);
 150         g_free(intc);
 151         g_free(nodename);
 152     }
 153
 154     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 155     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 156         nodename =
 157             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 158         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 159         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 160         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 161         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 162         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 163         g_free(nodename);
 164     }
 165     nodename = g_strdup_printf("/soc/clint@%lx",
 166         (long)memmap[SIFIVE_U_CLINT].base);
 167     qemu_fdt_add_subnode(fdt, nodename);
 168     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 169     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 170         0x0, memmap[SIFIVE_U_CLINT].base,
 171         0x0, memmap[SIFIVE_U_CLINT].size);
 172     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 173         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 174     g_free(cells);
 175     g_free(nodename);
 176
 177     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 178     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 179         nodename =
 180             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 181         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 182         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 183         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 184         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 185         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 186         g_free(nodename);
 187     }
 188     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 189         (long)memmap[SIFIVE_U_PLIC].base);
 190     qemu_fdt_add_subnode(fdt, nodename);
 191     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 192     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 193     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 194     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 195         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 196     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 197         0x0, memmap[SIFIVE_U_PLIC].base,
 198         0x0, memmap[SIFIVE_U_PLIC].size);
 199     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 200     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 201     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
 202     qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
 203     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
 204     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 205     g_free(cells);
 206     g_free(nodename);
 207
 208     nodename = g_strdup_printf("/uart@%lx",
 209         (long)memmap[SIFIVE_U_UART0].base);
 210     qemu_fdt_add_subnode(fdt, nodename);
 211     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 212     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 213         0x0, memmap[SIFIVE_U_UART0].base,
 214         0x0, memmap[SIFIVE_U_UART0].size);
 215     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 216     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
 217
 218     qemu_fdt_add_subnode(fdt, "/chosen");
 219     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 220     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 221     g_free(nodename);
 222 }
 223
 224 static void riscv_sifive_u_init(MachineState *machine)
 225 {
 226     const struct MemmapEntry *memmap = sifive_u_memmap;
 227
 228     SiFiveUState *s = g_new0(SiFiveUState, 1);
 229     MemoryRegion *sys_memory = get_system_memory();
 230     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 231     MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 232
 233     /* Initialize SOC */
 234     object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
 235     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
 236                               &error_abort);
 237     object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
 238                             &error_abort);
 239     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 240                             &error_abort);
 241     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 242                             &error_abort);
 243
 244     /* register RAM */
 245     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 246                            machine->ram_size, &error_fatal);
 247     memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base,
 248         main_mem);
 249
 250     /* create device tree */
 251     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 252
 253     /* boot rom */
 254     memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom",
 255                            memmap[SIFIVE_U_MROM].base, &error_fatal);
 256     memory_region_set_readonly(boot_rom, true);
 257     memory_region_add_subregion(sys_memory, 0x0, boot_rom);
 258
 259     if (machine->kernel_filename) {
 260         load_kernel(machine->kernel_filename);
 261     }
 262
 263     /* reset vector */
 264     uint32_t reset_vec[8] = {
 265         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 266         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 267         0xf1402573,                    /*     csrr   a0, mhartid  */
 268 #if defined(TARGET_RISCV32)
 269         0x0182a283,                    /*     lw     t0, 24(t0) */
 270 #elif defined(TARGET_RISCV64)
 271         0x0182b283,                    /*     ld     t0, 24(t0) */
 272 #endif
 273         0x00028067,                    /*     jr     t0 */
 274         0x00000000,
 275         memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
 276         0x00000000,
 277                                        /* dtb: */
 278     };
 279
 280     /* copy in the reset vector */
 281     copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_vec));
 282
 283     /* copy in the device tree */
 284     qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
 285     cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base +
 286         sizeof(reset_vec), s->fdt, s->fdt_size);
 287
 288     /* MMIO */
 289     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 290         (char *)SIFIVE_U_PLIC_HART_CONFIG,
 291         SIFIVE_U_PLIC_NUM_SOURCES,
 292         SIFIVE_U_PLIC_NUM_PRIORITIES,
 293         SIFIVE_U_PLIC_PRIORITY_BASE,
 294         SIFIVE_U_PLIC_PENDING_BASE,
 295         SIFIVE_U_PLIC_ENABLE_BASE,
 296         SIFIVE_U_PLIC_ENABLE_STRIDE,
 297         SIFIVE_U_PLIC_CONTEXT_BASE,
 298         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 299         memmap[SIFIVE_U_PLIC].size);
 300     sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base,
 301         serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
 302     /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base,
 303         serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
 304     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 305         memmap[SIFIVE_U_CLINT].size, smp_cpus,
 306         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 307 }
 308
 309 static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
 310 {
 311     return 0;
 312 }
 313
 314 static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
 315 {
 316     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 317     k->init = riscv_sifive_u_sysbus_device_init;
 318 }
 319
 320 static const TypeInfo riscv_sifive_u_device = {
 321     .name          = TYPE_SIFIVE_U,
 322     .parent        = TYPE_SYS_BUS_DEVICE,
 323     .instance_size = sizeof(SiFiveUState),
 324     .class_init    = riscv_sifive_u_class_init,
 325 };
 326
 327 static void riscv_sifive_u_register_types(void)
 328 {
 329     type_register_static(&riscv_sifive_u_device);
 330 }
 331
 332 type_init(riscv_sifive_u_register_types);
 333
 334 static void riscv_sifive_u_machine_init(MachineClass *mc)
 335 {
 336     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 337     mc->init = riscv_sifive_u_init;
 338     mc->max_cpus = 1;
 339 }
 340
 341 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)