2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "hw/qdev-properties.h"
19 #include "migration/vmstate.h"
20 #include "monitor/monitor.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
26 * XIVE Thread Interrupt Management context
30 * Convert a priority number to an Interrupt Pending Buffer (IPB)
31 * register, which indicates a pending interrupt at the priority
32 * corresponding to the bit number
34 static uint8_t priority_to_ipb(uint8_t priority
)
36 return priority
> XIVE_PRIORITY_MAX
?
37 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
42 * Interrupt Priority Register (PIPR), which contains the priority of
43 * the most favored pending notification.
45 static uint8_t ipb_to_pipr(uint8_t ibp
)
47 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
50 static uint8_t exception_mask(uint8_t ring
)
58 g_assert_not_reached();
62 static qemu_irq
xive_tctx_output(XiveTCTX
*tctx
, uint8_t ring
)
66 return 0; /* Not supported */
68 return tctx
->os_output
;
71 return tctx
->hv_output
;
77 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
79 uint8_t *regs
= &tctx
->regs
[ring
];
80 uint8_t nsr
= regs
[TM_NSR
];
81 uint8_t mask
= exception_mask(ring
);
83 qemu_irq_lower(xive_tctx_output(tctx
, ring
));
85 if (regs
[TM_NSR
] & mask
) {
86 uint8_t cppr
= regs
[TM_PIPR
];
90 /* Reset the pending buffer bit */
91 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
92 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
94 /* Drop Exception bit */
95 regs
[TM_NSR
] &= ~mask
;
98 return (nsr
<< 8) | regs
[TM_CPPR
];
101 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
103 uint8_t *regs
= &tctx
->regs
[ring
];
105 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
108 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
111 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
114 g_assert_not_reached();
116 qemu_irq_raise(xive_tctx_output(tctx
, ring
));
120 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
122 if (cppr
> XIVE_PRIORITY_MAX
) {
126 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
128 /* CPPR has changed, check if we need to raise a pending exception */
129 xive_tctx_notify(tctx
, ring
);
132 void xive_tctx_ipb_update(XiveTCTX
*tctx
, uint8_t ring
, uint8_t ipb
)
134 uint8_t *regs
= &tctx
->regs
[ring
];
137 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
138 xive_tctx_notify(tctx
, ring
);
141 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
143 return *((uint32_t *) &ring
[TM_WORD2
]);
147 * XIVE Thread Interrupt Management Area (TIMA)
150 static void xive_tm_set_hv_cppr(XivePresenter
*xptr
, XiveTCTX
*tctx
,
151 hwaddr offset
, uint64_t value
, unsigned size
)
153 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
156 static uint64_t xive_tm_ack_hv_reg(XivePresenter
*xptr
, XiveTCTX
*tctx
,
157 hwaddr offset
, unsigned size
)
159 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
163 hwaddr offset
, unsigned size
)
165 uint32_t qw2w2_prev
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
168 qw2w2
= xive_set_field32(TM_QW2W2_VP
, qw2w2_prev
, 0);
169 memcpy(&tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
], &qw2w2
, 4);
173 static void xive_tm_vt_push(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
174 uint64_t value
, unsigned size
)
176 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
179 static uint64_t xive_tm_vt_poll(XivePresenter
*xptr
, XiveTCTX
*tctx
,
180 hwaddr offset
, unsigned size
)
182 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
186 * Define an access map for each page of the TIMA that we will use in
187 * the memory region ops to filter values when doing loads and stores
188 * of raw registers values
190 * Registers accessibility bits :
198 static const uint8_t xive_tm_hw_view
[] = {
199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
205 static const uint8_t xive_tm_hv_view
[] = {
206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
212 static const uint8_t xive_tm_os_view
[] = {
213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
219 static const uint8_t xive_tm_user_view
[] = {
220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
227 * Overall TIMA access map for the thread interrupt management context
230 static const uint8_t *xive_tm_views
[] = {
231 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
232 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
233 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
234 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
238 * Computes a register access mask for a given offset in the TIMA
240 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
242 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
243 uint8_t reg_offset
= offset
& 0x3F;
244 uint8_t reg_mask
= write
? 0x1 : 0x2;
248 for (i
= 0; i
< size
; i
++) {
249 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
250 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
257 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
260 uint8_t ring_offset
= offset
& 0x30;
261 uint8_t reg_offset
= offset
& 0x3F;
262 uint64_t mask
= xive_tm_mask(offset
, size
, true);
266 * Only 4 or 8 bytes stores are allowed and the User ring is
269 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
270 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
271 HWADDR_PRIx
"\n", offset
);
276 * Use the register offset for the raw values and filter out
279 for (i
= 0; i
< size
; i
++) {
280 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
282 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
288 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
290 uint8_t ring_offset
= offset
& 0x30;
291 uint8_t reg_offset
= offset
& 0x3F;
292 uint64_t mask
= xive_tm_mask(offset
, size
, false);
297 * Only 4 or 8 bytes loads are allowed and the User ring is
300 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
301 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
302 HWADDR_PRIx
"\n", offset
);
306 /* Use the register offset for the raw values */
308 for (i
= 0; i
< size
; i
++) {
309 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
312 /* filter out reserved values */
317 * The TM context is mapped twice within each page. Stores and loads
318 * to the first mapping below 2K write and read the specified values
319 * without modification. The second mapping above 2K performs specific
320 * state changes (side effects) in addition to setting/returning the
321 * interrupt management area context of the processor thread.
323 static uint64_t xive_tm_ack_os_reg(XivePresenter
*xptr
, XiveTCTX
*tctx
,
324 hwaddr offset
, unsigned size
)
326 return xive_tctx_accept(tctx
, TM_QW1_OS
);
329 static void xive_tm_set_os_cppr(XivePresenter
*xptr
, XiveTCTX
*tctx
,
330 hwaddr offset
, uint64_t value
, unsigned size
)
332 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
336 * Adjust the IPB to allow a CPU to process event queues of other
337 * priorities during one physical interrupt cycle.
339 static void xive_tm_set_os_pending(XivePresenter
*xptr
, XiveTCTX
*tctx
,
340 hwaddr offset
, uint64_t value
, unsigned size
)
342 xive_tctx_ipb_update(tctx
, TM_QW1_OS
, priority_to_ipb(value
& 0xff));
345 static void xive_os_cam_decode(uint32_t cam
, uint8_t *nvt_blk
,
346 uint32_t *nvt_idx
, bool *vo
)
349 *nvt_blk
= xive_nvt_blk(cam
);
352 *nvt_idx
= xive_nvt_idx(cam
);
355 *vo
= !!(cam
& TM_QW1W2_VO
);
359 static uint32_t xive_tctx_get_os_cam(XiveTCTX
*tctx
, uint8_t *nvt_blk
,
360 uint32_t *nvt_idx
, bool *vo
)
362 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
363 uint32_t cam
= be32_to_cpu(qw1w2
);
365 xive_os_cam_decode(cam
, nvt_blk
, nvt_idx
, vo
);
369 static void xive_tctx_set_os_cam(XiveTCTX
*tctx
, uint32_t qw1w2
)
371 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
374 static uint64_t xive_tm_pull_os_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
375 hwaddr offset
, unsigned size
)
383 qw1w2
= xive_tctx_get_os_cam(tctx
, &nvt_blk
, &nvt_idx
, &vo
);
386 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: pulling invalid NVT %x/%x !?\n",
390 /* Invalidate CAM line */
391 qw1w2_new
= xive_set_field32(TM_QW1W2_VO
, qw1w2
, 0);
392 xive_tctx_set_os_cam(tctx
, qw1w2_new
);
396 static void xive_tctx_need_resend(XiveRouter
*xrtr
, XiveTCTX
*tctx
,
397 uint8_t nvt_blk
, uint32_t nvt_idx
)
403 * Grab the associated NVT to pull the pending bits, and merge
404 * them with the IPB of the thread interrupt context registers
406 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
407 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid NVT %x/%x\n",
412 ipb
= xive_get_field32(NVT_W4_IPB
, nvt
.w4
);
415 /* Reset the NVT value */
416 nvt
.w4
= xive_set_field32(NVT_W4_IPB
, nvt
.w4
, 0);
417 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
419 /* Merge in current context */
420 xive_tctx_ipb_update(tctx
, TM_QW1_OS
, ipb
);
425 * Updating the OS CAM line can trigger a resend of interrupt
427 static void xive_tm_push_os_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
428 hwaddr offset
, uint64_t value
, unsigned size
)
430 uint32_t cam
= value
;
431 uint32_t qw1w2
= cpu_to_be32(cam
);
436 xive_os_cam_decode(cam
, &nvt_blk
, &nvt_idx
, &vo
);
438 /* First update the registers */
439 xive_tctx_set_os_cam(tctx
, qw1w2
);
441 /* Check the interrupt pending bits */
443 xive_tctx_need_resend(XIVE_ROUTER(xptr
), tctx
, nvt_blk
, nvt_idx
);
448 * Define a mapping of "special" operations depending on the TIMA page
449 * offset and the size of the operation.
451 typedef struct XiveTmOp
{
455 void (*write_handler
)(XivePresenter
*xptr
, XiveTCTX
*tctx
,
457 uint64_t value
, unsigned size
);
458 uint64_t (*read_handler
)(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
462 static const XiveTmOp xive_tm_operations
[] = {
464 * MMIOs below 2K : raw values and special operations without side
467 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
468 { XIVE_TM_HV_PAGE
, TM_QW1_OS
+ TM_WORD2
, 4, xive_tm_push_os_ctx
, NULL
},
469 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
470 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
471 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
473 /* MMIOs above 2K : special operations with side effects */
474 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
475 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
476 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 4, NULL
, xive_tm_pull_os_ctx
},
477 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 8, NULL
, xive_tm_pull_os_ctx
},
478 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
479 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
480 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
483 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
485 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
486 uint32_t op_offset
= offset
& 0xFFF;
489 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
490 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
492 /* Accesses done from a more privileged TIMA page is allowed */
493 if (xto
->page_offset
>= page_offset
&&
494 xto
->op_offset
== op_offset
&&
496 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
506 void xive_tctx_tm_write(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
507 uint64_t value
, unsigned size
)
512 * TODO: check V bit in Q[0-3]W2
516 * First, check for special operations in the 2K region
518 if (offset
& 0x800) {
519 xto
= xive_tm_find_op(offset
, size
, true);
521 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA "
522 "@%"HWADDR_PRIx
"\n", offset
);
524 xto
->write_handler(xptr
, tctx
, offset
, value
, size
);
530 * Then, for special operations in the region below 2K.
532 xto
= xive_tm_find_op(offset
, size
, true);
534 xto
->write_handler(xptr
, tctx
, offset
, value
, size
);
539 * Finish with raw access to the register values
541 xive_tm_raw_write(tctx
, offset
, value
, size
);
544 uint64_t xive_tctx_tm_read(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
550 * TODO: check V bit in Q[0-3]W2
554 * First, check for special operations in the 2K region
556 if (offset
& 0x800) {
557 xto
= xive_tm_find_op(offset
, size
, false);
559 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
560 "@%"HWADDR_PRIx
"\n", offset
);
563 return xto
->read_handler(xptr
, tctx
, offset
, size
);
567 * Then, for special operations in the region below 2K.
569 xto
= xive_tm_find_op(offset
, size
, false);
571 return xto
->read_handler(xptr
, tctx
, offset
, size
);
575 * Finish with raw access to the register values
577 return xive_tm_raw_read(tctx
, offset
, size
);
580 static char *xive_tctx_ring_print(uint8_t *ring
)
582 uint32_t w2
= xive_tctx_word2(ring
);
584 return g_strdup_printf("%02x %02x %02x %02x %02x "
585 "%02x %02x %02x %08x",
586 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
587 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
591 static const char * const xive_tctx_ring_names
[] = {
592 "USER", "OS", "POOL", "PHYS",
596 * kvm_irqchip_in_kernel() will cause the compiler to turn this
597 * info a nop if CONFIG_KVM isn't defined.
599 #define xive_in_kernel(xptr) \
600 (kvm_irqchip_in_kernel() && \
602 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \
603 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \
606 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
611 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
612 * are hot plugged or unplugged.
618 cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
620 if (xive_in_kernel(tctx
->xptr
)) {
621 Error
*local_err
= NULL
;
623 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
625 error_report_err(local_err
);
630 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
633 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
634 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
635 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
636 xive_tctx_ring_names
[i
], s
);
641 void xive_tctx_reset(XiveTCTX
*tctx
)
643 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
645 /* Set some defaults */
646 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
647 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
648 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
651 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
654 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
655 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
656 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
657 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
660 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
662 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
665 Error
*local_err
= NULL
;
670 cpu
= POWERPC_CPU(tctx
->cs
);
672 switch (PPC_INPUT(env
)) {
673 case PPC_FLAGS_INPUT_POWER9
:
674 tctx
->hv_output
= env
->irq_inputs
[POWER9_INPUT_HINT
];
675 tctx
->os_output
= env
->irq_inputs
[POWER9_INPUT_INT
];
679 error_setg(errp
, "XIVE interrupt controller does not support "
680 "this CPU bus model");
684 /* Connect the presenter to the VCPU (required for CPU hotplug) */
685 if (xive_in_kernel(tctx
->xptr
)) {
686 kvmppc_xive_cpu_connect(tctx
, &local_err
);
688 error_propagate(errp
, local_err
);
694 static int vmstate_xive_tctx_pre_save(void *opaque
)
696 XiveTCTX
*tctx
= XIVE_TCTX(opaque
);
697 Error
*local_err
= NULL
;
700 if (xive_in_kernel(tctx
->xptr
)) {
701 ret
= kvmppc_xive_cpu_get_state(tctx
, &local_err
);
703 error_report_err(local_err
);
711 static int vmstate_xive_tctx_post_load(void *opaque
, int version_id
)
713 XiveTCTX
*tctx
= XIVE_TCTX(opaque
);
714 Error
*local_err
= NULL
;
717 if (xive_in_kernel(tctx
->xptr
)) {
719 * Required for hotplugged CPU, for which the state comes
720 * after all states of the machine.
722 ret
= kvmppc_xive_cpu_set_state(tctx
, &local_err
);
724 error_report_err(local_err
);
732 static const VMStateDescription vmstate_xive_tctx
= {
733 .name
= TYPE_XIVE_TCTX
,
735 .minimum_version_id
= 1,
736 .pre_save
= vmstate_xive_tctx_pre_save
,
737 .post_load
= vmstate_xive_tctx_post_load
,
738 .fields
= (VMStateField
[]) {
739 VMSTATE_BUFFER(regs
, XiveTCTX
),
740 VMSTATE_END_OF_LIST()
744 static Property xive_tctx_properties
[] = {
745 DEFINE_PROP_LINK("cpu", XiveTCTX
, cs
, TYPE_CPU
, CPUState
*),
746 DEFINE_PROP_LINK("presenter", XiveTCTX
, xptr
, TYPE_XIVE_PRESENTER
,
748 DEFINE_PROP_END_OF_LIST(),
751 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
753 DeviceClass
*dc
= DEVICE_CLASS(klass
);
755 dc
->desc
= "XIVE Interrupt Thread Context";
756 dc
->realize
= xive_tctx_realize
;
757 dc
->vmsd
= &vmstate_xive_tctx
;
758 device_class_set_props(dc
, xive_tctx_properties
);
760 * Reason: part of XIVE interrupt controller, needs to be wired up
761 * by xive_tctx_create().
763 dc
->user_creatable
= false;
766 static const TypeInfo xive_tctx_info
= {
767 .name
= TYPE_XIVE_TCTX
,
768 .parent
= TYPE_DEVICE
,
769 .instance_size
= sizeof(XiveTCTX
),
770 .class_init
= xive_tctx_class_init
,
773 Object
*xive_tctx_create(Object
*cpu
, XivePresenter
*xptr
, Error
**errp
)
777 obj
= object_new(TYPE_XIVE_TCTX
);
778 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
);
780 object_property_set_link(obj
, "cpu", cpu
, &error_abort
);
781 object_property_set_link(obj
, "presenter", OBJECT(xptr
), &error_abort
);
782 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
783 object_unparent(obj
);
789 void xive_tctx_destroy(XiveTCTX
*tctx
)
791 Object
*obj
= OBJECT(tctx
);
793 object_unparent(obj
);
800 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
802 uint8_t old_pq
= *pq
& 0x3;
810 static bool xive_esb_trigger(uint8_t *pq
)
812 uint8_t old_pq
= *pq
& 0x3;
816 xive_esb_set(pq
, XIVE_ESB_PENDING
);
818 case XIVE_ESB_PENDING
:
819 case XIVE_ESB_QUEUED
:
820 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
823 xive_esb_set(pq
, XIVE_ESB_OFF
);
826 g_assert_not_reached();
830 static bool xive_esb_eoi(uint8_t *pq
)
832 uint8_t old_pq
= *pq
& 0x3;
836 case XIVE_ESB_PENDING
:
837 xive_esb_set(pq
, XIVE_ESB_RESET
);
839 case XIVE_ESB_QUEUED
:
840 xive_esb_set(pq
, XIVE_ESB_PENDING
);
843 xive_esb_set(pq
, XIVE_ESB_OFF
);
846 g_assert_not_reached();
851 * XIVE Interrupt Source (or IVSE)
854 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
856 assert(srcno
< xsrc
->nr_irqs
);
858 return xsrc
->status
[srcno
] & 0x3;
861 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
863 assert(srcno
< xsrc
->nr_irqs
);
865 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
869 * Returns whether the event notification should be forwarded.
871 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
873 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
875 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
879 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
887 * Returns whether the event notification should be forwarded.
889 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
893 assert(srcno
< xsrc
->nr_irqs
);
895 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
897 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
898 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
899 qemu_log_mask(LOG_GUEST_ERROR
,
900 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
907 * Returns whether the event notification should be forwarded.
909 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
913 assert(srcno
< xsrc
->nr_irqs
);
915 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
918 * LSI sources do not set the Q bit but they can still be
919 * asserted, in which case we should forward a new event
922 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
923 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
924 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
931 * Forward the source event notification to the Router
933 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
935 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
938 xnc
->notify(xsrc
->xive
, srcno
);
943 * In a two pages ESB MMIO setting, even page is the trigger page, odd
944 * page is for management
946 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
948 return !((addr
>> shift
) & 1);
951 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
953 return xive_source_esb_has_2page(xsrc
) &&
954 addr_is_even(addr
, xsrc
->esb_shift
- 1);
959 * Trigger page Management/EOI page
961 * ESB MMIO setting 2 pages 1 or 2 pages
963 * 0x000 .. 0x3FF -1 EOI and return 0|1
964 * 0x400 .. 0x7FF -1 EOI and return 0|1
965 * 0x800 .. 0xBFF -1 return PQ
966 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
967 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
968 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
969 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
971 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
973 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
974 uint32_t offset
= addr
& 0xFFF;
975 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
978 /* In a two pages ESB MMIO setting, trigger page should not be read */
979 if (xive_source_is_trigger_page(xsrc
, addr
)) {
980 qemu_log_mask(LOG_GUEST_ERROR
,
981 "XIVE: invalid load on IRQ %d trigger page at "
982 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
987 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
988 ret
= xive_source_esb_eoi(xsrc
, srcno
);
990 /* Forward the source event notification for routing */
992 xive_source_notify(xsrc
, srcno
);
996 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
997 ret
= xive_source_esb_get(xsrc
, srcno
);
1000 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1001 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1002 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1003 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1004 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
1007 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
1016 * Trigger page Management/EOI page
1018 * ESB MMIO setting 2 pages 1 or 2 pages
1020 * 0x000 .. 0x3FF Trigger Trigger
1021 * 0x400 .. 0x7FF Trigger EOI
1022 * 0x800 .. 0xBFF Trigger undefined
1023 * 0xC00 .. 0xCFF Trigger PQ=00
1024 * 0xD00 .. 0xDFF Trigger PQ=01
1025 * 0xE00 .. 0xDFF Trigger PQ=10
1026 * 0xF00 .. 0xDFF Trigger PQ=11
1028 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
1029 uint64_t value
, unsigned size
)
1031 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
1032 uint32_t offset
= addr
& 0xFFF;
1033 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
1034 bool notify
= false;
1036 /* In a two pages ESB MMIO setting, trigger page only triggers */
1037 if (xive_source_is_trigger_page(xsrc
, addr
)) {
1038 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1044 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1047 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
1048 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
1049 qemu_log_mask(LOG_GUEST_ERROR
,
1050 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
1054 notify
= xive_source_esb_eoi(xsrc
, srcno
);
1057 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1058 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1059 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1060 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1061 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
1065 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
1071 /* Forward the source event notification for routing */
1073 xive_source_notify(xsrc
, srcno
);
1077 static const MemoryRegionOps xive_source_esb_ops
= {
1078 .read
= xive_source_esb_read
,
1079 .write
= xive_source_esb_write
,
1080 .endianness
= DEVICE_BIG_ENDIAN
,
1082 .min_access_size
= 8,
1083 .max_access_size
= 8,
1086 .min_access_size
= 8,
1087 .max_access_size
= 8,
1091 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
1093 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
1094 bool notify
= false;
1096 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
1098 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
1100 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
1104 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1108 /* Forward the source event notification for routing */
1110 xive_source_notify(xsrc
, srcno
);
1114 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
1118 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
1119 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
1121 if (pq
== XIVE_ESB_OFF
) {
1125 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
1126 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
1127 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1128 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1129 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
1133 static void xive_source_reset(void *dev
)
1135 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1137 /* Do not clear the LSI bitmap */
1139 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
1140 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
1143 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1145 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1146 size_t esb_len
= xive_source_esb_len(xsrc
);
1150 if (!xsrc
->nr_irqs
) {
1151 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1155 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1156 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1157 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1158 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1159 error_setg(errp
, "Invalid ESB shift setting");
1163 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1164 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1166 memory_region_init(&xsrc
->esb_mmio
, OBJECT(xsrc
), "xive.esb", esb_len
);
1167 memory_region_init_io(&xsrc
->esb_mmio_emulated
, OBJECT(xsrc
),
1168 &xive_source_esb_ops
, xsrc
, "xive.esb-emulated",
1170 memory_region_add_subregion(&xsrc
->esb_mmio
, 0, &xsrc
->esb_mmio_emulated
);
1172 qemu_register_reset(xive_source_reset
, dev
);
1175 static const VMStateDescription vmstate_xive_source
= {
1176 .name
= TYPE_XIVE_SOURCE
,
1178 .minimum_version_id
= 1,
1179 .fields
= (VMStateField
[]) {
1180 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1181 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1182 VMSTATE_END_OF_LIST()
1187 * The default XIVE interrupt source setting for the ESB MMIOs is two
1188 * 64k pages without Store EOI, to be in sync with KVM.
1190 static Property xive_source_properties
[] = {
1191 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1192 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1193 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1194 DEFINE_PROP_LINK("xive", XiveSource
, xive
, TYPE_XIVE_NOTIFIER
,
1196 DEFINE_PROP_END_OF_LIST(),
1199 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1201 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1203 dc
->desc
= "XIVE Interrupt Source";
1204 device_class_set_props(dc
, xive_source_properties
);
1205 dc
->realize
= xive_source_realize
;
1206 dc
->vmsd
= &vmstate_xive_source
;
1208 * Reason: part of XIVE interrupt controller, needs to be wired up,
1209 * e.g. by spapr_xive_instance_init().
1211 dc
->user_creatable
= false;
1214 static const TypeInfo xive_source_info
= {
1215 .name
= TYPE_XIVE_SOURCE
,
1216 .parent
= TYPE_DEVICE
,
1217 .instance_size
= sizeof(XiveSource
),
1218 .class_init
= xive_source_class_init
,
1225 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1227 uint64_t qaddr_base
= xive_end_qaddr(end
);
1228 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1229 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1230 uint32_t qentries
= 1 << (qsize
+ 10);
1234 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1236 monitor_printf(mon
, " [ ");
1237 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1238 for (i
= 0; i
< width
; i
++) {
1239 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1240 uint32_t qdata
= -1;
1242 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1244 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1245 HWADDR_PRIx
"\n", qaddr
);
1248 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1249 be32_to_cpu(qdata
));
1250 qindex
= (qindex
+ 1) & (qentries
- 1);
1252 monitor_printf(mon
, "]");
1255 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1257 uint64_t qaddr_base
= xive_end_qaddr(end
);
1258 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1259 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1260 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1261 uint32_t qentries
= 1 << (qsize
+ 10);
1263 uint32_t nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1264 uint32_t nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1265 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1268 if (!xive_end_is_valid(end
)) {
1272 pq
= xive_get_field32(END_W1_ESn
, end
->w1
);
1274 monitor_printf(mon
, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
1276 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1277 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1278 xive_end_is_valid(end
) ? 'v' : '-',
1279 xive_end_is_enqueue(end
) ? 'q' : '-',
1280 xive_end_is_notify(end
) ? 'n' : '-',
1281 xive_end_is_backlog(end
) ? 'b' : '-',
1282 xive_end_is_escalate(end
) ? 'e' : '-',
1283 xive_end_is_uncond_escalation(end
) ? 'u' : '-',
1284 xive_end_is_silent_escalation(end
) ? 's' : '-',
1285 priority
, nvt_blk
, nvt_idx
);
1288 monitor_printf(mon
, " eq:@%08"PRIx64
"% 6d/%5d ^%d",
1289 qaddr_base
, qindex
, qentries
, qgen
);
1290 xive_end_queue_pic_print_info(end
, 6, mon
);
1292 monitor_printf(mon
, "\n");
1295 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1297 uint64_t qaddr_base
= xive_end_qaddr(end
);
1298 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1299 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1300 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1302 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1303 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1304 uint32_t qentries
= 1 << (qsize
+ 10);
1306 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1307 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1308 HWADDR_PRIx
"\n", qaddr
);
1312 qindex
= (qindex
+ 1) & (qentries
- 1);
1315 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1317 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1320 void xive_end_eas_pic_print_info(XiveEND
*end
, uint32_t end_idx
,
1323 XiveEAS
*eas
= (XiveEAS
*) &end
->w4
;
1326 if (!xive_end_is_escalate(end
)) {
1330 pq
= xive_get_field32(END_W1_ESe
, end
->w1
);
1332 monitor_printf(mon
, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
1334 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1335 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1336 xive_eas_is_valid(eas
) ? 'V' : ' ',
1337 xive_eas_is_masked(eas
) ? 'M' : ' ',
1338 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1339 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1340 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1344 * XIVE Router (aka. Virtualization Controller or IVRE)
1347 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1350 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1352 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1355 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1358 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1360 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1363 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1364 XiveEND
*end
, uint8_t word_number
)
1366 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1368 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1371 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1374 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1376 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1379 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1380 XiveNVT
*nvt
, uint8_t word_number
)
1382 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1384 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1387 static int xive_router_get_block_id(XiveRouter
*xrtr
)
1389 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1391 return xrc
->get_block_id(xrtr
);
1394 static void xive_router_realize(DeviceState
*dev
, Error
**errp
)
1396 XiveRouter
*xrtr
= XIVE_ROUTER(dev
);
1402 * Encode the HW CAM line in the block group mode format :
1404 * chip << 19 | 0000000 0 0001 thread (7Bit)
1406 static uint32_t xive_tctx_hw_cam_line(XivePresenter
*xptr
, XiveTCTX
*tctx
)
1408 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1409 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1410 uint8_t blk
= xive_router_get_block_id(XIVE_ROUTER(xptr
));
1412 return xive_nvt_cam_line(blk
, 1 << 7 | (pir
& 0x7f));
1416 * The thread context register words are in big-endian format.
1418 int xive_presenter_tctx_match(XivePresenter
*xptr
, XiveTCTX
*tctx
,
1420 uint8_t nvt_blk
, uint32_t nvt_idx
,
1421 bool cam_ignore
, uint32_t logic_serv
)
1423 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1424 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1425 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1426 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1427 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1430 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1431 * identifier are ignored in the "CAM" match.
1435 if (cam_ignore
== true) {
1437 * F=0 & i=1: Logical server notification (bits ignored at
1438 * the end of the NVT identifier)
1440 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1445 /* F=0 & i=0: Specific NVT notification */
1448 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1449 cam
== xive_tctx_hw_cam_line(xptr
, tctx
)) {
1450 return TM_QW3_HV_PHYS
;
1454 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1455 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1456 return TM_QW2_HV_POOL
;
1460 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1461 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1465 /* F=1 : User level Event-Based Branch (EBB) notification */
1468 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1469 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1470 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1471 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1479 * This is our simple Xive Presenter Engine model. It is merged in the
1480 * Router as it does not require an extra object.
1482 * It receives notification requests sent by the IVRE to find one
1483 * matching NVT (or more) dispatched on the processor threads. In case
1484 * of a single NVT notification, the process is abreviated and the
1485 * thread is signaled if a match is found. In case of a logical server
1486 * notification (bits ignored at the end of the NVT identifier), the
1487 * IVPE and IVRE select a winning thread using different filters. This
1488 * involves 2 or 3 exchanges on the PowerBus that the model does not
1491 * The parameters represent what is sent on the PowerBus
1493 static bool xive_presenter_notify(XiveFabric
*xfb
, uint8_t format
,
1494 uint8_t nvt_blk
, uint32_t nvt_idx
,
1495 bool cam_ignore
, uint8_t priority
,
1496 uint32_t logic_serv
)
1498 XiveFabricClass
*xfc
= XIVE_FABRIC_GET_CLASS(xfb
);
1499 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1503 * Ask the machine to scan the interrupt controllers for a match
1505 count
= xfc
->match_nvt(xfb
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1506 priority
, logic_serv
, &match
);
1511 /* handle CPU exception delivery */
1513 xive_tctx_ipb_update(match
.tctx
, match
.ring
, priority_to_ipb(priority
));
1520 * Notification using the END ESe/ESn bit (Event State Buffer for
1521 * escalation and notification). Provide further coalescing in the
1524 static bool xive_router_end_es_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1525 uint32_t end_idx
, XiveEND
*end
,
1526 uint32_t end_esmask
)
1528 uint8_t pq
= xive_get_field32(end_esmask
, end
->w1
);
1529 bool notify
= xive_esb_trigger(&pq
);
1531 if (pq
!= xive_get_field32(end_esmask
, end
->w1
)) {
1532 end
->w1
= xive_set_field32(end_esmask
, end
->w1
, pq
);
1533 xive_router_write_end(xrtr
, end_blk
, end_idx
, end
, 1);
1536 /* ESe/n[Q]=1 : end of notification */
1541 * An END trigger can come from an event trigger (IPI or HW) or from
1542 * another chip. We don't model the PowerBus but the END trigger
1543 * message has the same parameters than in the function below.
1545 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1546 uint32_t end_idx
, uint32_t end_data
)
1556 /* END cache lookup */
1557 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1558 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1563 if (!xive_end_is_valid(&end
)) {
1564 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1569 if (xive_end_is_enqueue(&end
)) {
1570 xive_end_enqueue(&end
, end_data
);
1571 /* Enqueuing event data modifies the EQ toggle and index */
1572 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1576 * When the END is silent, we skip the notification part.
1578 if (xive_end_is_silent_escalation(&end
)) {
1583 * The W7 format depends on the F bit in W6. It defines the type
1584 * of the notification :
1586 * F=0 : single or multiple NVT notification
1587 * F=1 : User level Event-Based Branch (EBB) notification, no
1590 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1591 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1593 /* The END is masked */
1594 if (format
== 0 && priority
== 0xff) {
1599 * Check the END ESn (Event State Buffer for notification) for
1600 * even further coalescing in the Router
1602 if (!xive_end_is_notify(&end
)) {
1603 /* ESn[Q]=1 : end of notification */
1604 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1605 &end
, END_W1_ESn
)) {
1611 * Follows IVPE notification
1613 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
);
1614 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
.w6
);
1616 /* NVT cache lookup */
1617 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1618 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1623 if (!xive_nvt_is_valid(&nvt
)) {
1624 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1629 found
= xive_presenter_notify(xrtr
->xfb
, format
, nvt_blk
, nvt_idx
,
1630 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1632 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1634 /* TODO: Auto EOI. */
1641 * If no matching NVT is dispatched on a HW thread :
1642 * - specific VP: update the NVT structure if backlog is activated
1643 * - logical server : forward request to IVPE (not supported)
1645 if (xive_end_is_backlog(&end
)) {
1649 qemu_log_mask(LOG_GUEST_ERROR
,
1650 "XIVE: END %x/%x invalid config: F1 & backlog\n",
1655 * Record the IPB in the associated NVT structure for later
1656 * use. The presenter will resend the interrupt when the vCPU
1657 * is dispatched again on a HW thread.
1659 ipb
= xive_get_field32(NVT_W4_IPB
, nvt
.w4
) | priority_to_ipb(priority
);
1660 nvt
.w4
= xive_set_field32(NVT_W4_IPB
, nvt
.w4
, ipb
);
1661 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1664 * On HW, follows a "Broadcast Backlog" to IVPEs
1670 * If activated, escalate notification using the ESe PQ bits and
1673 if (!xive_end_is_escalate(&end
)) {
1678 * Check the END ESe (Event State Buffer for escalation) for even
1679 * further coalescing in the Router
1681 if (!xive_end_is_uncond_escalation(&end
)) {
1682 /* ESe[Q]=1 : end of notification */
1683 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1684 &end
, END_W1_ESe
)) {
1690 * The END trigger becomes an Escalation trigger
1692 xive_router_end_notify(xrtr
,
1693 xive_get_field32(END_W4_ESC_END_BLOCK
, end
.w4
),
1694 xive_get_field32(END_W4_ESC_END_INDEX
, end
.w4
),
1695 xive_get_field32(END_W5_ESC_END_DATA
, end
.w5
));
1698 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1700 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1701 uint8_t eas_blk
= XIVE_EAS_BLOCK(lisn
);
1702 uint32_t eas_idx
= XIVE_EAS_INDEX(lisn
);
1705 /* EAS cache lookup */
1706 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1707 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1712 * The IVRE checks the State Bit Cache at this point. We skip the
1713 * SBC lookup because the state bits of the sources are modeled
1714 * internally in QEMU.
1717 if (!xive_eas_is_valid(&eas
)) {
1718 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1722 if (xive_eas_is_masked(&eas
)) {
1723 /* Notification completed */
1728 * The event trigger becomes an END trigger
1730 xive_router_end_notify(xrtr
,
1731 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1732 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1733 xive_get_field64(EAS_END_DATA
, eas
.w
));
1736 static Property xive_router_properties
[] = {
1737 DEFINE_PROP_LINK("xive-fabric", XiveRouter
, xfb
,
1738 TYPE_XIVE_FABRIC
, XiveFabric
*),
1739 DEFINE_PROP_END_OF_LIST(),
1742 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1744 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1745 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1747 dc
->desc
= "XIVE Router Engine";
1748 device_class_set_props(dc
, xive_router_properties
);
1749 /* Parent is SysBusDeviceClass. No need to call its realize hook */
1750 dc
->realize
= xive_router_realize
;
1751 xnc
->notify
= xive_router_notify
;
1754 static const TypeInfo xive_router_info
= {
1755 .name
= TYPE_XIVE_ROUTER
,
1756 .parent
= TYPE_SYS_BUS_DEVICE
,
1758 .instance_size
= sizeof(XiveRouter
),
1759 .class_size
= sizeof(XiveRouterClass
),
1760 .class_init
= xive_router_class_init
,
1761 .interfaces
= (InterfaceInfo
[]) {
1762 { TYPE_XIVE_NOTIFIER
},
1763 { TYPE_XIVE_PRESENTER
},
1768 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1770 if (!xive_eas_is_valid(eas
)) {
1774 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1775 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1776 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1777 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1778 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1782 * END ESB MMIO loads
1784 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1786 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1787 uint32_t offset
= addr
& 0xFFF;
1791 uint32_t end_esmask
;
1796 * The block id should be deduced from the load address on the END
1797 * ESB MMIO but our model only supports a single block per XIVE chip.
1799 end_blk
= xive_router_get_block_id(xsrc
->xrtr
);
1800 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1802 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1803 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1808 if (!xive_end_is_valid(&end
)) {
1809 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1814 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1815 pq
= xive_get_field32(end_esmask
, end
.w1
);
1818 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1819 ret
= xive_esb_eoi(&pq
);
1821 /* Forward the source event notification for routing ?? */
1824 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1828 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1829 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1830 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1831 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1832 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1835 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1840 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1841 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1842 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1849 * END ESB MMIO stores are invalid
1851 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1852 uint64_t value
, unsigned size
)
1854 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1855 HWADDR_PRIx
"\n", addr
);
1858 static const MemoryRegionOps xive_end_source_ops
= {
1859 .read
= xive_end_source_read
,
1860 .write
= xive_end_source_write
,
1861 .endianness
= DEVICE_BIG_ENDIAN
,
1863 .min_access_size
= 8,
1864 .max_access_size
= 8,
1867 .min_access_size
= 8,
1868 .max_access_size
= 8,
1872 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1874 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1878 if (!xsrc
->nr_ends
) {
1879 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1883 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1884 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1885 error_setg(errp
, "Invalid ESB shift setting");
1890 * Each END is assigned an even/odd pair of MMIO pages, the even page
1891 * manages the ESn field while the odd page manages the ESe field.
1893 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1894 &xive_end_source_ops
, xsrc
, "xive.end",
1895 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1898 static Property xive_end_source_properties
[] = {
1899 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1900 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1901 DEFINE_PROP_LINK("xive", XiveENDSource
, xrtr
, TYPE_XIVE_ROUTER
,
1903 DEFINE_PROP_END_OF_LIST(),
1906 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1908 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1910 dc
->desc
= "XIVE END Source";
1911 device_class_set_props(dc
, xive_end_source_properties
);
1912 dc
->realize
= xive_end_source_realize
;
1914 * Reason: part of XIVE interrupt controller, needs to be wired up,
1915 * e.g. by spapr_xive_instance_init().
1917 dc
->user_creatable
= false;
1920 static const TypeInfo xive_end_source_info
= {
1921 .name
= TYPE_XIVE_END_SOURCE
,
1922 .parent
= TYPE_DEVICE
,
1923 .instance_size
= sizeof(XiveENDSource
),
1924 .class_init
= xive_end_source_class_init
,
1930 static const TypeInfo xive_notifier_info
= {
1931 .name
= TYPE_XIVE_NOTIFIER
,
1932 .parent
= TYPE_INTERFACE
,
1933 .class_size
= sizeof(XiveNotifierClass
),
1939 static const TypeInfo xive_presenter_info
= {
1940 .name
= TYPE_XIVE_PRESENTER
,
1941 .parent
= TYPE_INTERFACE
,
1942 .class_size
= sizeof(XivePresenterClass
),
1948 static const TypeInfo xive_fabric_info
= {
1949 .name
= TYPE_XIVE_FABRIC
,
1950 .parent
= TYPE_INTERFACE
,
1951 .class_size
= sizeof(XiveFabricClass
),
1954 static void xive_register_types(void)
1956 type_register_static(&xive_fabric_info
);
1957 type_register_static(&xive_source_info
);
1958 type_register_static(&xive_notifier_info
);
1959 type_register_static(&xive_presenter_info
);
1960 type_register_static(&xive_router_info
);
1961 type_register_static(&xive_end_source_info
);
1962 type_register_static(&xive_tctx_info
);
1965 type_init(xive_register_types
)