include/hw/net/allwinner_emac.h

   1 /*
   2  * Emulation of Allwinner EMAC Fast Ethernet controller and
   3  * Realtek RTL8201CP PHY
   4  *
   5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   6  *
   7  * Allwinner EMAC register definitions from Linux kernel are:
   8  *   Copyright 2012 Stefan Roese <sr@denx.de>
   9  *   Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
  10  *   Copyright 1997 Sten Wang
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22
  23 #ifndef ALLWINNER_EMAC_H
  24 #define ALLWINNER_EMAC_H
  25
  26 #include "net/net.h"
  27 #include "qemu/fifo8.h"
  28 #include "hw/net/mii.h"
  29
  30 #define TYPE_AW_EMAC "allwinner-emac"
  31 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
  32
  33 /*
  34  * Allwinner EMAC register list
  35  */
  36 #define EMAC_CTL_REG            0x00
  37
  38 #define EMAC_TX_MODE_REG        0x04
  39 #define EMAC_TX_FLOW_REG        0x08
  40 #define EMAC_TX_CTL0_REG        0x0C
  41 #define EMAC_TX_CTL1_REG        0x10
  42 #define EMAC_TX_INS_REG         0x14
  43 #define EMAC_TX_PL0_REG         0x18
  44 #define EMAC_TX_PL1_REG         0x1C
  45 #define EMAC_TX_STA_REG         0x20
  46 #define EMAC_TX_IO_DATA_REG     0x24
  47 #define EMAC_TX_IO_DATA1_REG    0x28
  48 #define EMAC_TX_TSVL0_REG       0x2C
  49 #define EMAC_TX_TSVH0_REG       0x30
  50 #define EMAC_TX_TSVL1_REG       0x34
  51 #define EMAC_TX_TSVH1_REG       0x38
  52
  53 #define EMAC_RX_CTL_REG         0x3C
  54 #define EMAC_RX_HASH0_REG       0x40
  55 #define EMAC_RX_HASH1_REG       0x44
  56 #define EMAC_RX_STA_REG         0x48
  57 #define EMAC_RX_IO_DATA_REG     0x4C
  58 #define EMAC_RX_FBC_REG         0x50
  59
  60 #define EMAC_INT_CTL_REG        0x54
  61 #define EMAC_INT_STA_REG        0x58
  62
  63 #define EMAC_MAC_CTL0_REG       0x5C
  64 #define EMAC_MAC_CTL1_REG       0x60
  65 #define EMAC_MAC_IPGT_REG       0x64
  66 #define EMAC_MAC_IPGR_REG       0x68
  67 #define EMAC_MAC_CLRT_REG       0x6C
  68 #define EMAC_MAC_MAXF_REG       0x70
  69 #define EMAC_MAC_SUPP_REG       0x74
  70 #define EMAC_MAC_TEST_REG       0x78
  71 #define EMAC_MAC_MCFG_REG       0x7C
  72 #define EMAC_MAC_MCMD_REG       0x80
  73 #define EMAC_MAC_MADR_REG       0x84
  74 #define EMAC_MAC_MWTD_REG       0x88
  75 #define EMAC_MAC_MRDD_REG       0x8C
  76 #define EMAC_MAC_MIND_REG       0x90
  77 #define EMAC_MAC_SSRR_REG       0x94
  78 #define EMAC_MAC_A0_REG         0x98
  79 #define EMAC_MAC_A1_REG         0x9C
  80 #define EMAC_MAC_A2_REG         0xA0
  81
  82 #define EMAC_SAFX_L_REG0        0xA4
  83 #define EMAC_SAFX_H_REG0        0xA8
  84 #define EMAC_SAFX_L_REG1        0xAC
  85 #define EMAC_SAFX_H_REG1        0xB0
  86 #define EMAC_SAFX_L_REG2        0xB4
  87 #define EMAC_SAFX_H_REG2        0xB8
  88 #define EMAC_SAFX_L_REG3        0xBC
  89 #define EMAC_SAFX_H_REG3        0xC0
  90
  91 /* CTL register fields */
  92 #define EMAC_CTL_RESET                  (1 << 0)
  93 #define EMAC_CTL_TX_EN                  (1 << 1)
  94 #define EMAC_CTL_RX_EN                  (1 << 2)
  95
  96 /* TX MODE register fields */
  97 #define EMAC_TX_MODE_ABORTED_FRAME_EN   (1 << 0)
  98 #define EMAC_TX_MODE_DMA_EN             (1 << 1)
  99
 100 /* RX CTL register fields */
 101 #define EMAC_RX_CTL_AUTO_DRQ_EN         (1 << 1)
 102 #define EMAC_RX_CTL_DMA_EN              (1 << 2)
 103 #define EMAC_RX_CTL_PASS_ALL_EN         (1 << 4)
 104 #define EMAC_RX_CTL_PASS_CTL_EN         (1 << 5)
 105 #define EMAC_RX_CTL_PASS_CRC_ERR_EN     (1 << 6)
 106 #define EMAC_RX_CTL_PASS_LEN_ERR_EN     (1 << 7)
 107 #define EMAC_RX_CTL_PASS_LEN_OOR_EN     (1 << 8)
 108 #define EMAC_RX_CTL_ACCEPT_UNICAST_EN   (1 << 16)
 109 #define EMAC_RX_CTL_DA_FILTER_EN        (1 << 17)
 110 #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20)
 111 #define EMAC_RX_CTL_HASH_FILTER_EN      (1 << 21)
 112 #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22)
 113 #define EMAC_RX_CTL_SA_FILTER_EN        (1 << 24)
 114 #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25)
 115
 116 /* RX IO DATA register fields */
 117 #define EMAC_RX_HEADER(len, status)     (((len) & 0xffff) | ((status) << 16))
 118 #define EMAC_RX_IO_DATA_STATUS_CRC_ERR  (1 << 4)
 119 #define EMAC_RX_IO_DATA_STATUS_LEN_ERR  (3 << 5)
 120 #define EMAC_RX_IO_DATA_STATUS_OK       (1 << 7)
 121 #define EMAC_UNDOCUMENTED_MAGIC         0x0143414d  /* header for RX frames */
 122
 123 /* INT CTL and INT STA registers fields */
 124 #define EMAC_INT_TX_CHAN(x) (1 << (x))
 125 #define EMAC_INT_RX         (1 << 8)
 126
 127 /* Due to lack of specifications, size of fifos is chosen arbitrarily */
 128 #define TX_FIFO_SIZE        (4 * 1024)
 129 #define RX_FIFO_SIZE        (32 * 1024)
 130
 131 #define NUM_TX_FIFOS        2
 132 #define RX_HDR_SIZE         8
 133 #define CRC_SIZE            4
 134
 135 #define PHY_REG_SHIFT       0
 136 #define PHY_ADDR_SHIFT      8
 137
 138 typedef struct RTL8201CPState {
 139     uint16_t bmcr;
 140     uint16_t bmsr;
 141     uint16_t anar;
 142     uint16_t anlpar;
 143 } RTL8201CPState;
 144
 145 typedef struct AwEmacState {
 146     /*< private >*/
 147     SysBusDevice  parent_obj;
 148     /*< public >*/
 149
 150     MemoryRegion   iomem;
 151     qemu_irq       irq;
 152     NICState       *nic;
 153     NICConf        conf;
 154     RTL8201CPState mii;
 155     uint8_t        phy_addr;
 156
 157     uint32_t       ctl;
 158     uint32_t       tx_mode;
 159     uint32_t       rx_ctl;
 160     uint32_t       int_ctl;
 161     uint32_t       int_sta;
 162     uint32_t       phy_target;
 163
 164     Fifo8          rx_fifo;
 165     uint32_t       rx_num_packets;
 166     uint32_t       rx_packet_size;
 167     uint32_t       rx_packet_pos;
 168
 169     Fifo8          tx_fifo[NUM_TX_FIFOS];
 170     uint32_t       tx_length[NUM_TX_FIFOS];
 171     uint32_t       tx_channel;
 172 } AwEmacState;
 173
 174 #endif