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target/avr: Ignore unimplemented WDR opcode
[qemu/ar7.git] / softmmu / memory.c
blob3bb533c0bced344eab16b23b8cce79e002b7f038
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/log.h"
18 #include "qapi/error.h"
19 #include "exec/memory.h"
20 #include "qapi/visitor.h"
21 #include "qemu/bitops.h"
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
24 #include "qemu/qemu-print.h"
25 #include "qom/object.h"
26 #include "trace.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/runstate.h"
32 #include "sysemu/tcg.h"
33 #include "qemu/accel.h"
34 #include "hw/boards.h"
35 #include "migration/vmstate.h"
36
37 //#define DEBUG_UNASSIGNED
38
39 static unsigned memory_region_transaction_depth;
40 static bool memory_region_update_pending;
41 static bool ioeventfd_update_pending;
42 bool global_dirty_log;
43
44 static QTAILQ_HEAD(, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
46
47 static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
50 static GHashTable *flat_views;
51
52 typedef struct AddrRange AddrRange;
53
54 /*
55 * Note that signed integers are needed for negative offsetting in aliases
56 * (large MemoryRegion::alias_offset).
57 */
58 struct AddrRange {
59 Int128 start;
60 Int128 size;
61 };
62
63 static AddrRange addrrange_make(Int128 start, Int128 size)
64 {
65 return (AddrRange) { start, size };
66 }
67
68 static bool addrrange_equal(AddrRange r1, AddrRange r2)
69 {
70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
71 }
72
73 static Int128 addrrange_end(AddrRange r)
74 {
75 return int128_add(r.start, r.size);
76 }
77
78 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
79 {
80 int128_addto(&range.start, delta);
81 return range;
82 }
83
84 static bool addrrange_contains(AddrRange range, Int128 addr)
85 {
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88 }
89
90 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91 {
92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
94 }
95
96 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97 {
98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
101 }
102
103 enum ListenerDirection { Forward, Reverse };
104
105 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
129 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
130 do { \
131 MemoryListener *_listener; \
132 \
133 switch (_direction) { \
134 case Forward: \
135 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
136 if (_listener->_callback) { \
137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
142 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
143 if (_listener->_callback) { \
144 _listener->_callback(_listener, _section, ##_args); \
145 } \
146 } \
147 break; \
148 default: \
149 abort(); \
150 } \
151 } while (0)
152
153 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
154 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
155 do { \
156 MemoryRegionSection mrs = section_from_flat_range(fr, \
157 address_space_to_flatview(as)); \
158 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
159 } while(0)
160
161 struct CoalescedMemoryRange {
162 AddrRange addr;
163 QTAILQ_ENTRY(CoalescedMemoryRange) link;
164 };
165
166 struct MemoryRegionIoeventfd {
167 AddrRange addr;
168 bool match_data;
169 uint64_t data;
170 EventNotifier *e;
171 };
172
173 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
174 MemoryRegionIoeventfd *b)
175 {
176 if (int128_lt(a->addr.start, b->addr.start)) {
177 return true;
178 } else if (int128_gt(a->addr.start, b->addr.start)) {
179 return false;
180 } else if (int128_lt(a->addr.size, b->addr.size)) {
181 return true;
182 } else if (int128_gt(a->addr.size, b->addr.size)) {
183 return false;
184 } else if (a->match_data < b->match_data) {
185 return true;
186 } else if (a->match_data > b->match_data) {
187 return false;
188 } else if (a->match_data) {
189 if (a->data < b->data) {
190 return true;
191 } else if (a->data > b->data) {
192 return false;
193 }
194 }
195 if (a->e < b->e) {
196 return true;
197 } else if (a->e > b->e) {
198 return false;
199 }
200 return false;
201 }
202
203 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
204 MemoryRegionIoeventfd *b)
205 {
206 if (int128_eq(a->addr.start, b->addr.start) &&
207 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
208 (int128_eq(a->addr.size, b->addr.size) &&
209 (a->match_data == b->match_data) &&
210 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
211 (a->e == b->e))))
212 return true;
213
214 return false;
215 }
216
217 /* Range of memory in the global map. Addresses are absolute. */
218 struct FlatRange {
219 MemoryRegion *mr;
220 hwaddr offset_in_region;
221 AddrRange addr;
222 uint8_t dirty_log_mask;
223 bool romd_mode;
224 bool readonly;
225 bool nonvolatile;
226 };
227
228 #define FOR_EACH_FLAT_RANGE(var, view) \
229 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
230
231 static inline MemoryRegionSection
232 section_from_flat_range(FlatRange *fr, FlatView *fv)
233 {
234 return (MemoryRegionSection) {
235 .mr = fr->mr,
236 .fv = fv,
237 .offset_within_region = fr->offset_in_region,
238 .size = fr->addr.size,
239 .offset_within_address_space = int128_get64(fr->addr.start),
240 .readonly = fr->readonly,
241 .nonvolatile = fr->nonvolatile,
242 };
243 }
244
245 static bool flatrange_equal(FlatRange *a, FlatRange *b)
246 {
247 return a->mr == b->mr
248 && addrrange_equal(a->addr, b->addr)
249 && a->offset_in_region == b->offset_in_region
250 && a->romd_mode == b->romd_mode
251 && a->readonly == b->readonly
252 && a->nonvolatile == b->nonvolatile;
253 }
254
255 static FlatView *flatview_new(MemoryRegion *mr_root)
256 {
257 FlatView *view;
258
259 view = g_new0(FlatView, 1);
260 view->ref = 1;
261 view->root = mr_root;
262 memory_region_ref(mr_root);
263 trace_flatview_new(view, mr_root);
264
265 return view;
266 }
267
268 /* Insert a range into a given position. Caller is responsible for maintaining
269 * sorting order.
270 */
271 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
272 {
273 if (view->nr == view->nr_allocated) {
274 view->nr_allocated = MAX(2 * view->nr, 10);
275 view->ranges = g_realloc(view->ranges,
276 view->nr_allocated * sizeof(*view->ranges));
277 }
278 memmove(view->ranges + pos + 1, view->ranges + pos,
279 (view->nr - pos) * sizeof(FlatRange));
280 view->ranges[pos] = *range;
281 memory_region_ref(range->mr);
282 ++view->nr;
283 }
284
285 static void flatview_destroy(FlatView *view)
286 {
287 int i;
288
289 trace_flatview_destroy(view, view->root);
290 if (view->dispatch) {
291 address_space_dispatch_free(view->dispatch);
292 }
293 for (i = 0; i < view->nr; i++) {
294 memory_region_unref(view->ranges[i].mr);
295 }
296 g_free(view->ranges);
297 memory_region_unref(view->root);
298 g_free(view);
299 }
300
301 static bool flatview_ref(FlatView *view)
302 {
303 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
304 }
305
306 void flatview_unref(FlatView *view)
307 {
308 if (qatomic_fetch_dec(&view->ref) == 1) {
309 trace_flatview_destroy_rcu(view, view->root);
310 assert(view->root);
311 call_rcu(view, flatview_destroy, rcu);
312 }
313 }
314
315 static bool can_merge(FlatRange *r1, FlatRange *r2)
316 {
317 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
318 && r1->mr == r2->mr
319 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
320 r1->addr.size),
321 int128_make64(r2->offset_in_region))
322 && r1->dirty_log_mask == r2->dirty_log_mask
323 && r1->romd_mode == r2->romd_mode
324 && r1->readonly == r2->readonly
325 && r1->nonvolatile == r2->nonvolatile;
326 }
327
328 /* Attempt to simplify a view by merging adjacent ranges */
329 static void flatview_simplify(FlatView *view)
330 {
331 unsigned i, j, k;
332
333 i = 0;
334 while (i < view->nr) {
335 j = i + 1;
336 while (j < view->nr
337 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
338 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
339 ++j;
340 }
341 ++i;
342 for (k = i; k < j; k++) {
343 memory_region_unref(view->ranges[k].mr);
344 }
345 memmove(&view->ranges[i], &view->ranges[j],
346 (view->nr - j) * sizeof(view->ranges[j]));
347 view->nr -= j - i;
348 }
349 }
350
351 static bool memory_region_big_endian(MemoryRegion *mr)
352 {
353 #ifdef TARGET_WORDS_BIGENDIAN
354 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
355 #else
356 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
357 #endif
358 }
359
360 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
361 {
362 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
363 switch (op & MO_SIZE) {
364 case MO_8:
365 break;
366 case MO_16:
367 *data = bswap16(*data);
368 break;
369 case MO_32:
370 *data = bswap32(*data);
371 break;
372 case MO_64:
373 *data = bswap64(*data);
374 break;
375 default:
376 g_assert_not_reached();
377 }
378 }
379 }
380
381 static inline void memory_region_shift_read_access(uint64_t *value,
382 signed shift,
383 uint64_t mask,
384 uint64_t tmp)
385 {
386 if (shift >= 0) {
387 *value |= (tmp & mask) << shift;
388 } else {
389 *value |= (tmp & mask) >> -shift;
390 }
391 }
392
393 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
394 signed shift,
395 uint64_t mask)
396 {
397 uint64_t tmp;
398
399 if (shift >= 0) {
400 tmp = (*value >> shift) & mask;
401 } else {
402 tmp = (*value << -shift) & mask;
403 }
404
405 return tmp;
406 }
407
408 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
409 {
410 MemoryRegion *root;
411 hwaddr abs_addr = offset;
412
413 abs_addr += mr->addr;
414 for (root = mr; root->container; ) {
415 root = root->container;
416 abs_addr += root->addr;
417 }
418
419 return abs_addr;
420 }
421
422 static int get_cpu_index(void)
423 {
424 if (current_cpu) {
425 return current_cpu->cpu_index;
426 }
427 return -1;
428 }
429
430 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
431 hwaddr addr,
432 uint64_t *value,
433 unsigned size,
434 signed shift,
435 uint64_t mask,
436 MemTxAttrs attrs)
437 {
438 uint64_t tmp;
439
440 tmp = mr->ops->read(mr->opaque, addr, size);
441 if (mr->subpage) {
442 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
443 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
444 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
445 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
446 }
447 memory_region_shift_read_access(value, shift, mask, tmp);
448 return MEMTX_OK;
449 }
450
451 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
452 hwaddr addr,
453 uint64_t *value,
454 unsigned size,
455 signed shift,
456 uint64_t mask,
457 MemTxAttrs attrs)
458 {
459 uint64_t tmp = 0;
460 MemTxResult r;
461
462 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
463 if (mr->subpage) {
464 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
465 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
466 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
467 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
468 }
469 memory_region_shift_read_access(value, shift, mask, tmp);
470 return r;
471 }
472
473 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
474 hwaddr addr,
475 uint64_t *value,
476 unsigned size,
477 signed shift,
478 uint64_t mask,
479 MemTxAttrs attrs)
480 {
481 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
482
483 if (mr->subpage) {
484 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
485 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
486 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
487 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
488 }
489 mr->ops->write(mr->opaque, addr, tmp, size);
490 return MEMTX_OK;
491 }
492
493 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
494 hwaddr addr,
495 uint64_t *value,
496 unsigned size,
497 signed shift,
498 uint64_t mask,
499 MemTxAttrs attrs)
500 {
501 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
502
503 if (mr->subpage) {
504 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
505 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
506 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
507 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
508 }
509 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
510 }
511
512 static MemTxResult access_with_adjusted_size(hwaddr addr,
513 uint64_t *value,
514 unsigned size,
515 unsigned access_size_min,
516 unsigned access_size_max,
517 MemTxResult (*access_fn)
518 (MemoryRegion *mr,
519 hwaddr addr,
520 uint64_t *value,
521 unsigned size,
522 signed shift,
523 uint64_t mask,
524 MemTxAttrs attrs),
525 MemoryRegion *mr,
526 MemTxAttrs attrs)
527 {
528 uint64_t access_mask;
529 unsigned access_size;
530 unsigned i;
531 MemTxResult r = MEMTX_OK;
532
533 if (!access_size_min) {
534 access_size_min = 1;
535 }
536 if (!access_size_max) {
537 access_size_max = 4;
538 }
539
540 /* FIXME: support unaligned access? */
541 access_size = MAX(MIN(size, access_size_max), access_size_min);
542 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
543 if (memory_region_big_endian(mr)) {
544 for (i = 0; i < size; i += access_size) {
545 r |= access_fn(mr, addr + i, value, access_size,
546 (size - access_size - i) * 8, access_mask, attrs);
547 }
548 } else {
549 for (i = 0; i < size; i += access_size) {
550 r |= access_fn(mr, addr + i, value, access_size, i * 8,
551 access_mask, attrs);
552 }
553 }
554 return r;
555 }
556
557 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
558 {
559 AddressSpace *as;
560
561 while (mr->container) {
562 mr = mr->container;
563 }
564 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
565 if (mr == as->root) {
566 return as;
567 }
568 }
569 return NULL;
570 }
571
572 /* Render a memory region into the global view. Ranges in @view obscure
573 * ranges in @mr.
574 */
575 static void render_memory_region(FlatView *view,
576 MemoryRegion *mr,
577 Int128 base,
578 AddrRange clip,
579 bool readonly,
580 bool nonvolatile)
581 {
582 MemoryRegion *subregion;
583 unsigned i;
584 hwaddr offset_in_region;
585 Int128 remain;
586 Int128 now;
587 FlatRange fr;
588 AddrRange tmp;
589
590 if (!mr->enabled) {
591 return;
592 }
593
594 int128_addto(&base, int128_make64(mr->addr));
595 readonly |= mr->readonly;
596 nonvolatile |= mr->nonvolatile;
597
598 tmp = addrrange_make(base, mr->size);
599
600 if (!addrrange_intersects(tmp, clip)) {
601 return;
602 }
603
604 clip = addrrange_intersection(tmp, clip);
605
606 if (mr->alias) {
607 int128_subfrom(&base, int128_make64(mr->alias->addr));
608 int128_subfrom(&base, int128_make64(mr->alias_offset));
609 render_memory_region(view, mr->alias, base, clip,
610 readonly, nonvolatile);
611 return;
612 }
613
614 /* Render subregions in priority order. */
615 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
616 render_memory_region(view, subregion, base, clip,
617 readonly, nonvolatile);
618 }
619
620 if (!mr->terminates) {
621 return;
622 }
623
624 offset_in_region = int128_get64(int128_sub(clip.start, base));
625 base = clip.start;
626 remain = clip.size;
627
628 fr.mr = mr;
629 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
630 fr.romd_mode = mr->romd_mode;
631 fr.readonly = readonly;
632 fr.nonvolatile = nonvolatile;
633
634 /* Render the region itself into any gaps left by the current view. */
635 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
636 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
637 continue;
638 }
639 if (int128_lt(base, view->ranges[i].addr.start)) {
640 now = int128_min(remain,
641 int128_sub(view->ranges[i].addr.start, base));
642 fr.offset_in_region = offset_in_region;
643 fr.addr = addrrange_make(base, now);
644 flatview_insert(view, i, &fr);
645 ++i;
646 int128_addto(&base, now);
647 offset_in_region += int128_get64(now);
648 int128_subfrom(&remain, now);
649 }
650 now = int128_sub(int128_min(int128_add(base, remain),
651 addrrange_end(view->ranges[i].addr)),
652 base);
653 int128_addto(&base, now);
654 offset_in_region += int128_get64(now);
655 int128_subfrom(&remain, now);
656 }
657 if (int128_nz(remain)) {
658 fr.offset_in_region = offset_in_region;
659 fr.addr = addrrange_make(base, remain);
660 flatview_insert(view, i, &fr);
661 }
662 }
663
664 void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
665 {
666 FlatRange *fr;
667
668 assert(fv);
669 assert(cb);
670
671 FOR_EACH_FLAT_RANGE(fr, fv) {
672 if (cb(fr->addr.start, fr->addr.size, fr->mr,
673 fr->offset_in_region, opaque)) {
674 break;
675 }
676 }
677 }
678
679 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
680 {
681 while (mr->enabled) {
682 if (mr->alias) {
683 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
684 /* The alias is included in its entirety. Use it as
685 * the "real" root, so that we can share more FlatViews.
686 */
687 mr = mr->alias;
688 continue;
689 }
690 } else if (!mr->terminates) {
691 unsigned int found = 0;
692 MemoryRegion *child, *next = NULL;
693 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
694 if (child->enabled) {
695 if (++found > 1) {
696 next = NULL;
697 break;
698 }
699 if (!child->addr && int128_ge(mr->size, child->size)) {
700 /* A child is included in its entirety. If it's the only
701 * enabled one, use it in the hope of finding an alias down the
702 * way. This will also let us share FlatViews.
703 */
704 next = child;
705 }
706 }
707 }
708 if (found == 0) {
709 return NULL;
710 }
711 if (next) {
712 mr = next;
713 continue;
714 }
715 }
716
717 return mr;
718 }
719
720 return NULL;
721 }
722
723 /* Render a memory topology into a list of disjoint absolute ranges. */
724 static FlatView *generate_memory_topology(MemoryRegion *mr)
725 {
726 int i;
727 FlatView *view;
728
729 view = flatview_new(mr);
730
731 if (mr) {
732 render_memory_region(view, mr, int128_zero(),
733 addrrange_make(int128_zero(), int128_2_64()),
734 false, false);
735 }
736 flatview_simplify(view);
737
738 view->dispatch = address_space_dispatch_new(view);
739 for (i = 0; i < view->nr; i++) {
740 MemoryRegionSection mrs =
741 section_from_flat_range(&view->ranges[i], view);
742 flatview_add_to_dispatch(view, &mrs);
743 }
744 address_space_dispatch_compact(view->dispatch);
745 g_hash_table_replace(flat_views, mr, view);
746
747 return view;
748 }
749
750 static void address_space_add_del_ioeventfds(AddressSpace *as,
751 MemoryRegionIoeventfd *fds_new,
752 unsigned fds_new_nb,
753 MemoryRegionIoeventfd *fds_old,
754 unsigned fds_old_nb)
755 {
756 unsigned iold, inew;
757 MemoryRegionIoeventfd *fd;
758 MemoryRegionSection section;
759
760 /* Generate a symmetric difference of the old and new fd sets, adding
761 * and deleting as necessary.
762 */
763
764 iold = inew = 0;
765 while (iold < fds_old_nb || inew < fds_new_nb) {
766 if (iold < fds_old_nb
767 && (inew == fds_new_nb
768 || memory_region_ioeventfd_before(&fds_old[iold],
769 &fds_new[inew]))) {
770 fd = &fds_old[iold];
771 section = (MemoryRegionSection) {
772 .fv = address_space_to_flatview(as),
773 .offset_within_address_space = int128_get64(fd->addr.start),
774 .size = fd->addr.size,
775 };
776 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
777 fd->match_data, fd->data, fd->e);
778 ++iold;
779 } else if (inew < fds_new_nb
780 && (iold == fds_old_nb
781 || memory_region_ioeventfd_before(&fds_new[inew],
782 &fds_old[iold]))) {
783 fd = &fds_new[inew];
784 section = (MemoryRegionSection) {
785 .fv = address_space_to_flatview(as),
786 .offset_within_address_space = int128_get64(fd->addr.start),
787 .size = fd->addr.size,
788 };
789 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
790 fd->match_data, fd->data, fd->e);
791 ++inew;
792 } else {
793 ++iold;
794 ++inew;
795 }
796 }
797 }
798
799 FlatView *address_space_get_flatview(AddressSpace *as)
800 {
801 FlatView *view;
802
803 RCU_READ_LOCK_GUARD();
804 do {
805 view = address_space_to_flatview(as);
806 /* If somebody has replaced as->current_map concurrently,
807 * flatview_ref returns false.
808 */
809 } while (!flatview_ref(view));
810 return view;
811 }
812
813 static void address_space_update_ioeventfds(AddressSpace *as)
814 {
815 FlatView *view;
816 FlatRange *fr;
817 unsigned ioeventfd_nb = 0;
818 unsigned ioeventfd_max;
819 MemoryRegionIoeventfd *ioeventfds;
820 AddrRange tmp;
821 unsigned i;
822
823 /*
824 * It is likely that the number of ioeventfds hasn't changed much, so use
825 * the previous size as the starting value, with some headroom to avoid
826 * gratuitous reallocations.
827 */
828 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
829 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
830
831 view = address_space_get_flatview(as);
832 FOR_EACH_FLAT_RANGE(fr, view) {
833 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
834 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
835 int128_sub(fr->addr.start,
836 int128_make64(fr->offset_in_region)));
837 if (addrrange_intersects(fr->addr, tmp)) {
838 ++ioeventfd_nb;
839 if (ioeventfd_nb > ioeventfd_max) {
840 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
841 ioeventfds = g_realloc(ioeventfds,
842 ioeventfd_max * sizeof(*ioeventfds));
843 }
844 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
845 ioeventfds[ioeventfd_nb-1].addr = tmp;
846 }
847 }
848 }
849
850 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
851 as->ioeventfds, as->ioeventfd_nb);
852
853 g_free(as->ioeventfds);
854 as->ioeventfds = ioeventfds;
855 as->ioeventfd_nb = ioeventfd_nb;
856 flatview_unref(view);
857 }
858
859 /*
860 * Notify the memory listeners about the coalesced IO change events of
861 * range `cmr'. Only the part that has intersection of the specified
862 * FlatRange will be sent.
863 */
864 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
865 CoalescedMemoryRange *cmr, bool add)
866 {
867 AddrRange tmp;
868
869 tmp = addrrange_shift(cmr->addr,
870 int128_sub(fr->addr.start,
871 int128_make64(fr->offset_in_region)));
872 if (!addrrange_intersects(tmp, fr->addr)) {
873 return;
874 }
875 tmp = addrrange_intersection(tmp, fr->addr);
876
877 if (add) {
878 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
879 int128_get64(tmp.start),
880 int128_get64(tmp.size));
881 } else {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 }
886 }
887
888 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
889 {
890 CoalescedMemoryRange *cmr;
891
892 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
893 flat_range_coalesced_io_notify(fr, as, cmr, false);
894 }
895 }
896
897 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
898 {
899 MemoryRegion *mr = fr->mr;
900 CoalescedMemoryRange *cmr;
901
902 if (QTAILQ_EMPTY(&mr->coalesced)) {
903 return;
904 }
905
906 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
907 flat_range_coalesced_io_notify(fr, as, cmr, true);
908 }
909 }
910
911 static void address_space_update_topology_pass(AddressSpace *as,
912 const FlatView *old_view,
913 const FlatView *new_view,
914 bool adding)
915 {
916 unsigned iold, inew;
917 FlatRange *frold, *frnew;
918
919 /* Generate a symmetric difference of the old and new memory maps.
920 * Kill ranges in the old map, and instantiate ranges in the new map.
921 */
922 iold = inew = 0;
923 while (iold < old_view->nr || inew < new_view->nr) {
924 if (iold < old_view->nr) {
925 frold = &old_view->ranges[iold];
926 } else {
927 frold = NULL;
928 }
929 if (inew < new_view->nr) {
930 frnew = &new_view->ranges[inew];
931 } else {
932 frnew = NULL;
933 }
934
935 if (frold
936 && (!frnew
937 || int128_lt(frold->addr.start, frnew->addr.start)
938 || (int128_eq(frold->addr.start, frnew->addr.start)
939 && !flatrange_equal(frold, frnew)))) {
940 /* In old but not in new, or in both but attributes changed. */
941
942 if (!adding) {
943 flat_range_coalesced_io_del(frold, as);
944 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
945 }
946
947 ++iold;
948 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
949 /* In both and unchanged (except logging may have changed) */
950
951 if (adding) {
952 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
953 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
954 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
955 frold->dirty_log_mask,
956 frnew->dirty_log_mask);
957 }
958 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
959 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
960 frold->dirty_log_mask,
961 frnew->dirty_log_mask);
962 }
963 }
964
965 ++iold;
966 ++inew;
967 } else {
968 /* In new */
969
970 if (adding) {
971 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
972 flat_range_coalesced_io_add(frnew, as);
973 }
974
975 ++inew;
976 }
977 }
978 }
979
980 static void flatviews_init(void)
981 {
982 static FlatView *empty_view;
983
984 if (flat_views) {
985 return;
986 }
987
988 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
989 (GDestroyNotify) flatview_unref);
990 if (!empty_view) {
991 empty_view = generate_memory_topology(NULL);
992 /* We keep it alive forever in the global variable. */
993 flatview_ref(empty_view);
994 } else {
995 g_hash_table_replace(flat_views, NULL, empty_view);
996 flatview_ref(empty_view);
997 }
998 }
999
1000 static void flatviews_reset(void)
1001 {
1002 AddressSpace *as;
1003
1004 if (flat_views) {
1005 g_hash_table_unref(flat_views);
1006 flat_views = NULL;
1007 }
1008 flatviews_init();
1009
1010 /* Render unique FVs */
1011 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1012 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1013
1014 if (g_hash_table_lookup(flat_views, physmr)) {
1015 continue;
1016 }
1017
1018 generate_memory_topology(physmr);
1019 }
1020 }
1021
1022 static void address_space_set_flatview(AddressSpace *as)
1023 {
1024 FlatView *old_view = address_space_to_flatview(as);
1025 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1026 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1027
1028 assert(new_view);
1029
1030 if (old_view == new_view) {
1031 return;
1032 }
1033
1034 if (old_view) {
1035 flatview_ref(old_view);
1036 }
1037
1038 flatview_ref(new_view);
1039
1040 if (!QTAILQ_EMPTY(&as->listeners)) {
1041 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1042
1043 if (!old_view2) {
1044 old_view2 = &tmpview;
1045 }
1046 address_space_update_topology_pass(as, old_view2, new_view, false);
1047 address_space_update_topology_pass(as, old_view2, new_view, true);
1048 }
1049
1050 /* Writes are protected by the BQL. */
1051 qatomic_rcu_set(&as->current_map, new_view);
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
1055
1056 /* Note that all the old MemoryRegions are still alive up to this
1057 * point. This relieves most MemoryListeners from the need to
1058 * ref/unref the MemoryRegions they get---unless they use them
1059 * outside the iothread mutex, in which case precise reference
1060 * counting is necessary.
1061 */
1062 if (old_view) {
1063 flatview_unref(old_view);
1064 }
1065 }
1066
1067 static void address_space_update_topology(AddressSpace *as)
1068 {
1069 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1070
1071 flatviews_init();
1072 if (!g_hash_table_lookup(flat_views, physmr)) {
1073 generate_memory_topology(physmr);
1074 }
1075 address_space_set_flatview(as);
1076 }
1077
1078 void memory_region_transaction_begin(void)
1079 {
1080 qemu_flush_coalesced_mmio_buffer();
1081 ++memory_region_transaction_depth;
1082 }
1083
1084 void memory_region_transaction_commit(void)
1085 {
1086 AddressSpace *as;
1087
1088 assert(memory_region_transaction_depth);
1089 assert(qemu_mutex_iothread_locked());
1090
1091 --memory_region_transaction_depth;
1092 if (!memory_region_transaction_depth) {
1093 if (memory_region_update_pending) {
1094 flatviews_reset();
1095
1096 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1097
1098 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1099 address_space_set_flatview(as);
1100 address_space_update_ioeventfds(as);
1101 }
1102 memory_region_update_pending = false;
1103 ioeventfd_update_pending = false;
1104 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1105 } else if (ioeventfd_update_pending) {
1106 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1107 address_space_update_ioeventfds(as);
1108 }
1109 ioeventfd_update_pending = false;
1110 }
1111 }
1112 }
1113
1114 static void memory_region_destructor_none(MemoryRegion *mr)
1115 {
1116 }
1117
1118 static void memory_region_destructor_ram(MemoryRegion *mr)
1119 {
1120 qemu_ram_free(mr->ram_block);
1121 }
1122
1123 static bool memory_region_need_escape(char c)
1124 {
1125 return c == '/' || c == '[' || c == '\\' || c == ']';
1126 }
1127
1128 static char *memory_region_escape_name(const char *name)
1129 {
1130 const char *p;
1131 char *escaped, *q;
1132 uint8_t c;
1133 size_t bytes = 0;
1134
1135 for (p = name; *p; p++) {
1136 bytes += memory_region_need_escape(*p) ? 4 : 1;
1137 }
1138 if (bytes == p - name) {
1139 return g_memdup(name, bytes + 1);
1140 }
1141
1142 escaped = g_malloc(bytes + 1);
1143 for (p = name, q = escaped; *p; p++) {
1144 c = *p;
1145 if (unlikely(memory_region_need_escape(c))) {
1146 *q++ = '\\';
1147 *q++ = 'x';
1148 *q++ = "0123456789abcdef"[c >> 4];
1149 c = "0123456789abcdef"[c & 15];
1150 }
1151 *q++ = c;
1152 }
1153 *q = 0;
1154 return escaped;
1155 }
1156
1157 static void memory_region_do_init(MemoryRegion *mr,
1158 Object *owner,
1159 const char *name,
1160 uint64_t size)
1161 {
1162 mr->size = int128_make64(size);
1163 if (size == UINT64_MAX) {
1164 mr->size = int128_2_64();
1165 }
1166 mr->name = g_strdup(name);
1167 mr->owner = owner;
1168 mr->ram_block = NULL;
1169
1170 if (name) {
1171 char *escaped_name = memory_region_escape_name(name);
1172 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1173
1174 if (!owner) {
1175 owner = container_get(qdev_get_machine(), "/unattached");
1176 }
1177
1178 object_property_add_child(owner, name_array, OBJECT(mr));
1179 object_unref(OBJECT(mr));
1180 g_free(name_array);
1181 g_free(escaped_name);
1182 }
1183 }
1184
1185 void memory_region_init(MemoryRegion *mr,
1186 Object *owner,
1187 const char *name,
1188 uint64_t size)
1189 {
1190 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1191 memory_region_do_init(mr, owner, name, size);
1192 }
1193
1194 static void memory_region_get_container(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
1197 {
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 char *path = (char *)"";
1200
1201 if (mr->container) {
1202 path = object_get_canonical_path(OBJECT(mr->container));
1203 }
1204 visit_type_str(v, name, &path, errp);
1205 if (mr->container) {
1206 g_free(path);
1207 }
1208 }
1209
1210 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1211 const char *part)
1212 {
1213 MemoryRegion *mr = MEMORY_REGION(obj);
1214
1215 return OBJECT(mr->container);
1216 }
1217
1218 static void memory_region_get_priority(Object *obj, Visitor *v,
1219 const char *name, void *opaque,
1220 Error **errp)
1221 {
1222 MemoryRegion *mr = MEMORY_REGION(obj);
1223 int32_t value = mr->priority;
1224
1225 visit_type_int32(v, name, &value, errp);
1226 }
1227
1228 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1229 void *opaque, Error **errp)
1230 {
1231 MemoryRegion *mr = MEMORY_REGION(obj);
1232 uint64_t value = memory_region_size(mr);
1233
1234 visit_type_uint64(v, name, &value, errp);
1235 }
1236
1237 static void memory_region_initfn(Object *obj)
1238 {
1239 MemoryRegion *mr = MEMORY_REGION(obj);
1240 ObjectProperty *op;
1241
1242 mr->ops = &unassigned_mem_ops;
1243 mr->enabled = true;
1244 mr->romd_mode = true;
1245 mr->destructor = memory_region_destructor_none;
1246 QTAILQ_INIT(&mr->subregions);
1247 QTAILQ_INIT(&mr->coalesced);
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add_uint64_ptr(OBJECT(mr), "addr",
1257 &mr->addr, OBJ_PROP_FLAG_READ);
1258 object_property_add(OBJECT(mr), "priority", "uint32",
1259 memory_region_get_priority,
1260 NULL, /* memory_region_set_priority */
1261 NULL, NULL);
1262 object_property_add(OBJECT(mr), "size", "uint64",
1263 memory_region_get_size,
1264 NULL, /* memory_region_set_size, */
1265 NULL, NULL);
1266 }
1267
1268 static void iommu_memory_region_initfn(Object *obj)
1269 {
1270 MemoryRegion *mr = MEMORY_REGION(obj);
1271
1272 mr->is_iommu = true;
1273 }
1274
1275 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1276 unsigned size)
1277 {
1278 #ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1280 #endif
1281 return 0;
1282 }
1283
1284 static void unassigned_mem_write(void *opaque, hwaddr addr,
1285 uint64_t val, unsigned size)
1286 {
1287 #ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1289 #endif
1290 }
1291
1292 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1293 unsigned size, bool is_write,
1294 MemTxAttrs attrs)
1295 {
1296 return false;
1297 }
1298
1299 const MemoryRegionOps unassigned_mem_ops = {
1300 .valid.accepts = unassigned_mem_accepts,
1301 .endianness = DEVICE_NATIVE_ENDIAN,
1302 };
1303
1304 static uint64_t memory_region_ram_device_read(void *opaque,
1305 hwaddr addr, unsigned size)
1306 {
1307 MemoryRegion *mr = opaque;
1308 uint64_t data = (uint64_t)~0;
1309
1310 switch (size) {
1311 case 1:
1312 data = *(uint8_t *)(mr->ram_block->host + addr);
1313 break;
1314 case 2:
1315 data = *(uint16_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 4:
1318 data = *(uint32_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 8:
1321 data = *(uint64_t *)(mr->ram_block->host + addr);
1322 break;
1323 }
1324
1325 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1326
1327 return data;
1328 }
1329
1330 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1331 uint64_t data, unsigned size)
1332 {
1333 MemoryRegion *mr = opaque;
1334
1335 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1336
1337 switch (size) {
1338 case 1:
1339 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1340 break;
1341 case 2:
1342 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1343 break;
1344 case 4:
1345 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1346 break;
1347 case 8:
1348 *(uint64_t *)(mr->ram_block->host + addr) = data;
1349 break;
1350 }
1351 }
1352
1353 static const MemoryRegionOps ram_device_mem_ops = {
1354 .read = memory_region_ram_device_read,
1355 .write = memory_region_ram_device_write,
1356 .endianness = DEVICE_HOST_ENDIAN,
1357 .valid = {
1358 .min_access_size = 1,
1359 .max_access_size = 8,
1360 .unaligned = true,
1361 },
1362 .impl = {
1363 .min_access_size = 1,
1364 .max_access_size = 8,
1365 .unaligned = true,
1366 },
1367 };
1368
1369 bool memory_region_access_valid(MemoryRegion *mr,
1370 hwaddr addr,
1371 unsigned size,
1372 bool is_write,
1373 MemTxAttrs attrs)
1374 {
1375 if (mr->ops->valid.accepts
1376 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
1377 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1378 "0x%" HWADDR_PRIX ", size %u, "
1379 "region '%s', reason: rejected\n",
1380 addr, size, memory_region_name(mr));
1381 return false;
1382 }
1383
1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1386 "0x%" HWADDR_PRIX ", size %u, "
1387 "region '%s', reason: unaligned\n",
1388 addr, size, memory_region_name(mr));
1389 return false;
1390 }
1391
1392 /* Treat zero as compatibility all valid */
1393 if (!mr->ops->valid.max_access_size) {
1394 return true;
1395 }
1396
1397 if (size > mr->ops->valid.max_access_size
1398 || size < mr->ops->valid.min_access_size) {
1399 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1400 "0x%" HWADDR_PRIX ", size %u, "
1401 "region '%s', reason: invalid size "
1402 "(min:%u max:%u)\n",
1403 addr, size, memory_region_name(mr),
1404 mr->ops->valid.min_access_size,
1405 mr->ops->valid.max_access_size);
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t *pval,
1414 unsigned size,
1415 MemTxAttrs attrs)
1416 {
1417 *pval = 0;
1418
1419 if (mr->ops->read) {
1420 return access_with_adjusted_size(addr, pval, size,
1421 mr->ops->impl.min_access_size,
1422 mr->ops->impl.max_access_size,
1423 memory_region_read_accessor,
1424 mr, attrs);
1425 } else {
1426 return access_with_adjusted_size(addr, pval, size,
1427 mr->ops->impl.min_access_size,
1428 mr->ops->impl.max_access_size,
1429 memory_region_read_with_attrs_accessor,
1430 mr, attrs);
1431 }
1432 }
1433
1434 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
1437 MemOp op,
1438 MemTxAttrs attrs)
1439 {
1440 unsigned size = memop_size(op);
1441 MemTxResult r;
1442
1443 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1444 *pval = unassigned_mem_read(mr, addr, size);
1445 return MEMTX_DECODE_ERROR;
1446 }
1447
1448 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1449 adjust_endianness(mr, pval, op);
1450 return r;
1451 }
1452
1453 /* Return true if an eventfd was signalled */
1454 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1455 hwaddr addr,
1456 uint64_t data,
1457 unsigned size,
1458 MemTxAttrs attrs)
1459 {
1460 MemoryRegionIoeventfd ioeventfd = {
1461 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1462 .data = data,
1463 };
1464 unsigned i;
1465
1466 for (i = 0; i < mr->ioeventfd_nb; i++) {
1467 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1468 ioeventfd.e = mr->ioeventfds[i].e;
1469
1470 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1471 event_notifier_set(ioeventfd.e);
1472 return true;
1473 }
1474 }
1475
1476 return false;
1477 }
1478
1479 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1480 hwaddr addr,
1481 uint64_t data,
1482 MemOp op,
1483 MemTxAttrs attrs)
1484 {
1485 unsigned size = memop_size(op);
1486
1487 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1488 unassigned_mem_write(mr, addr, data, size);
1489 return MEMTX_DECODE_ERROR;
1490 }
1491
1492 adjust_endianness(mr, &data, op);
1493
1494 if ((!kvm_eventfds_enabled()) &&
1495 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1496 return MEMTX_OK;
1497 }
1498
1499 if (mr->ops->write) {
1500 return access_with_adjusted_size(addr, &data, size,
1501 mr->ops->impl.min_access_size,
1502 mr->ops->impl.max_access_size,
1503 memory_region_write_accessor, mr,
1504 attrs);
1505 } else {
1506 return
1507 access_with_adjusted_size(addr, &data, size,
1508 mr->ops->impl.min_access_size,
1509 mr->ops->impl.max_access_size,
1510 memory_region_write_with_attrs_accessor,
1511 mr, attrs);
1512 }
1513 }
1514
1515 void memory_region_init_io(MemoryRegion *mr,
1516 Object *owner,
1517 const MemoryRegionOps *ops,
1518 void *opaque,
1519 const char *name,
1520 uint64_t size)
1521 {
1522 memory_region_init(mr, owner, name, size);
1523 mr->ops = ops ? ops : &unassigned_mem_ops;
1524 mr->opaque = opaque;
1525 mr->terminates = true;
1526 }
1527
1528 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1529 Object *owner,
1530 const char *name,
1531 uint64_t size,
1532 Error **errp)
1533 {
1534 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1535 }
1536
1537 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1538 Object *owner,
1539 const char *name,
1540 uint64_t size,
1541 bool share,
1542 Error **errp)
1543 {
1544 Error *err = NULL;
1545 memory_region_init(mr, owner, name, size);
1546 mr->ram = true;
1547 mr->terminates = true;
1548 mr->destructor = memory_region_destructor_ram;
1549 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1550 if (err) {
1551 mr->size = int128_zero();
1552 object_unparent(OBJECT(mr));
1553 error_propagate(errp, err);
1554 }
1555 }
1556
1557 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1558 Object *owner,
1559 const char *name,
1560 uint64_t size,
1561 uint64_t max_size,
1562 void (*resized)(const char*,
1563 uint64_t length,
1564 void *host),
1565 Error **errp)
1566 {
1567 Error *err = NULL;
1568 memory_region_init(mr, owner, name, size);
1569 mr->ram = true;
1570 mr->terminates = true;
1571 mr->destructor = memory_region_destructor_ram;
1572 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1573 mr, &err);
1574 if (err) {
1575 mr->size = int128_zero();
1576 object_unparent(OBJECT(mr));
1577 error_propagate(errp, err);
1578 }
1579 }
1580
1581 #ifdef CONFIG_POSIX
1582 void memory_region_init_ram_from_file(MemoryRegion *mr,
1583 Object *owner,
1584 const char *name,
1585 uint64_t size,
1586 uint64_t align,
1587 uint32_t ram_flags,
1588 const char *path,
1589 bool readonly,
1590 Error **errp)
1591 {
1592 Error *err = NULL;
1593 memory_region_init(mr, owner, name, size);
1594 mr->ram = true;
1595 mr->readonly = readonly;
1596 mr->terminates = true;
1597 mr->destructor = memory_region_destructor_ram;
1598 mr->align = align;
1599 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path,
1600 readonly, &err);
1601 if (err) {
1602 mr->size = int128_zero();
1603 object_unparent(OBJECT(mr));
1604 error_propagate(errp, err);
1605 }
1606 }
1607
1608 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1609 Object *owner,
1610 const char *name,
1611 uint64_t size,
1612 bool share,
1613 int fd,
1614 ram_addr_t offset,
1615 Error **errp)
1616 {
1617 Error *err = NULL;
1618 memory_region_init(mr, owner, name, size);
1619 mr->ram = true;
1620 mr->terminates = true;
1621 mr->destructor = memory_region_destructor_ram;
1622 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1623 share ? RAM_SHARED : 0,
1624 fd, offset, false, &err);
1625 if (err) {
1626 mr->size = int128_zero();
1627 object_unparent(OBJECT(mr));
1628 error_propagate(errp, err);
1629 }
1630 }
1631 #endif
1632
1633 void memory_region_init_ram_ptr(MemoryRegion *mr,
1634 Object *owner,
1635 const char *name,
1636 uint64_t size,
1637 void *ptr)
1638 {
1639 memory_region_init(mr, owner, name, size);
1640 mr->ram = true;
1641 mr->terminates = true;
1642 mr->destructor = memory_region_destructor_ram;
1643
1644 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1645 assert(ptr != NULL);
1646 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1647 }
1648
1649 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1650 Object *owner,
1651 const char *name,
1652 uint64_t size,
1653 void *ptr)
1654 {
1655 memory_region_init(mr, owner, name, size);
1656 mr->ram = true;
1657 mr->terminates = true;
1658 mr->ram_device = true;
1659 mr->ops = &ram_device_mem_ops;
1660 mr->opaque = mr;
1661 mr->destructor = memory_region_destructor_ram;
1662
1663 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1664 assert(ptr != NULL);
1665 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1666 }
1667
1668 void memory_region_init_alias(MemoryRegion *mr,
1669 Object *owner,
1670 const char *name,
1671 MemoryRegion *orig,
1672 hwaddr offset,
1673 uint64_t size)
1674 {
1675 memory_region_init(mr, owner, name, size);
1676 mr->alias = orig;
1677 mr->alias_offset = offset;
1678 }
1679
1680 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1681 Object *owner,
1682 const char *name,
1683 uint64_t size,
1684 Error **errp)
1685 {
1686 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1687 mr->readonly = true;
1688 }
1689
1690 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1691 Object *owner,
1692 const MemoryRegionOps *ops,
1693 void *opaque,
1694 const char *name,
1695 uint64_t size,
1696 Error **errp)
1697 {
1698 Error *err = NULL;
1699 assert(ops);
1700 memory_region_init(mr, owner, name, size);
1701 mr->ops = ops;
1702 mr->opaque = opaque;
1703 mr->terminates = true;
1704 mr->rom_device = true;
1705 mr->destructor = memory_region_destructor_ram;
1706 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1707 if (err) {
1708 mr->size = int128_zero();
1709 object_unparent(OBJECT(mr));
1710 error_propagate(errp, err);
1711 }
1712 }
1713
1714 void memory_region_init_iommu(void *_iommu_mr,
1715 size_t instance_size,
1716 const char *mrtypename,
1717 Object *owner,
1718 const char *name,
1719 uint64_t size)
1720 {
1721 struct IOMMUMemoryRegion *iommu_mr;
1722 struct MemoryRegion *mr;
1723
1724 object_initialize(_iommu_mr, instance_size, mrtypename);
1725 mr = MEMORY_REGION(_iommu_mr);
1726 memory_region_do_init(mr, owner, name, size);
1727 iommu_mr = IOMMU_MEMORY_REGION(mr);
1728 mr->terminates = true; /* then re-forwards */
1729 QLIST_INIT(&iommu_mr->iommu_notify);
1730 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1731 }
1732
1733 static void memory_region_finalize(Object *obj)
1734 {
1735 MemoryRegion *mr = MEMORY_REGION(obj);
1736
1737 assert(!mr->container);
1738
1739 /* We know the region is not visible in any address space (it
1740 * does not have a container and cannot be a root either because
1741 * it has no references, so we can blindly clear mr->enabled.
1742 * memory_region_set_enabled instead could trigger a transaction
1743 * and cause an infinite loop.
1744 */
1745 mr->enabled = false;
1746 memory_region_transaction_begin();
1747 while (!QTAILQ_EMPTY(&mr->subregions)) {
1748 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1749 memory_region_del_subregion(mr, subregion);
1750 }
1751 memory_region_transaction_commit();
1752
1753 mr->destructor(mr);
1754 memory_region_clear_coalescing(mr);
1755 g_free((char *)mr->name);
1756 g_free(mr->ioeventfds);
1757 }
1758
1759 Object *memory_region_owner(MemoryRegion *mr)
1760 {
1761 Object *obj = OBJECT(mr);
1762 return obj->parent;
1763 }
1764
1765 void memory_region_ref(MemoryRegion *mr)
1766 {
1767 /* MMIO callbacks most likely will access data that belongs
1768 * to the owner, hence the need to ref/unref the owner whenever
1769 * the memory region is in use.
1770 *
1771 * The memory region is a child of its owner. As long as the
1772 * owner doesn't call unparent itself on the memory region,
1773 * ref-ing the owner will also keep the memory region alive.
1774 * Memory regions without an owner are supposed to never go away;
1775 * we do not ref/unref them because it slows down DMA sensibly.
1776 */
1777 if (mr && mr->owner) {
1778 object_ref(mr->owner);
1779 }
1780 }
1781
1782 void memory_region_unref(MemoryRegion *mr)
1783 {
1784 if (mr && mr->owner) {
1785 object_unref(mr->owner);
1786 }
1787 }
1788
1789 uint64_t memory_region_size(MemoryRegion *mr)
1790 {
1791 if (int128_eq(mr->size, int128_2_64())) {
1792 return UINT64_MAX;
1793 }
1794 return int128_get64(mr->size);
1795 }
1796
1797 const char *memory_region_name(const MemoryRegion *mr)
1798 {
1799 if (!mr->name) {
1800 ((MemoryRegion *)mr)->name =
1801 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
1802 }
1803 return mr->name;
1804 }
1805
1806 bool memory_region_is_ram_device(MemoryRegion *mr)
1807 {
1808 return mr->ram_device;
1809 }
1810
1811 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1812 {
1813 uint8_t mask = mr->dirty_log_mask;
1814 RAMBlock *rb = mr->ram_block;
1815
1816 if (global_dirty_log && ((rb && qemu_ram_is_migratable(rb)) ||
1817 memory_region_is_iommu(mr))) {
1818 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1819 }
1820
1821 if (tcg_enabled() && rb) {
1822 /* TCG only cares about dirty memory logging for RAM, not IOMMU. */
1823 mask |= (1 << DIRTY_MEMORY_CODE);
1824 }
1825 return mask;
1826 }
1827
1828 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1829 {
1830 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1831 }
1832
1833 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1834 Error **errp)
1835 {
1836 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1837 IOMMUNotifier *iommu_notifier;
1838 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1839 int ret = 0;
1840
1841 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1842 flags |= iommu_notifier->notifier_flags;
1843 }
1844
1845 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1846 ret = imrc->notify_flag_changed(iommu_mr,
1847 iommu_mr->iommu_notify_flags,
1848 flags, errp);
1849 }
1850
1851 if (!ret) {
1852 iommu_mr->iommu_notify_flags = flags;
1853 }
1854 return ret;
1855 }
1856
1857 int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1858 uint64_t page_size_mask,
1859 Error **errp)
1860 {
1861 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1862 int ret = 0;
1863
1864 if (imrc->iommu_set_page_size_mask) {
1865 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1866 }
1867 return ret;
1868 }
1869
1870 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1871 IOMMUNotifier *n, Error **errp)
1872 {
1873 IOMMUMemoryRegion *iommu_mr;
1874 int ret;
1875
1876 if (mr->alias) {
1877 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1878 }
1879
1880 /* We need to register for at least one bitfield */
1881 iommu_mr = IOMMU_MEMORY_REGION(mr);
1882 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1883 assert(n->start <= n->end);
1884 assert(n->iommu_idx >= 0 &&
1885 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1886
1887 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1888 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1889 if (ret) {
1890 QLIST_REMOVE(n, node);
1891 }
1892 return ret;
1893 }
1894
1895 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1896 {
1897 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1898
1899 if (imrc->get_min_page_size) {
1900 return imrc->get_min_page_size(iommu_mr);
1901 }
1902 return TARGET_PAGE_SIZE;
1903 }
1904
1905 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1906 {
1907 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1908 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1909 hwaddr addr, granularity;
1910 IOMMUTLBEntry iotlb;
1911
1912 /* If the IOMMU has its own replay callback, override */
1913 if (imrc->replay) {
1914 imrc->replay(iommu_mr, n);
1915 return;
1916 }
1917
1918 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1919
1920 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1921 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1922 if (iotlb.perm != IOMMU_NONE) {
1923 n->notify(n, &iotlb);
1924 }
1925
1926 /* if (2^64 - MR size) < granularity, it's possible to get an
1927 * infinite loop here. This should catch such a wraparound */
1928 if ((addr + granularity) < addr) {
1929 break;
1930 }
1931 }
1932 }
1933
1934 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1935 IOMMUNotifier *n)
1936 {
1937 IOMMUMemoryRegion *iommu_mr;
1938
1939 if (mr->alias) {
1940 memory_region_unregister_iommu_notifier(mr->alias, n);
1941 return;
1942 }
1943 QLIST_REMOVE(n, node);
1944 iommu_mr = IOMMU_MEMORY_REGION(mr);
1945 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1946 }
1947
1948 void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
1949 IOMMUTLBEvent *event)
1950 {
1951 IOMMUTLBEntry *entry = &event->entry;
1952 hwaddr entry_end = entry->iova + entry->addr_mask;
1953 IOMMUTLBEntry tmp = *entry;
1954
1955 if (event->type == IOMMU_NOTIFIER_UNMAP) {
1956 assert(entry->perm == IOMMU_NONE);
1957 }
1958
1959 /*
1960 * Skip the notification if the notification does not overlap
1961 * with registered range.
1962 */
1963 if (notifier->start > entry_end || notifier->end < entry->iova) {
1964 return;
1965 }
1966
1967 if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
1968 /* Crop (iova, addr_mask) to range */
1969 tmp.iova = MAX(tmp.iova, notifier->start);
1970 tmp.addr_mask = MIN(entry_end, notifier->end) - tmp.iova;
1971 } else {
1972 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1973 }
1974
1975 if (event->type & notifier->notifier_flags) {
1976 notifier->notify(notifier, &tmp);
1977 }
1978 }
1979
1980 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1981 int iommu_idx,
1982 IOMMUTLBEvent event)
1983 {
1984 IOMMUNotifier *iommu_notifier;
1985
1986 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1987
1988 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1989 if (iommu_notifier->iommu_idx == iommu_idx) {
1990 memory_region_notify_iommu_one(iommu_notifier, &event);
1991 }
1992 }
1993 }
1994
1995 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1996 enum IOMMUMemoryRegionAttr attr,
1997 void *data)
1998 {
1999 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2000
2001 if (!imrc->get_attr) {
2002 return -EINVAL;
2003 }
2004
2005 return imrc->get_attr(iommu_mr, attr, data);
2006 }
2007
2008 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2009 MemTxAttrs attrs)
2010 {
2011 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2012
2013 if (!imrc->attrs_to_index) {
2014 return 0;
2015 }
2016
2017 return imrc->attrs_to_index(iommu_mr, attrs);
2018 }
2019
2020 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2021 {
2022 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2023
2024 if (!imrc->num_indexes) {
2025 return 1;
2026 }
2027
2028 return imrc->num_indexes(iommu_mr);
2029 }
2030
2031 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2032 {
2033 uint8_t mask = 1 << client;
2034 uint8_t old_logging;
2035
2036 assert(client == DIRTY_MEMORY_VGA);
2037 old_logging = mr->vga_logging_count;
2038 mr->vga_logging_count += log ? 1 : -1;
2039 if (!!old_logging == !!mr->vga_logging_count) {
2040 return;
2041 }
2042
2043 memory_region_transaction_begin();
2044 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2045 memory_region_update_pending |= mr->enabled;
2046 memory_region_transaction_commit();
2047 }
2048
2049 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2050 hwaddr size)
2051 {
2052 assert(mr->ram_block);
2053 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2054 size,
2055 memory_region_get_dirty_log_mask(mr));
2056 }
2057
2058 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2059 {
2060 MemoryListener *listener;
2061 AddressSpace *as;
2062 FlatView *view;
2063 FlatRange *fr;
2064
2065 /* If the same address space has multiple log_sync listeners, we
2066 * visit that address space's FlatView multiple times. But because
2067 * log_sync listeners are rare, it's still cheaper than walking each
2068 * address space once.
2069 */
2070 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2071 if (!listener->log_sync) {
2072 continue;
2073 }
2074 as = listener->address_space;
2075 view = address_space_get_flatview(as);
2076 FOR_EACH_FLAT_RANGE(fr, view) {
2077 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2078 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2079 listener->log_sync(listener, &mrs);
2080 }
2081 }
2082 flatview_unref(view);
2083 }
2084 }
2085
2086 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2087 hwaddr len)
2088 {
2089 MemoryRegionSection mrs;
2090 MemoryListener *listener;
2091 AddressSpace *as;
2092 FlatView *view;
2093 FlatRange *fr;
2094 hwaddr sec_start, sec_end, sec_size;
2095
2096 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2097 if (!listener->log_clear) {
2098 continue;
2099 }
2100 as = listener->address_space;
2101 view = address_space_get_flatview(as);
2102 FOR_EACH_FLAT_RANGE(fr, view) {
2103 if (!fr->dirty_log_mask || fr->mr != mr) {
2104 /*
2105 * Clear dirty bitmap operation only applies to those
2106 * regions whose dirty logging is at least enabled
2107 */
2108 continue;
2109 }
2110
2111 mrs = section_from_flat_range(fr, view);
2112
2113 sec_start = MAX(mrs.offset_within_region, start);
2114 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2115 sec_end = MIN(sec_end, start + len);
2116
2117 if (sec_start >= sec_end) {
2118 /*
2119 * If this memory region section has no intersection
2120 * with the requested range, skip.
2121 */
2122 continue;
2123 }
2124
2125 /* Valid case; shrink the section if needed */
2126 mrs.offset_within_address_space +=
2127 sec_start - mrs.offset_within_region;
2128 mrs.offset_within_region = sec_start;
2129 sec_size = sec_end - sec_start;
2130 mrs.size = int128_make64(sec_size);
2131 listener->log_clear(listener, &mrs);
2132 }
2133 flatview_unref(view);
2134 }
2135 }
2136
2137 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2138 hwaddr addr,
2139 hwaddr size,
2140 unsigned client)
2141 {
2142 DirtyBitmapSnapshot *snapshot;
2143 assert(mr->ram_block);
2144 memory_region_sync_dirty_bitmap(mr);
2145 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2146 memory_global_after_dirty_log_sync();
2147 return snapshot;
2148 }
2149
2150 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2151 hwaddr addr, hwaddr size)
2152 {
2153 assert(mr->ram_block);
2154 return cpu_physical_memory_snapshot_get_dirty(snap,
2155 memory_region_get_ram_addr(mr) + addr, size);
2156 }
2157
2158 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2159 {
2160 if (mr->readonly != readonly) {
2161 memory_region_transaction_begin();
2162 mr->readonly = readonly;
2163 memory_region_update_pending |= mr->enabled;
2164 memory_region_transaction_commit();
2165 }
2166 }
2167
2168 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2169 {
2170 if (mr->nonvolatile != nonvolatile) {
2171 memory_region_transaction_begin();
2172 mr->nonvolatile = nonvolatile;
2173 memory_region_update_pending |= mr->enabled;
2174 memory_region_transaction_commit();
2175 }
2176 }
2177
2178 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2179 {
2180 if (mr->romd_mode != romd_mode) {
2181 memory_region_transaction_begin();
2182 mr->romd_mode = romd_mode;
2183 memory_region_update_pending |= mr->enabled;
2184 memory_region_transaction_commit();
2185 }
2186 }
2187
2188 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2189 hwaddr size, unsigned client)
2190 {
2191 assert(mr->ram_block);
2192 cpu_physical_memory_test_and_clear_dirty(
2193 memory_region_get_ram_addr(mr) + addr, size, client);
2194 }
2195
2196 int memory_region_get_fd(MemoryRegion *mr)
2197 {
2198 int fd;
2199
2200 RCU_READ_LOCK_GUARD();
2201 while (mr->alias) {
2202 mr = mr->alias;
2203 }
2204 fd = mr->ram_block->fd;
2205
2206 return fd;
2207 }
2208
2209 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2210 {
2211 void *ptr;
2212 uint64_t offset = 0;
2213
2214 RCU_READ_LOCK_GUARD();
2215 while (mr->alias) {
2216 offset += mr->alias_offset;
2217 mr = mr->alias;
2218 }
2219 assert(mr->ram_block);
2220 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2221
2222 return ptr;
2223 }
2224
2225 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2226 {
2227 RAMBlock *block;
2228
2229 block = qemu_ram_block_from_host(ptr, false, offset);
2230 if (!block) {
2231 return NULL;
2232 }
2233
2234 return block->mr;
2235 }
2236
2237 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2238 {
2239 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2240 }
2241
2242 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2243 {
2244 assert(mr->ram_block);
2245
2246 qemu_ram_resize(mr->ram_block, newsize, errp);
2247 }
2248
2249 void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2250 {
2251 if (mr->ram_block) {
2252 qemu_ram_msync(mr->ram_block, addr, size);
2253 }
2254 }
2255
2256 void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
2257 {
2258 /*
2259 * Might be extended case needed to cover
2260 * different types of memory regions
2261 */
2262 if (mr->dirty_log_mask) {
2263 memory_region_msync(mr, addr, size);
2264 }
2265 }
2266
2267 /*
2268 * Call proper memory listeners about the change on the newly
2269 * added/removed CoalescedMemoryRange.
2270 */
2271 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2272 CoalescedMemoryRange *cmr,
2273 bool add)
2274 {
2275 AddressSpace *as;
2276 FlatView *view;
2277 FlatRange *fr;
2278
2279 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2280 view = address_space_get_flatview(as);
2281 FOR_EACH_FLAT_RANGE(fr, view) {
2282 if (fr->mr == mr) {
2283 flat_range_coalesced_io_notify(fr, as, cmr, add);
2284 }
2285 }
2286 flatview_unref(view);
2287 }
2288 }
2289
2290 void memory_region_set_coalescing(MemoryRegion *mr)
2291 {
2292 memory_region_clear_coalescing(mr);
2293 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2294 }
2295
2296 void memory_region_add_coalescing(MemoryRegion *mr,
2297 hwaddr offset,
2298 uint64_t size)
2299 {
2300 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2301
2302 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2303 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2304 memory_region_update_coalesced_range(mr, cmr, true);
2305 memory_region_set_flush_coalesced(mr);
2306 }
2307
2308 void memory_region_clear_coalescing(MemoryRegion *mr)
2309 {
2310 CoalescedMemoryRange *cmr;
2311
2312 if (QTAILQ_EMPTY(&mr->coalesced)) {
2313 return;
2314 }
2315
2316 qemu_flush_coalesced_mmio_buffer();
2317 mr->flush_coalesced_mmio = false;
2318
2319 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2320 cmr = QTAILQ_FIRST(&mr->coalesced);
2321 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2322 memory_region_update_coalesced_range(mr, cmr, false);
2323 g_free(cmr);
2324 }
2325 }
2326
2327 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2328 {
2329 mr->flush_coalesced_mmio = true;
2330 }
2331
2332 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2333 {
2334 qemu_flush_coalesced_mmio_buffer();
2335 if (QTAILQ_EMPTY(&mr->coalesced)) {
2336 mr->flush_coalesced_mmio = false;
2337 }
2338 }
2339
2340 static bool userspace_eventfd_warning;
2341
2342 void memory_region_add_eventfd(MemoryRegion *mr,
2343 hwaddr addr,
2344 unsigned size,
2345 bool match_data,
2346 uint64_t data,
2347 EventNotifier *e)
2348 {
2349 MemoryRegionIoeventfd mrfd = {
2350 .addr.start = int128_make64(addr),
2351 .addr.size = int128_make64(size),
2352 .match_data = match_data,
2353 .data = data,
2354 .e = e,
2355 };
2356 unsigned i;
2357
2358 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2359 userspace_eventfd_warning))) {
2360 userspace_eventfd_warning = true;
2361 error_report("Using eventfd without MMIO binding in KVM. "
2362 "Suboptimal performance expected");
2363 }
2364
2365 if (size) {
2366 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2367 }
2368 memory_region_transaction_begin();
2369 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2370 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2371 break;
2372 }
2373 }
2374 ++mr->ioeventfd_nb;
2375 mr->ioeventfds = g_realloc(mr->ioeventfds,
2376 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2377 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2378 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2379 mr->ioeventfds[i] = mrfd;
2380 ioeventfd_update_pending |= mr->enabled;
2381 memory_region_transaction_commit();
2382 }
2383
2384 void memory_region_del_eventfd(MemoryRegion *mr,
2385 hwaddr addr,
2386 unsigned size,
2387 bool match_data,
2388 uint64_t data,
2389 EventNotifier *e)
2390 {
2391 MemoryRegionIoeventfd mrfd = {
2392 .addr.start = int128_make64(addr),
2393 .addr.size = int128_make64(size),
2394 .match_data = match_data,
2395 .data = data,
2396 .e = e,
2397 };
2398 unsigned i;
2399
2400 if (size) {
2401 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2402 }
2403 memory_region_transaction_begin();
2404 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2405 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2406 break;
2407 }
2408 }
2409 assert(i != mr->ioeventfd_nb);
2410 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2411 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2412 --mr->ioeventfd_nb;
2413 mr->ioeventfds = g_realloc(mr->ioeventfds,
2414 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2415 ioeventfd_update_pending |= mr->enabled;
2416 memory_region_transaction_commit();
2417 }
2418
2419 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2420 {
2421 MemoryRegion *mr = subregion->container;
2422 MemoryRegion *other;
2423
2424 memory_region_transaction_begin();
2425
2426 memory_region_ref(subregion);
2427 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2428 if (subregion->priority >= other->priority) {
2429 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2430 goto done;
2431 }
2432 }
2433 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2434 done:
2435 memory_region_update_pending |= mr->enabled && subregion->enabled;
2436 memory_region_transaction_commit();
2437 }
2438
2439 static void memory_region_add_subregion_common(MemoryRegion *mr,
2440 hwaddr offset,
2441 MemoryRegion *subregion)
2442 {
2443 assert(!subregion->container);
2444 subregion->container = mr;
2445 subregion->addr = offset;
2446 memory_region_update_container_subregions(subregion);
2447 }
2448
2449 void memory_region_add_subregion(MemoryRegion *mr,
2450 hwaddr offset,
2451 MemoryRegion *subregion)
2452 {
2453 subregion->priority = 0;
2454 memory_region_add_subregion_common(mr, offset, subregion);
2455 }
2456
2457 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2458 hwaddr offset,
2459 MemoryRegion *subregion,
2460 int priority)
2461 {
2462 subregion->priority = priority;
2463 memory_region_add_subregion_common(mr, offset, subregion);
2464 }
2465
2466 void memory_region_del_subregion(MemoryRegion *mr,
2467 MemoryRegion *subregion)
2468 {
2469 memory_region_transaction_begin();
2470 assert(subregion->container == mr);
2471 subregion->container = NULL;
2472 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2473 memory_region_unref(subregion);
2474 memory_region_update_pending |= mr->enabled && subregion->enabled;
2475 memory_region_transaction_commit();
2476 }
2477
2478 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2479 {
2480 if (enabled == mr->enabled) {
2481 return;
2482 }
2483 memory_region_transaction_begin();
2484 mr->enabled = enabled;
2485 memory_region_update_pending = true;
2486 memory_region_transaction_commit();
2487 }
2488
2489 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2490 {
2491 Int128 s = int128_make64(size);
2492
2493 if (size == UINT64_MAX) {
2494 s = int128_2_64();
2495 }
2496 if (int128_eq(s, mr->size)) {
2497 return;
2498 }
2499 memory_region_transaction_begin();
2500 mr->size = s;
2501 memory_region_update_pending = true;
2502 memory_region_transaction_commit();
2503 }
2504
2505 static void memory_region_readd_subregion(MemoryRegion *mr)
2506 {
2507 MemoryRegion *container = mr->container;
2508
2509 if (container) {
2510 memory_region_transaction_begin();
2511 memory_region_ref(mr);
2512 memory_region_del_subregion(container, mr);
2513 mr->container = container;
2514 memory_region_update_container_subregions(mr);
2515 memory_region_unref(mr);
2516 memory_region_transaction_commit();
2517 }
2518 }
2519
2520 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2521 {
2522 if (addr != mr->addr) {
2523 mr->addr = addr;
2524 memory_region_readd_subregion(mr);
2525 }
2526 }
2527
2528 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2529 {
2530 assert(mr->alias);
2531
2532 if (offset == mr->alias_offset) {
2533 return;
2534 }
2535
2536 memory_region_transaction_begin();
2537 mr->alias_offset = offset;
2538 memory_region_update_pending |= mr->enabled;
2539 memory_region_transaction_commit();
2540 }
2541
2542 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2543 {
2544 return mr->align;
2545 }
2546
2547 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2548 {
2549 const AddrRange *addr = addr_;
2550 const FlatRange *fr = fr_;
2551
2552 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2553 return -1;
2554 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2555 return 1;
2556 }
2557 return 0;
2558 }
2559
2560 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2561 {
2562 return bsearch(&addr, view->ranges, view->nr,
2563 sizeof(FlatRange), cmp_flatrange_addr);
2564 }
2565
2566 bool memory_region_is_mapped(MemoryRegion *mr)
2567 {
2568 return mr->container ? true : false;
2569 }
2570
2571 /* Same as memory_region_find, but it does not add a reference to the
2572 * returned region. It must be called from an RCU critical section.
2573 */
2574 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2575 hwaddr addr, uint64_t size)
2576 {
2577 MemoryRegionSection ret = { .mr = NULL };
2578 MemoryRegion *root;
2579 AddressSpace *as;
2580 AddrRange range;
2581 FlatView *view;
2582 FlatRange *fr;
2583
2584 addr += mr->addr;
2585 for (root = mr; root->container; ) {
2586 root = root->container;
2587 addr += root->addr;
2588 }
2589
2590 as = memory_region_to_address_space(root);
2591 if (!as) {
2592 return ret;
2593 }
2594 range = addrrange_make(int128_make64(addr), int128_make64(size));
2595
2596 view = address_space_to_flatview(as);
2597 fr = flatview_lookup(view, range);
2598 if (!fr) {
2599 return ret;
2600 }
2601
2602 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2603 --fr;
2604 }
2605
2606 ret.mr = fr->mr;
2607 ret.fv = view;
2608 range = addrrange_intersection(range, fr->addr);
2609 ret.offset_within_region = fr->offset_in_region;
2610 ret.offset_within_region += int128_get64(int128_sub(range.start,
2611 fr->addr.start));
2612 ret.size = range.size;
2613 ret.offset_within_address_space = int128_get64(range.start);
2614 ret.readonly = fr->readonly;
2615 ret.nonvolatile = fr->nonvolatile;
2616 return ret;
2617 }
2618
2619 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2620 hwaddr addr, uint64_t size)
2621 {
2622 MemoryRegionSection ret;
2623 RCU_READ_LOCK_GUARD();
2624 ret = memory_region_find_rcu(mr, addr, size);
2625 if (ret.mr) {
2626 memory_region_ref(ret.mr);
2627 }
2628 return ret;
2629 }
2630
2631 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2632 {
2633 MemoryRegion *mr;
2634
2635 RCU_READ_LOCK_GUARD();
2636 mr = memory_region_find_rcu(container, addr, 1).mr;
2637 return mr && mr != container;
2638 }
2639
2640 void memory_global_dirty_log_sync(void)
2641 {
2642 memory_region_sync_dirty_bitmap(NULL);
2643 }
2644
2645 void memory_global_after_dirty_log_sync(void)
2646 {
2647 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2648 }
2649
2650 static VMChangeStateEntry *vmstate_change;
2651
2652 void memory_global_dirty_log_start(void)
2653 {
2654 if (vmstate_change) {
2655 qemu_del_vm_change_state_handler(vmstate_change);
2656 vmstate_change = NULL;
2657 }
2658
2659 global_dirty_log = true;
2660
2661 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2662
2663 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2664 memory_region_transaction_begin();
2665 memory_region_update_pending = true;
2666 memory_region_transaction_commit();
2667 }
2668
2669 static void memory_global_dirty_log_do_stop(void)
2670 {
2671 global_dirty_log = false;
2672
2673 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2674 memory_region_transaction_begin();
2675 memory_region_update_pending = true;
2676 memory_region_transaction_commit();
2677
2678 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2679 }
2680
2681 static void memory_vm_change_state_handler(void *opaque, bool running,
2682 RunState state)
2683 {
2684 if (running) {
2685 memory_global_dirty_log_do_stop();
2686
2687 if (vmstate_change) {
2688 qemu_del_vm_change_state_handler(vmstate_change);
2689 vmstate_change = NULL;
2690 }
2691 }
2692 }
2693
2694 void memory_global_dirty_log_stop(void)
2695 {
2696 if (!runstate_is_running()) {
2697 if (vmstate_change) {
2698 return;
2699 }
2700 vmstate_change = qemu_add_vm_change_state_handler(
2701 memory_vm_change_state_handler, NULL);
2702 return;
2703 }
2704
2705 memory_global_dirty_log_do_stop();
2706 }
2707
2708 static void listener_add_address_space(MemoryListener *listener,
2709 AddressSpace *as)
2710 {
2711 FlatView *view;
2712 FlatRange *fr;
2713
2714 if (listener->begin) {
2715 listener->begin(listener);
2716 }
2717 if (global_dirty_log) {
2718 if (listener->log_global_start) {
2719 listener->log_global_start(listener);
2720 }
2721 }
2722
2723 view = address_space_get_flatview(as);
2724 FOR_EACH_FLAT_RANGE(fr, view) {
2725 MemoryRegionSection section = section_from_flat_range(fr, view);
2726
2727 if (listener->region_add) {
2728 listener->region_add(listener, &section);
2729 }
2730 if (fr->dirty_log_mask && listener->log_start) {
2731 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2732 }
2733 }
2734 if (listener->commit) {
2735 listener->commit(listener);
2736 }
2737 flatview_unref(view);
2738 }
2739
2740 static void listener_del_address_space(MemoryListener *listener,
2741 AddressSpace *as)
2742 {
2743 FlatView *view;
2744 FlatRange *fr;
2745
2746 if (listener->begin) {
2747 listener->begin(listener);
2748 }
2749 view = address_space_get_flatview(as);
2750 FOR_EACH_FLAT_RANGE(fr, view) {
2751 MemoryRegionSection section = section_from_flat_range(fr, view);
2752
2753 if (fr->dirty_log_mask && listener->log_stop) {
2754 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2755 }
2756 if (listener->region_del) {
2757 listener->region_del(listener, &section);
2758 }
2759 }
2760 if (listener->commit) {
2761 listener->commit(listener);
2762 }
2763 flatview_unref(view);
2764 }
2765
2766 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2767 {
2768 MemoryListener *other = NULL;
2769
2770 listener->address_space = as;
2771 if (QTAILQ_EMPTY(&memory_listeners)
2772 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2773 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2774 } else {
2775 QTAILQ_FOREACH(other, &memory_listeners, link) {
2776 if (listener->priority < other->priority) {
2777 break;
2778 }
2779 }
2780 QTAILQ_INSERT_BEFORE(other, listener, link);
2781 }
2782
2783 if (QTAILQ_EMPTY(&as->listeners)
2784 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2785 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2786 } else {
2787 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2788 if (listener->priority < other->priority) {
2789 break;
2790 }
2791 }
2792 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2793 }
2794
2795 listener_add_address_space(listener, as);
2796 }
2797
2798 void memory_listener_unregister(MemoryListener *listener)
2799 {
2800 if (!listener->address_space) {
2801 return;
2802 }
2803
2804 listener_del_address_space(listener, listener->address_space);
2805 QTAILQ_REMOVE(&memory_listeners, listener, link);
2806 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2807 listener->address_space = NULL;
2808 }
2809
2810 void address_space_remove_listeners(AddressSpace *as)
2811 {
2812 while (!QTAILQ_EMPTY(&as->listeners)) {
2813 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2814 }
2815 }
2816
2817 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2818 {
2819 memory_region_ref(root);
2820 as->root = root;
2821 as->current_map = NULL;
2822 as->ioeventfd_nb = 0;
2823 as->ioeventfds = NULL;
2824 QTAILQ_INIT(&as->listeners);
2825 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2826 as->name = g_strdup(name ? name : "anonymous");
2827 address_space_update_topology(as);
2828 address_space_update_ioeventfds(as);
2829 }
2830
2831 static void do_address_space_destroy(AddressSpace *as)
2832 {
2833 assert(QTAILQ_EMPTY(&as->listeners));
2834
2835 flatview_unref(as->current_map);
2836 g_free(as->name);
2837 g_free(as->ioeventfds);
2838 memory_region_unref(as->root);
2839 }
2840
2841 void address_space_destroy(AddressSpace *as)
2842 {
2843 MemoryRegion *root = as->root;
2844
2845 /* Flush out anything from MemoryListeners listening in on this */
2846 memory_region_transaction_begin();
2847 as->root = NULL;
2848 memory_region_transaction_commit();
2849 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2850
2851 /* At this point, as->dispatch and as->current_map are dummy
2852 * entries that the guest should never use. Wait for the old
2853 * values to expire before freeing the data.
2854 */
2855 as->root = root;
2856 call_rcu(as, do_address_space_destroy, rcu);
2857 }
2858
2859 static const char *memory_region_type(MemoryRegion *mr)
2860 {
2861 if (mr->alias) {
2862 return memory_region_type(mr->alias);
2863 }
2864 if (memory_region_is_ram_device(mr)) {
2865 return "ramd";
2866 } else if (memory_region_is_romd(mr)) {
2867 return "romd";
2868 } else if (memory_region_is_rom(mr)) {
2869 return "rom";
2870 } else if (memory_region_is_ram(mr)) {
2871 return "ram";
2872 } else {
2873 return "i/o";
2874 }
2875 }
2876
2877 typedef struct MemoryRegionList MemoryRegionList;
2878
2879 struct MemoryRegionList {
2880 const MemoryRegion *mr;
2881 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2882 };
2883
2884 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2885
2886 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2887 int128_sub((size), int128_one())) : 0)
2888 #define MTREE_INDENT " "
2889
2890 static void mtree_expand_owner(const char *label, Object *obj)
2891 {
2892 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2893
2894 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2895 if (dev && dev->id) {
2896 qemu_printf(" id=%s", dev->id);
2897 } else {
2898 char *canonical_path = object_get_canonical_path(obj);
2899 if (canonical_path) {
2900 qemu_printf(" path=%s", canonical_path);
2901 g_free(canonical_path);
2902 } else {
2903 qemu_printf(" type=%s", object_get_typename(obj));
2904 }
2905 }
2906 qemu_printf("}");
2907 }
2908
2909 static void mtree_print_mr_owner(const MemoryRegion *mr)
2910 {
2911 Object *owner = mr->owner;
2912 Object *parent = memory_region_owner((MemoryRegion *)mr);
2913
2914 if (!owner && !parent) {
2915 qemu_printf(" orphan");
2916 return;
2917 }
2918 if (owner) {
2919 mtree_expand_owner("owner", owner);
2920 }
2921 if (parent && parent != owner) {
2922 mtree_expand_owner("parent", parent);
2923 }
2924 }
2925
2926 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2927 hwaddr base,
2928 MemoryRegionListHead *alias_print_queue,
2929 bool owner, bool display_disabled)
2930 {
2931 MemoryRegionList *new_ml, *ml, *next_ml;
2932 MemoryRegionListHead submr_print_queue;
2933 const MemoryRegion *submr;
2934 unsigned int i;
2935 hwaddr cur_start, cur_end;
2936
2937 if (!mr) {
2938 return;
2939 }
2940
2941 cur_start = base + mr->addr;
2942 cur_end = cur_start + MR_SIZE(mr->size);
2943
2944 /*
2945 * Try to detect overflow of memory region. This should never
2946 * happen normally. When it happens, we dump something to warn the
2947 * user who is observing this.
2948 */
2949 if (cur_start < base || cur_end < cur_start) {
2950 qemu_printf("[DETECTED OVERFLOW!] ");
2951 }
2952
2953 if (mr->alias) {
2954 MemoryRegionList *ml;
2955 bool found = false;
2956
2957 /* check if the alias is already in the queue */
2958 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2959 if (ml->mr == mr->alias) {
2960 found = true;
2961 }
2962 }
2963
2964 if (!found) {
2965 ml = g_new(MemoryRegionList, 1);
2966 ml->mr = mr->alias;
2967 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2968 }
2969 if (mr->enabled || display_disabled) {
2970 for (i = 0; i < level; i++) {
2971 qemu_printf(MTREE_INDENT);
2972 }
2973 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2974 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2975 "-" TARGET_FMT_plx "%s",
2976 cur_start, cur_end,
2977 mr->priority,
2978 mr->nonvolatile ? "nv-" : "",
2979 memory_region_type((MemoryRegion *)mr),
2980 memory_region_name(mr),
2981 memory_region_name(mr->alias),
2982 mr->alias_offset,
2983 mr->alias_offset + MR_SIZE(mr->size),
2984 mr->enabled ? "" : " [disabled]");
2985 if (owner) {
2986 mtree_print_mr_owner(mr);
2987 }
2988 qemu_printf("\n");
2989 }
2990 } else {
2991 if (mr->enabled || display_disabled) {
2992 for (i = 0; i < level; i++) {
2993 qemu_printf(MTREE_INDENT);
2994 }
2995 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2996 " (prio %d, %s%s): %s%s",
2997 cur_start, cur_end,
2998 mr->priority,
2999 mr->nonvolatile ? "nv-" : "",
3000 memory_region_type((MemoryRegion *)mr),
3001 memory_region_name(mr),
3002 mr->enabled ? "" : " [disabled]");
3003 if (owner) {
3004 mtree_print_mr_owner(mr);
3005 }
3006 qemu_printf("\n");
3007 }
3008 }
3009
3010 QTAILQ_INIT(&submr_print_queue);
3011
3012 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3013 new_ml = g_new(MemoryRegionList, 1);
3014 new_ml->mr = submr;
3015 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3016 if (new_ml->mr->addr < ml->mr->addr ||
3017 (new_ml->mr->addr == ml->mr->addr &&
3018 new_ml->mr->priority > ml->mr->priority)) {
3019 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3020 new_ml = NULL;
3021 break;
3022 }
3023 }
3024 if (new_ml) {
3025 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3026 }
3027 }
3028
3029 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3030 mtree_print_mr(ml->mr, level + 1, cur_start,
3031 alias_print_queue, owner, display_disabled);
3032 }
3033
3034 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3035 g_free(ml);
3036 }
3037 }
3038
3039 struct FlatViewInfo {
3040 int counter;
3041 bool dispatch_tree;
3042 bool owner;
3043 AccelClass *ac;
3044 };
3045
3046 static void mtree_print_flatview(gpointer key, gpointer value,
3047 gpointer user_data)
3048 {
3049 FlatView *view = key;
3050 GArray *fv_address_spaces = value;
3051 struct FlatViewInfo *fvi = user_data;
3052 FlatRange *range = &view->ranges[0];
3053 MemoryRegion *mr;
3054 int n = view->nr;
3055 int i;
3056 AddressSpace *as;
3057
3058 qemu_printf("FlatView #%d\n", fvi->counter);
3059 ++fvi->counter;
3060
3061 for (i = 0; i < fv_address_spaces->len; ++i) {
3062 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3063 qemu_printf(" AS \"%s\", root: %s",
3064 as->name, memory_region_name(as->root));
3065 if (as->root->alias) {
3066 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3067 }
3068 qemu_printf("\n");
3069 }
3070
3071 qemu_printf(" Root memory region: %s\n",
3072 view->root ? memory_region_name(view->root) : "(none)");
3073
3074 if (n <= 0) {
3075 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3076 return;
3077 }
3078
3079 while (n--) {
3080 mr = range->mr;
3081 if (range->offset_in_region) {
3082 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3083 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3084 int128_get64(range->addr.start),
3085 int128_get64(range->addr.start)
3086 + MR_SIZE(range->addr.size),
3087 mr->priority,
3088 range->nonvolatile ? "nv-" : "",
3089 range->readonly ? "rom" : memory_region_type(mr),
3090 memory_region_name(mr),
3091 range->offset_in_region);
3092 } else {
3093 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3094 " (prio %d, %s%s): %s",
3095 int128_get64(range->addr.start),
3096 int128_get64(range->addr.start)
3097 + MR_SIZE(range->addr.size),
3098 mr->priority,
3099 range->nonvolatile ? "nv-" : "",
3100 range->readonly ? "rom" : memory_region_type(mr),
3101 memory_region_name(mr));
3102 }
3103 if (fvi->owner) {
3104 mtree_print_mr_owner(mr);
3105 }
3106
3107 if (fvi->ac) {
3108 for (i = 0; i < fv_address_spaces->len; ++i) {
3109 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3110 if (fvi->ac->has_memory(current_machine, as,
3111 int128_get64(range->addr.start),
3112 MR_SIZE(range->addr.size) + 1)) {
3113 qemu_printf(" %s", fvi->ac->name);
3114 }
3115 }
3116 }
3117 qemu_printf("\n");
3118 range++;
3119 }
3120
3121 #if !defined(CONFIG_USER_ONLY)
3122 if (fvi->dispatch_tree && view->root) {
3123 mtree_print_dispatch(view->dispatch, view->root);
3124 }
3125 #endif
3126
3127 qemu_printf("\n");
3128 }
3129
3130 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3131 gpointer user_data)
3132 {
3133 FlatView *view = key;
3134 GArray *fv_address_spaces = value;
3135
3136 g_array_unref(fv_address_spaces);
3137 flatview_unref(view);
3138
3139 return true;
3140 }
3141
3142 void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
3143 {
3144 MemoryRegionListHead ml_head;
3145 MemoryRegionList *ml, *ml2;
3146 AddressSpace *as;
3147
3148 if (flatview) {
3149 FlatView *view;
3150 struct FlatViewInfo fvi = {
3151 .counter = 0,
3152 .dispatch_tree = dispatch_tree,
3153 .owner = owner,
3154 };
3155 GArray *fv_address_spaces;
3156 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3157 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
3158
3159 if (ac->has_memory) {
3160 fvi.ac = ac;
3161 }
3162
3163 /* Gather all FVs in one table */
3164 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3165 view = address_space_get_flatview(as);
3166
3167 fv_address_spaces = g_hash_table_lookup(views, view);
3168 if (!fv_address_spaces) {
3169 fv_address_spaces = g_array_new(false, false, sizeof(as));
3170 g_hash_table_insert(views, view, fv_address_spaces);
3171 }
3172
3173 g_array_append_val(fv_address_spaces, as);
3174 }
3175
3176 /* Print */
3177 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3178
3179 /* Free */
3180 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3181 g_hash_table_unref(views);
3182
3183 return;
3184 }
3185
3186 QTAILQ_INIT(&ml_head);
3187
3188 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3189 qemu_printf("address-space: %s\n", as->name);
3190 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
3191 qemu_printf("\n");
3192 }
3193
3194 /* print aliased regions */
3195 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3196 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3197 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
3198 qemu_printf("\n");
3199 }
3200
3201 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3202 g_free(ml);
3203 }
3204 }
3205
3206 void memory_region_init_ram(MemoryRegion *mr,
3207 Object *owner,
3208 const char *name,
3209 uint64_t size,
3210 Error **errp)
3211 {
3212 DeviceState *owner_dev;
3213 Error *err = NULL;
3214
3215 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3216 if (err) {
3217 error_propagate(errp, err);
3218 return;
3219 }
3220 /* This will assert if owner is neither NULL nor a DeviceState.
3221 * We only want the owner here for the purposes of defining a
3222 * unique name for migration. TODO: Ideally we should implement
3223 * a naming scheme for Objects which are not DeviceStates, in
3224 * which case we can relax this restriction.
3225 */
3226 owner_dev = DEVICE(owner);
3227 vmstate_register_ram(mr, owner_dev);
3228 }
3229
3230 void memory_region_init_rom(MemoryRegion *mr,
3231 Object *owner,
3232 const char *name,
3233 uint64_t size,
3234 Error **errp)
3235 {
3236 DeviceState *owner_dev;
3237 Error *err = NULL;
3238
3239 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3240 if (err) {
3241 error_propagate(errp, err);
3242 return;
3243 }
3244 /* This will assert if owner is neither NULL nor a DeviceState.
3245 * We only want the owner here for the purposes of defining a
3246 * unique name for migration. TODO: Ideally we should implement
3247 * a naming scheme for Objects which are not DeviceStates, in
3248 * which case we can relax this restriction.
3249 */
3250 owner_dev = DEVICE(owner);
3251 vmstate_register_ram(mr, owner_dev);
3252 }
3253
3254 void memory_region_init_rom_device(MemoryRegion *mr,
3255 Object *owner,
3256 const MemoryRegionOps *ops,
3257 void *opaque,
3258 const char *name,
3259 uint64_t size,
3260 Error **errp)
3261 {
3262 DeviceState *owner_dev;
3263 Error *err = NULL;
3264
3265 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3266 name, size, &err);
3267 if (err) {
3268 error_propagate(errp, err);
3269 return;
3270 }
3271 /* This will assert if owner is neither NULL nor a DeviceState.
3272 * We only want the owner here for the purposes of defining a
3273 * unique name for migration. TODO: Ideally we should implement
3274 * a naming scheme for Objects which are not DeviceStates, in
3275 * which case we can relax this restriction.
3276 */
3277 owner_dev = DEVICE(owner);
3278 vmstate_register_ram(mr, owner_dev);
3279 }
3280
3281 /*
3282 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3283 * the fuzz_dma_read_cb callback
3284 */
3285 #ifdef CONFIG_FUZZ
3286 void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3287 size_t len,
3288 MemoryRegion *mr)
3289 {
3290 }
3291 #endif
3292
3293 static const TypeInfo memory_region_info = {
3294 .parent = TYPE_OBJECT,
3295 .name = TYPE_MEMORY_REGION,
3296 .class_size = sizeof(MemoryRegionClass),
3297 .instance_size = sizeof(MemoryRegion),
3298 .instance_init = memory_region_initfn,
3299 .instance_finalize = memory_region_finalize,
3300 };
3301
3302 static const TypeInfo iommu_memory_region_info = {
3303 .parent = TYPE_MEMORY_REGION,
3304 .name = TYPE_IOMMU_MEMORY_REGION,
3305 .class_size = sizeof(IOMMUMemoryRegionClass),
3306 .instance_size = sizeof(IOMMUMemoryRegion),
3307 .instance_init = iommu_memory_region_initfn,
3308 .abstract = true,
3309 };
3310
3311 static void memory_register_types(void)
3312 {
3313 type_register_static(&memory_region_info);
3314 type_register_static(&iommu_memory_region_info);
3315 }
3316
3317 type_init(memory_register_types)
AR7 emulation for QEMU