hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qemu/error-report.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "hw/hw.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/pci/pci_bridge.h"
  32 #include "hw/pci/pci_bus.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/pci-host/sabre.h"
  35 #include "hw/i386/pc.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/timer/m48t59.h"
  38 #include "hw/block/fdc.h"
  39 #include "net/net.h"
  40 #include "qemu/timer.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/boards.h"
  43 #include "hw/nvram/sun_nvram.h"
  44 #include "hw/nvram/chrp_nvram.h"
  45 #include "hw/sparc/sparc64.h"
  46 #include "hw/nvram/fw_cfg.h"
  47 #include "hw/sysbus.h"
  48 #include "hw/ide.h"
  49 #include "hw/ide/pci.h"
  50 #include "hw/loader.h"
  51 #include "elf.h"
  52 #include "trace.h"
  53 #include "qemu/cutils.h"
  54
  55 #define KERNEL_LOAD_ADDR     0x00404000
  56 #define CMDLINE_ADDR         0x003ff000
  57 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  58 #define PROM_VADDR           0x000ffd00000ULL
  59 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  60 #define PBM_MEM_BASE         0x1ff00000000ULL
  61 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  62 #define PROM_FILENAME        "openbios-sparc64"
  63 #define NVRAM_SIZE           0x2000
  64 #define MAX_IDE_BUS          2
  65 #define BIOS_CFG_IOPORT      0x510
  66 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  67 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  68 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  69
  70 #define IVEC_MAX             0x40
  71
  72 struct hwdef {
  73     uint16_t machine_id;
  74     uint64_t prom_addr;
  75     uint64_t console_serial_base;
  76 };
  77
  78 typedef struct EbusState {
  79     /*< private >*/
  80     PCIDevice parent_obj;
  81
  82     ISABus *isa_bus;
  83     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  84     uint64_t console_serial_base;
  85     MemoryRegion bar0;
  86     MemoryRegion bar1;
  87 } EbusState;
  88
  89 #define TYPE_EBUS "ebus"
  90 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  91
  92 void DMA_init(ISABus *bus, int high_page_enable)
  93 {
  94 }
  95
  96 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  97                             Error **errp)
  98 {
  99     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 100 }
 101
 102 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 103                                   const char *arch, ram_addr_t RAM_size,
 104                                   const char *boot_devices,
 105                                   uint32_t kernel_image, uint32_t kernel_size,
 106                                   const char *cmdline,
 107                                   uint32_t initrd_image, uint32_t initrd_size,
 108                                   uint32_t NVRAM_image,
 109                                   int width, int height, int depth,
 110                                   const uint8_t *macaddr)
 111 {
 112     unsigned int i;
 113     int sysp_end;
 114     uint8_t image[0x1ff0];
 115     NvramClass *k = NVRAM_GET_CLASS(nvram);
 116
 117     memset(image, '\0', sizeof(image));
 118
 119     /* OpenBIOS nvram variables partition */
 120     sysp_end = chrp_nvram_create_system_partition(image, 0);
 121
 122     /* Free space partition */
 123     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 124
 125     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 126
 127     for (i = 0; i < sizeof(image); i++) {
 128         (k->write)(nvram, i, image[i]);
 129     }
 130
 131     return 0;
 132 }
 133
 134 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 135                                   const char *initrd_filename,
 136                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 137                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 138                                   uint64_t *kernel_entry)
 139 {
 140     int linux_boot;
 141     unsigned int i;
 142     long kernel_size;
 143     uint8_t *ptr;
 144     uint64_t kernel_top;
 145
 146     linux_boot = (kernel_filename != NULL);
 147
 148     kernel_size = 0;
 149     if (linux_boot) {
 150         int bswap_needed;
 151
 152 #ifdef BSWAP_NEEDED
 153         bswap_needed = 1;
 154 #else
 155         bswap_needed = 0;
 156 #endif
 157         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 158                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 159         if (kernel_size < 0) {
 160             *kernel_addr = KERNEL_LOAD_ADDR;
 161             *kernel_entry = KERNEL_LOAD_ADDR;
 162             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 163                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 164                                     TARGET_PAGE_SIZE);
 165         }
 166         if (kernel_size < 0) {
 167             kernel_size = load_image_targphys(kernel_filename,
 168                                               KERNEL_LOAD_ADDR,
 169                                               RAM_size - KERNEL_LOAD_ADDR);
 170         }
 171         if (kernel_size < 0) {
 172             error_report("could not load kernel '%s'", kernel_filename);
 173             exit(1);
 174         }
 175         /* load initrd above kernel */
 176         *initrd_size = 0;
 177         if (initrd_filename) {
 178             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 179
 180             *initrd_size = load_image_targphys(initrd_filename,
 181                                                *initrd_addr,
 182                                                RAM_size - *initrd_addr);
 183             if ((int)*initrd_size < 0) {
 184                 error_report("could not load initial ram disk '%s'",
 185                              initrd_filename);
 186                 exit(1);
 187             }
 188         }
 189         if (*initrd_size > 0) {
 190             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 191                 ptr = rom_ptr(*kernel_addr + i);
 192                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 193                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 194                     stl_p(ptr + 28, *initrd_size);
 195                     break;
 196                 }
 197             }
 198         }
 199     }
 200     return kernel_size;
 201 }
 202
 203 typedef struct ResetData {
 204     SPARCCPU *cpu;
 205     uint64_t prom_addr;
 206 } ResetData;
 207
 208 #define TYPE_SUN4U_POWER "power"
 209 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
 210
 211 typedef struct PowerDevice {
 212     SysBusDevice parent_obj;
 213
 214     MemoryRegion power_mmio;
 215 } PowerDevice;
 216
 217 /* Power */
 218 static void power_mem_write(void *opaque, hwaddr addr,
 219                             uint64_t val, unsigned size)
 220 {
 221     /* According to a real Ultra 5, bit 24 controls the power */
 222     if (val & 0x1000000) {
 223         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 224     }
 225 }
 226
 227 static const MemoryRegionOps power_mem_ops = {
 228     .write = power_mem_write,
 229     .endianness = DEVICE_NATIVE_ENDIAN,
 230     .valid = {
 231         .min_access_size = 4,
 232         .max_access_size = 4,
 233     },
 234 };
 235
 236 static void power_realize(DeviceState *dev, Error **errp)
 237 {
 238     PowerDevice *d = SUN4U_POWER(dev);
 239     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 240
 241     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 242                           "power", sizeof(uint32_t));
 243
 244     sysbus_init_mmio(sbd, &d->power_mmio);
 245 }
 246
 247 static void power_class_init(ObjectClass *klass, void *data)
 248 {
 249     DeviceClass *dc = DEVICE_CLASS(klass);
 250
 251     dc->realize = power_realize;
 252 }
 253
 254 static const TypeInfo power_info = {
 255     .name          = TYPE_SUN4U_POWER,
 256     .parent        = TYPE_SYS_BUS_DEVICE,
 257     .instance_size = sizeof(PowerDevice),
 258     .class_init    = power_class_init,
 259 };
 260
 261 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 262 {
 263     EbusState *s = EBUS(opaque);
 264     qemu_irq irq = s->isa_bus_irqs[n];
 265
 266     /* Pass ISA bus IRQs onto their gpio equivalent */
 267     trace_ebus_isa_irq_handler(n, level);
 268     if (irq) {
 269         qemu_set_irq(irq, level);
 270     }
 271 }
 272
 273 /* EBUS (Eight bit bus) bridge */
 274 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 275 {
 276     EbusState *s = EBUS(pci_dev);
 277     SysBusDevice *sbd;
 278     DeviceState *dev;
 279     qemu_irq *isa_irq;
 280     DriveInfo *fd[MAX_FD];
 281     int i;
 282
 283     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 284                              pci_address_space_io(pci_dev), errp);
 285     if (!s->isa_bus) {
 286         error_setg(errp, "unable to instantiate EBUS ISA bus");
 287         return;
 288     }
 289
 290     /* ISA bus */
 291     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 292     isa_bus_irqs(s->isa_bus, isa_irq);
 293     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 294                              ISA_NUM_IRQS);
 295
 296     /* Serial ports */
 297     i = 0;
 298     if (s->console_serial_base) {
 299         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 300                        0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 301         i++;
 302     }
 303     serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
 304
 305     /* Parallel ports */
 306     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 307
 308     /* Keyboard */
 309     isa_create_simple(s->isa_bus, "i8042");
 310
 311     /* Floppy */
 312     for (i = 0; i < MAX_FD; i++) {
 313         fd[i] = drive_get(IF_FLOPPY, 0, i);
 314     }
 315     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 316     if (fd[0]) {
 317         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 318                             &error_abort);
 319     }
 320     if (fd[1]) {
 321         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 322                             &error_abort);
 323     }
 324     qdev_prop_set_uint32(dev, "dma", -1);
 325     qdev_init_nofail(dev);
 326
 327     /* Power */
 328     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
 329     qdev_init_nofail(dev);
 330     sbd = SYS_BUS_DEVICE(dev);
 331     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 332                                 sysbus_mmio_get_region(sbd, 0));
 333
 334     /* PCI */
 335     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 336     pci_dev->config[0x05] = 0x00;
 337     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 338     pci_dev->config[0x07] = 0x03; // status = medium devsel
 339     pci_dev->config[0x09] = 0x00; // programming i/f
 340     pci_dev->config[0x0D] = 0x0a; // latency_timer
 341
 342     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 343                              0, 0x1000000);
 344     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 345     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 346                              0, 0x8000);
 347     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 348 }
 349
 350 static Property ebus_properties[] = {
 351     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 352                        console_serial_base, 0),
 353     DEFINE_PROP_END_OF_LIST(),
 354 };
 355
 356 static void ebus_class_init(ObjectClass *klass, void *data)
 357 {
 358     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360
 361     k->realize = ebus_realize;
 362     k->vendor_id = PCI_VENDOR_ID_SUN;
 363     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 364     k->revision = 0x01;
 365     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 366     dc->props = ebus_properties;
 367 }
 368
 369 static const TypeInfo ebus_info = {
 370     .name          = TYPE_EBUS,
 371     .parent        = TYPE_PCI_DEVICE,
 372     .class_init    = ebus_class_init,
 373     .instance_size = sizeof(EbusState),
 374     .interfaces = (InterfaceInfo[]) {
 375         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 376         { },
 377     },
 378 };
 379
 380 #define TYPE_OPENPROM "openprom"
 381 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 382
 383 typedef struct PROMState {
 384     SysBusDevice parent_obj;
 385
 386     MemoryRegion prom;
 387 } PROMState;
 388
 389 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 390 {
 391     hwaddr *base_addr = (hwaddr *)opaque;
 392     return addr + *base_addr - PROM_VADDR;
 393 }
 394
 395 /* Boot PROM (OpenBIOS) */
 396 static void prom_init(hwaddr addr, const char *bios_name)
 397 {
 398     DeviceState *dev;
 399     SysBusDevice *s;
 400     char *filename;
 401     int ret;
 402
 403     dev = qdev_create(NULL, TYPE_OPENPROM);
 404     qdev_init_nofail(dev);
 405     s = SYS_BUS_DEVICE(dev);
 406
 407     sysbus_mmio_map(s, 0, addr);
 408
 409     /* load boot prom */
 410     if (bios_name == NULL) {
 411         bios_name = PROM_FILENAME;
 412     }
 413     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 414     if (filename) {
 415         ret = load_elf(filename, translate_prom_address, &addr,
 416                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 417         if (ret < 0 || ret > PROM_SIZE_MAX) {
 418             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 419         }
 420         g_free(filename);
 421     } else {
 422         ret = -1;
 423     }
 424     if (ret < 0 || ret > PROM_SIZE_MAX) {
 425         error_report("could not load prom '%s'", bios_name);
 426         exit(1);
 427     }
 428 }
 429
 430 static void prom_init1(Object *obj)
 431 {
 432     PROMState *s = OPENPROM(obj);
 433     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 434
 435     memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
 436                            &error_fatal);
 437     vmstate_register_ram_global(&s->prom);
 438     memory_region_set_readonly(&s->prom, true);
 439     sysbus_init_mmio(dev, &s->prom);
 440 }
 441
 442 static Property prom_properties[] = {
 443     {/* end of property list */},
 444 };
 445
 446 static void prom_class_init(ObjectClass *klass, void *data)
 447 {
 448     DeviceClass *dc = DEVICE_CLASS(klass);
 449
 450     dc->props = prom_properties;
 451 }
 452
 453 static const TypeInfo prom_info = {
 454     .name          = TYPE_OPENPROM,
 455     .parent        = TYPE_SYS_BUS_DEVICE,
 456     .instance_size = sizeof(PROMState),
 457     .class_init    = prom_class_init,
 458     .instance_init = prom_init1,
 459 };
 460
 461
 462 #define TYPE_SUN4U_MEMORY "memory"
 463 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 464
 465 typedef struct RamDevice {
 466     SysBusDevice parent_obj;
 467
 468     MemoryRegion ram;
 469     uint64_t size;
 470 } RamDevice;
 471
 472 /* System RAM */
 473 static void ram_realize(DeviceState *dev, Error **errp)
 474 {
 475     RamDevice *d = SUN4U_RAM(dev);
 476     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 477
 478     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 479                            &error_fatal);
 480     vmstate_register_ram_global(&d->ram);
 481     sysbus_init_mmio(sbd, &d->ram);
 482 }
 483
 484 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 485 {
 486     DeviceState *dev;
 487     SysBusDevice *s;
 488     RamDevice *d;
 489
 490     /* allocate RAM */
 491     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 492     s = SYS_BUS_DEVICE(dev);
 493
 494     d = SUN4U_RAM(dev);
 495     d->size = RAM_size;
 496     qdev_init_nofail(dev);
 497
 498     sysbus_mmio_map(s, 0, addr);
 499 }
 500
 501 static Property ram_properties[] = {
 502     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 503     DEFINE_PROP_END_OF_LIST(),
 504 };
 505
 506 static void ram_class_init(ObjectClass *klass, void *data)
 507 {
 508     DeviceClass *dc = DEVICE_CLASS(klass);
 509
 510     dc->realize = ram_realize;
 511     dc->props = ram_properties;
 512 }
 513
 514 static const TypeInfo ram_info = {
 515     .name          = TYPE_SUN4U_MEMORY,
 516     .parent        = TYPE_SYS_BUS_DEVICE,
 517     .instance_size = sizeof(RamDevice),
 518     .class_init    = ram_class_init,
 519 };
 520
 521 static void sun4uv_init(MemoryRegion *address_space_mem,
 522                         MachineState *machine,
 523                         const struct hwdef *hwdef)
 524 {
 525     SPARCCPU *cpu;
 526     Nvram *nvram;
 527     unsigned int i;
 528     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 529     SabreState *sabre;
 530     PCIBus *pci_bus, *pci_busA, *pci_busB;
 531     PCIDevice *ebus, *pci_dev;
 532     SysBusDevice *s;
 533     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 534     DeviceState *iommu, *dev;
 535     FWCfgState *fw_cfg;
 536     NICInfo *nd;
 537     MACAddr macaddr;
 538     bool onboard_nic;
 539
 540     /* init CPUs */
 541     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 542
 543     /* IOMMU */
 544     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 545     qdev_init_nofail(iommu);
 546
 547     /* set up devices */
 548     ram_init(0, machine->ram_size);
 549
 550     prom_init(hwdef->prom_addr, bios_name);
 551
 552     /* Init sabre (PCI host bridge) */
 553     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
 554     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 555     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 556     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
 557                              &error_abort);
 558     qdev_init_nofail(DEVICE(sabre));
 559
 560     /* Wire up PCI interrupts to CPU */
 561     for (i = 0; i < IVEC_MAX; i++) {
 562         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 563             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 564     }
 565
 566     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 567     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 568     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 569
 570     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 571        reserved (leaving no slots free after on-board devices) however slots
 572        0-3 are free on busB */
 573     pci_bus->slot_reserved_mask = 0xfffffffc;
 574     pci_busA->slot_reserved_mask = 0xfffffff1;
 575     pci_busB->slot_reserved_mask = 0xfffffff0;
 576
 577     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 578     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 579                          hwdef->console_serial_base);
 580     qdev_init_nofail(DEVICE(ebus));
 581
 582     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 583     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 584         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 585     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 586         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 587     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 588         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 589     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 590         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 591     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 592         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 593
 594     pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 595
 596     memset(&macaddr, 0, sizeof(MACAddr));
 597     onboard_nic = false;
 598     for (i = 0; i < nb_nics; i++) {
 599         nd = &nd_table[i];
 600
 601         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 602             if (!onboard_nic) {
 603                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 604                                                    true, "sunhme");
 605                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 606                 onboard_nic = true;
 607             } else {
 608                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 609             }
 610         } else {
 611             pci_dev = pci_create(pci_busB, -1, nd->model);
 612         }
 613
 614         dev = &pci_dev->qdev;
 615         qdev_set_nic_properties(dev, nd);
 616         qdev_init_nofail(dev);
 617     }
 618
 619     /* If we don't have an onboard NIC, grab a default MAC address so that
 620      * we have a valid machine id */
 621     if (!onboard_nic) {
 622         qemu_macaddr_default_if_unset(&macaddr);
 623     }
 624
 625     ide_drive_get(hd, ARRAY_SIZE(hd));
 626
 627     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 628     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 629     qdev_init_nofail(&pci_dev->qdev);
 630     pci_ide_create_devs(pci_dev, hd);
 631
 632     /* Map NVRAM into I/O (ebus) space */
 633     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 634     s = SYS_BUS_DEVICE(nvram);
 635     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 636                                 sysbus_mmio_get_region(s, 0));
 637
 638     initrd_size = 0;
 639     initrd_addr = 0;
 640     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 641                                     machine->initrd_filename,
 642                                     ram_size, &initrd_size, &initrd_addr,
 643                                     &kernel_addr, &kernel_entry);
 644
 645     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 646                            machine->boot_order,
 647                            kernel_addr, kernel_size,
 648                            machine->kernel_cmdline,
 649                            initrd_addr, initrd_size,
 650                            /* XXX: need an option to load a NVRAM image */
 651                            0,
 652                            graphic_width, graphic_height, graphic_depth,
 653                            (uint8_t *)&macaddr);
 654
 655     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 656     qdev_prop_set_bit(dev, "dma_enabled", false);
 657     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 658     qdev_init_nofail(dev);
 659     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 660                                 &FW_CFG_IO(dev)->comb_iomem);
 661
 662     fw_cfg = FW_CFG(dev);
 663     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 664     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 665     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 666     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 667     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 668     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 669     if (machine->kernel_cmdline) {
 670         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 671                        strlen(machine->kernel_cmdline) + 1);
 672         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 673     } else {
 674         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 675     }
 676     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 677     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 678     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 679
 680     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 681     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 682     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 683
 684     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 685 }
 686
 687 enum {
 688     sun4u_id = 0,
 689     sun4v_id = 64,
 690 };
 691
 692 static const struct hwdef hwdefs[] = {
 693     /* Sun4u generic PC-like machine */
 694     {
 695         .machine_id = sun4u_id,
 696         .prom_addr = 0x1fff0000000ULL,
 697         .console_serial_base = 0,
 698     },
 699     /* Sun4v generic PC-like machine */
 700     {
 701         .machine_id = sun4v_id,
 702         .prom_addr = 0x1fff0000000ULL,
 703         .console_serial_base = 0,
 704     },
 705 };
 706
 707 /* Sun4u hardware initialisation */
 708 static void sun4u_init(MachineState *machine)
 709 {
 710     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 711 }
 712
 713 /* Sun4v hardware initialisation */
 714 static void sun4v_init(MachineState *machine)
 715 {
 716     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 717 }
 718
 719 static void sun4u_class_init(ObjectClass *oc, void *data)
 720 {
 721     MachineClass *mc = MACHINE_CLASS(oc);
 722
 723     mc->desc = "Sun4u platform";
 724     mc->init = sun4u_init;
 725     mc->block_default_type = IF_IDE;
 726     mc->max_cpus = 1; /* XXX for now */
 727     mc->is_default = 1;
 728     mc->default_boot_order = "c";
 729     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 730 }
 731
 732 static const TypeInfo sun4u_type = {
 733     .name = MACHINE_TYPE_NAME("sun4u"),
 734     .parent = TYPE_MACHINE,
 735     .class_init = sun4u_class_init,
 736 };
 737
 738 static void sun4v_class_init(ObjectClass *oc, void *data)
 739 {
 740     MachineClass *mc = MACHINE_CLASS(oc);
 741
 742     mc->desc = "Sun4v platform";
 743     mc->init = sun4v_init;
 744     mc->block_default_type = IF_IDE;
 745     mc->max_cpus = 1; /* XXX for now */
 746     mc->default_boot_order = "c";
 747     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 748 }
 749
 750 static const TypeInfo sun4v_type = {
 751     .name = MACHINE_TYPE_NAME("sun4v"),
 752     .parent = TYPE_MACHINE,
 753     .class_init = sun4v_class_init,
 754 };
 755
 756 static void sun4u_register_types(void)
 757 {
 758     type_register_static(&power_info);
 759     type_register_static(&ebus_info);
 760     type_register_static(&prom_info);
 761     type_register_static(&ram_info);
 762
 763     type_register_static(&sun4u_type);
 764     type_register_static(&sun4v_type);
 765 }
 766
 767 type_init(sun4u_register_types)