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docker: Fix test-mingw
[qemu/ar7.git] / target / unicore32 / translate.c
blob6c094d59d73eaca1913ba62bceac1fa03886e0e8
1 /*
2 * UniCore32 translation
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
10 */
11 #include "qemu/osdep.h"
12
13 #include "cpu.h"
14 #include "disas/disas.h"
15 #include "exec/exec-all.h"
16 #include "tcg-op.h"
17 #include "qemu/log.h"
18 #include "exec/cpu_ldst.h"
19 #include "exec/translator.h"
20
21 #include "exec/helper-proto.h"
22 #include "exec/helper-gen.h"
23
24 #include "trace-tcg.h"
25 #include "exec/log.h"
26
27
28 /* internal defines */
29 typedef struct DisasContext {
30 target_ulong pc;
31 int is_jmp;
32 /* Nonzero if this instruction has been conditionally skipped. */
33 int condjmp;
34 /* The label that will be jumped to when the instruction is skipped. */
35 TCGLabel *condlabel;
36 struct TranslationBlock *tb;
37 int singlestep_enabled;
38 #ifndef CONFIG_USER_ONLY
39 int user;
40 #endif
41 } DisasContext;
42
43 #ifndef CONFIG_USER_ONLY
44 #define IS_USER(s) (s->user)
45 #else
46 #define IS_USER(s) 1
47 #endif
48
49 /* is_jmp field values */
50 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
51 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
52 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
53 /* These instructions trap after executing, so defer them until after the
54 conditional executions state has been updated. */
55 #define DISAS_SYSCALL DISAS_TARGET_3
56
57 static TCGv_env cpu_env;
58 static TCGv_i32 cpu_R[32];
59
60 /* FIXME: These should be removed. */
61 static TCGv cpu_F0s, cpu_F1s;
62 static TCGv_i64 cpu_F0d, cpu_F1d;
63
64 #include "exec/gen-icount.h"
65
66 static const char *regnames[] = {
67 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
68 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
69 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
70 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
71
72 /* initialize TCG globals. */
73 void uc32_translate_init(void)
74 {
75 int i;
76
77 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
78 tcg_ctx.tcg_env = cpu_env;
79
80 for (i = 0; i < 32; i++) {
81 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
82 offsetof(CPUUniCore32State, regs[i]), regnames[i]);
83 }
84 }
85
86 static int num_temps;
87
88 /* Allocate a temporary variable. */
89 static TCGv_i32 new_tmp(void)
90 {
91 num_temps++;
92 return tcg_temp_new_i32();
93 }
94
95 /* Release a temporary variable. */
96 static void dead_tmp(TCGv tmp)
97 {
98 tcg_temp_free(tmp);
99 num_temps--;
100 }
101
102 static inline TCGv load_cpu_offset(int offset)
103 {
104 TCGv tmp = new_tmp();
105 tcg_gen_ld_i32(tmp, cpu_env, offset);
106 return tmp;
107 }
108
109 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
110
111 static inline void store_cpu_offset(TCGv var, int offset)
112 {
113 tcg_gen_st_i32(var, cpu_env, offset);
114 dead_tmp(var);
115 }
116
117 #define store_cpu_field(var, name) \
118 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
119
120 /* Set a variable to the value of a CPU register. */
121 static void load_reg_var(DisasContext *s, TCGv var, int reg)
122 {
123 if (reg == 31) {
124 uint32_t addr;
125 /* normaly, since we updated PC */
126 addr = (long)s->pc;
127 tcg_gen_movi_i32(var, addr);
128 } else {
129 tcg_gen_mov_i32(var, cpu_R[reg]);
130 }
131 }
132
133 /* Create a new temporary and set it to the value of a CPU register. */
134 static inline TCGv load_reg(DisasContext *s, int reg)
135 {
136 TCGv tmp = new_tmp();
137 load_reg_var(s, tmp, reg);
138 return tmp;
139 }
140
141 /* Set a CPU register. The source must be a temporary and will be
142 marked as dead. */
143 static void store_reg(DisasContext *s, int reg, TCGv var)
144 {
145 if (reg == 31) {
146 tcg_gen_andi_i32(var, var, ~3);
147 s->is_jmp = DISAS_JUMP;
148 }
149 tcg_gen_mov_i32(cpu_R[reg], var);
150 dead_tmp(var);
151 }
152
153 /* Value extensions. */
154 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
155 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
156 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
157 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
158
159 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
160 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
161 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
162 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
163 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
164 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
165 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
166 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
167 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
168 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
169 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
170 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
171 #define UCOP_COND (((insn) >> 25) & 0x0f)
172 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
173 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
174 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
175 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
176 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
177
178 #define UCOP_SET(i) ((insn) & (1 << (i)))
179 #define UCOP_SET_P UCOP_SET(28)
180 #define UCOP_SET_U UCOP_SET(27)
181 #define UCOP_SET_B UCOP_SET(26)
182 #define UCOP_SET_W UCOP_SET(25)
183 #define UCOP_SET_L UCOP_SET(24)
184 #define UCOP_SET_S UCOP_SET(24)
185
186 #define ILLEGAL cpu_abort(CPU(cpu), \
187 "Illegal UniCore32 instruction %x at line %d!", \
188 insn, __LINE__)
189
190 #ifndef CONFIG_USER_ONLY
191 static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
192 uint32_t insn)
193 {
194 UniCore32CPU *cpu = uc32_env_get_cpu(env);
195 TCGv tmp, tmp2, tmp3;
196 if ((insn & 0xfe000000) == 0xe0000000) {
197 tmp2 = new_tmp();
198 tmp3 = new_tmp();
199 tcg_gen_movi_i32(tmp2, UCOP_REG_N);
200 tcg_gen_movi_i32(tmp3, UCOP_IMM10);
201 if (UCOP_SET_L) {
202 tmp = new_tmp();
203 gen_helper_cp0_get(tmp, cpu_env, tmp2, tmp3);
204 store_reg(s, UCOP_REG_D, tmp);
205 } else {
206 tmp = load_reg(s, UCOP_REG_D);
207 gen_helper_cp0_set(cpu_env, tmp, tmp2, tmp3);
208 dead_tmp(tmp);
209 }
210 dead_tmp(tmp2);
211 dead_tmp(tmp3);
212 return;
213 }
214 ILLEGAL;
215 }
216
217 static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
218 uint32_t insn)
219 {
220 UniCore32CPU *cpu = uc32_env_get_cpu(env);
221 TCGv tmp;
222
223 if ((insn & 0xff003fff) == 0xe1000400) {
224 /*
225 * movc rd, pp.nn, #imm9
226 * rd: UCOP_REG_D
227 * nn: UCOP_REG_N (must be 0)
228 * imm9: 0
229 */
230 if (UCOP_REG_N == 0) {
231 tmp = new_tmp();
232 tcg_gen_movi_i32(tmp, 0);
233 store_reg(s, UCOP_REG_D, tmp);
234 return;
235 } else {
236 ILLEGAL;
237 }
238 }
239 if ((insn & 0xff003fff) == 0xe0000401) {
240 /*
241 * movc pp.nn, rn, #imm9
242 * rn: UCOP_REG_D
243 * nn: UCOP_REG_N (must be 1)
244 * imm9: 1
245 */
246 if (UCOP_REG_N == 1) {
247 tmp = load_reg(s, UCOP_REG_D);
248 gen_helper_cp1_putc(tmp);
249 dead_tmp(tmp);
250 return;
251 } else {
252 ILLEGAL;
253 }
254 }
255 ILLEGAL;
256 }
257 #endif
258
259 static inline void gen_set_asr(TCGv var, uint32_t mask)
260 {
261 TCGv tmp_mask = tcg_const_i32(mask);
262 gen_helper_asr_write(cpu_env, var, tmp_mask);
263 tcg_temp_free_i32(tmp_mask);
264 }
265 /* Set NZCV flags from the high 4 bits of var. */
266 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
267
268 static void gen_exception(int excp)
269 {
270 TCGv tmp = new_tmp();
271 tcg_gen_movi_i32(tmp, excp);
272 gen_helper_exception(cpu_env, tmp);
273 dead_tmp(tmp);
274 }
275
276 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
277
278 /* Set CF to the top bit of var. */
279 static void gen_set_CF_bit31(TCGv var)
280 {
281 TCGv tmp = new_tmp();
282 tcg_gen_shri_i32(tmp, var, 31);
283 gen_set_CF(tmp);
284 dead_tmp(tmp);
285 }
286
287 /* Set N and Z flags from var. */
288 static inline void gen_logic_CC(TCGv var)
289 {
290 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
291 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
292 }
293
294 /* dest = T0 + T1 + CF. */
295 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
296 {
297 TCGv tmp;
298 tcg_gen_add_i32(dest, t0, t1);
299 tmp = load_cpu_field(CF);
300 tcg_gen_add_i32(dest, dest, tmp);
301 dead_tmp(tmp);
302 }
303
304 /* dest = T0 - T1 + CF - 1. */
305 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
306 {
307 TCGv tmp;
308 tcg_gen_sub_i32(dest, t0, t1);
309 tmp = load_cpu_field(CF);
310 tcg_gen_add_i32(dest, dest, tmp);
311 tcg_gen_subi_i32(dest, dest, 1);
312 dead_tmp(tmp);
313 }
314
315 static void shifter_out_im(TCGv var, int shift)
316 {
317 TCGv tmp = new_tmp();
318 if (shift == 0) {
319 tcg_gen_andi_i32(tmp, var, 1);
320 } else {
321 tcg_gen_shri_i32(tmp, var, shift);
322 if (shift != 31) {
323 tcg_gen_andi_i32(tmp, tmp, 1);
324 }
325 }
326 gen_set_CF(tmp);
327 dead_tmp(tmp);
328 }
329
330 /* Shift by immediate. Includes special handling for shift == 0. */
331 static inline void gen_uc32_shift_im(TCGv var, int shiftop, int shift,
332 int flags)
333 {
334 switch (shiftop) {
335 case 0: /* LSL */
336 if (shift != 0) {
337 if (flags) {
338 shifter_out_im(var, 32 - shift);
339 }
340 tcg_gen_shli_i32(var, var, shift);
341 }
342 break;
343 case 1: /* LSR */
344 if (shift == 0) {
345 if (flags) {
346 tcg_gen_shri_i32(var, var, 31);
347 gen_set_CF(var);
348 }
349 tcg_gen_movi_i32(var, 0);
350 } else {
351 if (flags) {
352 shifter_out_im(var, shift - 1);
353 }
354 tcg_gen_shri_i32(var, var, shift);
355 }
356 break;
357 case 2: /* ASR */
358 if (shift == 0) {
359 shift = 32;
360 }
361 if (flags) {
362 shifter_out_im(var, shift - 1);
363 }
364 if (shift == 32) {
365 shift = 31;
366 }
367 tcg_gen_sari_i32(var, var, shift);
368 break;
369 case 3: /* ROR/RRX */
370 if (shift != 0) {
371 if (flags) {
372 shifter_out_im(var, shift - 1);
373 }
374 tcg_gen_rotri_i32(var, var, shift); break;
375 } else {
376 TCGv tmp = load_cpu_field(CF);
377 if (flags) {
378 shifter_out_im(var, 0);
379 }
380 tcg_gen_shri_i32(var, var, 1);
381 tcg_gen_shli_i32(tmp, tmp, 31);
382 tcg_gen_or_i32(var, var, tmp);
383 dead_tmp(tmp);
384 }
385 }
386 };
387
388 static inline void gen_uc32_shift_reg(TCGv var, int shiftop,
389 TCGv shift, int flags)
390 {
391 if (flags) {
392 switch (shiftop) {
393 case 0:
394 gen_helper_shl_cc(var, cpu_env, var, shift);
395 break;
396 case 1:
397 gen_helper_shr_cc(var, cpu_env, var, shift);
398 break;
399 case 2:
400 gen_helper_sar_cc(var, cpu_env, var, shift);
401 break;
402 case 3:
403 gen_helper_ror_cc(var, cpu_env, var, shift);
404 break;
405 }
406 } else {
407 switch (shiftop) {
408 case 0:
409 gen_helper_shl(var, var, shift);
410 break;
411 case 1:
412 gen_helper_shr(var, var, shift);
413 break;
414 case 2:
415 gen_helper_sar(var, var, shift);
416 break;
417 case 3:
418 tcg_gen_andi_i32(shift, shift, 0x1f);
419 tcg_gen_rotr_i32(var, var, shift);
420 break;
421 }
422 }
423 dead_tmp(shift);
424 }
425
426 static void gen_test_cc(int cc, TCGLabel *label)
427 {
428 TCGv tmp;
429 TCGv tmp2;
430 TCGLabel *inv;
431
432 switch (cc) {
433 case 0: /* eq: Z */
434 tmp = load_cpu_field(ZF);
435 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
436 break;
437 case 1: /* ne: !Z */
438 tmp = load_cpu_field(ZF);
439 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
440 break;
441 case 2: /* cs: C */
442 tmp = load_cpu_field(CF);
443 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
444 break;
445 case 3: /* cc: !C */
446 tmp = load_cpu_field(CF);
447 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
448 break;
449 case 4: /* mi: N */
450 tmp = load_cpu_field(NF);
451 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
452 break;
453 case 5: /* pl: !N */
454 tmp = load_cpu_field(NF);
455 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
456 break;
457 case 6: /* vs: V */
458 tmp = load_cpu_field(VF);
459 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
460 break;
461 case 7: /* vc: !V */
462 tmp = load_cpu_field(VF);
463 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
464 break;
465 case 8: /* hi: C && !Z */
466 inv = gen_new_label();
467 tmp = load_cpu_field(CF);
468 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
469 dead_tmp(tmp);
470 tmp = load_cpu_field(ZF);
471 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
472 gen_set_label(inv);
473 break;
474 case 9: /* ls: !C || Z */
475 tmp = load_cpu_field(CF);
476 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
477 dead_tmp(tmp);
478 tmp = load_cpu_field(ZF);
479 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
480 break;
481 case 10: /* ge: N == V -> N ^ V == 0 */
482 tmp = load_cpu_field(VF);
483 tmp2 = load_cpu_field(NF);
484 tcg_gen_xor_i32(tmp, tmp, tmp2);
485 dead_tmp(tmp2);
486 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
487 break;
488 case 11: /* lt: N != V -> N ^ V != 0 */
489 tmp = load_cpu_field(VF);
490 tmp2 = load_cpu_field(NF);
491 tcg_gen_xor_i32(tmp, tmp, tmp2);
492 dead_tmp(tmp2);
493 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
494 break;
495 case 12: /* gt: !Z && N == V */
496 inv = gen_new_label();
497 tmp = load_cpu_field(ZF);
498 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
499 dead_tmp(tmp);
500 tmp = load_cpu_field(VF);
501 tmp2 = load_cpu_field(NF);
502 tcg_gen_xor_i32(tmp, tmp, tmp2);
503 dead_tmp(tmp2);
504 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
505 gen_set_label(inv);
506 break;
507 case 13: /* le: Z || N != V */
508 tmp = load_cpu_field(ZF);
509 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
510 dead_tmp(tmp);
511 tmp = load_cpu_field(VF);
512 tmp2 = load_cpu_field(NF);
513 tcg_gen_xor_i32(tmp, tmp, tmp2);
514 dead_tmp(tmp2);
515 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
516 break;
517 default:
518 fprintf(stderr, "Bad condition code 0x%x\n", cc);
519 abort();
520 }
521 dead_tmp(tmp);
522 }
523
524 static const uint8_t table_logic_cc[16] = {
525 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
526 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
527 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
528 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
529 };
530
531 /* Set PC state from an immediate address. */
532 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
533 {
534 s->is_jmp = DISAS_UPDATE;
535 tcg_gen_movi_i32(cpu_R[31], addr & ~3);
536 }
537
538 /* Set PC state from var. var is marked as dead. */
539 static inline void gen_bx(DisasContext *s, TCGv var)
540 {
541 s->is_jmp = DISAS_UPDATE;
542 tcg_gen_andi_i32(cpu_R[31], var, ~3);
543 dead_tmp(var);
544 }
545
546 static inline void store_reg_bx(DisasContext *s, int reg, TCGv var)
547 {
548 store_reg(s, reg, var);
549 }
550
551 static inline TCGv gen_ld8s(TCGv addr, int index)
552 {
553 TCGv tmp = new_tmp();
554 tcg_gen_qemu_ld8s(tmp, addr, index);
555 return tmp;
556 }
557
558 static inline TCGv gen_ld8u(TCGv addr, int index)
559 {
560 TCGv tmp = new_tmp();
561 tcg_gen_qemu_ld8u(tmp, addr, index);
562 return tmp;
563 }
564
565 static inline TCGv gen_ld16s(TCGv addr, int index)
566 {
567 TCGv tmp = new_tmp();
568 tcg_gen_qemu_ld16s(tmp, addr, index);
569 return tmp;
570 }
571
572 static inline TCGv gen_ld16u(TCGv addr, int index)
573 {
574 TCGv tmp = new_tmp();
575 tcg_gen_qemu_ld16u(tmp, addr, index);
576 return tmp;
577 }
578
579 static inline TCGv gen_ld32(TCGv addr, int index)
580 {
581 TCGv tmp = new_tmp();
582 tcg_gen_qemu_ld32u(tmp, addr, index);
583 return tmp;
584 }
585
586 static inline void gen_st8(TCGv val, TCGv addr, int index)
587 {
588 tcg_gen_qemu_st8(val, addr, index);
589 dead_tmp(val);
590 }
591
592 static inline void gen_st16(TCGv val, TCGv addr, int index)
593 {
594 tcg_gen_qemu_st16(val, addr, index);
595 dead_tmp(val);
596 }
597
598 static inline void gen_st32(TCGv val, TCGv addr, int index)
599 {
600 tcg_gen_qemu_st32(val, addr, index);
601 dead_tmp(val);
602 }
603
604 static inline void gen_set_pc_im(uint32_t val)
605 {
606 tcg_gen_movi_i32(cpu_R[31], val);
607 }
608
609 /* Force a TB lookup after an instruction that changes the CPU state. */
610 static inline void gen_lookup_tb(DisasContext *s)
611 {
612 tcg_gen_movi_i32(cpu_R[31], s->pc & ~1);
613 s->is_jmp = DISAS_UPDATE;
614 }
615
616 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
617 TCGv var)
618 {
619 int val;
620 TCGv offset;
621
622 if (UCOP_SET(29)) {
623 /* immediate */
624 val = UCOP_IMM14;
625 if (!UCOP_SET_U) {
626 val = -val;
627 }
628 if (val != 0) {
629 tcg_gen_addi_i32(var, var, val);
630 }
631 } else {
632 /* shift/register */
633 offset = load_reg(s, UCOP_REG_M);
634 gen_uc32_shift_im(offset, UCOP_SH_OP, UCOP_SH_IM, 0);
635 if (!UCOP_SET_U) {
636 tcg_gen_sub_i32(var, var, offset);
637 } else {
638 tcg_gen_add_i32(var, var, offset);
639 }
640 dead_tmp(offset);
641 }
642 }
643
644 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
645 TCGv var)
646 {
647 int val;
648 TCGv offset;
649
650 if (UCOP_SET(26)) {
651 /* immediate */
652 val = (insn & 0x1f) | ((insn >> 4) & 0x3e0);
653 if (!UCOP_SET_U) {
654 val = -val;
655 }
656 if (val != 0) {
657 tcg_gen_addi_i32(var, var, val);
658 }
659 } else {
660 /* register */
661 offset = load_reg(s, UCOP_REG_M);
662 if (!UCOP_SET_U) {
663 tcg_gen_sub_i32(var, var, offset);
664 } else {
665 tcg_gen_add_i32(var, var, offset);
666 }
667 dead_tmp(offset);
668 }
669 }
670
671 static inline long ucf64_reg_offset(int reg)
672 {
673 if (reg & 1) {
674 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
675 + offsetof(CPU_DoubleU, l.upper);
676 } else {
677 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
678 + offsetof(CPU_DoubleU, l.lower);
679 }
680 }
681
682 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
683 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
684
685 /* UniCore-F64 single load/store I_offset */
686 static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
687 {
688 UniCore32CPU *cpu = uc32_env_get_cpu(env);
689 int offset;
690 TCGv tmp;
691 TCGv addr;
692
693 addr = load_reg(s, UCOP_REG_N);
694 if (!UCOP_SET_P && !UCOP_SET_W) {
695 ILLEGAL;
696 }
697
698 if (UCOP_SET_P) {
699 offset = UCOP_IMM10 << 2;
700 if (!UCOP_SET_U) {
701 offset = -offset;
702 }
703 if (offset != 0) {
704 tcg_gen_addi_i32(addr, addr, offset);
705 }
706 }
707
708 if (UCOP_SET_L) { /* load */
709 tmp = gen_ld32(addr, IS_USER(s));
710 ucf64_gen_st32(tmp, UCOP_REG_D);
711 } else { /* store */
712 tmp = ucf64_gen_ld32(UCOP_REG_D);
713 gen_st32(tmp, addr, IS_USER(s));
714 }
715
716 if (!UCOP_SET_P) {
717 offset = UCOP_IMM10 << 2;
718 if (!UCOP_SET_U) {
719 offset = -offset;
720 }
721 if (offset != 0) {
722 tcg_gen_addi_i32(addr, addr, offset);
723 }
724 }
725 if (UCOP_SET_W) {
726 store_reg(s, UCOP_REG_N, addr);
727 } else {
728 dead_tmp(addr);
729 }
730 }
731
732 /* UniCore-F64 load/store multiple words */
733 static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
734 {
735 UniCore32CPU *cpu = uc32_env_get_cpu(env);
736 unsigned int i;
737 int j, n, freg;
738 TCGv tmp;
739 TCGv addr;
740
741 if (UCOP_REG_D != 0) {
742 ILLEGAL;
743 }
744 if (UCOP_REG_N == 31) {
745 ILLEGAL;
746 }
747 if ((insn << 24) == 0) {
748 ILLEGAL;
749 }
750
751 addr = load_reg(s, UCOP_REG_N);
752
753 n = 0;
754 for (i = 0; i < 8; i++) {
755 if (UCOP_SET(i)) {
756 n++;
757 }
758 }
759
760 if (UCOP_SET_U) {
761 if (UCOP_SET_P) { /* pre increment */
762 tcg_gen_addi_i32(addr, addr, 4);
763 } /* unnecessary to do anything when post increment */
764 } else {
765 if (UCOP_SET_P) { /* pre decrement */
766 tcg_gen_addi_i32(addr, addr, -(n * 4));
767 } else { /* post decrement */
768 if (n != 1) {
769 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
770 }
771 }
772 }
773
774 freg = ((insn >> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
775
776 for (i = 0, j = 0; i < 8; i++, freg++) {
777 if (!UCOP_SET(i)) {
778 continue;
779 }
780
781 if (UCOP_SET_L) { /* load */
782 tmp = gen_ld32(addr, IS_USER(s));
783 ucf64_gen_st32(tmp, freg);
784 } else { /* store */
785 tmp = ucf64_gen_ld32(freg);
786 gen_st32(tmp, addr, IS_USER(s));
787 }
788
789 j++;
790 /* unnecessary to add after the last transfer */
791 if (j != n) {
792 tcg_gen_addi_i32(addr, addr, 4);
793 }
794 }
795
796 if (UCOP_SET_W) { /* write back */
797 if (UCOP_SET_U) {
798 if (!UCOP_SET_P) { /* post increment */
799 tcg_gen_addi_i32(addr, addr, 4);
800 } /* unnecessary to do anything when pre increment */
801 } else {
802 if (UCOP_SET_P) {
803 /* pre decrement */
804 if (n != 1) {
805 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
806 }
807 } else {
808 /* post decrement */
809 tcg_gen_addi_i32(addr, addr, -(n * 4));
810 }
811 }
812 store_reg(s, UCOP_REG_N, addr);
813 } else {
814 dead_tmp(addr);
815 }
816 }
817
818 /* UniCore-F64 mrc/mcr */
819 static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
820 {
821 UniCore32CPU *cpu = uc32_env_get_cpu(env);
822 TCGv tmp;
823
824 if ((insn & 0xfe0003ff) == 0xe2000000) {
825 /* control register */
826 if ((UCOP_REG_N != UC32_UCF64_FPSCR) || (UCOP_REG_D == 31)) {
827 ILLEGAL;
828 }
829 if (UCOP_SET(24)) {
830 /* CFF */
831 tmp = new_tmp();
832 gen_helper_ucf64_get_fpscr(tmp, cpu_env);
833 store_reg(s, UCOP_REG_D, tmp);
834 } else {
835 /* CTF */
836 tmp = load_reg(s, UCOP_REG_D);
837 gen_helper_ucf64_set_fpscr(cpu_env, tmp);
838 dead_tmp(tmp);
839 gen_lookup_tb(s);
840 }
841 return;
842 }
843 if ((insn & 0xfe0003ff) == 0xe0000000) {
844 /* general register */
845 if (UCOP_REG_D == 31) {
846 ILLEGAL;
847 }
848 if (UCOP_SET(24)) { /* MFF */
849 tmp = ucf64_gen_ld32(UCOP_REG_N);
850 store_reg(s, UCOP_REG_D, tmp);
851 } else { /* MTF */
852 tmp = load_reg(s, UCOP_REG_D);
853 ucf64_gen_st32(tmp, UCOP_REG_N);
854 }
855 return;
856 }
857 if ((insn & 0xfb000000) == 0xe9000000) {
858 /* MFFC */
859 if (UCOP_REG_D != 31) {
860 ILLEGAL;
861 }
862 if (UCOP_UCF64_COND & 0x8) {
863 ILLEGAL;
864 }
865
866 tmp = new_tmp();
867 tcg_gen_movi_i32(tmp, UCOP_UCF64_COND);
868 if (UCOP_SET(26)) {
869 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
870 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
871 gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, tmp, cpu_env);
872 } else {
873 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
874 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
875 gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, tmp, cpu_env);
876 }
877 dead_tmp(tmp);
878 return;
879 }
880 ILLEGAL;
881 }
882
883 /* UniCore-F64 convert instructions */
884 static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
885 {
886 UniCore32CPU *cpu = uc32_env_get_cpu(env);
887
888 if (UCOP_UCF64_FMT == 3) {
889 ILLEGAL;
890 }
891 if (UCOP_REG_N != 0) {
892 ILLEGAL;
893 }
894 switch (UCOP_UCF64_FUNC) {
895 case 0: /* cvt.s */
896 switch (UCOP_UCF64_FMT) {
897 case 1 /* d */:
898 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
899 gen_helper_ucf64_df2sf(cpu_F0s, cpu_F0d, cpu_env);
900 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
901 break;
902 case 2 /* w */:
903 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
904 gen_helper_ucf64_si2sf(cpu_F0s, cpu_F0s, cpu_env);
905 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
906 break;
907 default /* s */:
908 ILLEGAL;
909 break;
910 }
911 break;
912 case 1: /* cvt.d */
913 switch (UCOP_UCF64_FMT) {
914 case 0 /* s */:
915 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
916 gen_helper_ucf64_sf2df(cpu_F0d, cpu_F0s, cpu_env);
917 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
918 break;
919 case 2 /* w */:
920 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
921 gen_helper_ucf64_si2df(cpu_F0d, cpu_F0s, cpu_env);
922 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
923 break;
924 default /* d */:
925 ILLEGAL;
926 break;
927 }
928 break;
929 case 4: /* cvt.w */
930 switch (UCOP_UCF64_FMT) {
931 case 0 /* s */:
932 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
933 gen_helper_ucf64_sf2si(cpu_F0s, cpu_F0s, cpu_env);
934 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
935 break;
936 case 1 /* d */:
937 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
938 gen_helper_ucf64_df2si(cpu_F0s, cpu_F0d, cpu_env);
939 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
940 break;
941 default /* w */:
942 ILLEGAL;
943 break;
944 }
945 break;
946 default:
947 ILLEGAL;
948 }
949 }
950
951 /* UniCore-F64 compare instructions */
952 static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
953 {
954 UniCore32CPU *cpu = uc32_env_get_cpu(env);
955
956 if (UCOP_SET(25)) {
957 ILLEGAL;
958 }
959 if (UCOP_REG_D != 0) {
960 ILLEGAL;
961 }
962
963 ILLEGAL; /* TODO */
964 if (UCOP_SET(24)) {
965 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
966 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
967 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
968 } else {
969 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
970 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
971 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
972 }
973 }
974
975 #define gen_helper_ucf64_movs(x, y) do { } while (0)
976 #define gen_helper_ucf64_movd(x, y) do { } while (0)
977
978 #define UCF64_OP1(name) do { \
979 if (UCOP_REG_N != 0) { \
980 ILLEGAL; \
981 } \
982 switch (UCOP_UCF64_FMT) { \
983 case 0 /* s */: \
984 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
985 ucf64_reg_offset(UCOP_REG_M)); \
986 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
987 tcg_gen_st_i32(cpu_F0s, cpu_env, \
988 ucf64_reg_offset(UCOP_REG_D)); \
989 break; \
990 case 1 /* d */: \
991 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
992 ucf64_reg_offset(UCOP_REG_M)); \
993 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
994 tcg_gen_st_i64(cpu_F0d, cpu_env, \
995 ucf64_reg_offset(UCOP_REG_D)); \
996 break; \
997 case 2 /* w */: \
998 ILLEGAL; \
999 break; \
1000 } \
1001 } while (0)
1002
1003 #define UCF64_OP2(name) do { \
1004 switch (UCOP_UCF64_FMT) { \
1005 case 0 /* s */: \
1006 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1007 ucf64_reg_offset(UCOP_REG_N)); \
1008 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1009 ucf64_reg_offset(UCOP_REG_M)); \
1010 gen_helper_ucf64_##name##s(cpu_F0s, \
1011 cpu_F0s, cpu_F1s, cpu_env); \
1012 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1013 ucf64_reg_offset(UCOP_REG_D)); \
1014 break; \
1015 case 1 /* d */: \
1016 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1017 ucf64_reg_offset(UCOP_REG_N)); \
1018 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1019 ucf64_reg_offset(UCOP_REG_M)); \
1020 gen_helper_ucf64_##name##d(cpu_F0d, \
1021 cpu_F0d, cpu_F1d, cpu_env); \
1022 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1023 ucf64_reg_offset(UCOP_REG_D)); \
1024 break; \
1025 case 2 /* w */: \
1026 ILLEGAL; \
1027 break; \
1028 } \
1029 } while (0)
1030
1031 /* UniCore-F64 data processing */
1032 static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1033 {
1034 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1035
1036 if (UCOP_UCF64_FMT == 3) {
1037 ILLEGAL;
1038 }
1039 switch (UCOP_UCF64_FUNC) {
1040 case 0: /* add */
1041 UCF64_OP2(add);
1042 break;
1043 case 1: /* sub */
1044 UCF64_OP2(sub);
1045 break;
1046 case 2: /* mul */
1047 UCF64_OP2(mul);
1048 break;
1049 case 4: /* div */
1050 UCF64_OP2(div);
1051 break;
1052 case 5: /* abs */
1053 UCF64_OP1(abs);
1054 break;
1055 case 6: /* mov */
1056 UCF64_OP1(mov);
1057 break;
1058 case 7: /* neg */
1059 UCF64_OP1(neg);
1060 break;
1061 default:
1062 ILLEGAL;
1063 }
1064 }
1065
1066 /* Disassemble an F64 instruction */
1067 static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1068 {
1069 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1070
1071 if (!UCOP_SET(29)) {
1072 if (UCOP_SET(26)) {
1073 do_ucf64_ldst_m(env, s, insn);
1074 } else {
1075 do_ucf64_ldst_i(env, s, insn);
1076 }
1077 } else {
1078 if (UCOP_SET(5)) {
1079 switch ((insn >> 26) & 0x3) {
1080 case 0:
1081 do_ucf64_datap(env, s, insn);
1082 break;
1083 case 1:
1084 ILLEGAL;
1085 break;
1086 case 2:
1087 do_ucf64_fcvt(env, s, insn);
1088 break;
1089 case 3:
1090 do_ucf64_fcmp(env, s, insn);
1091 break;
1092 }
1093 } else {
1094 do_ucf64_trans(env, s, insn);
1095 }
1096 }
1097 }
1098
1099 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1100 {
1101 #ifndef CONFIG_USER_ONLY
1102 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1103 #else
1104 return true;
1105 #endif
1106 }
1107
1108 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
1109 {
1110 if (use_goto_tb(s, dest)) {
1111 tcg_gen_goto_tb(n);
1112 gen_set_pc_im(dest);
1113 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1114 } else {
1115 gen_set_pc_im(dest);
1116 tcg_gen_exit_tb(0);
1117 }
1118 }
1119
1120 static inline void gen_jmp(DisasContext *s, uint32_t dest)
1121 {
1122 if (unlikely(s->singlestep_enabled)) {
1123 /* An indirect jump so that we still trigger the debug exception. */
1124 gen_bx_im(s, dest);
1125 } else {
1126 gen_goto_tb(s, 0, dest);
1127 s->is_jmp = DISAS_TB_JUMP;
1128 }
1129 }
1130
1131 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1132 static int gen_set_psr(DisasContext *s, uint32_t mask, int bsr, TCGv t0)
1133 {
1134 TCGv tmp;
1135 if (bsr) {
1136 /* ??? This is also undefined in system mode. */
1137 if (IS_USER(s)) {
1138 return 1;
1139 }
1140
1141 tmp = load_cpu_field(bsr);
1142 tcg_gen_andi_i32(tmp, tmp, ~mask);
1143 tcg_gen_andi_i32(t0, t0, mask);
1144 tcg_gen_or_i32(tmp, tmp, t0);
1145 store_cpu_field(tmp, bsr);
1146 } else {
1147 gen_set_asr(t0, mask);
1148 }
1149 dead_tmp(t0);
1150 gen_lookup_tb(s);
1151 return 0;
1152 }
1153
1154 /* Generate an old-style exception return. Marks pc as dead. */
1155 static void gen_exception_return(DisasContext *s, TCGv pc)
1156 {
1157 TCGv tmp;
1158 store_reg(s, 31, pc);
1159 tmp = load_cpu_field(bsr);
1160 gen_set_asr(tmp, 0xffffffff);
1161 dead_tmp(tmp);
1162 s->is_jmp = DISAS_UPDATE;
1163 }
1164
1165 static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
1166 uint32_t insn)
1167 {
1168 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1169
1170 switch (UCOP_CPNUM) {
1171 #ifndef CONFIG_USER_ONLY
1172 case 0:
1173 disas_cp0_insn(env, s, insn);
1174 break;
1175 case 1:
1176 disas_ocd_insn(env, s, insn);
1177 break;
1178 #endif
1179 case 2:
1180 disas_ucf64_insn(env, s, insn);
1181 break;
1182 default:
1183 /* Unknown coprocessor. */
1184 cpu_abort(CPU(cpu), "Unknown coprocessor!");
1185 }
1186 }
1187
1188 /* data processing instructions */
1189 static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1190 {
1191 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1192 TCGv tmp;
1193 TCGv tmp2;
1194 int logic_cc;
1195
1196 if (UCOP_OPCODES == 0x0f || UCOP_OPCODES == 0x0d) {
1197 if (UCOP_SET(23)) { /* CMOV instructions */
1198 if ((UCOP_CMOV_COND == 0xe) || (UCOP_CMOV_COND == 0xf)) {
1199 ILLEGAL;
1200 }
1201 /* if not always execute, we generate a conditional jump to
1202 next instruction */
1203 s->condlabel = gen_new_label();
1204 gen_test_cc(UCOP_CMOV_COND ^ 1, s->condlabel);
1205 s->condjmp = 1;
1206 }
1207 }
1208
1209 logic_cc = table_logic_cc[UCOP_OPCODES] & (UCOP_SET_S >> 24);
1210
1211 if (UCOP_SET(29)) {
1212 unsigned int val;
1213 /* immediate operand */
1214 val = UCOP_IMM_9;
1215 if (UCOP_SH_IM) {
1216 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1217 }
1218 tmp2 = new_tmp();
1219 tcg_gen_movi_i32(tmp2, val);
1220 if (logic_cc && UCOP_SH_IM) {
1221 gen_set_CF_bit31(tmp2);
1222 }
1223 } else {
1224 /* register */
1225 tmp2 = load_reg(s, UCOP_REG_M);
1226 if (UCOP_SET(5)) {
1227 tmp = load_reg(s, UCOP_REG_S);
1228 gen_uc32_shift_reg(tmp2, UCOP_SH_OP, tmp, logic_cc);
1229 } else {
1230 gen_uc32_shift_im(tmp2, UCOP_SH_OP, UCOP_SH_IM, logic_cc);
1231 }
1232 }
1233
1234 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1235 tmp = load_reg(s, UCOP_REG_N);
1236 } else {
1237 TCGV_UNUSED(tmp);
1238 }
1239
1240 switch (UCOP_OPCODES) {
1241 case 0x00:
1242 tcg_gen_and_i32(tmp, tmp, tmp2);
1243 if (logic_cc) {
1244 gen_logic_CC(tmp);
1245 }
1246 store_reg_bx(s, UCOP_REG_D, tmp);
1247 break;
1248 case 0x01:
1249 tcg_gen_xor_i32(tmp, tmp, tmp2);
1250 if (logic_cc) {
1251 gen_logic_CC(tmp);
1252 }
1253 store_reg_bx(s, UCOP_REG_D, tmp);
1254 break;
1255 case 0x02:
1256 if (UCOP_SET_S && UCOP_REG_D == 31) {
1257 /* SUBS r31, ... is used for exception return. */
1258 if (IS_USER(s)) {
1259 ILLEGAL;
1260 }
1261 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1262 gen_exception_return(s, tmp);
1263 } else {
1264 if (UCOP_SET_S) {
1265 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1266 } else {
1267 tcg_gen_sub_i32(tmp, tmp, tmp2);
1268 }
1269 store_reg_bx(s, UCOP_REG_D, tmp);
1270 }
1271 break;
1272 case 0x03:
1273 if (UCOP_SET_S) {
1274 gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
1275 } else {
1276 tcg_gen_sub_i32(tmp, tmp2, tmp);
1277 }
1278 store_reg_bx(s, UCOP_REG_D, tmp);
1279 break;
1280 case 0x04:
1281 if (UCOP_SET_S) {
1282 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
1283 } else {
1284 tcg_gen_add_i32(tmp, tmp, tmp2);
1285 }
1286 store_reg_bx(s, UCOP_REG_D, tmp);
1287 break;
1288 case 0x05:
1289 if (UCOP_SET_S) {
1290 gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
1291 } else {
1292 gen_add_carry(tmp, tmp, tmp2);
1293 }
1294 store_reg_bx(s, UCOP_REG_D, tmp);
1295 break;
1296 case 0x06:
1297 if (UCOP_SET_S) {
1298 gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
1299 } else {
1300 gen_sub_carry(tmp, tmp, tmp2);
1301 }
1302 store_reg_bx(s, UCOP_REG_D, tmp);
1303 break;
1304 case 0x07:
1305 if (UCOP_SET_S) {
1306 gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
1307 } else {
1308 gen_sub_carry(tmp, tmp2, tmp);
1309 }
1310 store_reg_bx(s, UCOP_REG_D, tmp);
1311 break;
1312 case 0x08:
1313 if (UCOP_SET_S) {
1314 tcg_gen_and_i32(tmp, tmp, tmp2);
1315 gen_logic_CC(tmp);
1316 }
1317 dead_tmp(tmp);
1318 break;
1319 case 0x09:
1320 if (UCOP_SET_S) {
1321 tcg_gen_xor_i32(tmp, tmp, tmp2);
1322 gen_logic_CC(tmp);
1323 }
1324 dead_tmp(tmp);
1325 break;
1326 case 0x0a:
1327 if (UCOP_SET_S) {
1328 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1329 }
1330 dead_tmp(tmp);
1331 break;
1332 case 0x0b:
1333 if (UCOP_SET_S) {
1334 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
1335 }
1336 dead_tmp(tmp);
1337 break;
1338 case 0x0c:
1339 tcg_gen_or_i32(tmp, tmp, tmp2);
1340 if (logic_cc) {
1341 gen_logic_CC(tmp);
1342 }
1343 store_reg_bx(s, UCOP_REG_D, tmp);
1344 break;
1345 case 0x0d:
1346 if (logic_cc && UCOP_REG_D == 31) {
1347 /* MOVS r31, ... is used for exception return. */
1348 if (IS_USER(s)) {
1349 ILLEGAL;
1350 }
1351 gen_exception_return(s, tmp2);
1352 } else {
1353 if (logic_cc) {
1354 gen_logic_CC(tmp2);
1355 }
1356 store_reg_bx(s, UCOP_REG_D, tmp2);
1357 }
1358 break;
1359 case 0x0e:
1360 tcg_gen_andc_i32(tmp, tmp, tmp2);
1361 if (logic_cc) {
1362 gen_logic_CC(tmp);
1363 }
1364 store_reg_bx(s, UCOP_REG_D, tmp);
1365 break;
1366 default:
1367 case 0x0f:
1368 tcg_gen_not_i32(tmp2, tmp2);
1369 if (logic_cc) {
1370 gen_logic_CC(tmp2);
1371 }
1372 store_reg_bx(s, UCOP_REG_D, tmp2);
1373 break;
1374 }
1375 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1376 dead_tmp(tmp2);
1377 }
1378 }
1379
1380 /* multiply */
1381 static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1382 {
1383 TCGv tmp, tmp2, tmp3, tmp4;
1384
1385 if (UCOP_SET(27)) {
1386 /* 64 bit mul */
1387 tmp = load_reg(s, UCOP_REG_M);
1388 tmp2 = load_reg(s, UCOP_REG_N);
1389 if (UCOP_SET(26)) {
1390 tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
1391 } else {
1392 tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
1393 }
1394 if (UCOP_SET(25)) { /* mult accumulate */
1395 tmp3 = load_reg(s, UCOP_REG_LO);
1396 tmp4 = load_reg(s, UCOP_REG_HI);
1397 tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, tmp3, tmp4);
1398 dead_tmp(tmp3);
1399 dead_tmp(tmp4);
1400 }
1401 store_reg(s, UCOP_REG_LO, tmp);
1402 store_reg(s, UCOP_REG_HI, tmp2);
1403 } else {
1404 /* 32 bit mul */
1405 tmp = load_reg(s, UCOP_REG_M);
1406 tmp2 = load_reg(s, UCOP_REG_N);
1407 tcg_gen_mul_i32(tmp, tmp, tmp2);
1408 dead_tmp(tmp2);
1409 if (UCOP_SET(25)) {
1410 /* Add */
1411 tmp2 = load_reg(s, UCOP_REG_S);
1412 tcg_gen_add_i32(tmp, tmp, tmp2);
1413 dead_tmp(tmp2);
1414 }
1415 if (UCOP_SET_S) {
1416 gen_logic_CC(tmp);
1417 }
1418 store_reg(s, UCOP_REG_D, tmp);
1419 }
1420 }
1421
1422 /* miscellaneous instructions */
1423 static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1424 {
1425 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1426 unsigned int val;
1427 TCGv tmp;
1428
1429 if ((insn & 0xffffffe0) == 0x10ffc120) {
1430 /* Trivial implementation equivalent to bx. */
1431 tmp = load_reg(s, UCOP_REG_M);
1432 gen_bx(s, tmp);
1433 return;
1434 }
1435
1436 if ((insn & 0xfbffc000) == 0x30ffc000) {
1437 /* PSR = immediate */
1438 val = UCOP_IMM_9;
1439 if (UCOP_SH_IM) {
1440 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1441 }
1442 tmp = new_tmp();
1443 tcg_gen_movi_i32(tmp, val);
1444 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1445 ILLEGAL;
1446 }
1447 return;
1448 }
1449
1450 if ((insn & 0xfbffffe0) == 0x12ffc020) {
1451 /* PSR.flag = reg */
1452 tmp = load_reg(s, UCOP_REG_M);
1453 if (gen_set_psr(s, ASR_NZCV, UCOP_SET_B, tmp)) {
1454 ILLEGAL;
1455 }
1456 return;
1457 }
1458
1459 if ((insn & 0xfbffffe0) == 0x10ffc020) {
1460 /* PSR = reg */
1461 tmp = load_reg(s, UCOP_REG_M);
1462 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1463 ILLEGAL;
1464 }
1465 return;
1466 }
1467
1468 if ((insn & 0xfbf83fff) == 0x10f80000) {
1469 /* reg = PSR */
1470 if (UCOP_SET_B) {
1471 if (IS_USER(s)) {
1472 ILLEGAL;
1473 }
1474 tmp = load_cpu_field(bsr);
1475 } else {
1476 tmp = new_tmp();
1477 gen_helper_asr_read(tmp, cpu_env);
1478 }
1479 store_reg(s, UCOP_REG_D, tmp);
1480 return;
1481 }
1482
1483 if ((insn & 0xfbf83fe0) == 0x12f80120) {
1484 /* clz */
1485 tmp = load_reg(s, UCOP_REG_M);
1486 if (UCOP_SET(26)) {
1487 /* clo */
1488 tcg_gen_not_i32(tmp, tmp);
1489 }
1490 tcg_gen_clzi_i32(tmp, tmp, 32);
1491 store_reg(s, UCOP_REG_D, tmp);
1492 return;
1493 }
1494
1495 /* otherwise */
1496 ILLEGAL;
1497 }
1498
1499 /* load/store I_offset and R_offset */
1500 static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1501 {
1502 unsigned int mmu_idx;
1503 TCGv tmp;
1504 TCGv tmp2;
1505
1506 tmp2 = load_reg(s, UCOP_REG_N);
1507 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
1508
1509 /* immediate */
1510 if (UCOP_SET_P) {
1511 gen_add_data_offset(s, insn, tmp2);
1512 }
1513
1514 if (UCOP_SET_L) {
1515 /* load */
1516 if (UCOP_SET_B) {
1517 tmp = gen_ld8u(tmp2, mmu_idx);
1518 } else {
1519 tmp = gen_ld32(tmp2, mmu_idx);
1520 }
1521 } else {
1522 /* store */
1523 tmp = load_reg(s, UCOP_REG_D);
1524 if (UCOP_SET_B) {
1525 gen_st8(tmp, tmp2, mmu_idx);
1526 } else {
1527 gen_st32(tmp, tmp2, mmu_idx);
1528 }
1529 }
1530 if (!UCOP_SET_P) {
1531 gen_add_data_offset(s, insn, tmp2);
1532 store_reg(s, UCOP_REG_N, tmp2);
1533 } else if (UCOP_SET_W) {
1534 store_reg(s, UCOP_REG_N, tmp2);
1535 } else {
1536 dead_tmp(tmp2);
1537 }
1538 if (UCOP_SET_L) {
1539 /* Complete the load. */
1540 if (UCOP_REG_D == 31) {
1541 gen_bx(s, tmp);
1542 } else {
1543 store_reg(s, UCOP_REG_D, tmp);
1544 }
1545 }
1546 }
1547
1548 /* SWP instruction */
1549 static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1550 {
1551 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1552 TCGv addr;
1553 TCGv tmp;
1554 TCGv tmp2;
1555
1556 if ((insn & 0xff003fe0) != 0x40000120) {
1557 ILLEGAL;
1558 }
1559
1560 /* ??? This is not really atomic. However we know
1561 we never have multiple CPUs running in parallel,
1562 so it is good enough. */
1563 addr = load_reg(s, UCOP_REG_N);
1564 tmp = load_reg(s, UCOP_REG_M);
1565 if (UCOP_SET_B) {
1566 tmp2 = gen_ld8u(addr, IS_USER(s));
1567 gen_st8(tmp, addr, IS_USER(s));
1568 } else {
1569 tmp2 = gen_ld32(addr, IS_USER(s));
1570 gen_st32(tmp, addr, IS_USER(s));
1571 }
1572 dead_tmp(addr);
1573 store_reg(s, UCOP_REG_D, tmp2);
1574 }
1575
1576 /* load/store hw/sb */
1577 static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1578 {
1579 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1580 TCGv addr;
1581 TCGv tmp;
1582
1583 if (UCOP_SH_OP == 0) {
1584 do_swap(env, s, insn);
1585 return;
1586 }
1587
1588 addr = load_reg(s, UCOP_REG_N);
1589 if (UCOP_SET_P) {
1590 gen_add_datah_offset(s, insn, addr);
1591 }
1592
1593 if (UCOP_SET_L) { /* load */
1594 switch (UCOP_SH_OP) {
1595 case 1:
1596 tmp = gen_ld16u(addr, IS_USER(s));
1597 break;
1598 case 2:
1599 tmp = gen_ld8s(addr, IS_USER(s));
1600 break;
1601 default: /* see do_swap */
1602 case 3:
1603 tmp = gen_ld16s(addr, IS_USER(s));
1604 break;
1605 }
1606 } else { /* store */
1607 if (UCOP_SH_OP != 1) {
1608 ILLEGAL;
1609 }
1610 tmp = load_reg(s, UCOP_REG_D);
1611 gen_st16(tmp, addr, IS_USER(s));
1612 }
1613 /* Perform base writeback before the loaded value to
1614 ensure correct behavior with overlapping index registers. */
1615 if (!UCOP_SET_P) {
1616 gen_add_datah_offset(s, insn, addr);
1617 store_reg(s, UCOP_REG_N, addr);
1618 } else if (UCOP_SET_W) {
1619 store_reg(s, UCOP_REG_N, addr);
1620 } else {
1621 dead_tmp(addr);
1622 }
1623 if (UCOP_SET_L) {
1624 /* Complete the load. */
1625 store_reg(s, UCOP_REG_D, tmp);
1626 }
1627 }
1628
1629 /* load/store multiple words */
1630 static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1631 {
1632 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1633 unsigned int val, i, mmu_idx;
1634 int j, n, reg, user, loaded_base;
1635 TCGv tmp;
1636 TCGv tmp2;
1637 TCGv addr;
1638 TCGv loaded_var;
1639
1640 if (UCOP_SET(7)) {
1641 ILLEGAL;
1642 }
1643 /* XXX: store correct base if write back */
1644 user = 0;
1645 if (UCOP_SET_B) { /* S bit in instruction table */
1646 if (IS_USER(s)) {
1647 ILLEGAL; /* only usable in supervisor mode */
1648 }
1649 if (UCOP_SET(18) == 0) { /* pc reg */
1650 user = 1;
1651 }
1652 }
1653
1654 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
1655 addr = load_reg(s, UCOP_REG_N);
1656
1657 /* compute total size */
1658 loaded_base = 0;
1659 TCGV_UNUSED(loaded_var);
1660 n = 0;
1661 for (i = 0; i < 6; i++) {
1662 if (UCOP_SET(i)) {
1663 n++;
1664 }
1665 }
1666 for (i = 9; i < 19; i++) {
1667 if (UCOP_SET(i)) {
1668 n++;
1669 }
1670 }
1671 /* XXX: test invalid n == 0 case ? */
1672 if (UCOP_SET_U) {
1673 if (UCOP_SET_P) {
1674 /* pre increment */
1675 tcg_gen_addi_i32(addr, addr, 4);
1676 } else {
1677 /* post increment */
1678 }
1679 } else {
1680 if (UCOP_SET_P) {
1681 /* pre decrement */
1682 tcg_gen_addi_i32(addr, addr, -(n * 4));
1683 } else {
1684 /* post decrement */
1685 if (n != 1) {
1686 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1687 }
1688 }
1689 }
1690
1691 j = 0;
1692 reg = UCOP_SET(6) ? 16 : 0;
1693 for (i = 0; i < 19; i++, reg++) {
1694 if (i == 6) {
1695 i = i + 3;
1696 }
1697 if (UCOP_SET(i)) {
1698 if (UCOP_SET_L) { /* load */
1699 tmp = gen_ld32(addr, mmu_idx);
1700 if (reg == 31) {
1701 gen_bx(s, tmp);
1702 } else if (user) {
1703 tmp2 = tcg_const_i32(reg);
1704 gen_helper_set_user_reg(cpu_env, tmp2, tmp);
1705 tcg_temp_free_i32(tmp2);
1706 dead_tmp(tmp);
1707 } else if (reg == UCOP_REG_N) {
1708 loaded_var = tmp;
1709 loaded_base = 1;
1710 } else {
1711 store_reg(s, reg, tmp);
1712 }
1713 } else { /* store */
1714 if (reg == 31) {
1715 /* special case: r31 = PC + 4 */
1716 val = (long)s->pc;
1717 tmp = new_tmp();
1718 tcg_gen_movi_i32(tmp, val);
1719 } else if (user) {
1720 tmp = new_tmp();
1721 tmp2 = tcg_const_i32(reg);
1722 gen_helper_get_user_reg(tmp, cpu_env, tmp2);
1723 tcg_temp_free_i32(tmp2);
1724 } else {
1725 tmp = load_reg(s, reg);
1726 }
1727 gen_st32(tmp, addr, mmu_idx);
1728 }
1729 j++;
1730 /* no need to add after the last transfer */
1731 if (j != n) {
1732 tcg_gen_addi_i32(addr, addr, 4);
1733 }
1734 }
1735 }
1736 if (UCOP_SET_W) { /* write back */
1737 if (UCOP_SET_U) {
1738 if (UCOP_SET_P) {
1739 /* pre increment */
1740 } else {
1741 /* post increment */
1742 tcg_gen_addi_i32(addr, addr, 4);
1743 }
1744 } else {
1745 if (UCOP_SET_P) {
1746 /* pre decrement */
1747 if (n != 1) {
1748 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1749 }
1750 } else {
1751 /* post decrement */
1752 tcg_gen_addi_i32(addr, addr, -(n * 4));
1753 }
1754 }
1755 store_reg(s, UCOP_REG_N, addr);
1756 } else {
1757 dead_tmp(addr);
1758 }
1759 if (loaded_base) {
1760 store_reg(s, UCOP_REG_N, loaded_var);
1761 }
1762 if (UCOP_SET_B && !user) {
1763 /* Restore ASR from BSR. */
1764 tmp = load_cpu_field(bsr);
1765 gen_set_asr(tmp, 0xffffffff);
1766 dead_tmp(tmp);
1767 s->is_jmp = DISAS_UPDATE;
1768 }
1769 }
1770
1771 /* branch (and link) */
1772 static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1773 {
1774 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1775 unsigned int val;
1776 int32_t offset;
1777 TCGv tmp;
1778
1779 if (UCOP_COND == 0xf) {
1780 ILLEGAL;
1781 }
1782
1783 if (UCOP_COND != 0xe) {
1784 /* if not always execute, we generate a conditional jump to
1785 next instruction */
1786 s->condlabel = gen_new_label();
1787 gen_test_cc(UCOP_COND ^ 1, s->condlabel);
1788 s->condjmp = 1;
1789 }
1790
1791 val = (int32_t)s->pc;
1792 if (UCOP_SET_L) {
1793 tmp = new_tmp();
1794 tcg_gen_movi_i32(tmp, val);
1795 store_reg(s, 30, tmp);
1796 }
1797 offset = (((int32_t)insn << 8) >> 8);
1798 val += (offset << 2); /* unicore is pc+4 */
1799 gen_jmp(s, val);
1800 }
1801
1802 static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
1803 {
1804 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1805 unsigned int insn;
1806
1807 insn = cpu_ldl_code(env, s->pc);
1808 s->pc += 4;
1809
1810 /* UniCore instructions class:
1811 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1812 * AAA : see switch case
1813 * BBBB : opcodes or cond or PUBW
1814 * C : S OR L
1815 * D : 8
1816 * E : 5
1817 */
1818 switch (insn >> 29) {
1819 case 0x0:
1820 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1821 do_mult(env, s, insn);
1822 break;
1823 }
1824
1825 if (UCOP_SET(8)) {
1826 do_misc(env, s, insn);
1827 break;
1828 }
1829 case 0x1:
1830 if (((UCOP_OPCODES >> 2) == 2) && !UCOP_SET_S) {
1831 do_misc(env, s, insn);
1832 break;
1833 }
1834 do_datap(env, s, insn);
1835 break;
1836
1837 case 0x2:
1838 if (UCOP_SET(8) && UCOP_SET(5)) {
1839 do_ldst_hwsb(env, s, insn);
1840 break;
1841 }
1842 if (UCOP_SET(8) || UCOP_SET(5)) {
1843 ILLEGAL;
1844 }
1845 case 0x3:
1846 do_ldst_ir(env, s, insn);
1847 break;
1848
1849 case 0x4:
1850 if (UCOP_SET(8)) {
1851 ILLEGAL; /* extended instructions */
1852 }
1853 do_ldst_m(env, s, insn);
1854 break;
1855 case 0x5:
1856 do_branch(env, s, insn);
1857 break;
1858 case 0x6:
1859 /* Coprocessor. */
1860 disas_coproc_insn(env, s, insn);
1861 break;
1862 case 0x7:
1863 if (!UCOP_SET(28)) {
1864 disas_coproc_insn(env, s, insn);
1865 break;
1866 }
1867 if ((insn & 0xff000000) == 0xff000000) { /* syscall */
1868 gen_set_pc_im(s->pc);
1869 s->is_jmp = DISAS_SYSCALL;
1870 break;
1871 }
1872 ILLEGAL;
1873 }
1874 }
1875
1876 /* generate intermediate code for basic block 'tb'. */
1877 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
1878 {
1879 CPUUniCore32State *env = cs->env_ptr;
1880 DisasContext dc1, *dc = &dc1;
1881 target_ulong pc_start;
1882 uint32_t next_page_start;
1883 int num_insns;
1884 int max_insns;
1885
1886 /* generate intermediate code */
1887 num_temps = 0;
1888
1889 pc_start = tb->pc;
1890
1891 dc->tb = tb;
1892
1893 dc->is_jmp = DISAS_NEXT;
1894 dc->pc = pc_start;
1895 dc->singlestep_enabled = cs->singlestep_enabled;
1896 dc->condjmp = 0;
1897 cpu_F0s = tcg_temp_new_i32();
1898 cpu_F1s = tcg_temp_new_i32();
1899 cpu_F0d = tcg_temp_new_i64();
1900 cpu_F1d = tcg_temp_new_i64();
1901 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1902 num_insns = 0;
1903 max_insns = tb->cflags & CF_COUNT_MASK;
1904 if (max_insns == 0) {
1905 max_insns = CF_COUNT_MASK;
1906 }
1907 if (max_insns > TCG_MAX_INSNS) {
1908 max_insns = TCG_MAX_INSNS;
1909 }
1910
1911 #ifndef CONFIG_USER_ONLY
1912 if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
1913 dc->user = 1;
1914 } else {
1915 dc->user = 0;
1916 }
1917 #endif
1918
1919 gen_tb_start(tb);
1920 do {
1921 tcg_gen_insn_start(dc->pc);
1922 num_insns++;
1923
1924 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1925 gen_set_pc_im(dc->pc);
1926 gen_exception(EXCP_DEBUG);
1927 dc->is_jmp = DISAS_JUMP;
1928 /* The address covered by the breakpoint must be included in
1929 [tb->pc, tb->pc + tb->size) in order to for it to be
1930 properly cleared -- thus we increment the PC here so that
1931 the logic setting tb->size below does the right thing. */
1932 dc->pc += 4;
1933 goto done_generating;
1934 }
1935
1936 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
1937 gen_io_start();
1938 }
1939
1940 disas_uc32_insn(env, dc);
1941
1942 if (num_temps) {
1943 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
1944 num_temps = 0;
1945 }
1946
1947 if (dc->condjmp && !dc->is_jmp) {
1948 gen_set_label(dc->condlabel);
1949 dc->condjmp = 0;
1950 }
1951 /* Translation stops when a conditional branch is encountered.
1952 * Otherwise the subsequent code could get translated several times.
1953 * Also stop translation when a page boundary is reached. This
1954 * ensures prefetch aborts occur at the right place. */
1955 } while (!dc->is_jmp && !tcg_op_buf_full() &&
1956 !cs->singlestep_enabled &&
1957 !singlestep &&
1958 dc->pc < next_page_start &&
1959 num_insns < max_insns);
1960
1961 if (tb->cflags & CF_LAST_IO) {
1962 if (dc->condjmp) {
1963 /* FIXME: This can theoretically happen with self-modifying
1964 code. */
1965 cpu_abort(cs, "IO on conditional branch instruction");
1966 }
1967 gen_io_end();
1968 }
1969
1970 /* At this stage dc->condjmp will only be set when the skipped
1971 instruction was a conditional branch or trap, and the PC has
1972 already been written. */
1973 if (unlikely(cs->singlestep_enabled)) {
1974 /* Make sure the pc is updated, and raise a debug exception. */
1975 if (dc->condjmp) {
1976 if (dc->is_jmp == DISAS_SYSCALL) {
1977 gen_exception(UC32_EXCP_PRIV);
1978 } else {
1979 gen_exception(EXCP_DEBUG);
1980 }
1981 gen_set_label(dc->condlabel);
1982 }
1983 if (dc->condjmp || !dc->is_jmp) {
1984 gen_set_pc_im(dc->pc);
1985 dc->condjmp = 0;
1986 }
1987 if (dc->is_jmp == DISAS_SYSCALL && !dc->condjmp) {
1988 gen_exception(UC32_EXCP_PRIV);
1989 } else {
1990 gen_exception(EXCP_DEBUG);
1991 }
1992 } else {
1993 /* While branches must always occur at the end of an IT block,
1994 there are a few other things that can cause us to terminate
1995 the TB in the middel of an IT block:
1996 - Exception generating instructions (bkpt, swi, undefined).
1997 - Page boundaries.
1998 - Hardware watchpoints.
1999 Hardware breakpoints have already been handled and skip this code.
2000 */
2001 switch (dc->is_jmp) {
2002 case DISAS_NEXT:
2003 gen_goto_tb(dc, 1, dc->pc);
2004 break;
2005 default:
2006 case DISAS_JUMP:
2007 case DISAS_UPDATE:
2008 /* indicate that the hash table must be used to find the next TB */
2009 tcg_gen_exit_tb(0);
2010 break;
2011 case DISAS_TB_JUMP:
2012 /* nothing more to generate */
2013 break;
2014 case DISAS_SYSCALL:
2015 gen_exception(UC32_EXCP_PRIV);
2016 break;
2017 }
2018 if (dc->condjmp) {
2019 gen_set_label(dc->condlabel);
2020 gen_goto_tb(dc, 1, dc->pc);
2021 dc->condjmp = 0;
2022 }
2023 }
2024
2025 done_generating:
2026 gen_tb_end(tb, num_insns);
2027
2028 #ifdef DEBUG_DISAS
2029 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
2030 && qemu_log_in_addr_range(pc_start)) {
2031 qemu_log_lock();
2032 qemu_log("----------------\n");
2033 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2034 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
2035 qemu_log("\n");
2036 qemu_log_unlock();
2037 }
2038 #endif
2039 tb->size = dc->pc - pc_start;
2040 tb->icount = num_insns;
2041 }
2042
2043 static const char *cpu_mode_names[16] = {
2044 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2045 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2046 };
2047
2048 #undef UCF64_DUMP_STATE
2049 #ifdef UCF64_DUMP_STATE
2050 static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
2051 fprintf_function cpu_fprintf, int flags)
2052 {
2053 int i;
2054 union {
2055 uint32_t i;
2056 float s;
2057 } s0, s1;
2058 CPU_DoubleU d;
2059 /* ??? This assumes float64 and double have the same layout.
2060 Oh well, it's only debug dumps. */
2061 union {
2062 float64 f64;
2063 double d;
2064 } d0;
2065
2066 for (i = 0; i < 16; i++) {
2067 d.d = env->ucf64.regs[i];
2068 s0.i = d.l.lower;
2069 s1.i = d.l.upper;
2070 d0.f64 = d.d;
2071 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2072 i * 2, (int)s0.i, s0.s,
2073 i * 2 + 1, (int)s1.i, s1.s);
2074 cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
2075 i, (uint64_t)d0.f64, d0.d);
2076 }
2077 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
2078 }
2079 #else
2080 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2081 #endif
2082
2083 void uc32_cpu_dump_state(CPUState *cs, FILE *f,
2084 fprintf_function cpu_fprintf, int flags)
2085 {
2086 UniCore32CPU *cpu = UNICORE32_CPU(cs);
2087 CPUUniCore32State *env = &cpu->env;
2088 int i;
2089 uint32_t psr;
2090
2091 for (i = 0; i < 32; i++) {
2092 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2093 if ((i % 4) == 3) {
2094 cpu_fprintf(f, "\n");
2095 } else {
2096 cpu_fprintf(f, " ");
2097 }
2098 }
2099 psr = cpu_asr_read(env);
2100 cpu_fprintf(f, "PSR=%08x %c%c%c%c %s\n",
2101 psr,
2102 psr & (1 << 31) ? 'N' : '-',
2103 psr & (1 << 30) ? 'Z' : '-',
2104 psr & (1 << 29) ? 'C' : '-',
2105 psr & (1 << 28) ? 'V' : '-',
2106 cpu_mode_names[psr & 0xf]);
2107
2108 cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
2109 }
2110
2111 void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb,
2112 target_ulong *data)
2113 {
2114 env->regs[31] = data[0];
2115 }
AR7 emulation for QEMU