tests/libqos/virtio-pci.c

   1 /*
   2  * libqos virtio PCI driver
   3  *
   4  * Copyright (c) 2014 Marc Marí
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "libqtest.h"
  12 #include "libqos/virtio.h"
  13 #include "libqos/virtio-pci.h"
  14 #include "libqos/pci.h"
  15 #include "libqos/pci-pc.h"
  16 #include "libqos/malloc.h"
  17 #include "libqos/malloc-pc.h"
  18 #include "libqos/qgraph.h"
  19 #include "standard-headers/linux/virtio_ring.h"
  20 #include "standard-headers/linux/virtio_pci.h"
  21
  22 #include "hw/pci/pci.h"
  23 #include "hw/pci/pci_regs.h"
  24
  25 /* virtio-pci is a superclass of all virtio-xxx-pci devices;
  26  * the relation between virtio-pci and virtio-xxx-pci is implicit,
  27  * and therefore virtio-pci does not produce virtio and is not
  28  * reached by any edge, not even as a "contains" edge.
  29  * In facts, every device is a QVirtioPCIDevice with
  30  * additional fields, since every one has its own
  31  * number of queues and various attributes.
  32  * Virtio-pci provides default functions to start the
  33  * hw and destroy the object, and nodes that want to
  34  * override them should always remember to call the
  35  * original qvirtio_pci_destructor and qvirtio_pci_start_hw.
  36  */
  37
  38 static inline bool qvirtio_pci_is_big_endian(QVirtioPCIDevice *dev)
  39 {
  40     QPCIBus *bus = dev->pdev->bus;
  41
  42     /* FIXME: virtio 1.0 is always little-endian */
  43     return qtest_big_endian(bus->qts);
  44 }
  45
  46 #define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
  47
  48 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
  49 {
  50     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  51     return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  52 }
  53
  54 /* PCI is always read in little-endian order
  55  * but virtio ( < 1.0) is in guest order
  56  * so with a big-endian guest the order has been reversed,
  57  * reverse it again
  58  * virtio-1.0 is always little-endian, like PCI, but this
  59  * case will be managed inside qvirtio_pci_is_big_endian()
  60  */
  61
  62 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
  63 {
  64     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  65     uint16_t value;
  66
  67     value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  68     if (qvirtio_is_big_endian(d)) {
  69         value = bswap16(value);
  70     }
  71     return value;
  72 }
  73
  74 static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
  75 {
  76     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  77     uint32_t value;
  78
  79     value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  80     if (qvirtio_is_big_endian(d)) {
  81         value = bswap32(value);
  82     }
  83     return value;
  84 }
  85
  86 static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
  87 {
  88     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  89     uint64_t val;
  90
  91     val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  92     if (qvirtio_is_big_endian(d)) {
  93         val = bswap64(val);
  94     }
  95
  96     return val;
  97 }
  98
  99 static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
 100 {
 101     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 102     return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES);
 103 }
 104
 105 static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
 106 {
 107     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 108     qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES, features);
 109 }
 110
 111 static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
 112 {
 113     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 114     return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES);
 115 }
 116
 117 static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
 118 {
 119     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 120     return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS);
 121 }
 122
 123 static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
 124 {
 125     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 126     qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status);
 127 }
 128
 129 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
 130 {
 131     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 132     QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
 133     uint32_t data;
 134
 135     if (dev->pdev->msix_enabled) {
 136         g_assert_cmpint(vqpci->msix_entry, !=, -1);
 137         if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
 138             /* No ISR checking should be done if masked, but read anyway */
 139             return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
 140         } else {
 141             data = readl(vqpci->msix_addr);
 142             if (data == vqpci->msix_data) {
 143                 writel(vqpci->msix_addr, 0);
 144                 return true;
 145             } else {
 146                 return false;
 147             }
 148         }
 149     } else {
 150         return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
 151     }
 152 }
 153
 154 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
 155 {
 156     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 157     uint32_t data;
 158
 159     if (dev->pdev->msix_enabled) {
 160         g_assert_cmpint(dev->config_msix_entry, !=, -1);
 161         if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
 162             /* No ISR checking should be done if masked, but read anyway */
 163             return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
 164         } else {
 165             data = readl(dev->config_msix_addr);
 166             if (data == dev->config_msix_data) {
 167                 writel(dev->config_msix_addr, 0);
 168                 return true;
 169             } else {
 170                 return false;
 171             }
 172         }
 173     } else {
 174         return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
 175     }
 176 }
 177
 178 static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
 179 {
 180     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 181     qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_SEL, index);
 182 }
 183
 184 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
 185 {
 186     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 187     return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM);
 188 }
 189
 190 static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
 191 {
 192     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 193     qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn);
 194 }
 195
 196 static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
 197                                         QGuestAllocator *alloc, uint16_t index)
 198 {
 199     uint32_t feat;
 200     uint64_t addr;
 201     QVirtQueuePCI *vqpci;
 202     QVirtioPCIDevice *qvpcidev = container_of(d, QVirtioPCIDevice, vdev);
 203
 204     vqpci = g_malloc0(sizeof(*vqpci));
 205     feat = qvirtio_pci_get_guest_features(d);
 206
 207     qvirtio_pci_queue_select(d, index);
 208     vqpci->vq.index = index;
 209     vqpci->vq.size = qvirtio_pci_get_queue_size(d);
 210     vqpci->vq.free_head = 0;
 211     vqpci->vq.num_free = vqpci->vq.size;
 212     vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
 213     vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
 214     vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
 215
 216     vqpci->msix_entry = -1;
 217     vqpci->msix_addr = 0;
 218     vqpci->msix_data = 0x12345678;
 219
 220     /* Check different than 0 */
 221     g_assert_cmpint(vqpci->vq.size, !=, 0);
 222
 223     /* Check power of 2 */
 224     g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
 225
 226     addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
 227                                           VIRTIO_PCI_VRING_ALIGN));
 228     qvring_init(qvpcidev->pdev->bus->qts, alloc, &vqpci->vq, addr);
 229     qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);
 230
 231     return &vqpci->vq;
 232 }
 233
 234 static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
 235                                           QGuestAllocator *alloc)
 236 {
 237     QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
 238
 239     guest_free(alloc, vq->desc);
 240     g_free(vqpci);
 241 }
 242
 243 static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
 244 {
 245     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 246     qpci_io_writew(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
 247 }
 248
 249 const QVirtioBus qvirtio_pci = {
 250     .config_readb = qvirtio_pci_config_readb,
 251     .config_readw = qvirtio_pci_config_readw,
 252     .config_readl = qvirtio_pci_config_readl,
 253     .config_readq = qvirtio_pci_config_readq,
 254     .get_features = qvirtio_pci_get_features,
 255     .set_features = qvirtio_pci_set_features,
 256     .get_guest_features = qvirtio_pci_get_guest_features,
 257     .get_status = qvirtio_pci_get_status,
 258     .set_status = qvirtio_pci_set_status,
 259     .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
 260     .get_config_isr_status = qvirtio_pci_get_config_isr_status,
 261     .queue_select = qvirtio_pci_queue_select,
 262     .get_queue_size = qvirtio_pci_get_queue_size,
 263     .set_queue_address = qvirtio_pci_set_queue_address,
 264     .virtqueue_setup = qvirtio_pci_virtqueue_setup,
 265     .virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
 266     .virtqueue_kick = qvirtio_pci_virtqueue_kick,
 267 };
 268
 269 void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
 270 {
 271     qpci_device_enable(d->pdev);
 272     d->bar = qpci_iomap(d->pdev, 0, NULL);
 273 }
 274
 275 void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
 276 {
 277     qpci_iounmap(d->pdev, d->bar);
 278 }
 279
 280 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
 281                                         QGuestAllocator *alloc, uint16_t entry)
 282 {
 283     uint16_t vector;
 284     uint32_t control;
 285     uint64_t off;
 286
 287     g_assert(d->pdev->msix_enabled);
 288     off = d->pdev->msix_table_off + (entry * 16);
 289
 290     g_assert_cmpint(entry, >=, 0);
 291     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 292     vqpci->msix_entry = entry;
 293
 294     vqpci->msix_addr = guest_alloc(alloc, 4);
 295     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 296                    off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL);
 297     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 298                    off + PCI_MSIX_ENTRY_UPPER_ADDR,
 299                    (vqpci->msix_addr >> 32) & ~0UL);
 300     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 301                    off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
 302
 303     control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
 304                             off + PCI_MSIX_ENTRY_VECTOR_CTRL);
 305     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 306                    off + PCI_MSIX_ENTRY_VECTOR_CTRL,
 307                    control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 308
 309     qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
 310     qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry);
 311     vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR);
 312     g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
 313 }
 314
 315 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
 316                                         QGuestAllocator *alloc, uint16_t entry)
 317 {
 318     uint16_t vector;
 319     uint32_t control;
 320     uint64_t off;
 321
 322     g_assert(d->pdev->msix_enabled);
 323     off = d->pdev->msix_table_off + (entry * 16);
 324
 325     g_assert_cmpint(entry, >=, 0);
 326     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 327     d->config_msix_entry = entry;
 328
 329     d->config_msix_data = 0x12345678;
 330     d->config_msix_addr = guest_alloc(alloc, 4);
 331
 332     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 333                    off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL);
 334     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 335                    off + PCI_MSIX_ENTRY_UPPER_ADDR,
 336                    (d->config_msix_addr >> 32) & ~0UL);
 337     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 338                    off + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
 339
 340     control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
 341                             off + PCI_MSIX_ENTRY_VECTOR_CTRL);
 342     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 343                    off + PCI_MSIX_ENTRY_VECTOR_CTRL,
 344                    control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 345
 346     qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry);
 347     vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR);
 348     g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
 349 }
 350
 351 void qvirtio_pci_destructor(QOSGraphObject *obj)
 352 {
 353     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
 354     qvirtio_pci_device_disable(dev);
 355     g_free(dev->pdev);
 356 }
 357
 358 void qvirtio_pci_start_hw(QOSGraphObject *obj)
 359 {
 360     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
 361     qvirtio_pci_device_enable(dev);
 362     qvirtio_start_device(&dev->vdev);
 363 }
 364
 365 static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice *pci_dev)
 366 {
 367     dev->pdev = pci_dev;
 368     dev->vdev.device_type = qpci_config_readw(pci_dev, PCI_SUBSYSTEM_ID);
 369
 370     dev->config_msix_entry = -1;
 371
 372     dev->vdev.bus = &qvirtio_pci;
 373     dev->vdev.big_endian = qvirtio_pci_is_big_endian(dev);
 374
 375     /* each virtio-xxx-pci device should override at least this function */
 376     dev->obj.get_driver = NULL;
 377     dev->obj.start_hw = qvirtio_pci_start_hw;
 378     dev->obj.destructor = qvirtio_pci_destructor;
 379 }
 380
 381 void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr)
 382 {
 383     QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
 384     g_assert_nonnull(pci_dev);
 385     qvirtio_pci_init_from_pcidev(dev, pci_dev);
 386 }
 387
 388 QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr)
 389 {
 390     QVirtioPCIDevice *dev;
 391     QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
 392     if (!pci_dev) {
 393         return NULL;
 394     }
 395
 396     dev = g_new0(QVirtioPCIDevice, 1);
 397     qvirtio_pci_init_from_pcidev(dev, pci_dev);
 398     dev->obj.free = g_free;
 399     return dev;
 400 }