hw/scsi/esp-pci.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/pci/pci.h"
  27 #include "hw/nvram/eeprom93xx.h"
  28 #include "hw/scsi/esp.h"
  29 #include "trace.h"
  30 #include "qemu/log.h"
  31
  32 #define TYPE_AM53C974_DEVICE "am53c974"
  33
  34 #define PCI_ESP(obj) \
  35     OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
  36
  37 #define DMA_CMD   0x0
  38 #define DMA_STC   0x1
  39 #define DMA_SPA   0x2
  40 #define DMA_WBC   0x3
  41 #define DMA_WAC   0x4
  42 #define DMA_STAT  0x5
  43 #define DMA_SMDLA 0x6
  44 #define DMA_WMAC  0x7
  45
  46 #define DMA_CMD_MASK   0x03
  47 #define DMA_CMD_DIAG   0x04
  48 #define DMA_CMD_MDL    0x10
  49 #define DMA_CMD_INTE_P 0x20
  50 #define DMA_CMD_INTE_D 0x40
  51 #define DMA_CMD_DIR    0x80
  52
  53 #define DMA_STAT_PWDN    0x01
  54 #define DMA_STAT_ERROR   0x02
  55 #define DMA_STAT_ABORT   0x04
  56 #define DMA_STAT_DONE    0x08
  57 #define DMA_STAT_SCSIINT 0x10
  58 #define DMA_STAT_BCMBLT  0x20
  59
  60 #define SBAC_STATUS 0x1000
  61
  62 typedef struct PCIESPState {
  63     /*< private >*/
  64     PCIDevice parent_obj;
  65     /*< public >*/
  66
  67     MemoryRegion io;
  68     uint32_t dma_regs[8];
  69     uint32_t sbac;
  70     ESPState esp;
  71 } PCIESPState;
  72
  73 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
  74 {
  75     trace_esp_pci_dma_idle(val);
  76     esp_dma_enable(&pci->esp, 0, 0);
  77 }
  78
  79 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
  80 {
  81     trace_esp_pci_dma_blast(val);
  82     qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
  83 }
  84
  85 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
  86 {
  87     trace_esp_pci_dma_abort(val);
  88     if (pci->esp.current_req) {
  89         scsi_req_cancel(pci->esp.current_req);
  90     }
  91 }
  92
  93 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
  94 {
  95     trace_esp_pci_dma_start(val);
  96
  97     pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
  98     pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
  99     pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
 100
 101     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 102                                | DMA_STAT_DONE | DMA_STAT_ABORT
 103                                | DMA_STAT_ERROR | DMA_STAT_PWDN);
 104
 105     esp_dma_enable(&pci->esp, 0, 1);
 106 }
 107
 108 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
 109 {
 110     trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
 111     switch (saddr) {
 112     case DMA_CMD:
 113         pci->dma_regs[saddr] = val;
 114         switch (val & DMA_CMD_MASK) {
 115         case 0x0: /* IDLE */
 116             esp_pci_handle_idle(pci, val);
 117             break;
 118         case 0x1: /* BLAST */
 119             esp_pci_handle_blast(pci, val);
 120             break;
 121         case 0x2: /* ABORT */
 122             esp_pci_handle_abort(pci, val);
 123             break;
 124         case 0x3: /* START */
 125             esp_pci_handle_start(pci, val);
 126             break;
 127         default: /* can't happen */
 128             abort();
 129         }
 130         break;
 131     case DMA_STC:
 132     case DMA_SPA:
 133     case DMA_SMDLA:
 134         pci->dma_regs[saddr] = val;
 135         break;
 136     case DMA_STAT:
 137         if (!(pci->sbac & SBAC_STATUS)) {
 138             /* clear some bits on write */
 139             uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
 140             pci->dma_regs[DMA_STAT] &= ~(val & mask);
 141         }
 142         break;
 143     default:
 144         trace_esp_pci_error_invalid_write_dma(val, saddr);
 145         return;
 146     }
 147 }
 148
 149 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
 150 {
 151     uint32_t val;
 152
 153     val = pci->dma_regs[saddr];
 154     if (saddr == DMA_STAT) {
 155         if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
 156             val |= DMA_STAT_SCSIINT;
 157         }
 158         if (pci->sbac & SBAC_STATUS) {
 159             pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
 160                                          DMA_STAT_DONE);
 161         }
 162     }
 163
 164     trace_esp_pci_dma_read(saddr, val);
 165     return val;
 166 }
 167
 168 static void esp_pci_io_write(void *opaque, hwaddr addr,
 169                              uint64_t val, unsigned int size)
 170 {
 171     PCIESPState *pci = opaque;
 172
 173     if (size < 4 || addr & 3) {
 174         /* need to upgrade request: we only support 4-bytes accesses */
 175         uint32_t current = 0, mask;
 176         int shift;
 177
 178         if (addr < 0x40) {
 179             current = pci->esp.wregs[addr >> 2];
 180         } else if (addr < 0x60) {
 181             current = pci->dma_regs[(addr - 0x40) >> 2];
 182         } else if (addr < 0x74) {
 183             current = pci->sbac;
 184         }
 185
 186         shift = (4 - size) * 8;
 187         mask = (~(uint32_t)0 << shift) >> shift;
 188
 189         shift = ((4 - (addr & 3)) & 3) * 8;
 190         val <<= shift;
 191         val |= current & ~(mask << shift);
 192         addr &= ~3;
 193         size = 4;
 194     }
 195
 196     if (addr < 0x40) {
 197         /* SCSI core reg */
 198         esp_reg_write(&pci->esp, addr >> 2, val);
 199     } else if (addr < 0x60) {
 200         /* PCI DMA CCB */
 201         esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
 202     } else if (addr == 0x70) {
 203         /* DMA SCSI Bus and control */
 204         trace_esp_pci_sbac_write(pci->sbac, val);
 205         pci->sbac = val;
 206     } else {
 207         trace_esp_pci_error_invalid_write((int)addr);
 208     }
 209 }
 210
 211 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
 212                                 unsigned int size)
 213 {
 214     PCIESPState *pci = opaque;
 215     uint32_t ret;
 216
 217     if (addr < 0x40) {
 218         /* SCSI core reg */
 219         ret = esp_reg_read(&pci->esp, addr >> 2);
 220     } else if (addr < 0x60) {
 221         /* PCI DMA CCB */
 222         ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
 223     } else if (addr == 0x70) {
 224         /* DMA SCSI Bus and control */
 225         trace_esp_pci_sbac_read(pci->sbac);
 226         ret = pci->sbac;
 227     } else {
 228         /* Invalid region */
 229         trace_esp_pci_error_invalid_read((int)addr);
 230         ret = 0;
 231     }
 232
 233     /* give only requested data */
 234     ret >>= (addr & 3) * 8;
 235     ret &= ~(~(uint64_t)0 << (8 * size));
 236
 237     return ret;
 238 }
 239
 240 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
 241                                   DMADirection dir)
 242 {
 243     dma_addr_t addr;
 244     DMADirection expected_dir;
 245
 246     if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
 247         expected_dir = DMA_DIRECTION_FROM_DEVICE;
 248     } else {
 249         expected_dir = DMA_DIRECTION_TO_DEVICE;
 250     }
 251
 252     if (dir != expected_dir) {
 253         trace_esp_pci_error_invalid_dma_direction();
 254         return;
 255     }
 256
 257     if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
 258         qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
 259     }
 260
 261     addr = pci->dma_regs[DMA_SPA];
 262     if (pci->dma_regs[DMA_WBC] < len) {
 263         len = pci->dma_regs[DMA_WBC];
 264     }
 265
 266     pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
 267
 268     /* update status registers */
 269     pci->dma_regs[DMA_WBC] -= len;
 270     pci->dma_regs[DMA_WAC] += len;
 271     if (pci->dma_regs[DMA_WBC] == 0) {
 272         pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 273     }
 274 }
 275
 276 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
 277 {
 278     PCIESPState *pci = opaque;
 279     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
 280 }
 281
 282 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
 283 {
 284     PCIESPState *pci = opaque;
 285     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
 286 }
 287
 288 static const MemoryRegionOps esp_pci_io_ops = {
 289     .read = esp_pci_io_read,
 290     .write = esp_pci_io_write,
 291     .endianness = DEVICE_LITTLE_ENDIAN,
 292     .impl = {
 293         .min_access_size = 1,
 294         .max_access_size = 4,
 295     },
 296 };
 297
 298 static void esp_pci_hard_reset(DeviceState *dev)
 299 {
 300     PCIESPState *pci = PCI_ESP(dev);
 301     esp_hard_reset(&pci->esp);
 302     pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
 303                               | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
 304     pci->dma_regs[DMA_WBC] &= ~0xffff;
 305     pci->dma_regs[DMA_WAC] = 0xffffffff;
 306     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 307                                | DMA_STAT_DONE | DMA_STAT_ABORT
 308                                | DMA_STAT_ERROR);
 309     pci->dma_regs[DMA_WMAC] = 0xfffffffd;
 310 }
 311
 312 static const VMStateDescription vmstate_esp_pci_scsi = {
 313     .name = "pciespscsi",
 314     .version_id = 0,
 315     .minimum_version_id = 0,
 316     .fields = (VMStateField[]) {
 317         VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
 318         VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
 319         VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
 320         VMSTATE_END_OF_LIST()
 321     }
 322 };
 323
 324 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
 325                                      size_t resid)
 326 {
 327     ESPState *s = req->hba_private;
 328     PCIESPState *pci = container_of(s, PCIESPState, esp);
 329
 330     esp_command_complete(req, status, resid);
 331     pci->dma_regs[DMA_WBC] = 0;
 332     pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 333 }
 334
 335 static const struct SCSIBusInfo esp_pci_scsi_info = {
 336     .tcq = false,
 337     .max_target = ESP_MAX_DEVS,
 338     .max_lun = 7,
 339
 340     .transfer_data = esp_transfer_data,
 341     .complete = esp_pci_command_complete,
 342     .cancel = esp_request_cancelled,
 343 };
 344
 345 static int esp_pci_scsi_init(PCIDevice *dev)
 346 {
 347     PCIESPState *pci = PCI_ESP(dev);
 348     DeviceState *d = DEVICE(dev);
 349     ESPState *s = &pci->esp;
 350     uint8_t *pci_conf;
 351     Error *err = NULL;
 352
 353     pci_conf = dev->config;
 354
 355     /* Interrupt pin A */
 356     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 357
 358     s->dma_memory_read = esp_pci_dma_memory_read;
 359     s->dma_memory_write = esp_pci_dma_memory_write;
 360     s->dma_opaque = pci;
 361     s->chip_id = TCHI_AM53C974;
 362     memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
 363                           "esp-io", 0x80);
 364
 365     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
 366     s->irq = pci_allocate_irq(dev);
 367
 368     scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
 369     if (!d->hotplugged) {
 370         scsi_bus_legacy_handle_cmdline(&s->bus, &err);
 371         if (err != NULL) {
 372             error_free(err);
 373             return -1;
 374         }
 375     }
 376     return 0;
 377 }
 378
 379 static void esp_pci_scsi_uninit(PCIDevice *d)
 380 {
 381     PCIESPState *pci = PCI_ESP(d);
 382
 383     qemu_free_irq(pci->esp.irq);
 384 }
 385
 386 static void esp_pci_class_init(ObjectClass *klass, void *data)
 387 {
 388     DeviceClass *dc = DEVICE_CLASS(klass);
 389     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 390
 391     k->init = esp_pci_scsi_init;
 392     k->exit = esp_pci_scsi_uninit;
 393     k->vendor_id = PCI_VENDOR_ID_AMD;
 394     k->device_id = PCI_DEVICE_ID_AMD_SCSI;
 395     k->revision = 0x10;
 396     k->class_id = PCI_CLASS_STORAGE_SCSI;
 397     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 398     dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
 399     dc->reset = esp_pci_hard_reset;
 400     dc->vmsd = &vmstate_esp_pci_scsi;
 401 }
 402
 403 static const TypeInfo esp_pci_info = {
 404     .name = TYPE_AM53C974_DEVICE,
 405     .parent = TYPE_PCI_DEVICE,
 406     .instance_size = sizeof(PCIESPState),
 407     .class_init = esp_pci_class_init,
 408 };
 409
 410 typedef struct {
 411     PCIESPState pci;
 412     eeprom_t *eeprom;
 413 } DC390State;
 414
 415 #define TYPE_DC390_DEVICE "dc390"
 416 #define DC390(obj) \
 417     OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
 418
 419 #define EE_ADAPT_SCSI_ID 64
 420 #define EE_MODE2         65
 421 #define EE_DELAY         66
 422 #define EE_TAG_CMD_NUM   67
 423 #define EE_ADAPT_OPTIONS 68
 424 #define EE_BOOT_SCSI_ID  69
 425 #define EE_BOOT_SCSI_LUN 70
 426 #define EE_CHKSUM1       126
 427 #define EE_CHKSUM2       127
 428
 429 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
 430 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
 431 #define EE_ADAPT_OPTION_INT13           0x04
 432 #define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
 433
 434
 435 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
 436 {
 437     DC390State *pci = DC390(dev);
 438     uint32_t val;
 439
 440     val = pci_default_read_config(dev, addr, l);
 441
 442     if (addr == 0x00 && l == 1) {
 443         /* First byte of address space is AND-ed with EEPROM DO line */
 444         if (!eeprom93xx_read(pci->eeprom)) {
 445             val &= ~0xff;
 446         }
 447     }
 448
 449     return val;
 450 }
 451
 452 static void dc390_write_config(PCIDevice *dev,
 453                                uint32_t addr, uint32_t val, int l)
 454 {
 455     DC390State *pci = DC390(dev);
 456     if (addr == 0x80) {
 457         /* EEPROM write */
 458         int eesk = val & 0x80 ? 1 : 0;
 459         int eedi = val & 0x40 ? 1 : 0;
 460         eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
 461     } else if (addr == 0xc0) {
 462         /* EEPROM CS low */
 463         eeprom93xx_write(pci->eeprom, 0, 0, 0);
 464     } else {
 465         pci_default_write_config(dev, addr, val, l);
 466     }
 467 }
 468
 469 static int dc390_scsi_init(PCIDevice *dev)
 470 {
 471     DC390State *pci = DC390(dev);
 472     uint8_t *contents;
 473     uint16_t chksum = 0;
 474     int i, ret;
 475
 476     /* init base class */
 477     ret = esp_pci_scsi_init(dev);
 478     if (ret < 0) {
 479         return ret;
 480     }
 481
 482     /* EEPROM */
 483     pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
 484
 485     /* set default eeprom values */
 486     contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
 487
 488     for (i = 0; i < 16; i++) {
 489         contents[i * 2] = 0x57;
 490         contents[i * 2 + 1] = 0x00;
 491     }
 492     contents[EE_ADAPT_SCSI_ID] = 7;
 493     contents[EE_MODE2] = 0x0f;
 494     contents[EE_TAG_CMD_NUM] = 0x04;
 495     contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
 496                                | EE_ADAPT_OPTION_BOOT_FROM_CDROM
 497                                | EE_ADAPT_OPTION_INT13;
 498
 499     /* update eeprom checksum */
 500     for (i = 0; i < EE_CHKSUM1; i += 2) {
 501         chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
 502     }
 503     chksum = 0x1234 - chksum;
 504     contents[EE_CHKSUM1] = chksum & 0xff;
 505     contents[EE_CHKSUM2] = chksum >> 8;
 506
 507     return 0;
 508 }
 509
 510 static void dc390_class_init(ObjectClass *klass, void *data)
 511 {
 512     DeviceClass *dc = DEVICE_CLASS(klass);
 513     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 514
 515     k->init = dc390_scsi_init;
 516     k->config_read = dc390_read_config;
 517     k->config_write = dc390_write_config;
 518     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 519     dc->desc = "Tekram DC-390 SCSI adapter";
 520 }
 521
 522 static const TypeInfo dc390_info = {
 523     .name = "dc390",
 524     .parent = TYPE_AM53C974_DEVICE,
 525     .instance_size = sizeof(DC390State),
 526     .class_init = dc390_class_init,
 527 };
 528
 529 static void esp_pci_register_types(void)
 530 {
 531     type_register_static(&esp_pci_info);
 532     type_register_static(&dc390_info);
 533 }
 534
 535 type_init(esp_pci_register_types)