hw/microblaze/pic_cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU interrupt wrapper logic.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "pic_cpu.h"
  27
  28 #define D(x)
  29
  30 static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
  31 {
  32     MicroBlazeCPU *cpu = opaque;
  33     CPUState *cs = CPU(cpu);
  34     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  35
  36     if (level) {
  37         cpu_interrupt(cs, type);
  38     } else {
  39         cpu_reset_interrupt(cs, type);
  40     }
  41 }
  42
  43 qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
  44 {
  45     return qemu_allocate_irqs(microblaze_pic_cpu_handler, mb_env_get_cpu(env),
  46                               2);
  47 }