hw/isa/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "hw/isa/vt82c686.h"
  15 #include "hw/i2c/i2c.h"
  16 #include "hw/pci/pci.h"
  17 #include "hw/qdev-properties.h"
  18 #include "hw/isa/isa.h"
  19 #include "hw/isa/superio.h"
  20 #include "hw/sysbus.h"
  21 #include "migration/vmstate.h"
  22 #include "hw/mips/mips.h"
  23 #include "hw/isa/apm.h"
  24 #include "hw/acpi/acpi.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "qemu/module.h"
  27 #include "qemu/timer.h"
  28 #include "exec/address-spaces.h"
  29
  30 /* #define DEBUG_VT82C686B */
  31
  32 #ifdef DEBUG_VT82C686B
  33 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 typedef struct SuperIOConfig {
  39     uint8_t config[0x100];
  40     uint8_t index;
  41     uint8_t data;
  42 } SuperIOConfig;
  43
  44 typedef struct VT82C686BState {
  45     PCIDevice dev;
  46     MemoryRegion superio;
  47     SuperIOConfig superio_conf;
  48 } VT82C686BState;
  49
  50 #define TYPE_VT82C686B_DEVICE "VT82C686B"
  51 #define VT82C686B_DEVICE(obj) \
  52     OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE)
  53
  54 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
  55                                   unsigned size)
  56 {
  57     SuperIOConfig *superio_conf = opaque;
  58
  59     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x\n", addr, data);
  60     if (addr == 0x3f0) {
  61         superio_conf->index = data & 0xff;
  62     } else {
  63         bool can_write = true;
  64         /* 0x3f1 */
  65         switch (superio_conf->index) {
  66         case 0x00 ... 0xdf:
  67         case 0xe4:
  68         case 0xe5:
  69         case 0xe9 ... 0xed:
  70         case 0xf3:
  71         case 0xf5:
  72         case 0xf7:
  73         case 0xf9 ... 0xfb:
  74         case 0xfd ... 0xff:
  75             can_write = false;
  76             break;
  77         case 0xe7:
  78             if ((data & 0xff) != 0xfe) {
  79                 DPRINTF("change uart 1 base. unsupported yet\n");
  80                 can_write = false;
  81             }
  82             break;
  83         case 0xe8:
  84             if ((data & 0xff) != 0xbe) {
  85                 DPRINTF("change uart 2 base. unsupported yet\n");
  86                 can_write = false;
  87             }
  88             break;
  89         default:
  90             break;
  91
  92         }
  93         if (can_write) {
  94             superio_conf->config[superio_conf->index] = data & 0xff;
  95         }
  96     }
  97 }
  98
  99 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
 100 {
 101     SuperIOConfig *superio_conf = opaque;
 102
 103     DPRINTF("superio_ioport_readb  address 0x%x\n", addr);
 104     return superio_conf->config[superio_conf->index];
 105 }
 106
 107 static const MemoryRegionOps superio_ops = {
 108     .read = superio_ioport_readb,
 109     .write = superio_ioport_writeb,
 110     .endianness = DEVICE_NATIVE_ENDIAN,
 111     .impl = {
 112         .min_access_size = 1,
 113         .max_access_size = 1,
 114     },
 115 };
 116
 117 static void vt82c686b_isa_reset(DeviceState *dev)
 118 {
 119     VT82C686BState *vt82c = VT82C686B_DEVICE(dev);
 120     uint8_t *pci_conf = vt82c->dev.config;
 121
 122     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 123     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 124                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 125     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 126
 127     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 128     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 129     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 130     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 131     pci_conf[0x59] = 0x04;
 132     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 133     pci_conf[0x5f] = 0x04;
 134     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 135
 136     vt82c->superio_conf.config[0xe0] = 0x3c;
 137     vt82c->superio_conf.config[0xe2] = 0x03;
 138     vt82c->superio_conf.config[0xe3] = 0xfc;
 139     vt82c->superio_conf.config[0xe6] = 0xde;
 140     vt82c->superio_conf.config[0xe7] = 0xfe;
 141     vt82c->superio_conf.config[0xe8] = 0xbe;
 142 }
 143
 144 /* write config pci function0 registers. PCI-ISA bridge */
 145 static void vt82c686b_write_config(PCIDevice *d, uint32_t address,
 146                                    uint32_t val, int len)
 147 {
 148     VT82C686BState *vt686 = VT82C686B_DEVICE(d);
 149
 150     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x\n",
 151            address, val, len);
 152
 153     pci_default_write_config(d, address, val, len);
 154     if (address == 0x85) {  /* enable or disable super IO configure */
 155         memory_region_set_enabled(&vt686->superio, val & 0x2);
 156     }
 157 }
 158
 159 #define ACPI_DBG_IO_ADDR  0xb044
 160
 161 typedef struct VT686PMState {
 162     PCIDevice dev;
 163     MemoryRegion io;
 164     ACPIREGS ar;
 165     APMState apm;
 166     PMSMBus smb;
 167     uint32_t smb_io_base;
 168 } VT686PMState;
 169
 170 typedef struct VT686AC97State {
 171     PCIDevice dev;
 172 } VT686AC97State;
 173
 174 typedef struct VT686MC97State {
 175     PCIDevice dev;
 176 } VT686MC97State;
 177
 178 #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM"
 179 #define VT82C686B_PM_DEVICE(obj) \
 180     OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE)
 181
 182 #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97"
 183 #define VT82C686B_MC97_DEVICE(obj) \
 184     OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE)
 185
 186 #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97"
 187 #define VT82C686B_AC97_DEVICE(obj) \
 188     OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE)
 189
 190 static void pm_update_sci(VT686PMState *s)
 191 {
 192     int sci_level, pmsts;
 193
 194     pmsts = acpi_pm1_evt_get_sts(&s->ar);
 195     sci_level = (((pmsts & s->ar.pm1.evt.en) &
 196                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 197                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 198                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 199                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 200     pci_set_irq(&s->dev, sci_level);
 201     /* schedule a timer interruption if needed */
 202     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 203                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 204 }
 205
 206 static void pm_tmr_timer(ACPIREGS *ar)
 207 {
 208     VT686PMState *s = container_of(ar, VT686PMState, ar);
 209     pm_update_sci(s);
 210 }
 211
 212 static void pm_io_space_update(VT686PMState *s)
 213 {
 214     uint32_t pm_io_base;
 215
 216     pm_io_base = pci_get_long(s->dev.config + 0x40);
 217     pm_io_base &= 0xffc0;
 218
 219     memory_region_transaction_begin();
 220     memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
 221     memory_region_set_address(&s->io, pm_io_base);
 222     memory_region_transaction_commit();
 223 }
 224
 225 static void pm_write_config(PCIDevice *d,
 226                             uint32_t address, uint32_t val, int len)
 227 {
 228     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x\n",
 229            address, val, len);
 230     pci_default_write_config(d, address, val, len);
 231 }
 232
 233 static int vmstate_acpi_post_load(void *opaque, int version_id)
 234 {
 235     VT686PMState *s = opaque;
 236
 237     pm_io_space_update(s);
 238     return 0;
 239 }
 240
 241 static const VMStateDescription vmstate_acpi = {
 242     .name = "vt82c686b_pm",
 243     .version_id = 1,
 244     .minimum_version_id = 1,
 245     .post_load = vmstate_acpi_post_load,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 248         VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
 249         VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
 250         VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
 251         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 252         VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
 253         VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
 254         VMSTATE_END_OF_LIST()
 255     }
 256 };
 257
 258 /*
 259  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 260  * just register a PCI device now, functionalities will be implemented later.
 261  */
 262
 263 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
 264 {
 265     VT686AC97State *s = VT82C686B_AC97_DEVICE(dev);
 266     uint8_t *pci_conf = s->dev.config;
 267
 268     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 269                  PCI_COMMAND_PARITY);
 270     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 271                  PCI_STATUS_DEVSEL_MEDIUM);
 272     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 273 }
 274
 275 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 276 {
 277     PCIDevice *dev;
 278
 279     dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE);
 280     qdev_init_nofail(&dev->qdev);
 281 }
 282
 283 static void via_ac97_class_init(ObjectClass *klass, void *data)
 284 {
 285     DeviceClass *dc = DEVICE_CLASS(klass);
 286     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 287
 288     k->realize = vt82c686b_ac97_realize;
 289     k->vendor_id = PCI_VENDOR_ID_VIA;
 290     k->device_id = PCI_DEVICE_ID_VIA_AC97;
 291     k->revision = 0x50;
 292     k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
 293     set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
 294     dc->desc = "AC97";
 295 }
 296
 297 static const TypeInfo via_ac97_info = {
 298     .name          = TYPE_VT82C686B_AC97_DEVICE,
 299     .parent        = TYPE_PCI_DEVICE,
 300     .instance_size = sizeof(VT686AC97State),
 301     .class_init    = via_ac97_class_init,
 302     .interfaces = (InterfaceInfo[]) {
 303         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 304         { },
 305     },
 306 };
 307
 308 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
 309 {
 310     VT686MC97State *s = VT82C686B_MC97_DEVICE(dev);
 311     uint8_t *pci_conf = s->dev.config;
 312
 313     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 314                  PCI_COMMAND_VGA_PALETTE);
 315     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 316     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 317 }
 318
 319 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 320 {
 321     PCIDevice *dev;
 322
 323     dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE);
 324     qdev_init_nofail(&dev->qdev);
 325 }
 326
 327 static void via_mc97_class_init(ObjectClass *klass, void *data)
 328 {
 329     DeviceClass *dc = DEVICE_CLASS(klass);
 330     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 331
 332     k->realize = vt82c686b_mc97_realize;
 333     k->vendor_id = PCI_VENDOR_ID_VIA;
 334     k->device_id = PCI_DEVICE_ID_VIA_MC97;
 335     k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
 336     k->revision = 0x30;
 337     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 338     dc->desc = "MC97";
 339 }
 340
 341 static const TypeInfo via_mc97_info = {
 342     .name          = TYPE_VT82C686B_MC97_DEVICE,
 343     .parent        = TYPE_PCI_DEVICE,
 344     .instance_size = sizeof(VT686MC97State),
 345     .class_init    = via_mc97_class_init,
 346     .interfaces = (InterfaceInfo[]) {
 347         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 348         { },
 349     },
 350 };
 351
 352 /* vt82c686 pm init */
 353 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
 354 {
 355     VT686PMState *s = VT82C686B_PM_DEVICE(dev);
 356     uint8_t *pci_conf;
 357
 358     pci_conf = s->dev.config;
 359     pci_set_word(pci_conf + PCI_COMMAND, 0);
 360     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 361                  PCI_STATUS_DEVSEL_MEDIUM);
 362
 363     /* 0x48-0x4B is Power Management I/O Base */
 364     pci_set_long(pci_conf + 0x48, 0x00000001);
 365
 366     /* SMB ports:0xeee0~0xeeef */
 367     s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
 368     pci_conf[0x90] = s->smb_io_base | 1;
 369     pci_conf[0x91] = s->smb_io_base >> 8;
 370     pci_conf[0xd2] = 0x90;
 371     pm_smbus_init(DEVICE(s), &s->smb, false);
 372     memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
 373
 374     apm_init(dev, &s->apm, NULL, s);
 375
 376     memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
 377     memory_region_set_enabled(&s->io, false);
 378     memory_region_add_subregion(get_system_io(), 0, &s->io);
 379
 380     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 381     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 382     acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
 383 }
 384
 385 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 386                           qemu_irq sci_irq)
 387 {
 388     PCIDevice *dev;
 389     VT686PMState *s;
 390
 391     dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE);
 392     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 393
 394     s = VT82C686B_PM_DEVICE(dev);
 395
 396     qdev_init_nofail(&dev->qdev);
 397
 398     return s->smb.smbus;
 399 }
 400
 401 static Property via_pm_properties[] = {
 402     DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 403     DEFINE_PROP_END_OF_LIST(),
 404 };
 405
 406 static void via_pm_class_init(ObjectClass *klass, void *data)
 407 {
 408     DeviceClass *dc = DEVICE_CLASS(klass);
 409     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 410
 411     k->realize = vt82c686b_pm_realize;
 412     k->config_write = pm_write_config;
 413     k->vendor_id = PCI_VENDOR_ID_VIA;
 414     k->device_id = PCI_DEVICE_ID_VIA_ACPI;
 415     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 416     k->revision = 0x40;
 417     dc->desc = "PM";
 418     dc->vmsd = &vmstate_acpi;
 419     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 420     dc->props = via_pm_properties;
 421 }
 422
 423 static const TypeInfo via_pm_info = {
 424     .name          = TYPE_VT82C686B_PM_DEVICE,
 425     .parent        = TYPE_PCI_DEVICE,
 426     .instance_size = sizeof(VT686PMState),
 427     .class_init    = via_pm_class_init,
 428     .interfaces = (InterfaceInfo[]) {
 429         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 430         { },
 431     },
 432 };
 433
 434 static const VMStateDescription vmstate_via = {
 435     .name = "vt82c686b",
 436     .version_id = 1,
 437     .minimum_version_id = 1,
 438     .fields = (VMStateField[]) {
 439         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 440         VMSTATE_END_OF_LIST()
 441     }
 442 };
 443
 444 /* init the PCI-to-ISA bridge */
 445 static void vt82c686b_realize(PCIDevice *d, Error **errp)
 446 {
 447     VT82C686BState *vt82c = VT82C686B_DEVICE(d);
 448     uint8_t *pci_conf;
 449     ISABus *isa_bus;
 450     uint8_t *wmask;
 451     int i;
 452
 453     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
 454                           pci_address_space_io(d), errp);
 455     if (!isa_bus) {
 456         return;
 457     }
 458
 459     pci_conf = d->config;
 460     pci_config_set_prog_interface(pci_conf, 0x0);
 461
 462     wmask = d->wmask;
 463     for (i = 0x00; i < 0xff; i++) {
 464         if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
 465             wmask[i] = 0x00;
 466         }
 467     }
 468
 469     memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
 470                           &vt82c->superio_conf, "superio", 2);
 471     memory_region_set_enabled(&vt82c->superio, false);
 472     /*
 473      * The floppy also uses 0x3f0 and 0x3f1.
 474      * But we do not emulate a floppy, so just set it here.
 475      */
 476     memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
 477                                 &vt82c->superio);
 478 }
 479
 480 ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn)
 481 {
 482     PCIDevice *d;
 483
 484     d = pci_create_simple_multifunction(bus, devfn, true,
 485                                         TYPE_VT82C686B_DEVICE);
 486
 487     return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
 488 }
 489
 490 static void via_class_init(ObjectClass *klass, void *data)
 491 {
 492     DeviceClass *dc = DEVICE_CLASS(klass);
 493     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 494
 495     k->realize = vt82c686b_realize;
 496     k->config_write = vt82c686b_write_config;
 497     k->vendor_id = PCI_VENDOR_ID_VIA;
 498     k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
 499     k->class_id = PCI_CLASS_BRIDGE_ISA;
 500     k->revision = 0x40;
 501     dc->reset = vt82c686b_isa_reset;
 502     dc->desc = "ISA bridge";
 503     dc->vmsd = &vmstate_via;
 504     /*
 505      * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
 506      * e.g. by mips_fulong2e_init()
 507      */
 508     dc->user_creatable = false;
 509 }
 510
 511 static const TypeInfo via_info = {
 512     .name          = TYPE_VT82C686B_DEVICE,
 513     .parent        = TYPE_PCI_DEVICE,
 514     .instance_size = sizeof(VT82C686BState),
 515     .class_init    = via_class_init,
 516     .interfaces = (InterfaceInfo[]) {
 517         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 518         { },
 519     },
 520 };
 521
 522 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
 523 {
 524     ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
 525
 526     sc->serial.count = 2;
 527     sc->parallel.count = 1;
 528     sc->ide.count = 0;
 529     sc->floppy.count = 1;
 530 }
 531
 532 static const TypeInfo via_superio_info = {
 533     .name          = TYPE_VT82C686B_SUPERIO,
 534     .parent        = TYPE_ISA_SUPERIO,
 535     .instance_size = sizeof(ISASuperIODevice),
 536     .class_size    = sizeof(ISASuperIOClass),
 537     .class_init    = vt82c686b_superio_class_init,
 538 };
 539
 540 static void vt82c686b_register_types(void)
 541 {
 542     type_register_static(&via_ac97_info);
 543     type_register_static(&via_mc97_info);
 544     type_register_static(&via_pm_info);
 545     type_register_static(&via_superio_info);
 546     type_register_static(&via_info);
 547 }
 548
 549 type_init(vt82c686b_register_types)