4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
25 #include "sysemu/sysemu.h"
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
30 [ASPEED_IOMEM
] = 0x1E600000,
31 [ASPEED_FMC
] = 0x1E620000,
32 [ASPEED_SPI1
] = 0x1E630000,
33 [ASPEED_VIC
] = 0x1E6C0000,
34 [ASPEED_SDMC
] = 0x1E6E0000,
35 [ASPEED_SCU
] = 0x1E6E2000,
36 [ASPEED_XDMA
] = 0x1E6E7000,
37 [ASPEED_VIDEO
] = 0x1E700000,
38 [ASPEED_ADC
] = 0x1E6E9000,
39 [ASPEED_SRAM
] = 0x1E720000,
40 [ASPEED_SDHCI
] = 0x1E740000,
41 [ASPEED_GPIO
] = 0x1E780000,
42 [ASPEED_RTC
] = 0x1E781000,
43 [ASPEED_TIMER1
] = 0x1E782000,
44 [ASPEED_WDT
] = 0x1E785000,
45 [ASPEED_PWM
] = 0x1E786000,
46 [ASPEED_LPC
] = 0x1E789000,
47 [ASPEED_IBT
] = 0x1E789140,
48 [ASPEED_I2C
] = 0x1E78A000,
49 [ASPEED_ETH1
] = 0x1E660000,
50 [ASPEED_ETH2
] = 0x1E680000,
51 [ASPEED_UART1
] = 0x1E783000,
52 [ASPEED_UART5
] = 0x1E784000,
53 [ASPEED_VUART
] = 0x1E787000,
54 [ASPEED_SDRAM
] = 0x40000000,
57 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
58 [ASPEED_IOMEM
] = 0x1E600000,
59 [ASPEED_FMC
] = 0x1E620000,
60 [ASPEED_SPI1
] = 0x1E630000,
61 [ASPEED_SPI2
] = 0x1E631000,
62 [ASPEED_VIC
] = 0x1E6C0000,
63 [ASPEED_SDMC
] = 0x1E6E0000,
64 [ASPEED_SCU
] = 0x1E6E2000,
65 [ASPEED_XDMA
] = 0x1E6E7000,
66 [ASPEED_ADC
] = 0x1E6E9000,
67 [ASPEED_VIDEO
] = 0x1E700000,
68 [ASPEED_SRAM
] = 0x1E720000,
69 [ASPEED_SDHCI
] = 0x1E740000,
70 [ASPEED_GPIO
] = 0x1E780000,
71 [ASPEED_RTC
] = 0x1E781000,
72 [ASPEED_TIMER1
] = 0x1E782000,
73 [ASPEED_WDT
] = 0x1E785000,
74 [ASPEED_PWM
] = 0x1E786000,
75 [ASPEED_LPC
] = 0x1E789000,
76 [ASPEED_IBT
] = 0x1E789140,
77 [ASPEED_I2C
] = 0x1E78A000,
78 [ASPEED_ETH1
] = 0x1E660000,
79 [ASPEED_ETH2
] = 0x1E680000,
80 [ASPEED_UART1
] = 0x1E783000,
81 [ASPEED_UART5
] = 0x1E784000,
82 [ASPEED_VUART
] = 0x1E787000,
83 [ASPEED_SDRAM
] = 0x80000000,
86 static const int aspeed_soc_ast2400_irqmap
[] = {
100 [ASPEED_TIMER2
] = 17,
101 [ASPEED_TIMER3
] = 18,
102 [ASPEED_TIMER4
] = 35,
103 [ASPEED_TIMER5
] = 36,
104 [ASPEED_TIMER6
] = 37,
105 [ASPEED_TIMER7
] = 38,
106 [ASPEED_TIMER8
] = 39,
110 [ASPEED_IBT
] = 8, /* LPC */
118 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
120 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
122 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
124 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->irqmap
[ctrl
]);
127 static void aspeed_soc_init(Object
*obj
)
129 AspeedSoCState
*s
= ASPEED_SOC(obj
);
130 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
135 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
136 g_assert_not_reached();
139 for (i
= 0; i
< sc
->num_cpus
; i
++) {
140 object_initialize_child(obj
, "cpu[*]", OBJECT(&s
->cpu
[i
]),
141 sizeof(s
->cpu
[i
]), sc
->cpu_type
,
145 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
146 sysbus_init_child_obj(obj
, "scu", OBJECT(&s
->scu
), sizeof(s
->scu
),
148 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
150 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
151 "hw-strap1", &error_abort
);
152 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
153 "hw-strap2", &error_abort
);
154 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
155 "hw-prot-key", &error_abort
);
157 sysbus_init_child_obj(obj
, "vic", OBJECT(&s
->vic
), sizeof(s
->vic
),
160 sysbus_init_child_obj(obj
, "rtc", OBJECT(&s
->rtc
), sizeof(s
->rtc
),
163 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
164 sysbus_init_child_obj(obj
, "timerctrl", OBJECT(&s
->timerctrl
),
165 sizeof(s
->timerctrl
), typename
);
166 object_property_add_const_link(OBJECT(&s
->timerctrl
), "scu",
167 OBJECT(&s
->scu
), &error_abort
);
169 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
170 sysbus_init_child_obj(obj
, "i2c", OBJECT(&s
->i2c
), sizeof(s
->i2c
),
173 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
174 sysbus_init_child_obj(obj
, "fmc", OBJECT(&s
->fmc
), sizeof(s
->fmc
),
176 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs",
178 object_property_add_alias(obj
, "dram", OBJECT(&s
->fmc
), "dram",
181 for (i
= 0; i
< sc
->spis_num
; i
++) {
182 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
183 sysbus_init_child_obj(obj
, "spi[*]", OBJECT(&s
->spi
[i
]),
184 sizeof(s
->spi
[i
]), typename
);
187 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
188 sysbus_init_child_obj(obj
, "sdmc", OBJECT(&s
->sdmc
), sizeof(s
->sdmc
),
190 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
191 "ram-size", &error_abort
);
192 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
193 "max-ram-size", &error_abort
);
195 for (i
= 0; i
< sc
->wdts_num
; i
++) {
196 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
197 sysbus_init_child_obj(obj
, "wdt[*]", OBJECT(&s
->wdt
[i
]),
198 sizeof(s
->wdt
[i
]), typename
);
199 object_property_add_const_link(OBJECT(&s
->wdt
[i
]), "scu",
200 OBJECT(&s
->scu
), &error_abort
);
203 for (i
= 0; i
< sc
->macs_num
; i
++) {
204 sysbus_init_child_obj(obj
, "ftgmac100[*]", OBJECT(&s
->ftgmac100
[i
]),
205 sizeof(s
->ftgmac100
[i
]), TYPE_FTGMAC100
);
208 sysbus_init_child_obj(obj
, "xdma", OBJECT(&s
->xdma
), sizeof(s
->xdma
),
211 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
212 sysbus_init_child_obj(obj
, "gpio", OBJECT(&s
->gpio
), sizeof(s
->gpio
),
215 sysbus_init_child_obj(obj
, "sdc", OBJECT(&s
->sdhci
), sizeof(s
->sdhci
),
218 /* Init sd card slot class here so that they're under the correct parent */
219 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
220 sysbus_init_child_obj(obj
, "sdhci[*]", OBJECT(&s
->sdhci
.slots
[i
]),
221 sizeof(s
->sdhci
.slots
[i
]), TYPE_SYSBUS_SDHCI
);
225 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
228 AspeedSoCState
*s
= ASPEED_SOC(dev
);
229 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
230 Error
*err
= NULL
, *local_err
= NULL
;
233 create_unimplemented_device("aspeed_soc.io", sc
->memmap
[ASPEED_IOMEM
],
234 ASPEED_SOC_IOMEM_SIZE
);
236 /* Video engine stub */
237 create_unimplemented_device("aspeed.video", sc
->memmap
[ASPEED_VIDEO
],
240 if (s
->num_cpus
> sc
->num_cpus
) {
241 warn_report("%s: invalid number of CPUs %d, using default %d",
242 sc
->name
, s
->num_cpus
, sc
->num_cpus
);
243 s
->num_cpus
= sc
->num_cpus
;
247 for (i
= 0; i
< s
->num_cpus
; i
++) {
248 object_property_set_bool(OBJECT(&s
->cpu
[i
]), true, "realized", &err
);
250 error_propagate(errp
, err
);
256 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
257 sc
->sram_size
, &err
);
259 error_propagate(errp
, err
);
262 memory_region_add_subregion(get_system_memory(),
263 sc
->memmap
[ASPEED_SRAM
], &s
->sram
);
266 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
268 error_propagate(errp
, err
);
271 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_SCU
]);
274 object_property_set_bool(OBJECT(&s
->vic
), true, "realized", &err
);
276 error_propagate(errp
, err
);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->memmap
[ASPEED_VIC
]);
280 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
281 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
282 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
283 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
286 object_property_set_bool(OBJECT(&s
->rtc
), true, "realized", &err
);
288 error_propagate(errp
, err
);
291 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_RTC
]);
292 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
293 aspeed_soc_get_irq(s
, ASPEED_RTC
));
296 object_property_set_bool(OBJECT(&s
->timerctrl
), true, "realized", &err
);
298 error_propagate(errp
, err
);
301 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
302 sc
->memmap
[ASPEED_TIMER1
]);
303 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
304 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_TIMER1
+ i
);
305 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
308 /* UART - attach an 8250 to the IO space as our UART5 */
310 qemu_irq uart5
= aspeed_soc_get_irq(s
, ASPEED_UART5
);
311 serial_mm_init(get_system_memory(), sc
->memmap
[ASPEED_UART5
], 2,
312 uart5
, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN
);
316 object_property_set_bool(OBJECT(&s
->i2c
), true, "realized", &err
);
318 error_propagate(errp
, err
);
321 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_I2C
]);
322 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
323 aspeed_soc_get_irq(s
, ASPEED_I2C
));
325 /* FMC, The number of CS is set at the board level */
326 object_property_set_int(OBJECT(&s
->fmc
), sc
->memmap
[ASPEED_SDRAM
],
329 error_propagate(errp
, err
);
332 object_property_set_bool(OBJECT(&s
->fmc
), true, "realized", &err
);
334 error_propagate(errp
, err
);
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_FMC
]);
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
339 s
->fmc
.ctrl
->flash_window_base
);
340 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
341 aspeed_soc_get_irq(s
, ASPEED_FMC
));
344 for (i
= 0; i
< sc
->spis_num
; i
++) {
345 object_property_set_int(OBJECT(&s
->spi
[i
]), 1, "num-cs", &err
);
346 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
348 error_propagate(&err
, local_err
);
350 error_propagate(errp
, err
);
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
354 sc
->memmap
[ASPEED_SPI1
+ i
]);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
356 s
->spi
[i
].ctrl
->flash_window_base
);
359 /* SDMC - SDRAM Memory Controller */
360 object_property_set_bool(OBJECT(&s
->sdmc
), true, "realized", &err
);
362 error_propagate(errp
, err
);
365 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->memmap
[ASPEED_SDMC
]);
368 for (i
= 0; i
< sc
->wdts_num
; i
++) {
369 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
371 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized", &err
);
373 error_propagate(errp
, err
);
376 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
377 sc
->memmap
[ASPEED_WDT
] + i
* awc
->offset
);
381 for (i
= 0; i
< nb_nics
&& i
< sc
->macs_num
; i
++) {
382 qdev_set_nic_properties(DEVICE(&s
->ftgmac100
[i
]), &nd_table
[i
]);
383 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "aspeed",
385 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "realized",
387 error_propagate(&err
, local_err
);
389 error_propagate(errp
, err
);
392 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
393 sc
->memmap
[ASPEED_ETH1
+ i
]);
394 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
395 aspeed_soc_get_irq(s
, ASPEED_ETH1
+ i
));
399 object_property_set_bool(OBJECT(&s
->xdma
), true, "realized", &err
);
401 error_propagate(errp
, err
);
404 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
405 sc
->memmap
[ASPEED_XDMA
]);
406 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
407 aspeed_soc_get_irq(s
, ASPEED_XDMA
));
410 object_property_set_bool(OBJECT(&s
->gpio
), true, "realized", &err
);
412 error_propagate(errp
, err
);
415 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->memmap
[ASPEED_GPIO
]);
416 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
417 aspeed_soc_get_irq(s
, ASPEED_GPIO
));
420 object_property_set_bool(OBJECT(&s
->sdhci
), true, "realized", &err
);
422 error_propagate(errp
, err
);
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
426 sc
->memmap
[ASPEED_SDHCI
]);
427 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
428 aspeed_soc_get_irq(s
, ASPEED_SDHCI
));
430 static Property aspeed_soc_properties
[] = {
431 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState
, num_cpus
, 0),
432 DEFINE_PROP_END_OF_LIST(),
435 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
437 DeviceClass
*dc
= DEVICE_CLASS(oc
);
439 dc
->realize
= aspeed_soc_realize
;
440 /* Reason: Uses serial_hds and nd_table in realize() directly */
441 dc
->user_creatable
= false;
442 dc
->props
= aspeed_soc_properties
;
445 static const TypeInfo aspeed_soc_type_info
= {
446 .name
= TYPE_ASPEED_SOC
,
447 .parent
= TYPE_DEVICE
,
448 .instance_size
= sizeof(AspeedSoCState
),
449 .class_size
= sizeof(AspeedSoCClass
),
450 .class_init
= aspeed_soc_class_init
,
454 static void aspeed_soc_ast2400_class_init(ObjectClass
*oc
, void *data
)
456 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
458 sc
->name
= "ast2400-a1";
459 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm926");
460 sc
->silicon_rev
= AST2400_A1_SILICON_REV
;
461 sc
->sram_size
= 0x8000;
465 sc
->irqmap
= aspeed_soc_ast2400_irqmap
;
466 sc
->memmap
= aspeed_soc_ast2400_memmap
;
470 static const TypeInfo aspeed_soc_ast2400_type_info
= {
471 .name
= "ast2400-a1",
472 .parent
= TYPE_ASPEED_SOC
,
473 .instance_init
= aspeed_soc_init
,
474 .instance_size
= sizeof(AspeedSoCState
),
475 .class_init
= aspeed_soc_ast2400_class_init
,
478 static void aspeed_soc_ast2500_class_init(ObjectClass
*oc
, void *data
)
480 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
482 sc
->name
= "ast2500-a1";
483 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm1176");
484 sc
->silicon_rev
= AST2500_A1_SILICON_REV
;
485 sc
->sram_size
= 0x9000;
489 sc
->irqmap
= aspeed_soc_ast2500_irqmap
;
490 sc
->memmap
= aspeed_soc_ast2500_memmap
;
494 static const TypeInfo aspeed_soc_ast2500_type_info
= {
495 .name
= "ast2500-a1",
496 .parent
= TYPE_ASPEED_SOC
,
497 .instance_init
= aspeed_soc_init
,
498 .instance_size
= sizeof(AspeedSoCState
),
499 .class_init
= aspeed_soc_ast2500_class_init
,
501 static void aspeed_soc_register_types(void)
503 type_register_static(&aspeed_soc_type_info
);
504 type_register_static(&aspeed_soc_ast2400_type_info
);
505 type_register_static(&aspeed_soc_ast2500_type_info
);
508 type_init(aspeed_soc_register_types
)