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target-m68k: introduce read_imXX() functions
[qemu/ar7.git] / target-m68k / translate.c
bloba8ff5de2527ce121ad1d8615611f79dfe93b25d7
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 //#define DEBUG_DISPATCH 1
37
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
42
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
46 #include "qregs.def"
47 #undef DEFO32
48 #undef DEFO64
49 #undef DEFF64
50
51 static TCGv_i32 cpu_halted;
52 static TCGv_i32 cpu_exception_index;
53
54 static TCGv_env cpu_env;
55
56 static char cpu_reg_names[3*8*3 + 5*4];
57 static TCGv cpu_dregs[8];
58 static TCGv cpu_aregs[8];
59 static TCGv_i64 cpu_fregs[8];
60 static TCGv_i64 cpu_macc[4];
61
62 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
63 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
64 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
65 #define MACREG(acc) cpu_macc[acc]
66 #define QREG_SP cpu_aregs[7]
67
68 static TCGv NULL_QREG;
69 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
70 /* Used to distinguish stores from bad addressing modes. */
71 static TCGv store_dummy;
72
73 #include "exec/gen-icount.h"
74
75 void m68k_tcg_init(void)
76 {
77 char *p;
78 int i;
79
80 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
81 tcg_ctx.tcg_env = cpu_env;
82
83 #define DEFO32(name, offset) \
84 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
85 offsetof(CPUM68KState, offset), #name);
86 #define DEFO64(name, offset) \
87 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
88 offsetof(CPUM68KState, offset), #name);
89 #define DEFF64(name, offset) DEFO64(name, offset)
90 #include "qregs.def"
91 #undef DEFO32
92 #undef DEFO64
93 #undef DEFF64
94
95 cpu_halted = tcg_global_mem_new_i32(cpu_env,
96 -offsetof(M68kCPU, env) +
97 offsetof(CPUState, halted), "HALTED");
98 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
99 -offsetof(M68kCPU, env) +
100 offsetof(CPUState, exception_index),
101 "EXCEPTION");
102
103 p = cpu_reg_names;
104 for (i = 0; i < 8; i++) {
105 sprintf(p, "D%d", i);
106 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUM68KState, dregs[i]), p);
108 p += 3;
109 sprintf(p, "A%d", i);
110 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUM68KState, aregs[i]), p);
112 p += 3;
113 sprintf(p, "F%d", i);
114 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
115 offsetof(CPUM68KState, fregs[i]), p);
116 p += 3;
117 }
118 for (i = 0; i < 4; i++) {
119 sprintf(p, "ACC%d", i);
120 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
121 offsetof(CPUM68KState, macc[i]), p);
122 p += 5;
123 }
124
125 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
126 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
127 }
128
129 /* internal defines */
130 typedef struct DisasContext {
131 CPUM68KState *env;
132 target_ulong insn_pc; /* Start of the current instruction. */
133 target_ulong pc;
134 int is_jmp;
135 int cc_op;
136 int user;
137 uint32_t fpcr;
138 struct TranslationBlock *tb;
139 int singlestep_enabled;
140 TCGv_i64 mactmp;
141 int done_mac;
142 } DisasContext;
143
144 #define DISAS_JUMP_NEXT 4
145
146 #if defined(CONFIG_USER_ONLY)
147 #define IS_USER(s) 1
148 #else
149 #define IS_USER(s) s->user
150 #endif
151
152 /* XXX: move that elsewhere */
153 /* ??? Fix exceptions. */
154 static void *gen_throws_exception;
155 #define gen_last_qop NULL
156
157 #define OS_BYTE 0
158 #define OS_WORD 1
159 #define OS_LONG 2
160 #define OS_SINGLE 4
161 #define OS_DOUBLE 5
162
163 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
164
165 #ifdef DEBUG_DISPATCH
166 #define DISAS_INSN(name) \
167 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
168 uint16_t insn); \
169 static void disas_##name(CPUM68KState *env, DisasContext *s, \
170 uint16_t insn) \
171 { \
172 qemu_log("Dispatch " #name "\n"); \
173 real_disas_##name(env, s, insn); \
174 } \
175 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
176 uint16_t insn)
177 #else
178 #define DISAS_INSN(name) \
179 static void disas_##name(CPUM68KState *env, DisasContext *s, \
180 uint16_t insn)
181 #endif
182
183 /* Generate a load from the specified address. Narrow values are
184 sign extended to full register width. */
185 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
186 {
187 TCGv tmp;
188 int index = IS_USER(s);
189 tmp = tcg_temp_new_i32();
190 switch(opsize) {
191 case OS_BYTE:
192 if (sign)
193 tcg_gen_qemu_ld8s(tmp, addr, index);
194 else
195 tcg_gen_qemu_ld8u(tmp, addr, index);
196 break;
197 case OS_WORD:
198 if (sign)
199 tcg_gen_qemu_ld16s(tmp, addr, index);
200 else
201 tcg_gen_qemu_ld16u(tmp, addr, index);
202 break;
203 case OS_LONG:
204 case OS_SINGLE:
205 tcg_gen_qemu_ld32u(tmp, addr, index);
206 break;
207 default:
208 g_assert_not_reached();
209 }
210 gen_throws_exception = gen_last_qop;
211 return tmp;
212 }
213
214 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
215 {
216 TCGv_i64 tmp;
217 int index = IS_USER(s);
218 tmp = tcg_temp_new_i64();
219 tcg_gen_qemu_ldf64(tmp, addr, index);
220 gen_throws_exception = gen_last_qop;
221 return tmp;
222 }
223
224 /* Generate a store. */
225 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
226 {
227 int index = IS_USER(s);
228 switch(opsize) {
229 case OS_BYTE:
230 tcg_gen_qemu_st8(val, addr, index);
231 break;
232 case OS_WORD:
233 tcg_gen_qemu_st16(val, addr, index);
234 break;
235 case OS_LONG:
236 case OS_SINGLE:
237 tcg_gen_qemu_st32(val, addr, index);
238 break;
239 default:
240 g_assert_not_reached();
241 }
242 gen_throws_exception = gen_last_qop;
243 }
244
245 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
246 {
247 int index = IS_USER(s);
248 tcg_gen_qemu_stf64(val, addr, index);
249 gen_throws_exception = gen_last_qop;
250 }
251
252 typedef enum {
253 EA_STORE,
254 EA_LOADU,
255 EA_LOADS
256 } ea_what;
257
258 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
259 otherwise generate a store. */
260 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
261 ea_what what)
262 {
263 if (what == EA_STORE) {
264 gen_store(s, opsize, addr, val);
265 return store_dummy;
266 } else {
267 return gen_load(s, opsize, addr, what == EA_LOADS);
268 }
269 }
270
271 /* Read a 16-bit immediate constant */
272 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
273 {
274 uint16_t im;
275 im = cpu_lduw_code(env, s->pc);
276 s->pc += 2;
277 return im;
278 }
279
280 /* Read an 8-bit immediate constant */
281 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
282 {
283 return read_im16(env, s);
284 }
285
286 /* Read a 32-bit immediate constant. */
287 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
288 {
289 uint32_t im;
290 im = read_im16(env, s) << 16;
291 im |= 0xffff & read_im16(env, s);
292 return im;
293 }
294
295 /* Calculate and address index. */
296 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
297 {
298 TCGv add;
299 int scale;
300
301 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
302 if ((ext & 0x800) == 0) {
303 tcg_gen_ext16s_i32(tmp, add);
304 add = tmp;
305 }
306 scale = (ext >> 9) & 3;
307 if (scale != 0) {
308 tcg_gen_shli_i32(tmp, add, scale);
309 add = tmp;
310 }
311 return add;
312 }
313
314 /* Handle a base + index + displacement effective addresss.
315 A NULL_QREG base means pc-relative. */
316 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
317 {
318 uint32_t offset;
319 uint16_t ext;
320 TCGv add;
321 TCGv tmp;
322 uint32_t bd, od;
323
324 offset = s->pc;
325 ext = read_im16(env, s);
326
327 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
328 return NULL_QREG;
329
330 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
331 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
332 ext &= ~(3 << 9);
333 }
334
335 if (ext & 0x100) {
336 /* full extension word format */
337 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
338 return NULL_QREG;
339
340 if ((ext & 0x30) > 0x10) {
341 /* base displacement */
342 if ((ext & 0x30) == 0x20) {
343 bd = (int16_t)read_im16(env, s);
344 } else {
345 bd = read_im32(env, s);
346 }
347 } else {
348 bd = 0;
349 }
350 tmp = tcg_temp_new();
351 if ((ext & 0x44) == 0) {
352 /* pre-index */
353 add = gen_addr_index(ext, tmp);
354 } else {
355 add = NULL_QREG;
356 }
357 if ((ext & 0x80) == 0) {
358 /* base not suppressed */
359 if (IS_NULL_QREG(base)) {
360 base = tcg_const_i32(offset + bd);
361 bd = 0;
362 }
363 if (!IS_NULL_QREG(add)) {
364 tcg_gen_add_i32(tmp, add, base);
365 add = tmp;
366 } else {
367 add = base;
368 }
369 }
370 if (!IS_NULL_QREG(add)) {
371 if (bd != 0) {
372 tcg_gen_addi_i32(tmp, add, bd);
373 add = tmp;
374 }
375 } else {
376 add = tcg_const_i32(bd);
377 }
378 if ((ext & 3) != 0) {
379 /* memory indirect */
380 base = gen_load(s, OS_LONG, add, 0);
381 if ((ext & 0x44) == 4) {
382 add = gen_addr_index(ext, tmp);
383 tcg_gen_add_i32(tmp, add, base);
384 add = tmp;
385 } else {
386 add = base;
387 }
388 if ((ext & 3) > 1) {
389 /* outer displacement */
390 if ((ext & 3) == 2) {
391 od = (int16_t)read_im16(env, s);
392 } else {
393 od = read_im32(env, s);
394 }
395 } else {
396 od = 0;
397 }
398 if (od != 0) {
399 tcg_gen_addi_i32(tmp, add, od);
400 add = tmp;
401 }
402 }
403 } else {
404 /* brief extension word format */
405 tmp = tcg_temp_new();
406 add = gen_addr_index(ext, tmp);
407 if (!IS_NULL_QREG(base)) {
408 tcg_gen_add_i32(tmp, add, base);
409 if ((int8_t)ext)
410 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
411 } else {
412 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
413 }
414 add = tmp;
415 }
416 return add;
417 }
418
419 /* Update the CPU env CC_OP state. */
420 static inline void gen_flush_cc_op(DisasContext *s)
421 {
422 if (s->cc_op != CC_OP_DYNAMIC)
423 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
424 }
425
426 /* Evaluate all the CC flags. */
427 static inline void gen_flush_flags(DisasContext *s)
428 {
429 if (s->cc_op == CC_OP_FLAGS)
430 return;
431 gen_flush_cc_op(s);
432 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
433 s->cc_op = CC_OP_FLAGS;
434 }
435
436 static void gen_logic_cc(DisasContext *s, TCGv val)
437 {
438 tcg_gen_mov_i32(QREG_CC_DEST, val);
439 s->cc_op = CC_OP_LOGIC;
440 }
441
442 static void gen_update_cc_add(TCGv dest, TCGv src)
443 {
444 tcg_gen_mov_i32(QREG_CC_DEST, dest);
445 tcg_gen_mov_i32(QREG_CC_SRC, src);
446 }
447
448 static inline int opsize_bytes(int opsize)
449 {
450 switch (opsize) {
451 case OS_BYTE: return 1;
452 case OS_WORD: return 2;
453 case OS_LONG: return 4;
454 case OS_SINGLE: return 4;
455 case OS_DOUBLE: return 8;
456 default:
457 g_assert_not_reached();
458 }
459 }
460
461 /* Assign value to a register. If the width is less than the register width
462 only the low part of the register is set. */
463 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
464 {
465 TCGv tmp;
466 switch (opsize) {
467 case OS_BYTE:
468 tcg_gen_andi_i32(reg, reg, 0xffffff00);
469 tmp = tcg_temp_new();
470 tcg_gen_ext8u_i32(tmp, val);
471 tcg_gen_or_i32(reg, reg, tmp);
472 break;
473 case OS_WORD:
474 tcg_gen_andi_i32(reg, reg, 0xffff0000);
475 tmp = tcg_temp_new();
476 tcg_gen_ext16u_i32(tmp, val);
477 tcg_gen_or_i32(reg, reg, tmp);
478 break;
479 case OS_LONG:
480 case OS_SINGLE:
481 tcg_gen_mov_i32(reg, val);
482 break;
483 default:
484 g_assert_not_reached();
485 }
486 }
487
488 /* Sign or zero extend a value. */
489 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
490 {
491 TCGv tmp;
492
493 switch (opsize) {
494 case OS_BYTE:
495 tmp = tcg_temp_new();
496 if (sign)
497 tcg_gen_ext8s_i32(tmp, val);
498 else
499 tcg_gen_ext8u_i32(tmp, val);
500 break;
501 case OS_WORD:
502 tmp = tcg_temp_new();
503 if (sign)
504 tcg_gen_ext16s_i32(tmp, val);
505 else
506 tcg_gen_ext16u_i32(tmp, val);
507 break;
508 case OS_LONG:
509 case OS_SINGLE:
510 tmp = val;
511 break;
512 default:
513 g_assert_not_reached();
514 }
515 return tmp;
516 }
517
518 /* Generate code for an "effective address". Does not adjust the base
519 register for autoincrement addressing modes. */
520 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
521 int opsize)
522 {
523 TCGv reg;
524 TCGv tmp;
525 uint16_t ext;
526 uint32_t offset;
527
528 switch ((insn >> 3) & 7) {
529 case 0: /* Data register direct. */
530 case 1: /* Address register direct. */
531 return NULL_QREG;
532 case 2: /* Indirect register */
533 case 3: /* Indirect postincrement. */
534 return AREG(insn, 0);
535 case 4: /* Indirect predecrememnt. */
536 reg = AREG(insn, 0);
537 tmp = tcg_temp_new();
538 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
539 return tmp;
540 case 5: /* Indirect displacement. */
541 reg = AREG(insn, 0);
542 tmp = tcg_temp_new();
543 ext = read_im16(env, s);
544 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
545 return tmp;
546 case 6: /* Indirect index + displacement. */
547 reg = AREG(insn, 0);
548 return gen_lea_indexed(env, s, reg);
549 case 7: /* Other */
550 switch (insn & 7) {
551 case 0: /* Absolute short. */
552 offset = (int16_t)read_im16(env, s);
553 return tcg_const_i32(offset);
554 case 1: /* Absolute long. */
555 offset = read_im32(env, s);
556 return tcg_const_i32(offset);
557 case 2: /* pc displacement */
558 offset = s->pc;
559 offset += (int16_t)read_im16(env, s);
560 return tcg_const_i32(offset);
561 case 3: /* pc index+displacement. */
562 return gen_lea_indexed(env, s, NULL_QREG);
563 case 4: /* Immediate. */
564 default:
565 return NULL_QREG;
566 }
567 }
568 /* Should never happen. */
569 return NULL_QREG;
570 }
571
572 /* Helper function for gen_ea. Reuse the computed address between the
573 for read/write operands. */
574 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
575 uint16_t insn, int opsize, TCGv val,
576 TCGv *addrp, ea_what what)
577 {
578 TCGv tmp;
579
580 if (addrp && what == EA_STORE) {
581 tmp = *addrp;
582 } else {
583 tmp = gen_lea(env, s, insn, opsize);
584 if (IS_NULL_QREG(tmp))
585 return tmp;
586 if (addrp)
587 *addrp = tmp;
588 }
589 return gen_ldst(s, opsize, tmp, val, what);
590 }
591
592 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
593 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
594 ADDRP is non-null for readwrite operands. */
595 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
596 int opsize, TCGv val, TCGv *addrp, ea_what what)
597 {
598 TCGv reg;
599 TCGv result;
600 uint32_t offset;
601
602 switch ((insn >> 3) & 7) {
603 case 0: /* Data register direct. */
604 reg = DREG(insn, 0);
605 if (what == EA_STORE) {
606 gen_partset_reg(opsize, reg, val);
607 return store_dummy;
608 } else {
609 return gen_extend(reg, opsize, what == EA_LOADS);
610 }
611 case 1: /* Address register direct. */
612 reg = AREG(insn, 0);
613 if (what == EA_STORE) {
614 tcg_gen_mov_i32(reg, val);
615 return store_dummy;
616 } else {
617 return gen_extend(reg, opsize, what == EA_LOADS);
618 }
619 case 2: /* Indirect register */
620 reg = AREG(insn, 0);
621 return gen_ldst(s, opsize, reg, val, what);
622 case 3: /* Indirect postincrement. */
623 reg = AREG(insn, 0);
624 result = gen_ldst(s, opsize, reg, val, what);
625 /* ??? This is not exception safe. The instruction may still
626 fault after this point. */
627 if (what == EA_STORE || !addrp)
628 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
629 return result;
630 case 4: /* Indirect predecrememnt. */
631 {
632 TCGv tmp;
633 if (addrp && what == EA_STORE) {
634 tmp = *addrp;
635 } else {
636 tmp = gen_lea(env, s, insn, opsize);
637 if (IS_NULL_QREG(tmp))
638 return tmp;
639 if (addrp)
640 *addrp = tmp;
641 }
642 result = gen_ldst(s, opsize, tmp, val, what);
643 /* ??? This is not exception safe. The instruction may still
644 fault after this point. */
645 if (what == EA_STORE || !addrp) {
646 reg = AREG(insn, 0);
647 tcg_gen_mov_i32(reg, tmp);
648 }
649 }
650 return result;
651 case 5: /* Indirect displacement. */
652 case 6: /* Indirect index + displacement. */
653 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
654 case 7: /* Other */
655 switch (insn & 7) {
656 case 0: /* Absolute short. */
657 case 1: /* Absolute long. */
658 case 2: /* pc displacement */
659 case 3: /* pc index+displacement. */
660 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
661 case 4: /* Immediate. */
662 /* Sign extend values for consistency. */
663 switch (opsize) {
664 case OS_BYTE:
665 if (what == EA_LOADS) {
666 offset = (int8_t)read_im8(env, s);
667 } else {
668 offset = read_im8(env, s);
669 }
670 break;
671 case OS_WORD:
672 if (what == EA_LOADS) {
673 offset = (int16_t)read_im16(env, s);
674 } else {
675 offset = read_im16(env, s);
676 }
677 break;
678 case OS_LONG:
679 offset = read_im32(env, s);
680 break;
681 default:
682 g_assert_not_reached();
683 }
684 return tcg_const_i32(offset);
685 default:
686 return NULL_QREG;
687 }
688 }
689 /* Should never happen. */
690 return NULL_QREG;
691 }
692
693 /* This generates a conditional branch, clobbering all temporaries. */
694 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
695 {
696 TCGv tmp;
697
698 /* TODO: Optimize compare/branch pairs rather than always flushing
699 flag state to CC_OP_FLAGS. */
700 gen_flush_flags(s);
701 switch (cond) {
702 case 0: /* T */
703 tcg_gen_br(l1);
704 break;
705 case 1: /* F */
706 break;
707 case 2: /* HI (!C && !Z) */
708 tmp = tcg_temp_new();
709 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
710 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
711 break;
712 case 3: /* LS (C || Z) */
713 tmp = tcg_temp_new();
714 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
715 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
716 break;
717 case 4: /* CC (!C) */
718 tmp = tcg_temp_new();
719 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
720 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
721 break;
722 case 5: /* CS (C) */
723 tmp = tcg_temp_new();
724 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
725 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
726 break;
727 case 6: /* NE (!Z) */
728 tmp = tcg_temp_new();
729 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
731 break;
732 case 7: /* EQ (Z) */
733 tmp = tcg_temp_new();
734 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
735 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
736 break;
737 case 8: /* VC (!V) */
738 tmp = tcg_temp_new();
739 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
740 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
741 break;
742 case 9: /* VS (V) */
743 tmp = tcg_temp_new();
744 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
745 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
746 break;
747 case 10: /* PL (!N) */
748 tmp = tcg_temp_new();
749 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
750 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
751 break;
752 case 11: /* MI (N) */
753 tmp = tcg_temp_new();
754 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
755 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
756 break;
757 case 12: /* GE (!(N ^ V)) */
758 tmp = tcg_temp_new();
759 assert(CCF_V == (CCF_N >> 2));
760 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
761 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
762 tcg_gen_andi_i32(tmp, tmp, CCF_V);
763 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
764 break;
765 case 13: /* LT (N ^ V) */
766 tmp = tcg_temp_new();
767 assert(CCF_V == (CCF_N >> 2));
768 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
769 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
770 tcg_gen_andi_i32(tmp, tmp, CCF_V);
771 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
772 break;
773 case 14: /* GT (!(Z || (N ^ V))) */
774 tmp = tcg_temp_new();
775 assert(CCF_V == (CCF_N >> 2));
776 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
777 tcg_gen_shri_i32(tmp, tmp, 2);
778 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
779 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
780 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
781 break;
782 case 15: /* LE (Z || (N ^ V)) */
783 tmp = tcg_temp_new();
784 assert(CCF_V == (CCF_N >> 2));
785 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
786 tcg_gen_shri_i32(tmp, tmp, 2);
787 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
788 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
789 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
790 break;
791 default:
792 /* Should ever happen. */
793 abort();
794 }
795 }
796
797 DISAS_INSN(scc)
798 {
799 TCGLabel *l1;
800 int cond;
801 TCGv reg;
802
803 l1 = gen_new_label();
804 cond = (insn >> 8) & 0xf;
805 reg = DREG(insn, 0);
806 tcg_gen_andi_i32(reg, reg, 0xffffff00);
807 /* This is safe because we modify the reg directly, with no other values
808 live. */
809 gen_jmpcc(s, cond ^ 1, l1);
810 tcg_gen_ori_i32(reg, reg, 0xff);
811 gen_set_label(l1);
812 }
813
814 /* Force a TB lookup after an instruction that changes the CPU state. */
815 static void gen_lookup_tb(DisasContext *s)
816 {
817 gen_flush_cc_op(s);
818 tcg_gen_movi_i32(QREG_PC, s->pc);
819 s->is_jmp = DISAS_UPDATE;
820 }
821
822 /* Generate a jump to an immediate address. */
823 static void gen_jmp_im(DisasContext *s, uint32_t dest)
824 {
825 gen_flush_cc_op(s);
826 tcg_gen_movi_i32(QREG_PC, dest);
827 s->is_jmp = DISAS_JUMP;
828 }
829
830 /* Generate a jump to the address in qreg DEST. */
831 static void gen_jmp(DisasContext *s, TCGv dest)
832 {
833 gen_flush_cc_op(s);
834 tcg_gen_mov_i32(QREG_PC, dest);
835 s->is_jmp = DISAS_JUMP;
836 }
837
838 static void gen_exception(DisasContext *s, uint32_t where, int nr)
839 {
840 gen_flush_cc_op(s);
841 gen_jmp_im(s, where);
842 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
843 }
844
845 static inline void gen_addr_fault(DisasContext *s)
846 {
847 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
848 }
849
850 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
851 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
852 op_sign ? EA_LOADS : EA_LOADU); \
853 if (IS_NULL_QREG(result)) { \
854 gen_addr_fault(s); \
855 return; \
856 } \
857 } while (0)
858
859 #define DEST_EA(env, insn, opsize, val, addrp) do { \
860 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
861 if (IS_NULL_QREG(ea_result)) { \
862 gen_addr_fault(s); \
863 return; \
864 } \
865 } while (0)
866
867 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
868 {
869 #ifndef CONFIG_USER_ONLY
870 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
871 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
872 #else
873 return true;
874 #endif
875 }
876
877 /* Generate a jump to an immediate address. */
878 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
879 {
880 if (unlikely(s->singlestep_enabled)) {
881 gen_exception(s, dest, EXCP_DEBUG);
882 } else if (use_goto_tb(s, dest)) {
883 tcg_gen_goto_tb(n);
884 tcg_gen_movi_i32(QREG_PC, dest);
885 tcg_gen_exit_tb((uintptr_t)s->tb + n);
886 } else {
887 gen_jmp_im(s, dest);
888 tcg_gen_exit_tb(0);
889 }
890 s->is_jmp = DISAS_TB_JUMP;
891 }
892
893 DISAS_INSN(undef_mac)
894 {
895 gen_exception(s, s->pc - 2, EXCP_LINEA);
896 }
897
898 DISAS_INSN(undef_fpu)
899 {
900 gen_exception(s, s->pc - 2, EXCP_LINEF);
901 }
902
903 DISAS_INSN(undef)
904 {
905 M68kCPU *cpu = m68k_env_get_cpu(env);
906
907 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
908 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
909 }
910
911 DISAS_INSN(mulw)
912 {
913 TCGv reg;
914 TCGv tmp;
915 TCGv src;
916 int sign;
917
918 sign = (insn & 0x100) != 0;
919 reg = DREG(insn, 9);
920 tmp = tcg_temp_new();
921 if (sign)
922 tcg_gen_ext16s_i32(tmp, reg);
923 else
924 tcg_gen_ext16u_i32(tmp, reg);
925 SRC_EA(env, src, OS_WORD, sign, NULL);
926 tcg_gen_mul_i32(tmp, tmp, src);
927 tcg_gen_mov_i32(reg, tmp);
928 /* Unlike m68k, coldfire always clears the overflow bit. */
929 gen_logic_cc(s, tmp);
930 }
931
932 DISAS_INSN(divw)
933 {
934 TCGv reg;
935 TCGv tmp;
936 TCGv src;
937 int sign;
938
939 sign = (insn & 0x100) != 0;
940 reg = DREG(insn, 9);
941 if (sign) {
942 tcg_gen_ext16s_i32(QREG_DIV1, reg);
943 } else {
944 tcg_gen_ext16u_i32(QREG_DIV1, reg);
945 }
946 SRC_EA(env, src, OS_WORD, sign, NULL);
947 tcg_gen_mov_i32(QREG_DIV2, src);
948 if (sign) {
949 gen_helper_divs(cpu_env, tcg_const_i32(1));
950 } else {
951 gen_helper_divu(cpu_env, tcg_const_i32(1));
952 }
953
954 tmp = tcg_temp_new();
955 src = tcg_temp_new();
956 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
957 tcg_gen_shli_i32(src, QREG_DIV2, 16);
958 tcg_gen_or_i32(reg, tmp, src);
959 s->cc_op = CC_OP_FLAGS;
960 }
961
962 DISAS_INSN(divl)
963 {
964 TCGv num;
965 TCGv den;
966 TCGv reg;
967 uint16_t ext;
968
969 ext = read_im16(env, s);
970 if (ext & 0x87f8) {
971 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
972 return;
973 }
974 num = DREG(ext, 12);
975 reg = DREG(ext, 0);
976 tcg_gen_mov_i32(QREG_DIV1, num);
977 SRC_EA(env, den, OS_LONG, 0, NULL);
978 tcg_gen_mov_i32(QREG_DIV2, den);
979 if (ext & 0x0800) {
980 gen_helper_divs(cpu_env, tcg_const_i32(0));
981 } else {
982 gen_helper_divu(cpu_env, tcg_const_i32(0));
983 }
984 if ((ext & 7) == ((ext >> 12) & 7)) {
985 /* div */
986 tcg_gen_mov_i32 (reg, QREG_DIV1);
987 } else {
988 /* rem */
989 tcg_gen_mov_i32 (reg, QREG_DIV2);
990 }
991 s->cc_op = CC_OP_FLAGS;
992 }
993
994 DISAS_INSN(addsub)
995 {
996 TCGv reg;
997 TCGv dest;
998 TCGv src;
999 TCGv tmp;
1000 TCGv addr;
1001 int add;
1002
1003 add = (insn & 0x4000) != 0;
1004 reg = DREG(insn, 9);
1005 dest = tcg_temp_new();
1006 if (insn & 0x100) {
1007 SRC_EA(env, tmp, OS_LONG, 0, &addr);
1008 src = reg;
1009 } else {
1010 tmp = reg;
1011 SRC_EA(env, src, OS_LONG, 0, NULL);
1012 }
1013 if (add) {
1014 tcg_gen_add_i32(dest, tmp, src);
1015 gen_helper_xflag_lt(QREG_CC_X, dest, src);
1016 s->cc_op = CC_OP_ADD;
1017 } else {
1018 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
1019 tcg_gen_sub_i32(dest, tmp, src);
1020 s->cc_op = CC_OP_SUB;
1021 }
1022 gen_update_cc_add(dest, src);
1023 if (insn & 0x100) {
1024 DEST_EA(env, insn, OS_LONG, dest, &addr);
1025 } else {
1026 tcg_gen_mov_i32(reg, dest);
1027 }
1028 }
1029
1030
1031 /* Reverse the order of the bits in REG. */
1032 DISAS_INSN(bitrev)
1033 {
1034 TCGv reg;
1035 reg = DREG(insn, 0);
1036 gen_helper_bitrev(reg, reg);
1037 }
1038
1039 DISAS_INSN(bitop_reg)
1040 {
1041 int opsize;
1042 int op;
1043 TCGv src1;
1044 TCGv src2;
1045 TCGv tmp;
1046 TCGv addr;
1047 TCGv dest;
1048
1049 if ((insn & 0x38) != 0)
1050 opsize = OS_BYTE;
1051 else
1052 opsize = OS_LONG;
1053 op = (insn >> 6) & 3;
1054 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1055 src2 = DREG(insn, 9);
1056 dest = tcg_temp_new();
1057
1058 gen_flush_flags(s);
1059 tmp = tcg_temp_new();
1060 if (opsize == OS_BYTE)
1061 tcg_gen_andi_i32(tmp, src2, 7);
1062 else
1063 tcg_gen_andi_i32(tmp, src2, 31);
1064 src2 = tmp;
1065 tmp = tcg_temp_new();
1066 tcg_gen_shr_i32(tmp, src1, src2);
1067 tcg_gen_andi_i32(tmp, tmp, 1);
1068 tcg_gen_shli_i32(tmp, tmp, 2);
1069 /* Clear CCF_Z if bit set. */
1070 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1071 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1072
1073 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1074 switch (op) {
1075 case 1: /* bchg */
1076 tcg_gen_xor_i32(dest, src1, tmp);
1077 break;
1078 case 2: /* bclr */
1079 tcg_gen_not_i32(tmp, tmp);
1080 tcg_gen_and_i32(dest, src1, tmp);
1081 break;
1082 case 3: /* bset */
1083 tcg_gen_or_i32(dest, src1, tmp);
1084 break;
1085 default: /* btst */
1086 break;
1087 }
1088 if (op)
1089 DEST_EA(env, insn, opsize, dest, &addr);
1090 }
1091
1092 DISAS_INSN(sats)
1093 {
1094 TCGv reg;
1095 reg = DREG(insn, 0);
1096 gen_flush_flags(s);
1097 gen_helper_sats(reg, reg, QREG_CC_DEST);
1098 gen_logic_cc(s, reg);
1099 }
1100
1101 static void gen_push(DisasContext *s, TCGv val)
1102 {
1103 TCGv tmp;
1104
1105 tmp = tcg_temp_new();
1106 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1107 gen_store(s, OS_LONG, tmp, val);
1108 tcg_gen_mov_i32(QREG_SP, tmp);
1109 }
1110
1111 DISAS_INSN(movem)
1112 {
1113 TCGv addr;
1114 int i;
1115 uint16_t mask;
1116 TCGv reg;
1117 TCGv tmp;
1118 int is_load;
1119
1120 mask = read_im16(env, s);
1121 tmp = gen_lea(env, s, insn, OS_LONG);
1122 if (IS_NULL_QREG(tmp)) {
1123 gen_addr_fault(s);
1124 return;
1125 }
1126 addr = tcg_temp_new();
1127 tcg_gen_mov_i32(addr, tmp);
1128 is_load = ((insn & 0x0400) != 0);
1129 for (i = 0; i < 16; i++, mask >>= 1) {
1130 if (mask & 1) {
1131 if (i < 8)
1132 reg = DREG(i, 0);
1133 else
1134 reg = AREG(i, 0);
1135 if (is_load) {
1136 tmp = gen_load(s, OS_LONG, addr, 0);
1137 tcg_gen_mov_i32(reg, tmp);
1138 } else {
1139 gen_store(s, OS_LONG, addr, reg);
1140 }
1141 if (mask != 1)
1142 tcg_gen_addi_i32(addr, addr, 4);
1143 }
1144 }
1145 }
1146
1147 DISAS_INSN(bitop_im)
1148 {
1149 int opsize;
1150 int op;
1151 TCGv src1;
1152 uint32_t mask;
1153 int bitnum;
1154 TCGv tmp;
1155 TCGv addr;
1156
1157 if ((insn & 0x38) != 0)
1158 opsize = OS_BYTE;
1159 else
1160 opsize = OS_LONG;
1161 op = (insn >> 6) & 3;
1162
1163 bitnum = read_im16(env, s);
1164 if (bitnum & 0xff00) {
1165 disas_undef(env, s, insn);
1166 return;
1167 }
1168
1169 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1170
1171 gen_flush_flags(s);
1172 if (opsize == OS_BYTE)
1173 bitnum &= 7;
1174 else
1175 bitnum &= 31;
1176 mask = 1 << bitnum;
1177
1178 tmp = tcg_temp_new();
1179 assert (CCF_Z == (1 << 2));
1180 if (bitnum > 2)
1181 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1182 else if (bitnum < 2)
1183 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1184 else
1185 tcg_gen_mov_i32(tmp, src1);
1186 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1187 /* Clear CCF_Z if bit set. */
1188 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1189 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1190 if (op) {
1191 switch (op) {
1192 case 1: /* bchg */
1193 tcg_gen_xori_i32(tmp, src1, mask);
1194 break;
1195 case 2: /* bclr */
1196 tcg_gen_andi_i32(tmp, src1, ~mask);
1197 break;
1198 case 3: /* bset */
1199 tcg_gen_ori_i32(tmp, src1, mask);
1200 break;
1201 default: /* btst */
1202 break;
1203 }
1204 DEST_EA(env, insn, opsize, tmp, &addr);
1205 }
1206 }
1207
1208 DISAS_INSN(arith_im)
1209 {
1210 int op;
1211 uint32_t im;
1212 TCGv src1;
1213 TCGv dest;
1214 TCGv addr;
1215
1216 op = (insn >> 9) & 7;
1217 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1218 im = read_im32(env, s);
1219 dest = tcg_temp_new();
1220 switch (op) {
1221 case 0: /* ori */
1222 tcg_gen_ori_i32(dest, src1, im);
1223 gen_logic_cc(s, dest);
1224 break;
1225 case 1: /* andi */
1226 tcg_gen_andi_i32(dest, src1, im);
1227 gen_logic_cc(s, dest);
1228 break;
1229 case 2: /* subi */
1230 tcg_gen_mov_i32(dest, src1);
1231 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1232 tcg_gen_subi_i32(dest, dest, im);
1233 gen_update_cc_add(dest, tcg_const_i32(im));
1234 s->cc_op = CC_OP_SUB;
1235 break;
1236 case 3: /* addi */
1237 tcg_gen_mov_i32(dest, src1);
1238 tcg_gen_addi_i32(dest, dest, im);
1239 gen_update_cc_add(dest, tcg_const_i32(im));
1240 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1241 s->cc_op = CC_OP_ADD;
1242 break;
1243 case 5: /* eori */
1244 tcg_gen_xori_i32(dest, src1, im);
1245 gen_logic_cc(s, dest);
1246 break;
1247 case 6: /* cmpi */
1248 tcg_gen_mov_i32(dest, src1);
1249 tcg_gen_subi_i32(dest, dest, im);
1250 gen_update_cc_add(dest, tcg_const_i32(im));
1251 s->cc_op = CC_OP_SUB;
1252 break;
1253 default:
1254 abort();
1255 }
1256 if (op != 6) {
1257 DEST_EA(env, insn, OS_LONG, dest, &addr);
1258 }
1259 }
1260
1261 DISAS_INSN(byterev)
1262 {
1263 TCGv reg;
1264
1265 reg = DREG(insn, 0);
1266 tcg_gen_bswap32_i32(reg, reg);
1267 }
1268
1269 DISAS_INSN(move)
1270 {
1271 TCGv src;
1272 TCGv dest;
1273 int op;
1274 int opsize;
1275
1276 switch (insn >> 12) {
1277 case 1: /* move.b */
1278 opsize = OS_BYTE;
1279 break;
1280 case 2: /* move.l */
1281 opsize = OS_LONG;
1282 break;
1283 case 3: /* move.w */
1284 opsize = OS_WORD;
1285 break;
1286 default:
1287 abort();
1288 }
1289 SRC_EA(env, src, opsize, 1, NULL);
1290 op = (insn >> 6) & 7;
1291 if (op == 1) {
1292 /* movea */
1293 /* The value will already have been sign extended. */
1294 dest = AREG(insn, 9);
1295 tcg_gen_mov_i32(dest, src);
1296 } else {
1297 /* normal move */
1298 uint16_t dest_ea;
1299 dest_ea = ((insn >> 9) & 7) | (op << 3);
1300 DEST_EA(env, dest_ea, opsize, src, NULL);
1301 /* This will be correct because loads sign extend. */
1302 gen_logic_cc(s, src);
1303 }
1304 }
1305
1306 DISAS_INSN(negx)
1307 {
1308 TCGv reg;
1309
1310 gen_flush_flags(s);
1311 reg = DREG(insn, 0);
1312 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1313 }
1314
1315 DISAS_INSN(lea)
1316 {
1317 TCGv reg;
1318 TCGv tmp;
1319
1320 reg = AREG(insn, 9);
1321 tmp = gen_lea(env, s, insn, OS_LONG);
1322 if (IS_NULL_QREG(tmp)) {
1323 gen_addr_fault(s);
1324 return;
1325 }
1326 tcg_gen_mov_i32(reg, tmp);
1327 }
1328
1329 DISAS_INSN(clr)
1330 {
1331 int opsize;
1332
1333 switch ((insn >> 6) & 3) {
1334 case 0: /* clr.b */
1335 opsize = OS_BYTE;
1336 break;
1337 case 1: /* clr.w */
1338 opsize = OS_WORD;
1339 break;
1340 case 2: /* clr.l */
1341 opsize = OS_LONG;
1342 break;
1343 default:
1344 abort();
1345 }
1346 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1347 gen_logic_cc(s, tcg_const_i32(0));
1348 }
1349
1350 static TCGv gen_get_ccr(DisasContext *s)
1351 {
1352 TCGv dest;
1353
1354 gen_flush_flags(s);
1355 dest = tcg_temp_new();
1356 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1357 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1358 return dest;
1359 }
1360
1361 DISAS_INSN(move_from_ccr)
1362 {
1363 TCGv reg;
1364 TCGv ccr;
1365
1366 ccr = gen_get_ccr(s);
1367 reg = DREG(insn, 0);
1368 gen_partset_reg(OS_WORD, reg, ccr);
1369 }
1370
1371 DISAS_INSN(neg)
1372 {
1373 TCGv reg;
1374 TCGv src1;
1375
1376 reg = DREG(insn, 0);
1377 src1 = tcg_temp_new();
1378 tcg_gen_mov_i32(src1, reg);
1379 tcg_gen_neg_i32(reg, src1);
1380 s->cc_op = CC_OP_SUB;
1381 gen_update_cc_add(reg, src1);
1382 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1383 s->cc_op = CC_OP_SUB;
1384 }
1385
1386 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1387 {
1388 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1389 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1390 if (!ccr_only) {
1391 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1392 }
1393 }
1394
1395 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1396 int ccr_only)
1397 {
1398 TCGv tmp;
1399 TCGv reg;
1400
1401 s->cc_op = CC_OP_FLAGS;
1402 if ((insn & 0x38) == 0)
1403 {
1404 tmp = tcg_temp_new();
1405 reg = DREG(insn, 0);
1406 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1407 tcg_gen_shri_i32(tmp, reg, 4);
1408 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1409 if (!ccr_only) {
1410 gen_helper_set_sr(cpu_env, reg);
1411 }
1412 }
1413 else if ((insn & 0x3f) == 0x3c)
1414 {
1415 uint16_t val;
1416 val = read_im16(env, s);
1417 gen_set_sr_im(s, val, ccr_only);
1418 }
1419 else
1420 disas_undef(env, s, insn);
1421 }
1422
1423 DISAS_INSN(move_to_ccr)
1424 {
1425 gen_set_sr(env, s, insn, 1);
1426 }
1427
1428 DISAS_INSN(not)
1429 {
1430 TCGv reg;
1431
1432 reg = DREG(insn, 0);
1433 tcg_gen_not_i32(reg, reg);
1434 gen_logic_cc(s, reg);
1435 }
1436
1437 DISAS_INSN(swap)
1438 {
1439 TCGv src1;
1440 TCGv src2;
1441 TCGv reg;
1442
1443 src1 = tcg_temp_new();
1444 src2 = tcg_temp_new();
1445 reg = DREG(insn, 0);
1446 tcg_gen_shli_i32(src1, reg, 16);
1447 tcg_gen_shri_i32(src2, reg, 16);
1448 tcg_gen_or_i32(reg, src1, src2);
1449 gen_logic_cc(s, reg);
1450 }
1451
1452 DISAS_INSN(pea)
1453 {
1454 TCGv tmp;
1455
1456 tmp = gen_lea(env, s, insn, OS_LONG);
1457 if (IS_NULL_QREG(tmp)) {
1458 gen_addr_fault(s);
1459 return;
1460 }
1461 gen_push(s, tmp);
1462 }
1463
1464 DISAS_INSN(ext)
1465 {
1466 int op;
1467 TCGv reg;
1468 TCGv tmp;
1469
1470 reg = DREG(insn, 0);
1471 op = (insn >> 6) & 7;
1472 tmp = tcg_temp_new();
1473 if (op == 3)
1474 tcg_gen_ext16s_i32(tmp, reg);
1475 else
1476 tcg_gen_ext8s_i32(tmp, reg);
1477 if (op == 2)
1478 gen_partset_reg(OS_WORD, reg, tmp);
1479 else
1480 tcg_gen_mov_i32(reg, tmp);
1481 gen_logic_cc(s, tmp);
1482 }
1483
1484 DISAS_INSN(tst)
1485 {
1486 int opsize;
1487 TCGv tmp;
1488
1489 switch ((insn >> 6) & 3) {
1490 case 0: /* tst.b */
1491 opsize = OS_BYTE;
1492 break;
1493 case 1: /* tst.w */
1494 opsize = OS_WORD;
1495 break;
1496 case 2: /* tst.l */
1497 opsize = OS_LONG;
1498 break;
1499 default:
1500 abort();
1501 }
1502 SRC_EA(env, tmp, opsize, 1, NULL);
1503 gen_logic_cc(s, tmp);
1504 }
1505
1506 DISAS_INSN(pulse)
1507 {
1508 /* Implemented as a NOP. */
1509 }
1510
1511 DISAS_INSN(illegal)
1512 {
1513 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1514 }
1515
1516 /* ??? This should be atomic. */
1517 DISAS_INSN(tas)
1518 {
1519 TCGv dest;
1520 TCGv src1;
1521 TCGv addr;
1522
1523 dest = tcg_temp_new();
1524 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1525 gen_logic_cc(s, src1);
1526 tcg_gen_ori_i32(dest, src1, 0x80);
1527 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1528 }
1529
1530 DISAS_INSN(mull)
1531 {
1532 uint16_t ext;
1533 TCGv reg;
1534 TCGv src1;
1535 TCGv dest;
1536
1537 /* The upper 32 bits of the product are discarded, so
1538 muls.l and mulu.l are functionally equivalent. */
1539 ext = read_im16(env, s);
1540 if (ext & 0x87ff) {
1541 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1542 return;
1543 }
1544 reg = DREG(ext, 12);
1545 SRC_EA(env, src1, OS_LONG, 0, NULL);
1546 dest = tcg_temp_new();
1547 tcg_gen_mul_i32(dest, src1, reg);
1548 tcg_gen_mov_i32(reg, dest);
1549 /* Unlike m68k, coldfire always clears the overflow bit. */
1550 gen_logic_cc(s, dest);
1551 }
1552
1553 DISAS_INSN(link)
1554 {
1555 int16_t offset;
1556 TCGv reg;
1557 TCGv tmp;
1558
1559 offset = cpu_ldsw_code(env, s->pc);
1560 s->pc += 2;
1561 reg = AREG(insn, 0);
1562 tmp = tcg_temp_new();
1563 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1564 gen_store(s, OS_LONG, tmp, reg);
1565 if ((insn & 7) != 7)
1566 tcg_gen_mov_i32(reg, tmp);
1567 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1568 }
1569
1570 DISAS_INSN(unlk)
1571 {
1572 TCGv src;
1573 TCGv reg;
1574 TCGv tmp;
1575
1576 src = tcg_temp_new();
1577 reg = AREG(insn, 0);
1578 tcg_gen_mov_i32(src, reg);
1579 tmp = gen_load(s, OS_LONG, src, 0);
1580 tcg_gen_mov_i32(reg, tmp);
1581 tcg_gen_addi_i32(QREG_SP, src, 4);
1582 }
1583
1584 DISAS_INSN(nop)
1585 {
1586 }
1587
1588 DISAS_INSN(rts)
1589 {
1590 TCGv tmp;
1591
1592 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1593 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1594 gen_jmp(s, tmp);
1595 }
1596
1597 DISAS_INSN(jump)
1598 {
1599 TCGv tmp;
1600
1601 /* Load the target address first to ensure correct exception
1602 behavior. */
1603 tmp = gen_lea(env, s, insn, OS_LONG);
1604 if (IS_NULL_QREG(tmp)) {
1605 gen_addr_fault(s);
1606 return;
1607 }
1608 if ((insn & 0x40) == 0) {
1609 /* jsr */
1610 gen_push(s, tcg_const_i32(s->pc));
1611 }
1612 gen_jmp(s, tmp);
1613 }
1614
1615 DISAS_INSN(addsubq)
1616 {
1617 TCGv src1;
1618 TCGv src2;
1619 TCGv dest;
1620 int val;
1621 TCGv addr;
1622
1623 SRC_EA(env, src1, OS_LONG, 0, &addr);
1624 val = (insn >> 9) & 7;
1625 if (val == 0)
1626 val = 8;
1627 dest = tcg_temp_new();
1628 tcg_gen_mov_i32(dest, src1);
1629 if ((insn & 0x38) == 0x08) {
1630 /* Don't update condition codes if the destination is an
1631 address register. */
1632 if (insn & 0x0100) {
1633 tcg_gen_subi_i32(dest, dest, val);
1634 } else {
1635 tcg_gen_addi_i32(dest, dest, val);
1636 }
1637 } else {
1638 src2 = tcg_const_i32(val);
1639 if (insn & 0x0100) {
1640 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1641 tcg_gen_subi_i32(dest, dest, val);
1642 s->cc_op = CC_OP_SUB;
1643 } else {
1644 tcg_gen_addi_i32(dest, dest, val);
1645 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1646 s->cc_op = CC_OP_ADD;
1647 }
1648 gen_update_cc_add(dest, src2);
1649 }
1650 DEST_EA(env, insn, OS_LONG, dest, &addr);
1651 }
1652
1653 DISAS_INSN(tpf)
1654 {
1655 switch (insn & 7) {
1656 case 2: /* One extension word. */
1657 s->pc += 2;
1658 break;
1659 case 3: /* Two extension words. */
1660 s->pc += 4;
1661 break;
1662 case 4: /* No extension words. */
1663 break;
1664 default:
1665 disas_undef(env, s, insn);
1666 }
1667 }
1668
1669 DISAS_INSN(branch)
1670 {
1671 int32_t offset;
1672 uint32_t base;
1673 int op;
1674 TCGLabel *l1;
1675
1676 base = s->pc;
1677 op = (insn >> 8) & 0xf;
1678 offset = (int8_t)insn;
1679 if (offset == 0) {
1680 offset = (int16_t)read_im16(env, s);
1681 } else if (offset == -1) {
1682 offset = read_im32(env, s);
1683 }
1684 if (op == 1) {
1685 /* bsr */
1686 gen_push(s, tcg_const_i32(s->pc));
1687 }
1688 gen_flush_cc_op(s);
1689 if (op > 1) {
1690 /* Bcc */
1691 l1 = gen_new_label();
1692 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1693 gen_jmp_tb(s, 1, base + offset);
1694 gen_set_label(l1);
1695 gen_jmp_tb(s, 0, s->pc);
1696 } else {
1697 /* Unconditional branch. */
1698 gen_jmp_tb(s, 0, base + offset);
1699 }
1700 }
1701
1702 DISAS_INSN(moveq)
1703 {
1704 uint32_t val;
1705
1706 val = (int8_t)insn;
1707 tcg_gen_movi_i32(DREG(insn, 9), val);
1708 gen_logic_cc(s, tcg_const_i32(val));
1709 }
1710
1711 DISAS_INSN(mvzs)
1712 {
1713 int opsize;
1714 TCGv src;
1715 TCGv reg;
1716
1717 if (insn & 0x40)
1718 opsize = OS_WORD;
1719 else
1720 opsize = OS_BYTE;
1721 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1722 reg = DREG(insn, 9);
1723 tcg_gen_mov_i32(reg, src);
1724 gen_logic_cc(s, src);
1725 }
1726
1727 DISAS_INSN(or)
1728 {
1729 TCGv reg;
1730 TCGv dest;
1731 TCGv src;
1732 TCGv addr;
1733
1734 reg = DREG(insn, 9);
1735 dest = tcg_temp_new();
1736 if (insn & 0x100) {
1737 SRC_EA(env, src, OS_LONG, 0, &addr);
1738 tcg_gen_or_i32(dest, src, reg);
1739 DEST_EA(env, insn, OS_LONG, dest, &addr);
1740 } else {
1741 SRC_EA(env, src, OS_LONG, 0, NULL);
1742 tcg_gen_or_i32(dest, src, reg);
1743 tcg_gen_mov_i32(reg, dest);
1744 }
1745 gen_logic_cc(s, dest);
1746 }
1747
1748 DISAS_INSN(suba)
1749 {
1750 TCGv src;
1751 TCGv reg;
1752
1753 SRC_EA(env, src, OS_LONG, 0, NULL);
1754 reg = AREG(insn, 9);
1755 tcg_gen_sub_i32(reg, reg, src);
1756 }
1757
1758 DISAS_INSN(subx)
1759 {
1760 TCGv reg;
1761 TCGv src;
1762
1763 gen_flush_flags(s);
1764 reg = DREG(insn, 9);
1765 src = DREG(insn, 0);
1766 gen_helper_subx_cc(reg, cpu_env, reg, src);
1767 }
1768
1769 DISAS_INSN(mov3q)
1770 {
1771 TCGv src;
1772 int val;
1773
1774 val = (insn >> 9) & 7;
1775 if (val == 0)
1776 val = -1;
1777 src = tcg_const_i32(val);
1778 gen_logic_cc(s, src);
1779 DEST_EA(env, insn, OS_LONG, src, NULL);
1780 }
1781
1782 DISAS_INSN(cmp)
1783 {
1784 int op;
1785 TCGv src;
1786 TCGv reg;
1787 TCGv dest;
1788 int opsize;
1789
1790 op = (insn >> 6) & 3;
1791 switch (op) {
1792 case 0: /* cmp.b */
1793 opsize = OS_BYTE;
1794 s->cc_op = CC_OP_CMPB;
1795 break;
1796 case 1: /* cmp.w */
1797 opsize = OS_WORD;
1798 s->cc_op = CC_OP_CMPW;
1799 break;
1800 case 2: /* cmp.l */
1801 opsize = OS_LONG;
1802 s->cc_op = CC_OP_SUB;
1803 break;
1804 default:
1805 abort();
1806 }
1807 SRC_EA(env, src, opsize, 1, NULL);
1808 reg = DREG(insn, 9);
1809 dest = tcg_temp_new();
1810 tcg_gen_sub_i32(dest, reg, src);
1811 gen_update_cc_add(dest, src);
1812 }
1813
1814 DISAS_INSN(cmpa)
1815 {
1816 int opsize;
1817 TCGv src;
1818 TCGv reg;
1819 TCGv dest;
1820
1821 if (insn & 0x100) {
1822 opsize = OS_LONG;
1823 } else {
1824 opsize = OS_WORD;
1825 }
1826 SRC_EA(env, src, opsize, 1, NULL);
1827 reg = AREG(insn, 9);
1828 dest = tcg_temp_new();
1829 tcg_gen_sub_i32(dest, reg, src);
1830 gen_update_cc_add(dest, src);
1831 s->cc_op = CC_OP_SUB;
1832 }
1833
1834 DISAS_INSN(eor)
1835 {
1836 TCGv src;
1837 TCGv reg;
1838 TCGv dest;
1839 TCGv addr;
1840
1841 SRC_EA(env, src, OS_LONG, 0, &addr);
1842 reg = DREG(insn, 9);
1843 dest = tcg_temp_new();
1844 tcg_gen_xor_i32(dest, src, reg);
1845 gen_logic_cc(s, dest);
1846 DEST_EA(env, insn, OS_LONG, dest, &addr);
1847 }
1848
1849 DISAS_INSN(and)
1850 {
1851 TCGv src;
1852 TCGv reg;
1853 TCGv dest;
1854 TCGv addr;
1855
1856 reg = DREG(insn, 9);
1857 dest = tcg_temp_new();
1858 if (insn & 0x100) {
1859 SRC_EA(env, src, OS_LONG, 0, &addr);
1860 tcg_gen_and_i32(dest, src, reg);
1861 DEST_EA(env, insn, OS_LONG, dest, &addr);
1862 } else {
1863 SRC_EA(env, src, OS_LONG, 0, NULL);
1864 tcg_gen_and_i32(dest, src, reg);
1865 tcg_gen_mov_i32(reg, dest);
1866 }
1867 gen_logic_cc(s, dest);
1868 }
1869
1870 DISAS_INSN(adda)
1871 {
1872 TCGv src;
1873 TCGv reg;
1874
1875 SRC_EA(env, src, OS_LONG, 0, NULL);
1876 reg = AREG(insn, 9);
1877 tcg_gen_add_i32(reg, reg, src);
1878 }
1879
1880 DISAS_INSN(addx)
1881 {
1882 TCGv reg;
1883 TCGv src;
1884
1885 gen_flush_flags(s);
1886 reg = DREG(insn, 9);
1887 src = DREG(insn, 0);
1888 gen_helper_addx_cc(reg, cpu_env, reg, src);
1889 s->cc_op = CC_OP_FLAGS;
1890 }
1891
1892 /* TODO: This could be implemented without helper functions. */
1893 DISAS_INSN(shift_im)
1894 {
1895 TCGv reg;
1896 int tmp;
1897 TCGv shift;
1898
1899 reg = DREG(insn, 0);
1900 tmp = (insn >> 9) & 7;
1901 if (tmp == 0)
1902 tmp = 8;
1903 shift = tcg_const_i32(tmp);
1904 /* No need to flush flags becuse we know we will set C flag. */
1905 if (insn & 0x100) {
1906 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1907 } else {
1908 if (insn & 8) {
1909 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1910 } else {
1911 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1912 }
1913 }
1914 s->cc_op = CC_OP_SHIFT;
1915 }
1916
1917 DISAS_INSN(shift_reg)
1918 {
1919 TCGv reg;
1920 TCGv shift;
1921
1922 reg = DREG(insn, 0);
1923 shift = DREG(insn, 9);
1924 /* Shift by zero leaves C flag unmodified. */
1925 gen_flush_flags(s);
1926 if (insn & 0x100) {
1927 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1928 } else {
1929 if (insn & 8) {
1930 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1931 } else {
1932 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1933 }
1934 }
1935 s->cc_op = CC_OP_SHIFT;
1936 }
1937
1938 DISAS_INSN(ff1)
1939 {
1940 TCGv reg;
1941 reg = DREG(insn, 0);
1942 gen_logic_cc(s, reg);
1943 gen_helper_ff1(reg, reg);
1944 }
1945
1946 static TCGv gen_get_sr(DisasContext *s)
1947 {
1948 TCGv ccr;
1949 TCGv sr;
1950
1951 ccr = gen_get_ccr(s);
1952 sr = tcg_temp_new();
1953 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1954 tcg_gen_or_i32(sr, sr, ccr);
1955 return sr;
1956 }
1957
1958 DISAS_INSN(strldsr)
1959 {
1960 uint16_t ext;
1961 uint32_t addr;
1962
1963 addr = s->pc - 2;
1964 ext = read_im16(env, s);
1965 if (ext != 0x46FC) {
1966 gen_exception(s, addr, EXCP_UNSUPPORTED);
1967 return;
1968 }
1969 ext = read_im16(env, s);
1970 if (IS_USER(s) || (ext & SR_S) == 0) {
1971 gen_exception(s, addr, EXCP_PRIVILEGE);
1972 return;
1973 }
1974 gen_push(s, gen_get_sr(s));
1975 gen_set_sr_im(s, ext, 0);
1976 }
1977
1978 DISAS_INSN(move_from_sr)
1979 {
1980 TCGv reg;
1981 TCGv sr;
1982
1983 if (IS_USER(s)) {
1984 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1985 return;
1986 }
1987 sr = gen_get_sr(s);
1988 reg = DREG(insn, 0);
1989 gen_partset_reg(OS_WORD, reg, sr);
1990 }
1991
1992 DISAS_INSN(move_to_sr)
1993 {
1994 if (IS_USER(s)) {
1995 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1996 return;
1997 }
1998 gen_set_sr(env, s, insn, 0);
1999 gen_lookup_tb(s);
2000 }
2001
2002 DISAS_INSN(move_from_usp)
2003 {
2004 if (IS_USER(s)) {
2005 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2006 return;
2007 }
2008 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
2009 offsetof(CPUM68KState, sp[M68K_USP]));
2010 }
2011
2012 DISAS_INSN(move_to_usp)
2013 {
2014 if (IS_USER(s)) {
2015 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2016 return;
2017 }
2018 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2019 offsetof(CPUM68KState, sp[M68K_USP]));
2020 }
2021
2022 DISAS_INSN(halt)
2023 {
2024 gen_exception(s, s->pc, EXCP_HALT_INSN);
2025 }
2026
2027 DISAS_INSN(stop)
2028 {
2029 uint16_t ext;
2030
2031 if (IS_USER(s)) {
2032 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2033 return;
2034 }
2035
2036 ext = read_im16(env, s);
2037
2038 gen_set_sr_im(s, ext, 0);
2039 tcg_gen_movi_i32(cpu_halted, 1);
2040 gen_exception(s, s->pc, EXCP_HLT);
2041 }
2042
2043 DISAS_INSN(rte)
2044 {
2045 if (IS_USER(s)) {
2046 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2047 return;
2048 }
2049 gen_exception(s, s->pc - 2, EXCP_RTE);
2050 }
2051
2052 DISAS_INSN(movec)
2053 {
2054 uint16_t ext;
2055 TCGv reg;
2056
2057 if (IS_USER(s)) {
2058 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2059 return;
2060 }
2061
2062 ext = read_im16(env, s);
2063
2064 if (ext & 0x8000) {
2065 reg = AREG(ext, 12);
2066 } else {
2067 reg = DREG(ext, 12);
2068 }
2069 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2070 gen_lookup_tb(s);
2071 }
2072
2073 DISAS_INSN(intouch)
2074 {
2075 if (IS_USER(s)) {
2076 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2077 return;
2078 }
2079 /* ICache fetch. Implement as no-op. */
2080 }
2081
2082 DISAS_INSN(cpushl)
2083 {
2084 if (IS_USER(s)) {
2085 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2086 return;
2087 }
2088 /* Cache push/invalidate. Implement as no-op. */
2089 }
2090
2091 DISAS_INSN(wddata)
2092 {
2093 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2094 }
2095
2096 DISAS_INSN(wdebug)
2097 {
2098 M68kCPU *cpu = m68k_env_get_cpu(env);
2099
2100 if (IS_USER(s)) {
2101 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2102 return;
2103 }
2104 /* TODO: Implement wdebug. */
2105 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2106 }
2107
2108 DISAS_INSN(trap)
2109 {
2110 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2111 }
2112
2113 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2114 immediately before the next FP instruction is executed. */
2115 DISAS_INSN(fpu)
2116 {
2117 uint16_t ext;
2118 int32_t offset;
2119 int opmode;
2120 TCGv_i64 src;
2121 TCGv_i64 dest;
2122 TCGv_i64 res;
2123 TCGv tmp32;
2124 int round;
2125 int set_dest;
2126 int opsize;
2127
2128 ext = read_im16(env, s);
2129 opmode = ext & 0x7f;
2130 switch ((ext >> 13) & 7) {
2131 case 0: case 2:
2132 break;
2133 case 1:
2134 goto undef;
2135 case 3: /* fmove out */
2136 src = FREG(ext, 7);
2137 tmp32 = tcg_temp_new_i32();
2138 /* fmove */
2139 /* ??? TODO: Proper behavior on overflow. */
2140 switch ((ext >> 10) & 7) {
2141 case 0:
2142 opsize = OS_LONG;
2143 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2144 break;
2145 case 1:
2146 opsize = OS_SINGLE;
2147 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2148 break;
2149 case 4:
2150 opsize = OS_WORD;
2151 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2152 break;
2153 case 5: /* OS_DOUBLE */
2154 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2155 switch ((insn >> 3) & 7) {
2156 case 2:
2157 case 3:
2158 break;
2159 case 4:
2160 tcg_gen_addi_i32(tmp32, tmp32, -8);
2161 break;
2162 case 5:
2163 offset = cpu_ldsw_code(env, s->pc);
2164 s->pc += 2;
2165 tcg_gen_addi_i32(tmp32, tmp32, offset);
2166 break;
2167 default:
2168 goto undef;
2169 }
2170 gen_store64(s, tmp32, src);
2171 switch ((insn >> 3) & 7) {
2172 case 3:
2173 tcg_gen_addi_i32(tmp32, tmp32, 8);
2174 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2175 break;
2176 case 4:
2177 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2178 break;
2179 }
2180 tcg_temp_free_i32(tmp32);
2181 return;
2182 case 6:
2183 opsize = OS_BYTE;
2184 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2185 break;
2186 default:
2187 goto undef;
2188 }
2189 DEST_EA(env, insn, opsize, tmp32, NULL);
2190 tcg_temp_free_i32(tmp32);
2191 return;
2192 case 4: /* fmove to control register. */
2193 switch ((ext >> 10) & 7) {
2194 case 4: /* FPCR */
2195 /* Not implemented. Ignore writes. */
2196 break;
2197 case 1: /* FPIAR */
2198 case 2: /* FPSR */
2199 default:
2200 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2201 (ext >> 10) & 7);
2202 }
2203 break;
2204 case 5: /* fmove from control register. */
2205 switch ((ext >> 10) & 7) {
2206 case 4: /* FPCR */
2207 /* Not implemented. Always return zero. */
2208 tmp32 = tcg_const_i32(0);
2209 break;
2210 case 1: /* FPIAR */
2211 case 2: /* FPSR */
2212 default:
2213 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2214 (ext >> 10) & 7);
2215 goto undef;
2216 }
2217 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2218 break;
2219 case 6: /* fmovem */
2220 case 7:
2221 {
2222 TCGv addr;
2223 uint16_t mask;
2224 int i;
2225 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2226 goto undef;
2227 tmp32 = gen_lea(env, s, insn, OS_LONG);
2228 if (IS_NULL_QREG(tmp32)) {
2229 gen_addr_fault(s);
2230 return;
2231 }
2232 addr = tcg_temp_new_i32();
2233 tcg_gen_mov_i32(addr, tmp32);
2234 mask = 0x80;
2235 for (i = 0; i < 8; i++) {
2236 if (ext & mask) {
2237 dest = FREG(i, 0);
2238 if (ext & (1 << 13)) {
2239 /* store */
2240 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2241 } else {
2242 /* load */
2243 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2244 }
2245 if (ext & (mask - 1))
2246 tcg_gen_addi_i32(addr, addr, 8);
2247 }
2248 mask >>= 1;
2249 }
2250 tcg_temp_free_i32(addr);
2251 }
2252 return;
2253 }
2254 if (ext & (1 << 14)) {
2255 /* Source effective address. */
2256 switch ((ext >> 10) & 7) {
2257 case 0: opsize = OS_LONG; break;
2258 case 1: opsize = OS_SINGLE; break;
2259 case 4: opsize = OS_WORD; break;
2260 case 5: opsize = OS_DOUBLE; break;
2261 case 6: opsize = OS_BYTE; break;
2262 default:
2263 goto undef;
2264 }
2265 if (opsize == OS_DOUBLE) {
2266 tmp32 = tcg_temp_new_i32();
2267 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2268 switch ((insn >> 3) & 7) {
2269 case 2:
2270 case 3:
2271 break;
2272 case 4:
2273 tcg_gen_addi_i32(tmp32, tmp32, -8);
2274 break;
2275 case 5:
2276 offset = cpu_ldsw_code(env, s->pc);
2277 s->pc += 2;
2278 tcg_gen_addi_i32(tmp32, tmp32, offset);
2279 break;
2280 case 7:
2281 offset = cpu_ldsw_code(env, s->pc);
2282 offset += s->pc - 2;
2283 s->pc += 2;
2284 tcg_gen_addi_i32(tmp32, tmp32, offset);
2285 break;
2286 default:
2287 goto undef;
2288 }
2289 src = gen_load64(s, tmp32);
2290 switch ((insn >> 3) & 7) {
2291 case 3:
2292 tcg_gen_addi_i32(tmp32, tmp32, 8);
2293 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2294 break;
2295 case 4:
2296 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2297 break;
2298 }
2299 tcg_temp_free_i32(tmp32);
2300 } else {
2301 SRC_EA(env, tmp32, opsize, 1, NULL);
2302 src = tcg_temp_new_i64();
2303 switch (opsize) {
2304 case OS_LONG:
2305 case OS_WORD:
2306 case OS_BYTE:
2307 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2308 break;
2309 case OS_SINGLE:
2310 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2311 break;
2312 }
2313 }
2314 } else {
2315 /* Source register. */
2316 src = FREG(ext, 10);
2317 }
2318 dest = FREG(ext, 7);
2319 res = tcg_temp_new_i64();
2320 if (opmode != 0x3a)
2321 tcg_gen_mov_f64(res, dest);
2322 round = 1;
2323 set_dest = 1;
2324 switch (opmode) {
2325 case 0: case 0x40: case 0x44: /* fmove */
2326 tcg_gen_mov_f64(res, src);
2327 break;
2328 case 1: /* fint */
2329 gen_helper_iround_f64(res, cpu_env, src);
2330 round = 0;
2331 break;
2332 case 3: /* fintrz */
2333 gen_helper_itrunc_f64(res, cpu_env, src);
2334 round = 0;
2335 break;
2336 case 4: case 0x41: case 0x45: /* fsqrt */
2337 gen_helper_sqrt_f64(res, cpu_env, src);
2338 break;
2339 case 0x18: case 0x58: case 0x5c: /* fabs */
2340 gen_helper_abs_f64(res, src);
2341 break;
2342 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2343 gen_helper_chs_f64(res, src);
2344 break;
2345 case 0x20: case 0x60: case 0x64: /* fdiv */
2346 gen_helper_div_f64(res, cpu_env, res, src);
2347 break;
2348 case 0x22: case 0x62: case 0x66: /* fadd */
2349 gen_helper_add_f64(res, cpu_env, res, src);
2350 break;
2351 case 0x23: case 0x63: case 0x67: /* fmul */
2352 gen_helper_mul_f64(res, cpu_env, res, src);
2353 break;
2354 case 0x28: case 0x68: case 0x6c: /* fsub */
2355 gen_helper_sub_f64(res, cpu_env, res, src);
2356 break;
2357 case 0x38: /* fcmp */
2358 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2359 set_dest = 0;
2360 round = 0;
2361 break;
2362 case 0x3a: /* ftst */
2363 tcg_gen_mov_f64(res, src);
2364 set_dest = 0;
2365 round = 0;
2366 break;
2367 default:
2368 goto undef;
2369 }
2370 if (ext & (1 << 14)) {
2371 tcg_temp_free_i64(src);
2372 }
2373 if (round) {
2374 if (opmode & 0x40) {
2375 if ((opmode & 0x4) != 0)
2376 round = 0;
2377 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2378 round = 0;
2379 }
2380 }
2381 if (round) {
2382 TCGv tmp = tcg_temp_new_i32();
2383 gen_helper_f64_to_f32(tmp, cpu_env, res);
2384 gen_helper_f32_to_f64(res, cpu_env, tmp);
2385 tcg_temp_free_i32(tmp);
2386 }
2387 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2388 if (set_dest) {
2389 tcg_gen_mov_f64(dest, res);
2390 }
2391 tcg_temp_free_i64(res);
2392 return;
2393 undef:
2394 /* FIXME: Is this right for offset addressing modes? */
2395 s->pc -= 2;
2396 disas_undef_fpu(env, s, insn);
2397 }
2398
2399 DISAS_INSN(fbcc)
2400 {
2401 uint32_t offset;
2402 uint32_t addr;
2403 TCGv flag;
2404 TCGLabel *l1;
2405
2406 addr = s->pc;
2407 offset = cpu_ldsw_code(env, s->pc);
2408 s->pc += 2;
2409 if (insn & (1 << 6)) {
2410 offset = (offset << 16) | read_im16(env, s);
2411 }
2412
2413 l1 = gen_new_label();
2414 /* TODO: Raise BSUN exception. */
2415 flag = tcg_temp_new();
2416 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2417 /* Jump to l1 if condition is true. */
2418 switch (insn & 0xf) {
2419 case 0: /* f */
2420 break;
2421 case 1: /* eq (=0) */
2422 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2423 break;
2424 case 2: /* ogt (=1) */
2425 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2426 break;
2427 case 3: /* oge (=0 or =1) */
2428 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2429 break;
2430 case 4: /* olt (=-1) */
2431 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2432 break;
2433 case 5: /* ole (=-1 or =0) */
2434 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2435 break;
2436 case 6: /* ogl (=-1 or =1) */
2437 tcg_gen_andi_i32(flag, flag, 1);
2438 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2439 break;
2440 case 7: /* or (=2) */
2441 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2442 break;
2443 case 8: /* un (<2) */
2444 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2445 break;
2446 case 9: /* ueq (=0 or =2) */
2447 tcg_gen_andi_i32(flag, flag, 1);
2448 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2449 break;
2450 case 10: /* ugt (>0) */
2451 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2452 break;
2453 case 11: /* uge (>=0) */
2454 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2455 break;
2456 case 12: /* ult (=-1 or =2) */
2457 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2458 break;
2459 case 13: /* ule (!=1) */
2460 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2461 break;
2462 case 14: /* ne (!=0) */
2463 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2464 break;
2465 case 15: /* t */
2466 tcg_gen_br(l1);
2467 break;
2468 }
2469 gen_jmp_tb(s, 0, s->pc);
2470 gen_set_label(l1);
2471 gen_jmp_tb(s, 1, addr + offset);
2472 }
2473
2474 DISAS_INSN(frestore)
2475 {
2476 M68kCPU *cpu = m68k_env_get_cpu(env);
2477
2478 /* TODO: Implement frestore. */
2479 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2480 }
2481
2482 DISAS_INSN(fsave)
2483 {
2484 M68kCPU *cpu = m68k_env_get_cpu(env);
2485
2486 /* TODO: Implement fsave. */
2487 cpu_abort(CPU(cpu), "FSAVE not implemented");
2488 }
2489
2490 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2491 {
2492 TCGv tmp = tcg_temp_new();
2493 if (s->env->macsr & MACSR_FI) {
2494 if (upper)
2495 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2496 else
2497 tcg_gen_shli_i32(tmp, val, 16);
2498 } else if (s->env->macsr & MACSR_SU) {
2499 if (upper)
2500 tcg_gen_sari_i32(tmp, val, 16);
2501 else
2502 tcg_gen_ext16s_i32(tmp, val);
2503 } else {
2504 if (upper)
2505 tcg_gen_shri_i32(tmp, val, 16);
2506 else
2507 tcg_gen_ext16u_i32(tmp, val);
2508 }
2509 return tmp;
2510 }
2511
2512 static void gen_mac_clear_flags(void)
2513 {
2514 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2515 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2516 }
2517
2518 DISAS_INSN(mac)
2519 {
2520 TCGv rx;
2521 TCGv ry;
2522 uint16_t ext;
2523 int acc;
2524 TCGv tmp;
2525 TCGv addr;
2526 TCGv loadval;
2527 int dual;
2528 TCGv saved_flags;
2529
2530 if (!s->done_mac) {
2531 s->mactmp = tcg_temp_new_i64();
2532 s->done_mac = 1;
2533 }
2534
2535 ext = read_im16(env, s);
2536
2537 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2538 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2539 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2540 disas_undef(env, s, insn);
2541 return;
2542 }
2543 if (insn & 0x30) {
2544 /* MAC with load. */
2545 tmp = gen_lea(env, s, insn, OS_LONG);
2546 addr = tcg_temp_new();
2547 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2548 /* Load the value now to ensure correct exception behavior.
2549 Perform writeback after reading the MAC inputs. */
2550 loadval = gen_load(s, OS_LONG, addr, 0);
2551
2552 acc ^= 1;
2553 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2554 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2555 } else {
2556 loadval = addr = NULL_QREG;
2557 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2558 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2559 }
2560
2561 gen_mac_clear_flags();
2562 #if 0
2563 l1 = -1;
2564 /* Disabled because conditional branches clobber temporary vars. */
2565 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2566 /* Skip the multiply if we know we will ignore it. */
2567 l1 = gen_new_label();
2568 tmp = tcg_temp_new();
2569 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2570 gen_op_jmp_nz32(tmp, l1);
2571 }
2572 #endif
2573
2574 if ((ext & 0x0800) == 0) {
2575 /* Word. */
2576 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2577 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2578 }
2579 if (s->env->macsr & MACSR_FI) {
2580 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2581 } else {
2582 if (s->env->macsr & MACSR_SU)
2583 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2584 else
2585 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2586 switch ((ext >> 9) & 3) {
2587 case 1:
2588 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2589 break;
2590 case 3:
2591 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2592 break;
2593 }
2594 }
2595
2596 if (dual) {
2597 /* Save the overflow flag from the multiply. */
2598 saved_flags = tcg_temp_new();
2599 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2600 } else {
2601 saved_flags = NULL_QREG;
2602 }
2603
2604 #if 0
2605 /* Disabled because conditional branches clobber temporary vars. */
2606 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2607 /* Skip the accumulate if the value is already saturated. */
2608 l1 = gen_new_label();
2609 tmp = tcg_temp_new();
2610 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2611 gen_op_jmp_nz32(tmp, l1);
2612 }
2613 #endif
2614
2615 if (insn & 0x100)
2616 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2617 else
2618 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2619
2620 if (s->env->macsr & MACSR_FI)
2621 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2622 else if (s->env->macsr & MACSR_SU)
2623 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2624 else
2625 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2626
2627 #if 0
2628 /* Disabled because conditional branches clobber temporary vars. */
2629 if (l1 != -1)
2630 gen_set_label(l1);
2631 #endif
2632
2633 if (dual) {
2634 /* Dual accumulate variant. */
2635 acc = (ext >> 2) & 3;
2636 /* Restore the overflow flag from the multiplier. */
2637 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2638 #if 0
2639 /* Disabled because conditional branches clobber temporary vars. */
2640 if ((s->env->macsr & MACSR_OMC) != 0) {
2641 /* Skip the accumulate if the value is already saturated. */
2642 l1 = gen_new_label();
2643 tmp = tcg_temp_new();
2644 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2645 gen_op_jmp_nz32(tmp, l1);
2646 }
2647 #endif
2648 if (ext & 2)
2649 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2650 else
2651 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2652 if (s->env->macsr & MACSR_FI)
2653 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2654 else if (s->env->macsr & MACSR_SU)
2655 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2656 else
2657 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2658 #if 0
2659 /* Disabled because conditional branches clobber temporary vars. */
2660 if (l1 != -1)
2661 gen_set_label(l1);
2662 #endif
2663 }
2664 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2665
2666 if (insn & 0x30) {
2667 TCGv rw;
2668 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2669 tcg_gen_mov_i32(rw, loadval);
2670 /* FIXME: Should address writeback happen with the masked or
2671 unmasked value? */
2672 switch ((insn >> 3) & 7) {
2673 case 3: /* Post-increment. */
2674 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2675 break;
2676 case 4: /* Pre-decrement. */
2677 tcg_gen_mov_i32(AREG(insn, 0), addr);
2678 }
2679 }
2680 }
2681
2682 DISAS_INSN(from_mac)
2683 {
2684 TCGv rx;
2685 TCGv_i64 acc;
2686 int accnum;
2687
2688 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2689 accnum = (insn >> 9) & 3;
2690 acc = MACREG(accnum);
2691 if (s->env->macsr & MACSR_FI) {
2692 gen_helper_get_macf(rx, cpu_env, acc);
2693 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2694 tcg_gen_extrl_i64_i32(rx, acc);
2695 } else if (s->env->macsr & MACSR_SU) {
2696 gen_helper_get_macs(rx, acc);
2697 } else {
2698 gen_helper_get_macu(rx, acc);
2699 }
2700 if (insn & 0x40) {
2701 tcg_gen_movi_i64(acc, 0);
2702 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2703 }
2704 }
2705
2706 DISAS_INSN(move_mac)
2707 {
2708 /* FIXME: This can be done without a helper. */
2709 int src;
2710 TCGv dest;
2711 src = insn & 3;
2712 dest = tcg_const_i32((insn >> 9) & 3);
2713 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2714 gen_mac_clear_flags();
2715 gen_helper_mac_set_flags(cpu_env, dest);
2716 }
2717
2718 DISAS_INSN(from_macsr)
2719 {
2720 TCGv reg;
2721
2722 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2723 tcg_gen_mov_i32(reg, QREG_MACSR);
2724 }
2725
2726 DISAS_INSN(from_mask)
2727 {
2728 TCGv reg;
2729 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2730 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2731 }
2732
2733 DISAS_INSN(from_mext)
2734 {
2735 TCGv reg;
2736 TCGv acc;
2737 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2738 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2739 if (s->env->macsr & MACSR_FI)
2740 gen_helper_get_mac_extf(reg, cpu_env, acc);
2741 else
2742 gen_helper_get_mac_exti(reg, cpu_env, acc);
2743 }
2744
2745 DISAS_INSN(macsr_to_ccr)
2746 {
2747 tcg_gen_movi_i32(QREG_CC_X, 0);
2748 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2749 s->cc_op = CC_OP_FLAGS;
2750 }
2751
2752 DISAS_INSN(to_mac)
2753 {
2754 TCGv_i64 acc;
2755 TCGv val;
2756 int accnum;
2757 accnum = (insn >> 9) & 3;
2758 acc = MACREG(accnum);
2759 SRC_EA(env, val, OS_LONG, 0, NULL);
2760 if (s->env->macsr & MACSR_FI) {
2761 tcg_gen_ext_i32_i64(acc, val);
2762 tcg_gen_shli_i64(acc, acc, 8);
2763 } else if (s->env->macsr & MACSR_SU) {
2764 tcg_gen_ext_i32_i64(acc, val);
2765 } else {
2766 tcg_gen_extu_i32_i64(acc, val);
2767 }
2768 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2769 gen_mac_clear_flags();
2770 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2771 }
2772
2773 DISAS_INSN(to_macsr)
2774 {
2775 TCGv val;
2776 SRC_EA(env, val, OS_LONG, 0, NULL);
2777 gen_helper_set_macsr(cpu_env, val);
2778 gen_lookup_tb(s);
2779 }
2780
2781 DISAS_INSN(to_mask)
2782 {
2783 TCGv val;
2784 SRC_EA(env, val, OS_LONG, 0, NULL);
2785 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2786 }
2787
2788 DISAS_INSN(to_mext)
2789 {
2790 TCGv val;
2791 TCGv acc;
2792 SRC_EA(env, val, OS_LONG, 0, NULL);
2793 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2794 if (s->env->macsr & MACSR_FI)
2795 gen_helper_set_mac_extf(cpu_env, val, acc);
2796 else if (s->env->macsr & MACSR_SU)
2797 gen_helper_set_mac_exts(cpu_env, val, acc);
2798 else
2799 gen_helper_set_mac_extu(cpu_env, val, acc);
2800 }
2801
2802 static disas_proc opcode_table[65536];
2803
2804 static void
2805 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2806 {
2807 int i;
2808 int from;
2809 int to;
2810
2811 /* Sanity check. All set bits must be included in the mask. */
2812 if (opcode & ~mask) {
2813 fprintf(stderr,
2814 "qemu internal error: bogus opcode definition %04x/%04x\n",
2815 opcode, mask);
2816 abort();
2817 }
2818 /* This could probably be cleverer. For now just optimize the case where
2819 the top bits are known. */
2820 /* Find the first zero bit in the mask. */
2821 i = 0x8000;
2822 while ((i & mask) != 0)
2823 i >>= 1;
2824 /* Iterate over all combinations of this and lower bits. */
2825 if (i == 0)
2826 i = 1;
2827 else
2828 i <<= 1;
2829 from = opcode & ~(i - 1);
2830 to = from + i;
2831 for (i = from; i < to; i++) {
2832 if ((i & mask) == opcode)
2833 opcode_table[i] = proc;
2834 }
2835 }
2836
2837 /* Register m68k opcode handlers. Order is important.
2838 Later insn override earlier ones. */
2839 void register_m68k_insns (CPUM68KState *env)
2840 {
2841 /* Build the opcode table only once to avoid
2842 multithreading issues. */
2843 if (opcode_table[0] != NULL) {
2844 return;
2845 }
2846
2847 /* use BASE() for instruction available
2848 * for CF_ISA_A and M68000.
2849 */
2850 #define BASE(name, opcode, mask) \
2851 register_opcode(disas_##name, 0x##opcode, 0x##mask)
2852 #define INSN(name, opcode, mask, feature) do { \
2853 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2854 BASE(name, opcode, mask); \
2855 } while(0)
2856 BASE(undef, 0000, 0000);
2857 INSN(arith_im, 0080, fff8, CF_ISA_A);
2858 INSN(arith_im, 0000, ff00, M68000);
2859 INSN(undef, 00c0, ffc0, M68000);
2860 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2861 BASE(bitop_reg, 0100, f1c0);
2862 BASE(bitop_reg, 0140, f1c0);
2863 BASE(bitop_reg, 0180, f1c0);
2864 BASE(bitop_reg, 01c0, f1c0);
2865 INSN(arith_im, 0280, fff8, CF_ISA_A);
2866 INSN(arith_im, 0200, ff00, M68000);
2867 INSN(undef, 02c0, ffc0, M68000);
2868 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2869 INSN(arith_im, 0480, fff8, CF_ISA_A);
2870 INSN(arith_im, 0400, ff00, M68000);
2871 INSN(undef, 04c0, ffc0, M68000);
2872 INSN(arith_im, 0600, ff00, M68000);
2873 INSN(undef, 06c0, ffc0, M68000);
2874 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2875 INSN(arith_im, 0680, fff8, CF_ISA_A);
2876 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2877 INSN(arith_im, 0c00, ff00, M68000);
2878 BASE(bitop_im, 0800, ffc0);
2879 BASE(bitop_im, 0840, ffc0);
2880 BASE(bitop_im, 0880, ffc0);
2881 BASE(bitop_im, 08c0, ffc0);
2882 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2883 INSN(arith_im, 0a00, ff00, M68000);
2884 BASE(move, 1000, f000);
2885 BASE(move, 2000, f000);
2886 BASE(move, 3000, f000);
2887 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2888 INSN(negx, 4080, fff8, CF_ISA_A);
2889 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2890 INSN(move_from_sr, 40c0, ffc0, M68000);
2891 BASE(lea, 41c0, f1c0);
2892 BASE(clr, 4200, ff00);
2893 BASE(undef, 42c0, ffc0);
2894 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2895 INSN(neg, 4480, fff8, CF_ISA_A);
2896 INSN(neg, 4400, ff00, M68000);
2897 INSN(undef, 44c0, ffc0, M68000);
2898 BASE(move_to_ccr, 44c0, ffc0);
2899 INSN(not, 4680, fff8, CF_ISA_A);
2900 INSN(not, 4600, ff00, M68000);
2901 INSN(undef, 46c0, ffc0, M68000);
2902 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2903 BASE(pea, 4840, ffc0);
2904 BASE(swap, 4840, fff8);
2905 BASE(movem, 48c0, fbc0);
2906 BASE(ext, 4880, fff8);
2907 BASE(ext, 48c0, fff8);
2908 BASE(ext, 49c0, fff8);
2909 BASE(tst, 4a00, ff00);
2910 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2911 INSN(tas, 4ac0, ffc0, M68000);
2912 INSN(halt, 4ac8, ffff, CF_ISA_A);
2913 INSN(pulse, 4acc, ffff, CF_ISA_A);
2914 BASE(illegal, 4afc, ffff);
2915 INSN(mull, 4c00, ffc0, CF_ISA_A);
2916 INSN(mull, 4c00, ffc0, LONG_MULDIV);
2917 INSN(divl, 4c40, ffc0, CF_ISA_A);
2918 INSN(divl, 4c40, ffc0, LONG_MULDIV);
2919 INSN(sats, 4c80, fff8, CF_ISA_B);
2920 BASE(trap, 4e40, fff0);
2921 BASE(link, 4e50, fff8);
2922 BASE(unlk, 4e58, fff8);
2923 INSN(move_to_usp, 4e60, fff8, USP);
2924 INSN(move_from_usp, 4e68, fff8, USP);
2925 BASE(nop, 4e71, ffff);
2926 BASE(stop, 4e72, ffff);
2927 BASE(rte, 4e73, ffff);
2928 BASE(rts, 4e75, ffff);
2929 INSN(movec, 4e7b, ffff, CF_ISA_A);
2930 BASE(jump, 4e80, ffc0);
2931 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2932 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2933 INSN(jump, 4ec0, ffc0, M68000);
2934 INSN(addsubq, 5000, f080, M68000);
2935 INSN(addsubq, 5080, f0c0, M68000);
2936 INSN(scc, 50c0, f0f8, CF_ISA_A);
2937 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2938 INSN(tpf, 51f8, fff8, CF_ISA_A);
2939
2940 /* Branch instructions. */
2941 BASE(branch, 6000, f000);
2942 /* Disable long branch instructions, then add back the ones we want. */
2943 BASE(undef, 60ff, f0ff); /* All long branches. */
2944 INSN(branch, 60ff, f0ff, CF_ISA_B);
2945 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2946 INSN(branch, 60ff, ffff, BRAL);
2947 INSN(branch, 60ff, f0ff, BCCL);
2948
2949 BASE(moveq, 7000, f100);
2950 INSN(mvzs, 7100, f100, CF_ISA_B);
2951 BASE(or, 8000, f000);
2952 BASE(divw, 80c0, f0c0);
2953 BASE(addsub, 9000, f000);
2954 INSN(subx, 9180, f1f8, CF_ISA_A);
2955 INSN(suba, 91c0, f1c0, CF_ISA_A);
2956
2957 BASE(undef_mac, a000, f000);
2958 INSN(mac, a000, f100, CF_EMAC);
2959 INSN(from_mac, a180, f9b0, CF_EMAC);
2960 INSN(move_mac, a110, f9fc, CF_EMAC);
2961 INSN(from_macsr,a980, f9f0, CF_EMAC);
2962 INSN(from_mask, ad80, fff0, CF_EMAC);
2963 INSN(from_mext, ab80, fbf0, CF_EMAC);
2964 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2965 INSN(to_mac, a100, f9c0, CF_EMAC);
2966 INSN(to_macsr, a900, ffc0, CF_EMAC);
2967 INSN(to_mext, ab00, fbc0, CF_EMAC);
2968 INSN(to_mask, ad00, ffc0, CF_EMAC);
2969
2970 INSN(mov3q, a140, f1c0, CF_ISA_B);
2971 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2972 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2973 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2974 INSN(cmp, b080, f1c0, CF_ISA_A);
2975 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2976 INSN(cmp, b000, f100, M68000);
2977 INSN(eor, b100, f100, M68000);
2978 INSN(cmpa, b0c0, f0c0, M68000);
2979 INSN(eor, b180, f1c0, CF_ISA_A);
2980 BASE(and, c000, f000);
2981 BASE(mulw, c0c0, f0c0);
2982 BASE(addsub, d000, f000);
2983 INSN(addx, d180, f1f8, CF_ISA_A);
2984 INSN(adda, d1c0, f1c0, CF_ISA_A);
2985 INSN(adda, d0c0, f0c0, M68000);
2986 INSN(shift_im, e080, f0f0, CF_ISA_A);
2987 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2988 INSN(undef_fpu, f000, f000, CF_ISA_A);
2989 INSN(fpu, f200, ffc0, CF_FPU);
2990 INSN(fbcc, f280, ffc0, CF_FPU);
2991 INSN(frestore, f340, ffc0, CF_FPU);
2992 INSN(fsave, f340, ffc0, CF_FPU);
2993 INSN(intouch, f340, ffc0, CF_ISA_A);
2994 INSN(cpushl, f428, ff38, CF_ISA_A);
2995 INSN(wddata, fb00, ff00, CF_ISA_A);
2996 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2997 #undef INSN
2998 }
2999
3000 /* ??? Some of this implementation is not exception safe. We should always
3001 write back the result to memory before setting the condition codes. */
3002 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
3003 {
3004 uint16_t insn;
3005
3006 insn = read_im16(env, s);
3007
3008 opcode_table[insn](env, s, insn);
3009 }
3010
3011 /* generate intermediate code for basic block 'tb'. */
3012 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
3013 {
3014 M68kCPU *cpu = m68k_env_get_cpu(env);
3015 CPUState *cs = CPU(cpu);
3016 DisasContext dc1, *dc = &dc1;
3017 target_ulong pc_start;
3018 int pc_offset;
3019 int num_insns;
3020 int max_insns;
3021
3022 /* generate intermediate code */
3023 pc_start = tb->pc;
3024
3025 dc->tb = tb;
3026
3027 dc->env = env;
3028 dc->is_jmp = DISAS_NEXT;
3029 dc->pc = pc_start;
3030 dc->cc_op = CC_OP_DYNAMIC;
3031 dc->singlestep_enabled = cs->singlestep_enabled;
3032 dc->fpcr = env->fpcr;
3033 dc->user = (env->sr & SR_S) == 0;
3034 dc->done_mac = 0;
3035 num_insns = 0;
3036 max_insns = tb->cflags & CF_COUNT_MASK;
3037 if (max_insns == 0) {
3038 max_insns = CF_COUNT_MASK;
3039 }
3040 if (max_insns > TCG_MAX_INSNS) {
3041 max_insns = TCG_MAX_INSNS;
3042 }
3043
3044 gen_tb_start(tb);
3045 do {
3046 pc_offset = dc->pc - pc_start;
3047 gen_throws_exception = NULL;
3048 tcg_gen_insn_start(dc->pc);
3049 num_insns++;
3050
3051 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3052 gen_exception(dc, dc->pc, EXCP_DEBUG);
3053 dc->is_jmp = DISAS_JUMP;
3054 /* The address covered by the breakpoint must be included in
3055 [tb->pc, tb->pc + tb->size) in order to for it to be
3056 properly cleared -- thus we increment the PC here so that
3057 the logic setting tb->size below does the right thing. */
3058 dc->pc += 2;
3059 break;
3060 }
3061
3062 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3063 gen_io_start();
3064 }
3065
3066 dc->insn_pc = dc->pc;
3067 disas_m68k_insn(env, dc);
3068 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3069 !cs->singlestep_enabled &&
3070 !singlestep &&
3071 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3072 num_insns < max_insns);
3073
3074 if (tb->cflags & CF_LAST_IO)
3075 gen_io_end();
3076 if (unlikely(cs->singlestep_enabled)) {
3077 /* Make sure the pc is updated, and raise a debug exception. */
3078 if (!dc->is_jmp) {
3079 gen_flush_cc_op(dc);
3080 tcg_gen_movi_i32(QREG_PC, dc->pc);
3081 }
3082 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3083 } else {
3084 switch(dc->is_jmp) {
3085 case DISAS_NEXT:
3086 gen_flush_cc_op(dc);
3087 gen_jmp_tb(dc, 0, dc->pc);
3088 break;
3089 default:
3090 case DISAS_JUMP:
3091 case DISAS_UPDATE:
3092 gen_flush_cc_op(dc);
3093 /* indicate that the hash table must be used to find the next TB */
3094 tcg_gen_exit_tb(0);
3095 break;
3096 case DISAS_TB_JUMP:
3097 /* nothing more to generate */
3098 break;
3099 }
3100 }
3101 gen_tb_end(tb, num_insns);
3102
3103 #ifdef DEBUG_DISAS
3104 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3105 && qemu_log_in_addr_range(pc_start)) {
3106 qemu_log("----------------\n");
3107 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3108 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3109 qemu_log("\n");
3110 }
3111 #endif
3112 tb->size = dc->pc - pc_start;
3113 tb->icount = num_insns;
3114 }
3115
3116 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3117 int flags)
3118 {
3119 M68kCPU *cpu = M68K_CPU(cs);
3120 CPUM68KState *env = &cpu->env;
3121 int i;
3122 uint16_t sr;
3123 CPU_DoubleU u;
3124 for (i = 0; i < 8; i++)
3125 {
3126 u.d = env->fregs[i];
3127 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3128 i, env->dregs[i], i, env->aregs[i],
3129 i, u.l.upper, u.l.lower, *(double *)&u.d);
3130 }
3131 cpu_fprintf (f, "PC = %08x ", env->pc);
3132 sr = env->sr;
3133 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3134 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3135 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3136 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3137 }
3138
3139 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3140 target_ulong *data)
3141 {
3142 env->pc = data[0];
3143 }
AR7 emulation for QEMU