4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "cpu_loop-common.h"
25 /***********************************************************/
26 /* CPUX86 core interface */
28 uint64_t cpu_get_tsc(CPUX86State
*env
)
30 return cpu_get_host_ticks();
33 static void write_dt(void *ptr
, unsigned long addr
, unsigned long limit
,
38 e1
= (addr
<< 16) | (limit
& 0xffff);
39 e2
= ((addr
>> 16) & 0xff) | (addr
& 0xff000000) | (limit
& 0x000f0000);
46 static uint64_t *idt_table
;
48 static void set_gate64(void *ptr
, unsigned int type
, unsigned int dpl
,
49 uint64_t addr
, unsigned int sel
)
52 e1
= (addr
& 0xffff) | (sel
<< 16);
53 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
57 p
[2] = tswap32(addr
>> 32);
60 /* only dpl matters as we do only user space emulation */
61 static void set_idt(int n
, unsigned int dpl
)
63 set_gate64(idt_table
+ n
* 2, 0, dpl
, 0, 0);
66 static void set_gate(void *ptr
, unsigned int type
, unsigned int dpl
,
67 uint32_t addr
, unsigned int sel
)
70 e1
= (addr
& 0xffff) | (sel
<< 16);
71 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
77 /* only dpl matters as we do only user space emulation */
78 static void set_idt(int n
, unsigned int dpl
)
80 set_gate(idt_table
+ n
, 0, dpl
, 0, 0);
84 void cpu_loop(CPUX86State
*env
)
86 CPUState
*cs
= env_cpu(env
);
90 target_siginfo_t info
;
94 trapnr
= cpu_exec(cs
);
96 process_queued_cpu_work(cs
);
100 /* linux syscall from int $0x80 */
101 ret
= do_syscall(env
,
110 if (ret
== -TARGET_ERESTARTSYS
) {
112 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
113 env
->regs
[R_EAX
] = ret
;
118 /* linux syscall from syscall instruction */
119 ret
= do_syscall(env
,
128 if (ret
== -TARGET_ERESTARTSYS
) {
130 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
131 env
->regs
[R_EAX
] = ret
;
137 info
.si_signo
= TARGET_SIGBUS
;
139 info
.si_code
= TARGET_SI_KERNEL
;
140 info
._sifields
._sigfault
._addr
= 0;
141 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
144 /* XXX: potential problem if ABI32 */
145 #ifndef TARGET_X86_64
146 if (env
->eflags
& VM_MASK
) {
147 handle_vm86_fault(env
);
151 info
.si_signo
= TARGET_SIGSEGV
;
153 info
.si_code
= TARGET_SI_KERNEL
;
154 info
._sifields
._sigfault
._addr
= 0;
155 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
159 info
.si_signo
= TARGET_SIGSEGV
;
161 if (!(env
->error_code
& 1))
162 info
.si_code
= TARGET_SEGV_MAPERR
;
164 info
.si_code
= TARGET_SEGV_ACCERR
;
165 info
._sifields
._sigfault
._addr
= env
->cr
[2];
166 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
169 #ifndef TARGET_X86_64
170 if (env
->eflags
& VM_MASK
) {
171 handle_vm86_trap(env
, trapnr
);
175 /* division by zero */
176 info
.si_signo
= TARGET_SIGFPE
;
178 info
.si_code
= TARGET_FPE_INTDIV
;
179 info
._sifields
._sigfault
._addr
= env
->eip
;
180 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
185 #ifndef TARGET_X86_64
186 if (env
->eflags
& VM_MASK
) {
187 handle_vm86_trap(env
, trapnr
);
191 info
.si_signo
= TARGET_SIGTRAP
;
193 if (trapnr
== EXCP01_DB
) {
194 info
.si_code
= TARGET_TRAP_BRKPT
;
195 info
._sifields
._sigfault
._addr
= env
->eip
;
197 info
.si_code
= TARGET_SI_KERNEL
;
198 info
._sifields
._sigfault
._addr
= 0;
200 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
205 #ifndef TARGET_X86_64
206 if (env
->eflags
& VM_MASK
) {
207 handle_vm86_trap(env
, trapnr
);
211 info
.si_signo
= TARGET_SIGSEGV
;
213 info
.si_code
= TARGET_SI_KERNEL
;
214 info
._sifields
._sigfault
._addr
= 0;
215 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
219 info
.si_signo
= TARGET_SIGILL
;
221 info
.si_code
= TARGET_ILL_ILLOPN
;
222 info
._sifields
._sigfault
._addr
= env
->eip
;
223 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
226 /* just indicate that signals should be handled asap */
229 info
.si_signo
= TARGET_SIGTRAP
;
231 info
.si_code
= TARGET_TRAP_BRKPT
;
232 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
235 cpu_exec_step_atomic(cs
);
238 pc
= env
->segs
[R_CS
].base
+ env
->eip
;
239 EXCP_DUMP(env
, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
243 process_pending_signals(env
);
247 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
249 env
->cr
[0] = CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
;
250 env
->hflags
|= HF_PE_MASK
| HF_CPL_MASK
;
251 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
252 env
->cr
[4] |= CR4_OSFXSR_MASK
;
253 env
->hflags
|= HF_OSFXSR_MASK
;
256 /* enable 64 bit mode if possible */
257 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
)) {
258 fprintf(stderr
, "The selected x86 CPU does not support 64 bit mode\n");
261 env
->cr
[4] |= CR4_PAE_MASK
;
262 env
->efer
|= MSR_EFER_LMA
| MSR_EFER_LME
;
263 env
->hflags
|= HF_LMA_MASK
;
266 /* flags setup : we activate the IRQs by default as in user mode */
267 env
->eflags
|= IF_MASK
;
269 /* linux register setup */
271 env
->regs
[R_EAX
] = regs
->rax
;
272 env
->regs
[R_EBX
] = regs
->rbx
;
273 env
->regs
[R_ECX
] = regs
->rcx
;
274 env
->regs
[R_EDX
] = regs
->rdx
;
275 env
->regs
[R_ESI
] = regs
->rsi
;
276 env
->regs
[R_EDI
] = regs
->rdi
;
277 env
->regs
[R_EBP
] = regs
->rbp
;
278 env
->regs
[R_ESP
] = regs
->rsp
;
279 env
->eip
= regs
->rip
;
281 env
->regs
[R_EAX
] = regs
->eax
;
282 env
->regs
[R_EBX
] = regs
->ebx
;
283 env
->regs
[R_ECX
] = regs
->ecx
;
284 env
->regs
[R_EDX
] = regs
->edx
;
285 env
->regs
[R_ESI
] = regs
->esi
;
286 env
->regs
[R_EDI
] = regs
->edi
;
287 env
->regs
[R_EBP
] = regs
->ebp
;
288 env
->regs
[R_ESP
] = regs
->esp
;
289 env
->eip
= regs
->eip
;
292 /* linux interrupt setup */
294 env
->idt
.limit
= 511;
296 env
->idt
.limit
= 255;
298 env
->idt
.base
= target_mmap(0, sizeof(uint64_t) * (env
->idt
.limit
+ 1),
299 PROT_READ
|PROT_WRITE
,
300 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
301 idt_table
= g2h(env
->idt
.base
);
324 /* linux segment setup */
327 env
->gdt
.base
= target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES
,
328 PROT_READ
|PROT_WRITE
,
329 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
330 env
->gdt
.limit
= sizeof(uint64_t) * TARGET_GDT_ENTRIES
- 1;
331 gdt_table
= g2h(env
->gdt
.base
);
333 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
334 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
335 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
337 /* 64 bit code segment */
338 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
339 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
341 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
343 write_dt(&gdt_table
[__USER_DS
>> 3], 0, 0xfffff,
344 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
345 (3 << DESC_DPL_SHIFT
) | (0x2 << DESC_TYPE_SHIFT
));
347 cpu_x86_load_seg(env
, R_CS
, __USER_CS
);
348 cpu_x86_load_seg(env
, R_SS
, __USER_DS
);
350 cpu_x86_load_seg(env
, R_DS
, __USER_DS
);
351 cpu_x86_load_seg(env
, R_ES
, __USER_DS
);
352 cpu_x86_load_seg(env
, R_FS
, __USER_DS
);
353 cpu_x86_load_seg(env
, R_GS
, __USER_DS
);
354 /* This hack makes Wine work... */
355 env
->segs
[R_FS
].selector
= 0;
357 cpu_x86_load_seg(env
, R_DS
, 0);
358 cpu_x86_load_seg(env
, R_ES
, 0);
359 cpu_x86_load_seg(env
, R_FS
, 0);
360 cpu_x86_load_seg(env
, R_GS
, 0);