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acpi: make bios_linker_loader_add_checksum() API offset based
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob06d6204749432a43904cd8b6824b4c9b1d90d602
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include <glib.h>
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 */
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
71
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #else
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
78 #endif
79
80 typedef struct AcpiMcfgInfo {
81 uint64_t mcfg_base;
82 uint32_t mcfg_size;
83 } AcpiMcfgInfo;
84
85 typedef struct AcpiPmInfo {
86 bool s3_disabled;
87 bool s4_disabled;
88 bool pcihp_bridge_en;
89 uint8_t s4_val;
90 uint16_t sci_int;
91 uint8_t acpi_enable_cmd;
92 uint8_t acpi_disable_cmd;
93 uint32_t gpe0_blk;
94 uint32_t gpe0_blk_len;
95 uint32_t io_base;
96 uint16_t cpu_hp_io_base;
97 uint16_t mem_hp_io_base;
98 uint16_t mem_hp_io_len;
99 uint16_t pcihp_io_base;
100 uint16_t pcihp_io_len;
101 } AcpiPmInfo;
102
103 typedef struct AcpiMiscInfo {
104 bool is_piix4;
105 bool has_hpet;
106 TPMVersion tpm_version;
107 const unsigned char *dsdt_code;
108 unsigned dsdt_size;
109 uint16_t pvpanic_port;
110 uint16_t applesmc_io_base;
111 } AcpiMiscInfo;
112
113 typedef struct AcpiBuildPciBusHotplugState {
114 GArray *device_table;
115 GArray *notify_table;
116 struct AcpiBuildPciBusHotplugState *parent;
117 bool pcihp_bridge_en;
118 } AcpiBuildPciBusHotplugState;
119
120 static void acpi_get_pm_info(AcpiPmInfo *pm)
121 {
122 Object *piix = piix4_pm_find();
123 Object *lpc = ich9_lpc_find();
124 Object *obj = NULL;
125 QObject *o;
126
127 pm->cpu_hp_io_base = 0;
128 pm->pcihp_io_base = 0;
129 pm->pcihp_io_len = 0;
130 if (piix) {
131 obj = piix;
132 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
133 pm->pcihp_io_base =
134 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
135 pm->pcihp_io_len =
136 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
137 }
138 if (lpc) {
139 obj = lpc;
140 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
141 }
142 assert(obj);
143
144 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
145 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
146
147 /* Fill in optional s3/s4 related properties */
148 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
149 if (o) {
150 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
151 } else {
152 pm->s3_disabled = false;
153 }
154 qobject_decref(o);
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
156 if (o) {
157 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
158 } else {
159 pm->s4_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
163 if (o) {
164 pm->s4_val = qint_get_int(qobject_to_qint(o));
165 } else {
166 pm->s4_val = false;
167 }
168 qobject_decref(o);
169
170 /* Fill in mandatory properties */
171 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
172
173 pm->acpi_enable_cmd = object_property_get_int(obj,
174 ACPI_PM_PROP_ACPI_ENABLE_CMD,
175 NULL);
176 pm->acpi_disable_cmd = object_property_get_int(obj,
177 ACPI_PM_PROP_ACPI_DISABLE_CMD,
178 NULL);
179 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
180 NULL);
181 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
182 NULL);
183 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
184 NULL);
185 pm->pcihp_bridge_en =
186 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
187 NULL);
188 }
189
190 static void acpi_get_misc_info(AcpiMiscInfo *info)
191 {
192 Object *piix = piix4_pm_find();
193 Object *lpc = ich9_lpc_find();
194 assert(!!piix != !!lpc);
195
196 if (piix) {
197 info->is_piix4 = true;
198 }
199 if (lpc) {
200 info->is_piix4 = false;
201 }
202
203 info->has_hpet = hpet_find();
204 info->tpm_version = tpm_get_version();
205 info->pvpanic_port = pvpanic_port();
206 info->applesmc_io_base = applesmc_port();
207 }
208
209 /*
210 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
211 * On i386 arch we only have two pci hosts, so we can look only for them.
212 */
213 static Object *acpi_get_i386_pci_host(void)
214 {
215 PCIHostState *host;
216
217 host = OBJECT_CHECK(PCIHostState,
218 object_resolve_path("/machine/i440fx", NULL),
219 TYPE_PCI_HOST_BRIDGE);
220 if (!host) {
221 host = OBJECT_CHECK(PCIHostState,
222 object_resolve_path("/machine/q35", NULL),
223 TYPE_PCI_HOST_BRIDGE);
224 }
225
226 return OBJECT(host);
227 }
228
229 static void acpi_get_pci_info(PcPciInfo *info)
230 {
231 Object *pci_host;
232
233
234 pci_host = acpi_get_i386_pci_host();
235 g_assert(pci_host);
236
237 info->w32.begin = object_property_get_int(pci_host,
238 PCI_HOST_PROP_PCI_HOLE_START,
239 NULL);
240 info->w32.end = object_property_get_int(pci_host,
241 PCI_HOST_PROP_PCI_HOLE_END,
242 NULL);
243 info->w64.begin = object_property_get_int(pci_host,
244 PCI_HOST_PROP_PCI_HOLE64_START,
245 NULL);
246 info->w64.end = object_property_get_int(pci_host,
247 PCI_HOST_PROP_PCI_HOLE64_END,
248 NULL);
249 }
250
251 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
252
253 static void acpi_align_size(GArray *blob, unsigned align)
254 {
255 /* Align size to multiple of given size. This reduces the chance
256 * we need to change size in the future (breaking cross version migration).
257 */
258 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
259 }
260
261 /* FACS */
262 static void
263 build_facs(GArray *table_data, BIOSLinker *linker)
264 {
265 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
266 memcpy(&facs->signature, "FACS", 4);
267 facs->length = cpu_to_le32(sizeof(*facs));
268 }
269
270 /* Load chipset information in FADT */
271 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
272 {
273 fadt->model = 1;
274 fadt->reserved1 = 0;
275 fadt->sci_int = cpu_to_le16(pm->sci_int);
276 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
277 fadt->acpi_enable = pm->acpi_enable_cmd;
278 fadt->acpi_disable = pm->acpi_disable_cmd;
279 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
280 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
281 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
282 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
283 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
284 /* EVT, CNT, TMR length matches hw/acpi/core.c */
285 fadt->pm1_evt_len = 4;
286 fadt->pm1_cnt_len = 2;
287 fadt->pm_tmr_len = 4;
288 fadt->gpe0_blk_len = pm->gpe0_blk_len;
289 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
290 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
291 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
292 (1 << ACPI_FADT_F_PROC_C1) |
293 (1 << ACPI_FADT_F_SLP_BUTTON) |
294 (1 << ACPI_FADT_F_RTC_S4));
295 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
296 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
297 * For more than 8 CPUs, "Clustered Logical" mode has to be used
298 */
299 if (max_cpus > 8) {
300 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
301 }
302 fadt->century = RTC_CENTURY;
303 }
304
305
306 /* FADT */
307 static void
308 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
309 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
310 const char *oem_id, const char *oem_table_id)
311 {
312 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
313 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
314 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
315
316 /* FACS address to be filled by Guest linker */
317 bios_linker_loader_add_pointer(linker,
318 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
319 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
320
321 /* DSDT address to be filled by Guest linker */
322 fadt_setup(fadt, pm);
323 bios_linker_loader_add_pointer(linker,
324 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
325 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
326
327 build_header(linker, table_data,
328 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
329 }
330
331 static void
332 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
333 {
334 MachineClass *mc = MACHINE_GET_CLASS(pcms);
335 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
336 int madt_start = table_data->len;
337
338 AcpiMultipleApicTable *madt;
339 AcpiMadtIoApic *io_apic;
340 AcpiMadtIntsrcovr *intsrcovr;
341 AcpiMadtLocalNmi *local_nmi;
342 int i;
343
344 madt = acpi_data_push(table_data, sizeof *madt);
345 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
346 madt->flags = cpu_to_le32(1);
347
348 for (i = 0; i < apic_ids->len; i++) {
349 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
350 int apic_id = apic_ids->cpus[i].arch_id;
351
352 apic->type = ACPI_APIC_PROCESSOR;
353 apic->length = sizeof(*apic);
354 apic->processor_id = i;
355 apic->local_apic_id = apic_id;
356 if (apic_ids->cpus[i].cpu != NULL) {
357 apic->flags = cpu_to_le32(1);
358 } else {
359 /* ACPI spec says that LAPIC entry for non present
360 * CPU may be omitted from MADT or it must be marked
361 * as disabled. However omitting non present CPU from
362 * MADT breaks hotplug on linux. So possible CPUs
363 * should be put in MADT but kept disabled.
364 */
365 apic->flags = cpu_to_le32(0);
366 }
367 }
368 g_free(apic_ids);
369
370 io_apic = acpi_data_push(table_data, sizeof *io_apic);
371 io_apic->type = ACPI_APIC_IO;
372 io_apic->length = sizeof(*io_apic);
373 #define ACPI_BUILD_IOAPIC_ID 0x0
374 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
375 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
376 io_apic->interrupt = cpu_to_le32(0);
377
378 if (pcms->apic_xrupt_override) {
379 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
380 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
381 intsrcovr->length = sizeof(*intsrcovr);
382 intsrcovr->source = 0;
383 intsrcovr->gsi = cpu_to_le32(2);
384 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
385 }
386 for (i = 1; i < 16; i++) {
387 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
388 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
389 /* No need for a INT source override structure. */
390 continue;
391 }
392 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
393 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
394 intsrcovr->length = sizeof(*intsrcovr);
395 intsrcovr->source = i;
396 intsrcovr->gsi = cpu_to_le32(i);
397 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
398 }
399
400 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
401 local_nmi->type = ACPI_APIC_LOCAL_NMI;
402 local_nmi->length = sizeof(*local_nmi);
403 local_nmi->processor_id = 0xff; /* all processors */
404 local_nmi->flags = cpu_to_le16(0);
405 local_nmi->lint = 1; /* ACPI_LINT1 */
406
407 build_header(linker, table_data,
408 (void *)(table_data->data + madt_start), "APIC",
409 table_data->len - madt_start, 1, NULL, NULL);
410 }
411
412 /* Assign BSEL property to all buses. In the future, this can be changed
413 * to only assign to buses that support hotplug.
414 */
415 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
416 {
417 unsigned *bsel_alloc = opaque;
418 unsigned *bus_bsel;
419
420 if (qbus_is_hotpluggable(BUS(bus))) {
421 bus_bsel = g_malloc(sizeof *bus_bsel);
422
423 *bus_bsel = (*bsel_alloc)++;
424 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
425 bus_bsel, NULL);
426 }
427
428 return bsel_alloc;
429 }
430
431 static void acpi_set_pci_info(void)
432 {
433 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
434 unsigned bsel_alloc = 0;
435
436 if (bus) {
437 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
438 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
439 }
440 }
441
442 static void build_append_pcihp_notify_entry(Aml *method, int slot)
443 {
444 Aml *if_ctx;
445 int32_t devfn = PCI_DEVFN(slot, 0);
446
447 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
448 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
449 aml_append(method, if_ctx);
450 }
451
452 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
453 bool pcihp_bridge_en)
454 {
455 Aml *dev, *notify_method, *method;
456 QObject *bsel;
457 PCIBus *sec;
458 int i;
459
460 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
461 if (bsel) {
462 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
463
464 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
465 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
466 }
467
468 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
469 DeviceClass *dc;
470 PCIDeviceClass *pc;
471 PCIDevice *pdev = bus->devices[i];
472 int slot = PCI_SLOT(i);
473 bool hotplug_enabled_dev;
474 bool bridge_in_acpi;
475
476 if (!pdev) {
477 if (bsel) { /* add hotplug slots for non present devices */
478 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
479 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
480 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
481 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
482 aml_append(method,
483 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
484 );
485 aml_append(dev, method);
486 aml_append(parent_scope, dev);
487
488 build_append_pcihp_notify_entry(notify_method, slot);
489 }
490 continue;
491 }
492
493 pc = PCI_DEVICE_GET_CLASS(pdev);
494 dc = DEVICE_GET_CLASS(pdev);
495
496 /* When hotplug for bridges is enabled, bridges are
497 * described in ACPI separately (see build_pci_bus_end).
498 * In this case they aren't themselves hot-pluggable.
499 * Hotplugged bridges *are* hot-pluggable.
500 */
501 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
502 !DEVICE(pdev)->hotplugged;
503
504 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
505
506 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
507 continue;
508 }
509
510 /* start to compose PCI slot descriptor */
511 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
512 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
513
514 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
515 /* add VGA specific AML methods */
516 int s3d;
517
518 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
519 s3d = 3;
520 } else {
521 s3d = 0;
522 }
523
524 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
525 aml_append(method, aml_return(aml_int(0)));
526 aml_append(dev, method);
527
528 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
529 aml_append(method, aml_return(aml_int(0)));
530 aml_append(dev, method);
531
532 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
533 aml_append(method, aml_return(aml_int(s3d)));
534 aml_append(dev, method);
535 } else if (hotplug_enabled_dev) {
536 /* add _SUN/_EJ0 to make slot hotpluggable */
537 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
538
539 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
540 aml_append(method,
541 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
542 );
543 aml_append(dev, method);
544
545 if (bsel) {
546 build_append_pcihp_notify_entry(notify_method, slot);
547 }
548 } else if (bridge_in_acpi) {
549 /*
550 * device is coldplugged bridge,
551 * add child device descriptions into its scope
552 */
553 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
554
555 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
556 }
557 /* slot descriptor has been composed, add it into parent context */
558 aml_append(parent_scope, dev);
559 }
560
561 if (bsel) {
562 aml_append(parent_scope, notify_method);
563 }
564
565 /* Append PCNT method to notify about events on local and child buses.
566 * Add unconditionally for root since DSDT expects it.
567 */
568 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
569
570 /* If bus supports hotplug select it and notify about local events */
571 if (bsel) {
572 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
573 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
574 aml_append(method,
575 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
576 );
577 aml_append(method,
578 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
579 );
580 }
581
582 /* Notify about child bus events in any case */
583 if (pcihp_bridge_en) {
584 QLIST_FOREACH(sec, &bus->child, sibling) {
585 int32_t devfn = sec->parent_dev->devfn;
586
587 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
588 }
589 }
590 aml_append(parent_scope, method);
591 qobject_decref(bsel);
592 }
593
594 /**
595 * build_prt_entry:
596 * @link_name: link name for PCI route entry
597 *
598 * build AML package containing a PCI route entry for @link_name
599 */
600 static Aml *build_prt_entry(const char *link_name)
601 {
602 Aml *a_zero = aml_int(0);
603 Aml *pkg = aml_package(4);
604 aml_append(pkg, a_zero);
605 aml_append(pkg, a_zero);
606 aml_append(pkg, aml_name("%s", link_name));
607 aml_append(pkg, a_zero);
608 return pkg;
609 }
610
611 /*
612 * initialize_route - Initialize the interrupt routing rule
613 * through a specific LINK:
614 * if (lnk_idx == idx)
615 * route using link 'link_name'
616 */
617 static Aml *initialize_route(Aml *route, const char *link_name,
618 Aml *lnk_idx, int idx)
619 {
620 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
621 Aml *pkg = build_prt_entry(link_name);
622
623 aml_append(if_ctx, aml_store(pkg, route));
624
625 return if_ctx;
626 }
627
628 /*
629 * build_prt - Define interrupt rounting rules
630 *
631 * Returns an array of 128 routes, one for each device,
632 * based on device location.
633 * The main goal is to equaly distribute the interrupts
634 * over the 4 existing ACPI links (works only for i440fx).
635 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
636 *
637 */
638 static Aml *build_prt(bool is_pci0_prt)
639 {
640 Aml *method, *while_ctx, *pin, *res;
641
642 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
643 res = aml_local(0);
644 pin = aml_local(1);
645 aml_append(method, aml_store(aml_package(128), res));
646 aml_append(method, aml_store(aml_int(0), pin));
647
648 /* while (pin < 128) */
649 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
650 {
651 Aml *slot = aml_local(2);
652 Aml *lnk_idx = aml_local(3);
653 Aml *route = aml_local(4);
654
655 /* slot = pin >> 2 */
656 aml_append(while_ctx,
657 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
658 /* lnk_idx = (slot + pin) & 3 */
659 aml_append(while_ctx,
660 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
661 lnk_idx));
662
663 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
664 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
665 if (is_pci0_prt) {
666 Aml *if_device_1, *if_pin_4, *else_pin_4;
667
668 /* device 1 is the power-management device, needs SCI */
669 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
670 {
671 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
672 {
673 aml_append(if_pin_4,
674 aml_store(build_prt_entry("LNKS"), route));
675 }
676 aml_append(if_device_1, if_pin_4);
677 else_pin_4 = aml_else();
678 {
679 aml_append(else_pin_4,
680 aml_store(build_prt_entry("LNKA"), route));
681 }
682 aml_append(if_device_1, else_pin_4);
683 }
684 aml_append(while_ctx, if_device_1);
685 } else {
686 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
687 }
688 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
689 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
690
691 /* route[0] = 0x[slot]FFFF */
692 aml_append(while_ctx,
693 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
694 NULL),
695 aml_index(route, aml_int(0))));
696 /* route[1] = pin & 3 */
697 aml_append(while_ctx,
698 aml_store(aml_and(pin, aml_int(3), NULL),
699 aml_index(route, aml_int(1))));
700 /* res[pin] = route */
701 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
702 /* pin++ */
703 aml_append(while_ctx, aml_increment(pin));
704 }
705 aml_append(method, while_ctx);
706 /* return res*/
707 aml_append(method, aml_return(res));
708
709 return method;
710 }
711
712 typedef struct CrsRangeEntry {
713 uint64_t base;
714 uint64_t limit;
715 } CrsRangeEntry;
716
717 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
718 {
719 CrsRangeEntry *entry;
720
721 entry = g_malloc(sizeof(*entry));
722 entry->base = base;
723 entry->limit = limit;
724
725 g_ptr_array_add(ranges, entry);
726 }
727
728 static void crs_range_free(gpointer data)
729 {
730 CrsRangeEntry *entry = (CrsRangeEntry *)data;
731 g_free(entry);
732 }
733
734 static gint crs_range_compare(gconstpointer a, gconstpointer b)
735 {
736 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
737 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
738
739 return (int64_t)entry_a->base - (int64_t)entry_b->base;
740 }
741
742 /*
743 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
744 * interval, computes the 'free' ranges from the same interval.
745 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
746 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
747 */
748 static void crs_replace_with_free_ranges(GPtrArray *ranges,
749 uint64_t start, uint64_t end)
750 {
751 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
752 uint64_t free_base = start;
753 int i;
754
755 g_ptr_array_sort(ranges, crs_range_compare);
756 for (i = 0; i < ranges->len; i++) {
757 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
758
759 if (free_base < used->base) {
760 crs_range_insert(free_ranges, free_base, used->base - 1);
761 }
762
763 free_base = used->limit + 1;
764 }
765
766 if (free_base < end) {
767 crs_range_insert(free_ranges, free_base, end);
768 }
769
770 g_ptr_array_set_size(ranges, 0);
771 for (i = 0; i < free_ranges->len; i++) {
772 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
773 }
774
775 g_ptr_array_free(free_ranges, false);
776 }
777
778 /*
779 * crs_range_merge - merges adjacent ranges in the given array.
780 * Array elements are deleted and replaced with the merged ranges.
781 */
782 static void crs_range_merge(GPtrArray *range)
783 {
784 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
785 CrsRangeEntry *entry;
786 uint64_t range_base, range_limit;
787 int i;
788
789 if (!range->len) {
790 return;
791 }
792
793 g_ptr_array_sort(range, crs_range_compare);
794
795 entry = g_ptr_array_index(range, 0);
796 range_base = entry->base;
797 range_limit = entry->limit;
798 for (i = 1; i < range->len; i++) {
799 entry = g_ptr_array_index(range, i);
800 if (entry->base - 1 == range_limit) {
801 range_limit = entry->limit;
802 } else {
803 crs_range_insert(tmp, range_base, range_limit);
804 range_base = entry->base;
805 range_limit = entry->limit;
806 }
807 }
808 crs_range_insert(tmp, range_base, range_limit);
809
810 g_ptr_array_set_size(range, 0);
811 for (i = 0; i < tmp->len; i++) {
812 entry = g_ptr_array_index(tmp, i);
813 crs_range_insert(range, entry->base, entry->limit);
814 }
815 g_ptr_array_free(tmp, true);
816 }
817
818 static Aml *build_crs(PCIHostState *host,
819 GPtrArray *io_ranges, GPtrArray *mem_ranges)
820 {
821 Aml *crs = aml_resource_template();
822 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
823 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
824 CrsRangeEntry *entry;
825 uint8_t max_bus = pci_bus_num(host->bus);
826 uint8_t type;
827 int devfn;
828 int i;
829
830 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
831 uint64_t range_base, range_limit;
832 PCIDevice *dev = host->bus->devices[devfn];
833
834 if (!dev) {
835 continue;
836 }
837
838 for (i = 0; i < PCI_NUM_REGIONS; i++) {
839 PCIIORegion *r = &dev->io_regions[i];
840
841 range_base = r->addr;
842 range_limit = r->addr + r->size - 1;
843
844 /*
845 * Work-around for old bioses
846 * that do not support multiple root buses
847 */
848 if (!range_base || range_base > range_limit) {
849 continue;
850 }
851
852 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
853 crs_range_insert(host_io_ranges, range_base, range_limit);
854 } else { /* "memory" */
855 crs_range_insert(host_mem_ranges, range_base, range_limit);
856 }
857 }
858
859 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
860 if (type == PCI_HEADER_TYPE_BRIDGE) {
861 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
862 if (subordinate > max_bus) {
863 max_bus = subordinate;
864 }
865
866 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
867 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
868
869 /*
870 * Work-around for old bioses
871 * that do not support multiple root buses
872 */
873 if (range_base && range_base <= range_limit) {
874 crs_range_insert(host_io_ranges, range_base, range_limit);
875 }
876
877 range_base =
878 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
879 range_limit =
880 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
881
882 /*
883 * Work-around for old bioses
884 * that do not support multiple root buses
885 */
886 if (range_base && range_base <= range_limit) {
887 crs_range_insert(host_mem_ranges, range_base, range_limit);
888 }
889
890 range_base =
891 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
892 range_limit =
893 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
894
895 /*
896 * Work-around for old bioses
897 * that do not support multiple root buses
898 */
899 if (range_base && range_base <= range_limit) {
900 crs_range_insert(host_mem_ranges, range_base, range_limit);
901 }
902 }
903 }
904
905 crs_range_merge(host_io_ranges);
906 for (i = 0; i < host_io_ranges->len; i++) {
907 entry = g_ptr_array_index(host_io_ranges, i);
908 aml_append(crs,
909 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
910 AML_POS_DECODE, AML_ENTIRE_RANGE,
911 0, entry->base, entry->limit, 0,
912 entry->limit - entry->base + 1));
913 crs_range_insert(io_ranges, entry->base, entry->limit);
914 }
915 g_ptr_array_free(host_io_ranges, true);
916
917 crs_range_merge(host_mem_ranges);
918 for (i = 0; i < host_mem_ranges->len; i++) {
919 entry = g_ptr_array_index(host_mem_ranges, i);
920 aml_append(crs,
921 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
922 AML_MAX_FIXED, AML_NON_CACHEABLE,
923 AML_READ_WRITE,
924 0, entry->base, entry->limit, 0,
925 entry->limit - entry->base + 1));
926 crs_range_insert(mem_ranges, entry->base, entry->limit);
927 }
928 g_ptr_array_free(host_mem_ranges, true);
929
930 aml_append(crs,
931 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
932 0,
933 pci_bus_num(host->bus),
934 max_bus,
935 0,
936 max_bus - pci_bus_num(host->bus) + 1));
937
938 return crs;
939 }
940
941 static void build_memory_devices(Aml *sb_scope, int nr_mem,
942 uint16_t io_base, uint16_t io_len)
943 {
944 int i;
945 Aml *scope;
946 Aml *crs;
947 Aml *field;
948 Aml *dev;
949 Aml *method;
950 Aml *ifctx;
951
952 /* build memory devices */
953 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
954 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
955 aml_append(scope,
956 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
957 );
958
959 crs = aml_resource_template();
960 aml_append(crs,
961 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
962 );
963 aml_append(scope, aml_name_decl("_CRS", crs));
964
965 aml_append(scope, aml_operation_region(
966 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
967 aml_int(io_base), io_len)
968 );
969
970 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
971 AML_NOLOCK, AML_PRESERVE);
972 aml_append(field, /* read only */
973 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
974 aml_append(field, /* read only */
975 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
976 aml_append(field, /* read only */
977 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
978 aml_append(field, /* read only */
979 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
980 aml_append(field, /* read only */
981 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
982 aml_append(scope, field);
983
984 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
985 AML_NOLOCK, AML_WRITE_AS_ZEROS);
986 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
987 aml_append(field, /* 1 if enabled, read only */
988 aml_named_field(MEMORY_SLOT_ENABLED, 1));
989 aml_append(field,
990 /*(read) 1 if has a insert event. (write) 1 to clear event */
991 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
992 aml_append(field,
993 /* (read) 1 if has a remove event. (write) 1 to clear event */
994 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
995 aml_append(field,
996 /* initiates device eject, write only */
997 aml_named_field(MEMORY_SLOT_EJECT, 1));
998 aml_append(scope, field);
999
1000 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1001 AML_NOLOCK, AML_PRESERVE);
1002 aml_append(field, /* DIMM selector, write only */
1003 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1004 aml_append(field, /* _OST event code, write only */
1005 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1006 aml_append(field, /* _OST status code, write only */
1007 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1008 aml_append(scope, field);
1009 aml_append(sb_scope, scope);
1010
1011 for (i = 0; i < nr_mem; i++) {
1012 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1013 const char *s;
1014
1015 dev = aml_device("MP%02X", i);
1016 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1017 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1018
1019 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1020 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1021 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1022 aml_append(dev, method);
1023
1024 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1025 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1026 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1027 aml_append(dev, method);
1028
1029 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1030 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1031 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1032 aml_append(dev, method);
1033
1034 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1035 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1036
1037 aml_append(method, aml_return(aml_call4(
1038 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1039 )));
1040 aml_append(dev, method);
1041
1042 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1043 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1044 aml_append(method, aml_return(aml_call2(
1045 s, aml_name("_UID"), aml_arg(0))));
1046 aml_append(dev, method);
1047
1048 aml_append(sb_scope, dev);
1049 }
1050
1051 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1052 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1053 */
1054 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1055 for (i = 0; i < nr_mem; i++) {
1056 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1057 aml_append(ifctx,
1058 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1059 );
1060 aml_append(method, ifctx);
1061 }
1062 aml_append(sb_scope, method);
1063 }
1064
1065 static void build_hpet_aml(Aml *table)
1066 {
1067 Aml *crs;
1068 Aml *field;
1069 Aml *method;
1070 Aml *if_ctx;
1071 Aml *scope = aml_scope("_SB");
1072 Aml *dev = aml_device("HPET");
1073 Aml *zero = aml_int(0);
1074 Aml *id = aml_local(0);
1075 Aml *period = aml_local(1);
1076
1077 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1078 aml_append(dev, aml_name_decl("_UID", zero));
1079
1080 aml_append(dev,
1081 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1082 HPET_LEN));
1083 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1084 aml_append(field, aml_named_field("VEND", 32));
1085 aml_append(field, aml_named_field("PRD", 32));
1086 aml_append(dev, field);
1087
1088 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1089 aml_append(method, aml_store(aml_name("VEND"), id));
1090 aml_append(method, aml_store(aml_name("PRD"), period));
1091 aml_append(method, aml_shiftright(id, aml_int(16), id));
1092 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1093 aml_equal(id, aml_int(0xffff))));
1094 {
1095 aml_append(if_ctx, aml_return(zero));
1096 }
1097 aml_append(method, if_ctx);
1098
1099 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1100 aml_lgreater(period, aml_int(100000000))));
1101 {
1102 aml_append(if_ctx, aml_return(zero));
1103 }
1104 aml_append(method, if_ctx);
1105
1106 aml_append(method, aml_return(aml_int(0x0F)));
1107 aml_append(dev, method);
1108
1109 crs = aml_resource_template();
1110 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1111 aml_append(dev, aml_name_decl("_CRS", crs));
1112
1113 aml_append(scope, dev);
1114 aml_append(table, scope);
1115 }
1116
1117 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1118 {
1119 Aml *dev, *fdi;
1120 uint8_t maxc, maxh, maxs;
1121
1122 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1123
1124 dev = aml_device("FLP%c", 'A' + idx);
1125
1126 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1127
1128 fdi = aml_package(16);
1129 aml_append(fdi, aml_int(idx)); /* Drive Number */
1130 aml_append(fdi,
1131 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1132 /*
1133 * the values below are the limits of the drive, and are thus independent
1134 * of the inserted media
1135 */
1136 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1137 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1138 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1139 /*
1140 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1141 * the drive type, so shall we
1142 */
1143 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1144 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1145 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1146 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1147 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1148 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1149 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1150 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1151 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1152 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1153 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1154
1155 aml_append(dev, aml_name_decl("_FDI", fdi));
1156 return dev;
1157 }
1158
1159 static Aml *build_fdc_device_aml(ISADevice *fdc)
1160 {
1161 int i;
1162 Aml *dev;
1163 Aml *crs;
1164
1165 #define ACPI_FDE_MAX_FD 4
1166 uint32_t fde_buf[5] = {
1167 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1168 cpu_to_le32(2) /* tape presence (2 == never present) */
1169 };
1170
1171 dev = aml_device("FDC0");
1172 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1173
1174 crs = aml_resource_template();
1175 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1176 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1177 aml_append(crs, aml_irq_no_flags(6));
1178 aml_append(crs,
1179 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1180 aml_append(dev, aml_name_decl("_CRS", crs));
1181
1182 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1183 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1184
1185 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1186 fde_buf[i] = cpu_to_le32(1); /* drive present */
1187 aml_append(dev, build_fdinfo_aml(i, type));
1188 }
1189 }
1190 aml_append(dev, aml_name_decl("_FDE",
1191 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1192
1193 return dev;
1194 }
1195
1196 static Aml *build_rtc_device_aml(void)
1197 {
1198 Aml *dev;
1199 Aml *crs;
1200
1201 dev = aml_device("RTC");
1202 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1203 crs = aml_resource_template();
1204 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1205 aml_append(crs, aml_irq_no_flags(8));
1206 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1207 aml_append(dev, aml_name_decl("_CRS", crs));
1208
1209 return dev;
1210 }
1211
1212 static Aml *build_kbd_device_aml(void)
1213 {
1214 Aml *dev;
1215 Aml *crs;
1216 Aml *method;
1217
1218 dev = aml_device("KBD");
1219 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1220
1221 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1222 aml_append(method, aml_return(aml_int(0x0f)));
1223 aml_append(dev, method);
1224
1225 crs = aml_resource_template();
1226 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1227 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1228 aml_append(crs, aml_irq_no_flags(1));
1229 aml_append(dev, aml_name_decl("_CRS", crs));
1230
1231 return dev;
1232 }
1233
1234 static Aml *build_mouse_device_aml(void)
1235 {
1236 Aml *dev;
1237 Aml *crs;
1238 Aml *method;
1239
1240 dev = aml_device("MOU");
1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1242
1243 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1244 aml_append(method, aml_return(aml_int(0x0f)));
1245 aml_append(dev, method);
1246
1247 crs = aml_resource_template();
1248 aml_append(crs, aml_irq_no_flags(12));
1249 aml_append(dev, aml_name_decl("_CRS", crs));
1250
1251 return dev;
1252 }
1253
1254 static Aml *build_lpt_device_aml(void)
1255 {
1256 Aml *dev;
1257 Aml *crs;
1258 Aml *method;
1259 Aml *if_ctx;
1260 Aml *else_ctx;
1261 Aml *zero = aml_int(0);
1262 Aml *is_present = aml_local(0);
1263
1264 dev = aml_device("LPT");
1265 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1266
1267 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1268 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1269 if_ctx = aml_if(aml_equal(is_present, zero));
1270 {
1271 aml_append(if_ctx, aml_return(aml_int(0x00)));
1272 }
1273 aml_append(method, if_ctx);
1274 else_ctx = aml_else();
1275 {
1276 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1277 }
1278 aml_append(method, else_ctx);
1279 aml_append(dev, method);
1280
1281 crs = aml_resource_template();
1282 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1283 aml_append(crs, aml_irq_no_flags(7));
1284 aml_append(dev, aml_name_decl("_CRS", crs));
1285
1286 return dev;
1287 }
1288
1289 static Aml *build_com_device_aml(uint8_t uid)
1290 {
1291 Aml *dev;
1292 Aml *crs;
1293 Aml *method;
1294 Aml *if_ctx;
1295 Aml *else_ctx;
1296 Aml *zero = aml_int(0);
1297 Aml *is_present = aml_local(0);
1298 const char *enabled_field = "CAEN";
1299 uint8_t irq = 4;
1300 uint16_t io_port = 0x03F8;
1301
1302 assert(uid == 1 || uid == 2);
1303 if (uid == 2) {
1304 enabled_field = "CBEN";
1305 irq = 3;
1306 io_port = 0x02F8;
1307 }
1308
1309 dev = aml_device("COM%d", uid);
1310 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1311 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1312
1313 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1314 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1315 if_ctx = aml_if(aml_equal(is_present, zero));
1316 {
1317 aml_append(if_ctx, aml_return(aml_int(0x00)));
1318 }
1319 aml_append(method, if_ctx);
1320 else_ctx = aml_else();
1321 {
1322 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1323 }
1324 aml_append(method, else_ctx);
1325 aml_append(dev, method);
1326
1327 crs = aml_resource_template();
1328 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1329 aml_append(crs, aml_irq_no_flags(irq));
1330 aml_append(dev, aml_name_decl("_CRS", crs));
1331
1332 return dev;
1333 }
1334
1335 static void build_isa_devices_aml(Aml *table)
1336 {
1337 ISADevice *fdc = pc_find_fdc0();
1338
1339 Aml *scope = aml_scope("_SB.PCI0.ISA");
1340
1341 aml_append(scope, build_rtc_device_aml());
1342 aml_append(scope, build_kbd_device_aml());
1343 aml_append(scope, build_mouse_device_aml());
1344 if (fdc) {
1345 aml_append(scope, build_fdc_device_aml(fdc));
1346 }
1347 aml_append(scope, build_lpt_device_aml());
1348 aml_append(scope, build_com_device_aml(1));
1349 aml_append(scope, build_com_device_aml(2));
1350
1351 aml_append(table, scope);
1352 }
1353
1354 static void build_dbg_aml(Aml *table)
1355 {
1356 Aml *field;
1357 Aml *method;
1358 Aml *while_ctx;
1359 Aml *scope = aml_scope("\\");
1360 Aml *buf = aml_local(0);
1361 Aml *len = aml_local(1);
1362 Aml *idx = aml_local(2);
1363
1364 aml_append(scope,
1365 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1366 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1367 aml_append(field, aml_named_field("DBGB", 8));
1368 aml_append(scope, field);
1369
1370 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1371
1372 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1373 aml_append(method, aml_to_buffer(buf, buf));
1374 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1375 aml_append(method, aml_store(aml_int(0), idx));
1376
1377 while_ctx = aml_while(aml_lless(idx, len));
1378 aml_append(while_ctx,
1379 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1380 aml_append(while_ctx, aml_increment(idx));
1381 aml_append(method, while_ctx);
1382
1383 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1384 aml_append(scope, method);
1385
1386 aml_append(table, scope);
1387 }
1388
1389 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1390 {
1391 Aml *dev;
1392 Aml *crs;
1393 Aml *method;
1394 uint32_t irqs[] = {5, 10, 11};
1395
1396 dev = aml_device("%s", name);
1397 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1398 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1399
1400 crs = aml_resource_template();
1401 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1402 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1403 aml_append(dev, aml_name_decl("_PRS", crs));
1404
1405 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1406 aml_append(method, aml_return(aml_call1("IQST", reg)));
1407 aml_append(dev, method);
1408
1409 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1410 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1411 aml_append(dev, method);
1412
1413 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1414 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1415 aml_append(dev, method);
1416
1417 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1418 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1419 aml_append(method, aml_store(aml_name("PRRI"), reg));
1420 aml_append(dev, method);
1421
1422 return dev;
1423 }
1424
1425 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1426 {
1427 Aml *dev;
1428 Aml *crs;
1429 Aml *method;
1430 uint32_t irqs;
1431
1432 dev = aml_device("%s", name);
1433 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1434 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1435
1436 crs = aml_resource_template();
1437 irqs = gsi;
1438 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1439 AML_SHARED, &irqs, 1));
1440 aml_append(dev, aml_name_decl("_PRS", crs));
1441
1442 aml_append(dev, aml_name_decl("_CRS", crs));
1443
1444 /*
1445 * _DIS can be no-op because the interrupt cannot be disabled.
1446 */
1447 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1448 aml_append(dev, method);
1449
1450 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1451 aml_append(dev, method);
1452
1453 return dev;
1454 }
1455
1456 /* _CRS method - get current settings */
1457 static Aml *build_iqcr_method(bool is_piix4)
1458 {
1459 Aml *if_ctx;
1460 uint32_t irqs;
1461 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1462 Aml *crs = aml_resource_template();
1463
1464 irqs = 0;
1465 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1466 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1467 aml_append(method, aml_name_decl("PRR0", crs));
1468
1469 aml_append(method,
1470 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1471
1472 if (is_piix4) {
1473 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1474 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1475 aml_append(method, if_ctx);
1476 } else {
1477 aml_append(method,
1478 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1479 aml_name("PRRI")));
1480 }
1481
1482 aml_append(method, aml_return(aml_name("PRR0")));
1483 return method;
1484 }
1485
1486 /* _STA method - get status */
1487 static Aml *build_irq_status_method(void)
1488 {
1489 Aml *if_ctx;
1490 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1491
1492 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1493 aml_append(if_ctx, aml_return(aml_int(0x09)));
1494 aml_append(method, if_ctx);
1495 aml_append(method, aml_return(aml_int(0x0B)));
1496 return method;
1497 }
1498
1499 static void build_piix4_pci0_int(Aml *table)
1500 {
1501 Aml *dev;
1502 Aml *crs;
1503 Aml *field;
1504 Aml *method;
1505 uint32_t irqs;
1506 Aml *sb_scope = aml_scope("_SB");
1507 Aml *pci0_scope = aml_scope("PCI0");
1508
1509 aml_append(pci0_scope, build_prt(true));
1510 aml_append(sb_scope, pci0_scope);
1511
1512 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1513 aml_append(field, aml_named_field("PRQ0", 8));
1514 aml_append(field, aml_named_field("PRQ1", 8));
1515 aml_append(field, aml_named_field("PRQ2", 8));
1516 aml_append(field, aml_named_field("PRQ3", 8));
1517 aml_append(sb_scope, field);
1518
1519 aml_append(sb_scope, build_irq_status_method());
1520 aml_append(sb_scope, build_iqcr_method(true));
1521
1522 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1523 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1524 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1525 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1526
1527 dev = aml_device("LNKS");
1528 {
1529 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1530 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1531
1532 crs = aml_resource_template();
1533 irqs = 9;
1534 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1535 AML_ACTIVE_HIGH, AML_SHARED,
1536 &irqs, 1));
1537 aml_append(dev, aml_name_decl("_PRS", crs));
1538
1539 /* The SCI cannot be disabled and is always attached to GSI 9,
1540 * so these are no-ops. We only need this link to override the
1541 * polarity to active high and match the content of the MADT.
1542 */
1543 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1544 aml_append(method, aml_return(aml_int(0x0b)));
1545 aml_append(dev, method);
1546
1547 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1548 aml_append(dev, method);
1549
1550 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1551 aml_append(method, aml_return(aml_name("_PRS")));
1552 aml_append(dev, method);
1553
1554 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1555 aml_append(dev, method);
1556 }
1557 aml_append(sb_scope, dev);
1558
1559 aml_append(table, sb_scope);
1560 }
1561
1562 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1563 {
1564 int i;
1565 int head;
1566 Aml *pkg;
1567 char base = name[3] < 'E' ? 'A' : 'E';
1568 char *s = g_strdup(name);
1569 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1570
1571 assert(strlen(s) == 4);
1572
1573 head = name[3] - base;
1574 for (i = 0; i < 4; i++) {
1575 if (head + i > 3) {
1576 head = i * -1;
1577 }
1578 s[3] = base + head + i;
1579 pkg = aml_package(4);
1580 aml_append(pkg, a_nr);
1581 aml_append(pkg, aml_int(i));
1582 aml_append(pkg, aml_name("%s", s));
1583 aml_append(pkg, aml_int(0));
1584 aml_append(ctx, pkg);
1585 }
1586 g_free(s);
1587 }
1588
1589 static Aml *build_q35_routing_table(const char *str)
1590 {
1591 int i;
1592 Aml *pkg;
1593 char *name = g_strdup_printf("%s ", str);
1594
1595 pkg = aml_package(128);
1596 for (i = 0; i < 0x18; i++) {
1597 name[3] = 'E' + (i & 0x3);
1598 append_q35_prt_entry(pkg, i, name);
1599 }
1600
1601 name[3] = 'E';
1602 append_q35_prt_entry(pkg, 0x18, name);
1603
1604 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1605 for (i = 0x0019; i < 0x1e; i++) {
1606 name[3] = 'A';
1607 append_q35_prt_entry(pkg, i, name);
1608 }
1609
1610 /* PCIe->PCI bridge. use PIRQ[E-H] */
1611 name[3] = 'E';
1612 append_q35_prt_entry(pkg, 0x1e, name);
1613 name[3] = 'A';
1614 append_q35_prt_entry(pkg, 0x1f, name);
1615
1616 g_free(name);
1617 return pkg;
1618 }
1619
1620 static void build_q35_pci0_int(Aml *table)
1621 {
1622 Aml *field;
1623 Aml *method;
1624 Aml *sb_scope = aml_scope("_SB");
1625 Aml *pci0_scope = aml_scope("PCI0");
1626
1627 /* Zero => PIC mode, One => APIC Mode */
1628 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1629 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1630 {
1631 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1632 }
1633 aml_append(table, method);
1634
1635 aml_append(pci0_scope,
1636 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1637 aml_append(pci0_scope,
1638 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1639
1640 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1641 {
1642 Aml *if_ctx;
1643 Aml *else_ctx;
1644
1645 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1646 section 6.2.8.1 */
1647 /* Note: we provide the same info as the PCI routing
1648 table of the Bochs BIOS */
1649 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1650 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1651 aml_append(method, if_ctx);
1652 else_ctx = aml_else();
1653 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1654 aml_append(method, else_ctx);
1655 }
1656 aml_append(pci0_scope, method);
1657 aml_append(sb_scope, pci0_scope);
1658
1659 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1660 aml_append(field, aml_named_field("PRQA", 8));
1661 aml_append(field, aml_named_field("PRQB", 8));
1662 aml_append(field, aml_named_field("PRQC", 8));
1663 aml_append(field, aml_named_field("PRQD", 8));
1664 aml_append(field, aml_reserved_field(0x20));
1665 aml_append(field, aml_named_field("PRQE", 8));
1666 aml_append(field, aml_named_field("PRQF", 8));
1667 aml_append(field, aml_named_field("PRQG", 8));
1668 aml_append(field, aml_named_field("PRQH", 8));
1669 aml_append(sb_scope, field);
1670
1671 aml_append(sb_scope, build_irq_status_method());
1672 aml_append(sb_scope, build_iqcr_method(false));
1673
1674 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1675 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1676 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1677 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1678 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1679 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1680 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1681 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1682
1683 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1684 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1685 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1686 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1687 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1688 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1689 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1690 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1691
1692 aml_append(table, sb_scope);
1693 }
1694
1695 static void build_q35_isa_bridge(Aml *table)
1696 {
1697 Aml *dev;
1698 Aml *scope;
1699 Aml *field;
1700
1701 scope = aml_scope("_SB.PCI0");
1702 dev = aml_device("ISA");
1703 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1704
1705 /* ICH9 PCI to ISA irq remapping */
1706 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1707 aml_int(0x60), 0x0C));
1708
1709 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1710 aml_int(0x80), 0x02));
1711 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1712 aml_append(field, aml_named_field("COMA", 3));
1713 aml_append(field, aml_reserved_field(1));
1714 aml_append(field, aml_named_field("COMB", 3));
1715 aml_append(field, aml_reserved_field(1));
1716 aml_append(field, aml_named_field("LPTD", 2));
1717 aml_append(dev, field);
1718
1719 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1720 aml_int(0x82), 0x02));
1721 /* enable bits */
1722 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1723 aml_append(field, aml_named_field("CAEN", 1));
1724 aml_append(field, aml_named_field("CBEN", 1));
1725 aml_append(field, aml_named_field("LPEN", 1));
1726 aml_append(dev, field);
1727
1728 aml_append(scope, dev);
1729 aml_append(table, scope);
1730 }
1731
1732 static void build_piix4_pm(Aml *table)
1733 {
1734 Aml *dev;
1735 Aml *scope;
1736
1737 scope = aml_scope("_SB.PCI0");
1738 dev = aml_device("PX13");
1739 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1740
1741 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1742 aml_int(0x00), 0xff));
1743 aml_append(scope, dev);
1744 aml_append(table, scope);
1745 }
1746
1747 static void build_piix4_isa_bridge(Aml *table)
1748 {
1749 Aml *dev;
1750 Aml *scope;
1751 Aml *field;
1752
1753 scope = aml_scope("_SB.PCI0");
1754 dev = aml_device("ISA");
1755 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1756
1757 /* PIIX PCI to ISA irq remapping */
1758 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1759 aml_int(0x60), 0x04));
1760 /* enable bits */
1761 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1762 /* Offset(0x5f),, 7, */
1763 aml_append(field, aml_reserved_field(0x2f8));
1764 aml_append(field, aml_reserved_field(7));
1765 aml_append(field, aml_named_field("LPEN", 1));
1766 /* Offset(0x67),, 3, */
1767 aml_append(field, aml_reserved_field(0x38));
1768 aml_append(field, aml_reserved_field(3));
1769 aml_append(field, aml_named_field("CAEN", 1));
1770 aml_append(field, aml_reserved_field(3));
1771 aml_append(field, aml_named_field("CBEN", 1));
1772 aml_append(dev, field);
1773
1774 aml_append(scope, dev);
1775 aml_append(table, scope);
1776 }
1777
1778 static void build_piix4_pci_hotplug(Aml *table)
1779 {
1780 Aml *scope;
1781 Aml *field;
1782 Aml *method;
1783
1784 scope = aml_scope("_SB.PCI0");
1785
1786 aml_append(scope,
1787 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1788 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1789 aml_append(field, aml_named_field("PCIU", 32));
1790 aml_append(field, aml_named_field("PCID", 32));
1791 aml_append(scope, field);
1792
1793 aml_append(scope,
1794 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1795 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1796 aml_append(field, aml_named_field("B0EJ", 32));
1797 aml_append(scope, field);
1798
1799 aml_append(scope,
1800 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1801 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1802 aml_append(field, aml_named_field("BNUM", 32));
1803 aml_append(scope, field);
1804
1805 aml_append(scope, aml_mutex("BLCK", 0));
1806
1807 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1808 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1809 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1810 aml_append(method,
1811 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1812 aml_append(method, aml_release(aml_name("BLCK")));
1813 aml_append(method, aml_return(aml_int(0)));
1814 aml_append(scope, method);
1815
1816 aml_append(table, scope);
1817 }
1818
1819 static Aml *build_q35_osc_method(void)
1820 {
1821 Aml *if_ctx;
1822 Aml *if_ctx2;
1823 Aml *else_ctx;
1824 Aml *method;
1825 Aml *a_cwd1 = aml_name("CDW1");
1826 Aml *a_ctrl = aml_name("CTRL");
1827
1828 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1829 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1830
1831 if_ctx = aml_if(aml_equal(
1832 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1833 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1834 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1835
1836 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1837 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1838
1839 /*
1840 * Always allow native PME, AER (no dependencies)
1841 * Never allow SHPC (no SHPC controller in this system)
1842 */
1843 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1844
1845 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1846 /* Unknown revision */
1847 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1848 aml_append(if_ctx, if_ctx2);
1849
1850 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1851 /* Capabilities bits were masked */
1852 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1853 aml_append(if_ctx, if_ctx2);
1854
1855 /* Update DWORD3 in the buffer */
1856 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1857 aml_append(method, if_ctx);
1858
1859 else_ctx = aml_else();
1860 /* Unrecognized UUID */
1861 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1862 aml_append(method, else_ctx);
1863
1864 aml_append(method, aml_return(aml_arg(3)));
1865 return method;
1866 }
1867
1868 static void
1869 build_dsdt(GArray *table_data, BIOSLinker *linker,
1870 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1871 PcPciInfo *pci, MachineState *machine)
1872 {
1873 CrsRangeEntry *entry;
1874 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1875 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1876 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1877 PCMachineState *pcms = PC_MACHINE(machine);
1878 uint32_t nr_mem = machine->ram_slots;
1879 int root_bus_limit = 0xFF;
1880 PCIBus *bus = NULL;
1881 int i;
1882
1883 dsdt = init_aml_allocator();
1884
1885 /* Reserve space for header */
1886 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1887
1888 build_dbg_aml(dsdt);
1889 if (misc->is_piix4) {
1890 sb_scope = aml_scope("_SB");
1891 dev = aml_device("PCI0");
1892 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1893 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1894 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1895 aml_append(sb_scope, dev);
1896 aml_append(dsdt, sb_scope);
1897
1898 build_hpet_aml(dsdt);
1899 build_piix4_pm(dsdt);
1900 build_piix4_isa_bridge(dsdt);
1901 build_isa_devices_aml(dsdt);
1902 build_piix4_pci_hotplug(dsdt);
1903 build_piix4_pci0_int(dsdt);
1904 } else {
1905 sb_scope = aml_scope("_SB");
1906 aml_append(sb_scope,
1907 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1908 aml_append(sb_scope,
1909 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1910 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1911 aml_append(field, aml_named_field("PCIB", 8));
1912 aml_append(sb_scope, field);
1913 aml_append(dsdt, sb_scope);
1914
1915 sb_scope = aml_scope("_SB");
1916 dev = aml_device("PCI0");
1917 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1918 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1919 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1920 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1921 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1922 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1923 aml_append(dev, build_q35_osc_method());
1924 aml_append(sb_scope, dev);
1925 aml_append(dsdt, sb_scope);
1926
1927 build_hpet_aml(dsdt);
1928 build_q35_isa_bridge(dsdt);
1929 build_isa_devices_aml(dsdt);
1930 build_q35_pci0_int(dsdt);
1931 }
1932
1933 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1934 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1935 pm->mem_hp_io_len);
1936
1937 scope = aml_scope("_GPE");
1938 {
1939 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1940
1941 if (misc->is_piix4) {
1942 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1943 aml_append(method,
1944 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1945 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1946 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1947 aml_append(scope, method);
1948 }
1949
1950 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1951 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1952 aml_append(scope, method);
1953 }
1954 aml_append(dsdt, scope);
1955
1956 bus = PC_MACHINE(machine)->bus;
1957 if (bus) {
1958 QLIST_FOREACH(bus, &bus->child, sibling) {
1959 uint8_t bus_num = pci_bus_num(bus);
1960 uint8_t numa_node = pci_bus_numa_node(bus);
1961
1962 /* look only for expander root buses */
1963 if (!pci_bus_is_root(bus)) {
1964 continue;
1965 }
1966
1967 if (bus_num < root_bus_limit) {
1968 root_bus_limit = bus_num - 1;
1969 }
1970
1971 scope = aml_scope("\\_SB");
1972 dev = aml_device("PC%.02X", bus_num);
1973 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1974 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1975 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1976
1977 if (numa_node != NUMA_NODE_UNASSIGNED) {
1978 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1979 }
1980
1981 aml_append(dev, build_prt(false));
1982 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1983 io_ranges, mem_ranges);
1984 aml_append(dev, aml_name_decl("_CRS", crs));
1985 aml_append(scope, dev);
1986 aml_append(dsdt, scope);
1987 }
1988 }
1989
1990 scope = aml_scope("\\_SB.PCI0");
1991 /* build PCI0._CRS */
1992 crs = aml_resource_template();
1993 aml_append(crs,
1994 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1995 0x0000, 0x0, root_bus_limit,
1996 0x0000, root_bus_limit + 1));
1997 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1998
1999 aml_append(crs,
2000 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2001 AML_POS_DECODE, AML_ENTIRE_RANGE,
2002 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2003
2004 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2005 for (i = 0; i < io_ranges->len; i++) {
2006 entry = g_ptr_array_index(io_ranges, i);
2007 aml_append(crs,
2008 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2009 AML_POS_DECODE, AML_ENTIRE_RANGE,
2010 0x0000, entry->base, entry->limit,
2011 0x0000, entry->limit - entry->base + 1));
2012 }
2013
2014 aml_append(crs,
2015 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2016 AML_CACHEABLE, AML_READ_WRITE,
2017 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2018
2019 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2020 for (i = 0; i < mem_ranges->len; i++) {
2021 entry = g_ptr_array_index(mem_ranges, i);
2022 aml_append(crs,
2023 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2024 AML_NON_CACHEABLE, AML_READ_WRITE,
2025 0, entry->base, entry->limit,
2026 0, entry->limit - entry->base + 1));
2027 }
2028
2029 if (pci->w64.begin) {
2030 aml_append(crs,
2031 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2032 AML_CACHEABLE, AML_READ_WRITE,
2033 0, pci->w64.begin, pci->w64.end - 1, 0,
2034 pci->w64.end - pci->w64.begin));
2035 }
2036
2037 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2038 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2039 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2040 }
2041 aml_append(scope, aml_name_decl("_CRS", crs));
2042
2043 /* reserve GPE0 block resources */
2044 dev = aml_device("GPE0");
2045 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2046 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2047 /* device present, functioning, decoding, not shown in UI */
2048 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2049 crs = aml_resource_template();
2050 aml_append(crs,
2051 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2052 );
2053 aml_append(dev, aml_name_decl("_CRS", crs));
2054 aml_append(scope, dev);
2055
2056 g_ptr_array_free(io_ranges, true);
2057 g_ptr_array_free(mem_ranges, true);
2058
2059 /* reserve PCIHP resources */
2060 if (pm->pcihp_io_len) {
2061 dev = aml_device("PHPR");
2062 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2063 aml_append(dev,
2064 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2065 /* device present, functioning, decoding, not shown in UI */
2066 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2067 crs = aml_resource_template();
2068 aml_append(crs,
2069 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2070 pm->pcihp_io_len)
2071 );
2072 aml_append(dev, aml_name_decl("_CRS", crs));
2073 aml_append(scope, dev);
2074 }
2075 aml_append(dsdt, scope);
2076
2077 /* create S3_ / S4_ / S5_ packages if necessary */
2078 scope = aml_scope("\\");
2079 if (!pm->s3_disabled) {
2080 pkg = aml_package(4);
2081 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2082 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2083 aml_append(pkg, aml_int(0)); /* reserved */
2084 aml_append(pkg, aml_int(0)); /* reserved */
2085 aml_append(scope, aml_name_decl("_S3", pkg));
2086 }
2087
2088 if (!pm->s4_disabled) {
2089 pkg = aml_package(4);
2090 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2091 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2092 aml_append(pkg, aml_int(pm->s4_val));
2093 aml_append(pkg, aml_int(0)); /* reserved */
2094 aml_append(pkg, aml_int(0)); /* reserved */
2095 aml_append(scope, aml_name_decl("_S4", pkg));
2096 }
2097
2098 pkg = aml_package(4);
2099 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2100 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2101 aml_append(pkg, aml_int(0)); /* reserved */
2102 aml_append(pkg, aml_int(0)); /* reserved */
2103 aml_append(scope, aml_name_decl("_S5", pkg));
2104 aml_append(dsdt, scope);
2105
2106 /* create fw_cfg node, unconditionally */
2107 {
2108 /* when using port i/o, the 8-bit data register *always* overlaps
2109 * with half of the 16-bit control register. Hence, the total size
2110 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2111 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2112 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2113 "dma_enabled", NULL) ?
2114 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2115 FW_CFG_CTL_SIZE;
2116
2117 scope = aml_scope("\\_SB.PCI0");
2118 dev = aml_device("FWCF");
2119
2120 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2121
2122 /* device present, functioning, decoding, not shown in UI */
2123 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2124
2125 crs = aml_resource_template();
2126 aml_append(crs,
2127 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2128 );
2129 aml_append(dev, aml_name_decl("_CRS", crs));
2130
2131 aml_append(scope, dev);
2132 aml_append(dsdt, scope);
2133 }
2134
2135 if (misc->applesmc_io_base) {
2136 scope = aml_scope("\\_SB.PCI0.ISA");
2137 dev = aml_device("SMC");
2138
2139 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2140 /* device present, functioning, decoding, not shown in UI */
2141 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2142
2143 crs = aml_resource_template();
2144 aml_append(crs,
2145 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2146 0x01, APPLESMC_MAX_DATA_LENGTH)
2147 );
2148 aml_append(crs, aml_irq_no_flags(6));
2149 aml_append(dev, aml_name_decl("_CRS", crs));
2150
2151 aml_append(scope, dev);
2152 aml_append(dsdt, scope);
2153 }
2154
2155 if (misc->pvpanic_port) {
2156 scope = aml_scope("\\_SB.PCI0.ISA");
2157
2158 dev = aml_device("PEVT");
2159 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2160
2161 crs = aml_resource_template();
2162 aml_append(crs,
2163 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2164 );
2165 aml_append(dev, aml_name_decl("_CRS", crs));
2166
2167 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2168 aml_int(misc->pvpanic_port), 1));
2169 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2170 aml_append(field, aml_named_field("PEPT", 8));
2171 aml_append(dev, field);
2172
2173 /* device present, functioning, decoding, shown in UI */
2174 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2175
2176 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2177 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2178 aml_append(method, aml_return(aml_local(0)));
2179 aml_append(dev, method);
2180
2181 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2182 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2183 aml_append(dev, method);
2184
2185 aml_append(scope, dev);
2186 aml_append(dsdt, scope);
2187 }
2188
2189 sb_scope = aml_scope("\\_SB");
2190 {
2191 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2192 pm->mem_hp_io_len);
2193
2194 {
2195 Object *pci_host;
2196 PCIBus *bus = NULL;
2197
2198 pci_host = acpi_get_i386_pci_host();
2199 if (pci_host) {
2200 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2201 }
2202
2203 if (bus) {
2204 Aml *scope = aml_scope("PCI0");
2205 /* Scan all PCI buses. Generate tables to support hotplug. */
2206 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2207
2208 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2209 dev = aml_device("ISA.TPM");
2210 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2211 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2212 crs = aml_resource_template();
2213 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2214 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2215 /*
2216 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2217 Rewrite to take IRQ from TPM device model and
2218 fix default IRQ value there to use some unused IRQ
2219 */
2220 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2221 aml_append(dev, aml_name_decl("_CRS", crs));
2222 aml_append(scope, dev);
2223 }
2224
2225 aml_append(sb_scope, scope);
2226 }
2227 }
2228 aml_append(dsdt, sb_scope);
2229 }
2230
2231 /* copy AML table into ACPI tables blob and patch header there */
2232 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2233 build_header(linker, table_data,
2234 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2235 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2236 free_aml_allocator();
2237 }
2238
2239 static void
2240 build_hpet(GArray *table_data, BIOSLinker *linker)
2241 {
2242 Acpi20Hpet *hpet;
2243
2244 hpet = acpi_data_push(table_data, sizeof(*hpet));
2245 /* Note timer_block_id value must be kept in sync with value advertised by
2246 * emulated hpet
2247 */
2248 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2249 hpet->addr.address = cpu_to_le64(HPET_BASE);
2250 build_header(linker, table_data,
2251 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2252 }
2253
2254 static void
2255 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2256 {
2257 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2258 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2259 unsigned log_addr_offset =
2260 (char *)&tcpa->log_area_start_address - table_data->data;
2261
2262 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2263 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2264 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2265
2266 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2267 false /* high memory */);
2268
2269 /* log area start address to be filled by Guest linker */
2270 bios_linker_loader_add_pointer(linker,
2271 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2272 ACPI_BUILD_TPMLOG_FILE, 0);
2273
2274 build_header(linker, table_data,
2275 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2276 }
2277
2278 static void
2279 build_tpm2(GArray *table_data, BIOSLinker *linker)
2280 {
2281 Acpi20TPM2 *tpm2_ptr;
2282
2283 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2284
2285 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2286 tpm2_ptr->control_area_address = cpu_to_le64(0);
2287 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2288
2289 build_header(linker, table_data,
2290 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2291 }
2292
2293 static void
2294 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2295 {
2296 AcpiSystemResourceAffinityTable *srat;
2297 AcpiSratProcessorAffinity *core;
2298 AcpiSratMemoryAffinity *numamem;
2299
2300 int i;
2301 uint64_t curnode;
2302 int srat_start, numa_start, slots;
2303 uint64_t mem_len, mem_base, next_base;
2304 MachineClass *mc = MACHINE_GET_CLASS(machine);
2305 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2306 PCMachineState *pcms = PC_MACHINE(machine);
2307 ram_addr_t hotplugabble_address_space_size =
2308 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2309 NULL);
2310
2311 srat_start = table_data->len;
2312
2313 srat = acpi_data_push(table_data, sizeof *srat);
2314 srat->reserved1 = cpu_to_le32(1);
2315
2316 for (i = 0; i < apic_ids->len; i++) {
2317 int apic_id = apic_ids->cpus[i].arch_id;
2318
2319 core = acpi_data_push(table_data, sizeof *core);
2320 core->type = ACPI_SRAT_PROCESSOR_APIC;
2321 core->length = sizeof(*core);
2322 core->local_apic_id = apic_id;
2323 curnode = pcms->node_cpu[apic_id];
2324 core->proximity_lo = curnode;
2325 memset(core->proximity_hi, 0, 3);
2326 core->local_sapic_eid = 0;
2327 core->flags = cpu_to_le32(1);
2328 }
2329
2330
2331 /* the memory map is a bit tricky, it contains at least one hole
2332 * from 640k-1M and possibly another one from 3.5G-4G.
2333 */
2334 next_base = 0;
2335 numa_start = table_data->len;
2336
2337 numamem = acpi_data_push(table_data, sizeof *numamem);
2338 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2339 next_base = 1024 * 1024;
2340 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2341 mem_base = next_base;
2342 mem_len = pcms->node_mem[i - 1];
2343 if (i == 1) {
2344 mem_len -= 1024 * 1024;
2345 }
2346 next_base = mem_base + mem_len;
2347
2348 /* Cut out the ACPI_PCI hole */
2349 if (mem_base <= pcms->below_4g_mem_size &&
2350 next_base > pcms->below_4g_mem_size) {
2351 mem_len -= next_base - pcms->below_4g_mem_size;
2352 if (mem_len > 0) {
2353 numamem = acpi_data_push(table_data, sizeof *numamem);
2354 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2355 MEM_AFFINITY_ENABLED);
2356 }
2357 mem_base = 1ULL << 32;
2358 mem_len = next_base - pcms->below_4g_mem_size;
2359 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2360 }
2361 numamem = acpi_data_push(table_data, sizeof *numamem);
2362 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2363 MEM_AFFINITY_ENABLED);
2364 }
2365 slots = (table_data->len - numa_start) / sizeof *numamem;
2366 for (; slots < pcms->numa_nodes + 2; slots++) {
2367 numamem = acpi_data_push(table_data, sizeof *numamem);
2368 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2369 }
2370
2371 /*
2372 * Entry is required for Windows to enable memory hotplug in OS.
2373 * Memory devices may override proximity set by this entry,
2374 * providing _PXM method if necessary.
2375 */
2376 if (hotplugabble_address_space_size) {
2377 numamem = acpi_data_push(table_data, sizeof *numamem);
2378 build_srat_memory(numamem, pcms->hotplug_memory.base,
2379 hotplugabble_address_space_size, 0,
2380 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2381 }
2382
2383 build_header(linker, table_data,
2384 (void *)(table_data->data + srat_start),
2385 "SRAT",
2386 table_data->len - srat_start, 1, NULL, NULL);
2387 g_free(apic_ids);
2388 }
2389
2390 static void
2391 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2392 {
2393 AcpiTableMcfg *mcfg;
2394 const char *sig;
2395 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2396
2397 mcfg = acpi_data_push(table_data, len);
2398 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2399 /* Only a single allocation so no need to play with segments */
2400 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2401 mcfg->allocation[0].start_bus_number = 0;
2402 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2403
2404 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2405 * To avoid table size changes (which create migration issues),
2406 * always create the table even if there are no allocations,
2407 * but set the signature to a reserved value in this case.
2408 * ACPI spec requires OSPMs to ignore such tables.
2409 */
2410 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2411 /* Reserved signature: ignored by OSPM */
2412 sig = "QEMU";
2413 } else {
2414 sig = "MCFG";
2415 }
2416 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2417 }
2418
2419 static void
2420 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2421 {
2422 int dmar_start = table_data->len;
2423
2424 AcpiTableDmar *dmar;
2425 AcpiDmarHardwareUnit *drhd;
2426
2427 dmar = acpi_data_push(table_data, sizeof(*dmar));
2428 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2429 dmar->flags = 0; /* No intr_remap for now */
2430
2431 /* DMAR Remapping Hardware Unit Definition structure */
2432 drhd = acpi_data_push(table_data, sizeof(*drhd));
2433 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2434 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2435 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2436 drhd->pci_segment = cpu_to_le16(0);
2437 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2438
2439 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2440 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2441 }
2442
2443 static GArray *
2444 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2445 {
2446 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2447 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2448 unsigned rsdt_pa_offset =
2449 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2450
2451 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2452 true /* fseg memory */);
2453
2454 memcpy(&rsdp->signature, "RSD PTR ", 8);
2455 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2456 /* Address to be filled by Guest linker */
2457 bios_linker_loader_add_pointer(linker,
2458 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2459 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2460
2461 /* Checksum to be filled by Guest linker */
2462 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2463 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2464 (char *)&rsdp->checksum - rsdp_table->data);
2465
2466 return rsdp_table;
2467 }
2468
2469 typedef
2470 struct AcpiBuildState {
2471 /* Copy of table in RAM (for patching). */
2472 MemoryRegion *table_mr;
2473 /* Is table patched? */
2474 uint8_t patched;
2475 void *rsdp;
2476 MemoryRegion *rsdp_mr;
2477 MemoryRegion *linker_mr;
2478 } AcpiBuildState;
2479
2480 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2481 {
2482 Object *pci_host;
2483 QObject *o;
2484
2485 pci_host = acpi_get_i386_pci_host();
2486 g_assert(pci_host);
2487
2488 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2489 if (!o) {
2490 return false;
2491 }
2492 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2493 qobject_decref(o);
2494
2495 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2496 assert(o);
2497 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2498 qobject_decref(o);
2499 return true;
2500 }
2501
2502 static bool acpi_has_iommu(void)
2503 {
2504 bool ambiguous;
2505 Object *intel_iommu;
2506
2507 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2508 &ambiguous);
2509 return intel_iommu && !ambiguous;
2510 }
2511
2512 static
2513 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2514 {
2515 PCMachineState *pcms = PC_MACHINE(machine);
2516 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2517 GArray *table_offsets;
2518 unsigned facs, dsdt, rsdt, fadt;
2519 AcpiPmInfo pm;
2520 AcpiMiscInfo misc;
2521 AcpiMcfgInfo mcfg;
2522 PcPciInfo pci;
2523 uint8_t *u;
2524 size_t aml_len = 0;
2525 GArray *tables_blob = tables->table_data;
2526 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2527
2528 acpi_get_pm_info(&pm);
2529 acpi_get_misc_info(&misc);
2530 acpi_get_pci_info(&pci);
2531 acpi_get_slic_oem(&slic_oem);
2532
2533 table_offsets = g_array_new(false, true /* clear */,
2534 sizeof(uint32_t));
2535 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2536
2537 bios_linker_loader_alloc(tables->linker,
2538 ACPI_BUILD_TABLE_FILE, tables_blob,
2539 64 /* Ensure FACS is aligned */,
2540 false /* high memory */);
2541
2542 /*
2543 * FACS is pointed to by FADT.
2544 * We place it first since it's the only table that has alignment
2545 * requirements.
2546 */
2547 facs = tables_blob->len;
2548 build_facs(tables_blob, tables->linker);
2549
2550 /* DSDT is pointed to by FADT */
2551 dsdt = tables_blob->len;
2552 build_dsdt(tables_blob, tables->linker, &pm, &misc, &pci, machine);
2553
2554 /* Count the size of the DSDT and SSDT, we will need it for legacy
2555 * sizing of ACPI tables.
2556 */
2557 aml_len += tables_blob->len - dsdt;
2558
2559 /* ACPI tables pointed to by RSDT */
2560 fadt = tables_blob->len;
2561 acpi_add_table(table_offsets, tables_blob);
2562 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2563 slic_oem.id, slic_oem.table_id);
2564 aml_len += tables_blob->len - fadt;
2565
2566 acpi_add_table(table_offsets, tables_blob);
2567 build_madt(tables_blob, tables->linker, pcms);
2568
2569 if (misc.has_hpet) {
2570 acpi_add_table(table_offsets, tables_blob);
2571 build_hpet(tables_blob, tables->linker);
2572 }
2573 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2574 acpi_add_table(table_offsets, tables_blob);
2575 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2576
2577 if (misc.tpm_version == TPM_VERSION_2_0) {
2578 acpi_add_table(table_offsets, tables_blob);
2579 build_tpm2(tables_blob, tables->linker);
2580 }
2581 }
2582 if (pcms->numa_nodes) {
2583 acpi_add_table(table_offsets, tables_blob);
2584 build_srat(tables_blob, tables->linker, machine);
2585 }
2586 if (acpi_get_mcfg(&mcfg)) {
2587 acpi_add_table(table_offsets, tables_blob);
2588 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2589 }
2590 if (acpi_has_iommu()) {
2591 acpi_add_table(table_offsets, tables_blob);
2592 build_dmar_q35(tables_blob, tables->linker);
2593 }
2594 if (pcms->acpi_nvdimm_state.is_enabled) {
2595 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2596 pcms->acpi_nvdimm_state.dsm_mem);
2597 }
2598
2599 /* Add tables supplied by user (if any) */
2600 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2601 unsigned len = acpi_table_len(u);
2602
2603 acpi_add_table(table_offsets, tables_blob);
2604 g_array_append_vals(tables_blob, u, len);
2605 }
2606
2607 /* RSDT is pointed to by RSDP */
2608 rsdt = tables_blob->len;
2609 build_rsdt(tables_blob, tables->linker, table_offsets,
2610 slic_oem.id, slic_oem.table_id);
2611
2612 /* RSDP is in FSEG memory, so allocate it separately */
2613 build_rsdp(tables->rsdp, tables->linker, rsdt);
2614
2615 /* We'll expose it all to Guest so we want to reduce
2616 * chance of size changes.
2617 *
2618 * We used to align the tables to 4k, but of course this would
2619 * too simple to be enough. 4k turned out to be too small an
2620 * alignment very soon, and in fact it is almost impossible to
2621 * keep the table size stable for all (max_cpus, max_memory_slots)
2622 * combinations. So the table size is always 64k for pc-i440fx-2.1
2623 * and we give an error if the table grows beyond that limit.
2624 *
2625 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2626 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2627 * than 2.0 and we can always pad the smaller tables with zeros. We can
2628 * then use the exact size of the 2.0 tables.
2629 *
2630 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2631 */
2632 if (pcmc->legacy_acpi_table_size) {
2633 /* Subtracting aml_len gives the size of fixed tables. Then add the
2634 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2635 */
2636 int legacy_aml_len =
2637 pcmc->legacy_acpi_table_size +
2638 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2639 int legacy_table_size =
2640 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2641 ACPI_BUILD_ALIGN_SIZE);
2642 if (tables_blob->len > legacy_table_size) {
2643 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2644 error_report("Warning: migration may not work.");
2645 }
2646 g_array_set_size(tables_blob, legacy_table_size);
2647 } else {
2648 /* Make sure we have a buffer in case we need to resize the tables. */
2649 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2650 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2651 error_report("Warning: ACPI tables are larger than 64k.");
2652 error_report("Warning: migration may not work.");
2653 error_report("Warning: please remove CPUs, NUMA nodes, "
2654 "memory slots or PCI bridges.");
2655 }
2656 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2657 }
2658
2659 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2660
2661 /* Cleanup memory that's no longer used. */
2662 g_array_free(table_offsets, true);
2663 }
2664
2665 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2666 {
2667 uint32_t size = acpi_data_len(data);
2668
2669 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2670 memory_region_ram_resize(mr, size, &error_abort);
2671
2672 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2673 memory_region_set_dirty(mr, 0, size);
2674 }
2675
2676 static void acpi_build_update(void *build_opaque)
2677 {
2678 AcpiBuildState *build_state = build_opaque;
2679 AcpiBuildTables tables;
2680
2681 /* No state to update or already patched? Nothing to do. */
2682 if (!build_state || build_state->patched) {
2683 return;
2684 }
2685 build_state->patched = 1;
2686
2687 acpi_build_tables_init(&tables);
2688
2689 acpi_build(&tables, MACHINE(qdev_get_machine()));
2690
2691 acpi_ram_update(build_state->table_mr, tables.table_data);
2692
2693 if (build_state->rsdp) {
2694 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2695 } else {
2696 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2697 }
2698
2699 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2700 acpi_build_tables_cleanup(&tables, true);
2701 }
2702
2703 static void acpi_build_reset(void *build_opaque)
2704 {
2705 AcpiBuildState *build_state = build_opaque;
2706 build_state->patched = 0;
2707 }
2708
2709 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2710 GArray *blob, const char *name,
2711 uint64_t max_size)
2712 {
2713 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2714 name, acpi_build_update, build_state);
2715 }
2716
2717 static const VMStateDescription vmstate_acpi_build = {
2718 .name = "acpi_build",
2719 .version_id = 1,
2720 .minimum_version_id = 1,
2721 .fields = (VMStateField[]) {
2722 VMSTATE_UINT8(patched, AcpiBuildState),
2723 VMSTATE_END_OF_LIST()
2724 },
2725 };
2726
2727 void acpi_setup(void)
2728 {
2729 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2730 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2731 AcpiBuildTables tables;
2732 AcpiBuildState *build_state;
2733
2734 if (!pcms->fw_cfg) {
2735 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2736 return;
2737 }
2738
2739 if (!pcmc->has_acpi_build) {
2740 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2741 return;
2742 }
2743
2744 if (!acpi_enabled) {
2745 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2746 return;
2747 }
2748
2749 build_state = g_malloc0(sizeof *build_state);
2750
2751 acpi_set_pci_info();
2752
2753 acpi_build_tables_init(&tables);
2754 acpi_build(&tables, MACHINE(pcms));
2755
2756 /* Now expose it all to Guest */
2757 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2758 ACPI_BUILD_TABLE_FILE,
2759 ACPI_BUILD_TABLE_MAX_SIZE);
2760 assert(build_state->table_mr != NULL);
2761
2762 build_state->linker_mr =
2763 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2764 "etc/table-loader", 0);
2765
2766 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2767 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2768
2769 if (!pcmc->rsdp_in_ram) {
2770 /*
2771 * Keep for compatibility with old machine types.
2772 * Though RSDP is small, its contents isn't immutable, so
2773 * we'll update it along with the rest of tables on guest access.
2774 */
2775 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2776
2777 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2778 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2779 acpi_build_update, build_state,
2780 build_state->rsdp, rsdp_size);
2781 build_state->rsdp_mr = NULL;
2782 } else {
2783 build_state->rsdp = NULL;
2784 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2785 ACPI_BUILD_RSDP_FILE, 0);
2786 }
2787
2788 qemu_register_reset(acpi_build_reset, build_state);
2789 acpi_build_reset(build_state);
2790 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2791
2792 /* Cleanup tables but don't free the memory: we track it
2793 * in build_state.
2794 */
2795 acpi_build_tables_cleanup(&tables, false);
2796 }
AR7 emulation for QEMU