2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/ppc/spapr_drc.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/kvm.h"
49 #include "sysemu/hostmem.h"
50 #include "sysemu/numa.h"
52 #include "hw/vfio/vfio.h"
54 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
55 #define RTAS_QUERY_FN 0
56 #define RTAS_CHANGE_FN 1
57 #define RTAS_RESET_FN 2
58 #define RTAS_CHANGE_MSI_FN 3
59 #define RTAS_CHANGE_MSIX_FN 4
61 /* Interrupt types to return on RTAS_CHANGE_* */
62 #define RTAS_TYPE_MSI 1
63 #define RTAS_TYPE_MSIX 2
65 #define FDT_NAME_MAX 128
75 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
)
79 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
80 if (sphb
->buid
!= buid
) {
89 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
92 sPAPRPHBState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
93 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
94 int bus_num
= (config_addr
>> 16) & 0xFF;
95 int devfn
= (config_addr
>> 8) & 0xFF;
101 return pci_find_device(phb
->bus
, bus_num
, devfn
);
104 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
106 /* This handles the encoding of extended config space addresses */
107 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
110 static void finish_read_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
111 uint32_t addr
, uint32_t size
,
117 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
118 /* access must be 1, 2 or 4 bytes */
119 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
123 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
124 addr
= rtas_pci_cfgaddr(addr
);
126 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
127 /* Access must be to a valid device, within bounds and
128 * naturally aligned */
129 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
133 val
= pci_host_config_read_common(pci_dev
, addr
,
134 pci_config_size(pci_dev
), size
);
136 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
137 rtas_st(rets
, 1, val
);
140 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
141 uint32_t token
, uint32_t nargs
,
143 uint32_t nret
, target_ulong rets
)
148 if ((nargs
!= 4) || (nret
!= 2)) {
149 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
153 buid
= rtas_ldq(args
, 1);
154 size
= rtas_ld(args
, 3);
155 addr
= rtas_ld(args
, 0);
157 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
160 static void rtas_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
161 uint32_t token
, uint32_t nargs
,
163 uint32_t nret
, target_ulong rets
)
167 if ((nargs
!= 2) || (nret
!= 2)) {
168 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
172 size
= rtas_ld(args
, 1);
173 addr
= rtas_ld(args
, 0);
175 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
178 static void finish_write_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
179 uint32_t addr
, uint32_t size
,
180 uint32_t val
, target_ulong rets
)
184 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
185 /* access must be 1, 2 or 4 bytes */
186 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
190 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
191 addr
= rtas_pci_cfgaddr(addr
);
193 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
194 /* Access must be to a valid device, within bounds and
195 * naturally aligned */
196 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
200 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
203 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
206 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
207 uint32_t token
, uint32_t nargs
,
209 uint32_t nret
, target_ulong rets
)
212 uint32_t val
, size
, addr
;
214 if ((nargs
!= 5) || (nret
!= 1)) {
215 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
219 buid
= rtas_ldq(args
, 1);
220 val
= rtas_ld(args
, 4);
221 size
= rtas_ld(args
, 3);
222 addr
= rtas_ld(args
, 0);
224 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
227 static void rtas_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
228 uint32_t token
, uint32_t nargs
,
230 uint32_t nret
, target_ulong rets
)
232 uint32_t val
, size
, addr
;
234 if ((nargs
!= 3) || (nret
!= 1)) {
235 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
240 val
= rtas_ld(args
, 2);
241 size
= rtas_ld(args
, 1);
242 addr
= rtas_ld(args
, 0);
244 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
248 * Set MSI/MSIX message data.
249 * This is required for msi_notify()/msix_notify() which
250 * will write at the addresses via spapr_msi_write().
252 * If hwaddr == 0, all entries will have .data == first_irq i.e.
253 * table will be reset.
255 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
256 unsigned first_irq
, unsigned req_num
)
259 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
262 msi_set_message(pdev
, msg
);
263 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
267 for (i
= 0; i
< req_num
; ++i
) {
268 msix_set_message(pdev
, i
, msg
);
269 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
276 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
277 uint32_t token
, uint32_t nargs
,
278 target_ulong args
, uint32_t nret
,
281 uint32_t config_addr
= rtas_ld(args
, 0);
282 uint64_t buid
= rtas_ldq(args
, 1);
283 unsigned int func
= rtas_ld(args
, 3);
284 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
285 unsigned int seq_num
= rtas_ld(args
, 5);
286 unsigned int ret_intr_type
;
287 unsigned int irq
, max_irqs
= 0;
288 sPAPRPHBState
*phb
= NULL
;
289 PCIDevice
*pdev
= NULL
;
291 int *config_addr_key
;
295 case RTAS_CHANGE_MSI_FN
:
297 ret_intr_type
= RTAS_TYPE_MSI
;
299 case RTAS_CHANGE_MSIX_FN
:
300 ret_intr_type
= RTAS_TYPE_MSIX
;
303 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
304 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
308 /* Fins sPAPRPHBState */
309 phb
= spapr_pci_find_phb(spapr
, buid
);
311 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
314 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
318 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
323 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
324 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
328 xics_spapr_free(spapr
->xics
, msi
->first_irq
, msi
->num
);
329 if (msi_present(pdev
)) {
330 spapr_msi_setmsg(pdev
, 0, false, 0, 0);
332 if (msix_present(pdev
)) {
333 spapr_msi_setmsg(pdev
, 0, true, 0, 0);
335 g_hash_table_remove(phb
->msi
, &config_addr
);
337 trace_spapr_pci_msi("Released MSIs", config_addr
);
338 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
345 /* Check if the device supports as many IRQs as requested */
346 if (ret_intr_type
== RTAS_TYPE_MSI
) {
347 max_irqs
= msi_nr_vectors_allocated(pdev
);
348 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
349 max_irqs
= pdev
->msix_entries_nr
;
352 error_report("Requested interrupt type %d is not enabled for device %x",
353 ret_intr_type
, config_addr
);
354 rtas_st(rets
, 0, -1); /* Hardware error */
357 /* Correct the number if the guest asked for too many */
358 if (req_num
> max_irqs
) {
359 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
361 irq
= 0; /* to avoid misleading trace */
366 irq
= xics_spapr_alloc_block(spapr
->xics
, req_num
, false,
367 ret_intr_type
== RTAS_TYPE_MSI
, &err
);
369 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
371 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
375 /* Release previous MSIs */
377 xics_spapr_free(spapr
->xics
, msi
->first_irq
, msi
->num
);
378 g_hash_table_remove(phb
->msi
, &config_addr
);
381 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
382 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
385 /* Add MSI device to cache */
386 msi
= g_new(spapr_pci_msi
, 1);
387 msi
->first_irq
= irq
;
389 config_addr_key
= g_new(int, 1);
390 *config_addr_key
= config_addr
;
391 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
394 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
395 rtas_st(rets
, 1, req_num
);
396 rtas_st(rets
, 2, ++seq_num
);
398 rtas_st(rets
, 3, ret_intr_type
);
401 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
404 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
405 sPAPRMachineState
*spapr
,
412 uint32_t config_addr
= rtas_ld(args
, 0);
413 uint64_t buid
= rtas_ldq(args
, 1);
414 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
415 sPAPRPHBState
*phb
= NULL
;
416 PCIDevice
*pdev
= NULL
;
419 /* Find sPAPRPHBState */
420 phb
= spapr_pci_find_phb(spapr
, buid
);
422 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
425 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
429 /* Find device descriptor and start IRQ */
430 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
431 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
432 trace_spapr_pci_msi("Failed to return vector", config_addr
);
433 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
436 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
437 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
440 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
441 rtas_st(rets
, 1, intr_src_num
);
442 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
445 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
446 sPAPRMachineState
*spapr
,
447 uint32_t token
, uint32_t nargs
,
448 target_ulong args
, uint32_t nret
,
452 uint32_t addr
, option
;
456 if ((nargs
!= 4) || (nret
!= 1)) {
457 goto param_error_exit
;
460 buid
= rtas_ldq(args
, 1);
461 addr
= rtas_ld(args
, 0);
462 option
= rtas_ld(args
, 3);
464 sphb
= spapr_pci_find_phb(spapr
, buid
);
466 goto param_error_exit
;
469 if (!spapr_phb_eeh_available(sphb
)) {
470 goto param_error_exit
;
473 ret
= spapr_phb_vfio_eeh_set_option(sphb
, addr
, option
);
474 rtas_st(rets
, 0, ret
);
478 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
481 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
482 sPAPRMachineState
*spapr
,
483 uint32_t token
, uint32_t nargs
,
484 target_ulong args
, uint32_t nret
,
489 uint32_t addr
, option
;
492 if ((nargs
!= 4) || (nret
!= 2)) {
493 goto param_error_exit
;
496 buid
= rtas_ldq(args
, 1);
497 sphb
= spapr_pci_find_phb(spapr
, buid
);
499 goto param_error_exit
;
502 if (!spapr_phb_eeh_available(sphb
)) {
503 goto param_error_exit
;
507 * We always have PE address of form "00BB0001". "BB"
508 * represents the bus number of PE's primary bus.
510 option
= rtas_ld(args
, 3);
512 case RTAS_GET_PE_ADDR
:
513 addr
= rtas_ld(args
, 0);
514 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
516 goto param_error_exit
;
519 rtas_st(rets
, 1, (pci_bus_num(pdev
->bus
) << 16) + 1);
521 case RTAS_GET_PE_MODE
:
522 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
525 goto param_error_exit
;
528 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
532 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
535 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
536 sPAPRMachineState
*spapr
,
537 uint32_t token
, uint32_t nargs
,
538 target_ulong args
, uint32_t nret
,
545 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
546 goto param_error_exit
;
549 buid
= rtas_ldq(args
, 1);
550 sphb
= spapr_pci_find_phb(spapr
, buid
);
552 goto param_error_exit
;
555 if (!spapr_phb_eeh_available(sphb
)) {
556 goto param_error_exit
;
559 ret
= spapr_phb_vfio_eeh_get_state(sphb
, &state
);
560 rtas_st(rets
, 0, ret
);
561 if (ret
!= RTAS_OUT_SUCCESS
) {
565 rtas_st(rets
, 1, state
);
566 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
567 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
569 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
574 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
577 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
578 sPAPRMachineState
*spapr
,
579 uint32_t token
, uint32_t nargs
,
580 target_ulong args
, uint32_t nret
,
588 if ((nargs
!= 4) || (nret
!= 1)) {
589 goto param_error_exit
;
592 buid
= rtas_ldq(args
, 1);
593 option
= rtas_ld(args
, 3);
594 sphb
= spapr_pci_find_phb(spapr
, buid
);
596 goto param_error_exit
;
599 if (!spapr_phb_eeh_available(sphb
)) {
600 goto param_error_exit
;
603 ret
= spapr_phb_vfio_eeh_reset(sphb
, option
);
604 rtas_st(rets
, 0, ret
);
608 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
611 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
612 sPAPRMachineState
*spapr
,
613 uint32_t token
, uint32_t nargs
,
614 target_ulong args
, uint32_t nret
,
621 if ((nargs
!= 3) || (nret
!= 1)) {
622 goto param_error_exit
;
625 buid
= rtas_ldq(args
, 1);
626 sphb
= spapr_pci_find_phb(spapr
, buid
);
628 goto param_error_exit
;
631 if (!spapr_phb_eeh_available(sphb
)) {
632 goto param_error_exit
;
635 ret
= spapr_phb_vfio_eeh_configure(sphb
);
636 rtas_st(rets
, 0, ret
);
640 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
643 /* To support it later */
644 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
645 sPAPRMachineState
*spapr
,
646 uint32_t token
, uint32_t nargs
,
647 target_ulong args
, uint32_t nret
,
654 if ((nargs
!= 8) || (nret
!= 1)) {
655 goto param_error_exit
;
658 buid
= rtas_ldq(args
, 1);
659 sphb
= spapr_pci_find_phb(spapr
, buid
);
661 goto param_error_exit
;
664 if (!spapr_phb_eeh_available(sphb
)) {
665 goto param_error_exit
;
668 option
= rtas_ld(args
, 7);
670 case RTAS_SLOT_TEMP_ERR_LOG
:
671 case RTAS_SLOT_PERM_ERR_LOG
:
674 goto param_error_exit
;
677 /* We don't have error log yet */
678 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
682 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
685 static int pci_spapr_swizzle(int slot
, int pin
)
687 return (slot
+ pin
) % PCI_NUM_PINS
;
690 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
693 * Here we need to convert pci_dev + irq_num to some unique value
694 * which is less than number of IRQs on the specific bus (4). We
695 * use standard PCI swizzling, that is (slot number + pin number)
698 return pci_spapr_swizzle(PCI_SLOT(pci_dev
->devfn
), irq_num
);
701 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
704 * Here we use the number returned by pci_spapr_map_irq to find a
705 * corresponding qemu_irq.
707 sPAPRPHBState
*phb
= opaque
;
709 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
710 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
713 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
715 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
718 route
.mode
= PCI_INTX_ENABLED
;
719 route
.irq
= sphb
->lsi_table
[pin
].irq
;
725 * MSI/MSIX memory region implementation.
726 * The handler handles both MSI and MSIX.
727 * For MSI-X, the vector number is encoded as a part of the address,
729 * For MSI, the vector number is encoded in least bits in data.
731 static void spapr_msi_write(void *opaque
, hwaddr addr
,
732 uint64_t data
, unsigned size
)
734 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
737 trace_spapr_pci_msi_write(addr
, data
, irq
);
739 qemu_irq_pulse(xics_get_qirq(spapr
->xics
, irq
));
742 static const MemoryRegionOps spapr_msi_ops
= {
743 /* There is no .read as the read result is undefined by PCI spec */
745 .write
= spapr_msi_write
,
746 .endianness
= DEVICE_LITTLE_ENDIAN
752 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
754 sPAPRPHBState
*phb
= opaque
;
756 return &phb
->iommu_as
;
759 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
761 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
763 /* Get the PCI VFIO host id */
764 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
769 /* Construct the path of the file that will give us the DT location */
770 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
772 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
777 /* Construct and read from host device tree the loc-code */
778 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
780 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
790 static char *spapr_phb_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
793 const char *devtype
= "qemu";
794 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
796 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
797 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
804 * For emulated devices and VFIO-failure case, make up
807 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
808 devtype
, pdev
->name
, sphb
->index
, busnr
,
809 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
813 /* Macros to operate with address in OF binding to PCI */
814 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
815 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
816 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
817 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
818 #define b_ss(x) b_x((x), 24, 2) /* the space code */
819 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
820 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
821 #define b_fff(x) b_x((x), 8, 3) /* function number */
822 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
824 /* for 'reg'/'assigned-addresses' OF properties */
825 #define RESOURCE_CELLS_SIZE 2
826 #define RESOURCE_CELLS_ADDRESS 3
828 typedef struct ResourceFields
{
834 } QEMU_PACKED ResourceFields
;
836 typedef struct ResourceProps
{
837 ResourceFields reg
[8];
838 ResourceFields assigned
[7];
840 uint32_t assigned_len
;
843 /* fill in the 'reg'/'assigned-resources' OF properties for
844 * a PCI device. 'reg' describes resource requirements for a
845 * device's IO/MEM regions, 'assigned-addresses' describes the
846 * actual resource assignments.
848 * the properties are arrays of ('phys-addr', 'size') pairs describing
849 * the addressable regions of the PCI device, where 'phys-addr' is a
850 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
851 * (phys.hi, phys.mid, phys.lo), and 'size' is a
852 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
854 * phys.hi = 0xYYXXXXZZ, where:
859 * ||| + 00 if configuration space
860 * ||| + 01 if IO region,
861 * ||| + 10 if 32-bit MEM region
862 * ||| + 11 if 64-bit MEM region
864 * ||+------ for non-relocatable IO: 1 if aliased
865 * || for relocatable IO: 1 if below 64KB
866 * || for MEM: 1 if below 1MB
867 * |+------- 1 if region is prefetchable
868 * +-------- 1 if region is non-relocatable
869 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
871 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
874 * phys.mid and phys.lo correspond respectively to the hi/lo portions
875 * of the actual address of the region.
877 * how the phys-addr/size values are used differ slightly between
878 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
879 * an additional description for the config space region of the
880 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
881 * to describe the region as relocatable, with an address-mapping
882 * that corresponds directly to the PHB's address space for the
883 * resource. 'assigned-addresses' always has n=1 set with an absolute
884 * address assigned for the resource. in general, 'assigned-addresses'
885 * won't be populated, since addresses for PCI devices are generally
886 * unmapped initially and left to the guest to assign.
888 * note also that addresses defined in these properties are, at least
889 * for PAPR guests, relative to the PHBs IO/MEM windows, and
890 * correspond directly to the addresses in the BARs.
892 * in accordance with PCI Bus Binding to Open Firmware,
893 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
896 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
898 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
899 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
900 b_ddddd(PCI_SLOT(d
->devfn
)) |
901 b_fff(PCI_FUNC(d
->devfn
)));
902 ResourceFields
*reg
, *assigned
;
903 int i
, reg_idx
= 0, assigned_idx
= 0;
905 /* config space region */
906 reg
= &rp
->reg
[reg_idx
++];
907 reg
->phys_hi
= cpu_to_be32(dev_id
);
913 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
914 if (!d
->io_regions
[i
].size
) {
918 reg
= &rp
->reg
[reg_idx
++];
920 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
921 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
922 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
923 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
924 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
926 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
930 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
931 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
933 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
937 assigned
= &rp
->assigned
[assigned_idx
++];
938 assigned
->phys_hi
= cpu_to_be32(reg
->phys_hi
| b_n(1));
939 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
940 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
941 assigned
->size_hi
= reg
->size_hi
;
942 assigned
->size_lo
= reg
->size_lo
;
945 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
946 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
949 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
952 static int spapr_populate_pci_child_dt(PCIDevice
*dev
, void *fdt
, int offset
,
956 bool is_bridge
= false;
959 uint32_t drc_index
= spapr_phb_get_pci_drc_index(sphb
, dev
);
960 uint32_t max_msi
, max_msix
;
962 if (pci_default_read_config(dev
, PCI_HEADER_TYPE
, 1) ==
963 PCI_HEADER_TYPE_BRIDGE
) {
967 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
968 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id",
969 pci_default_read_config(dev
, PCI_VENDOR_ID
, 2)));
970 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id",
971 pci_default_read_config(dev
, PCI_DEVICE_ID
, 2)));
972 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id",
973 pci_default_read_config(dev
, PCI_REVISION_ID
, 1)));
974 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code",
975 pci_default_read_config(dev
, PCI_CLASS_PROG
, 3)));
976 if (pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)) {
977 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts",
978 pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)));
982 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant",
983 pci_default_read_config(dev
, PCI_MIN_GNT
, 1)));
984 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency",
985 pci_default_read_config(dev
, PCI_MAX_LAT
, 1)));
988 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)) {
989 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id",
990 pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)));
993 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)) {
994 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
995 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)));
998 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size",
999 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1)));
1001 /* the following fdt cells are masked off the pci status register */
1002 pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
1003 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
1004 PCI_STATUS_DEVSEL_MASK
& pci_status
));
1006 if (pci_status
& PCI_STATUS_FAST_BACK
) {
1007 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
1009 if (pci_status
& PCI_STATUS_66MHZ
) {
1010 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1012 if (pci_status
& PCI_STATUS_UDF
) {
1013 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1016 /* NOTE: this is normally generated by firmware via path/unit name,
1017 * but in our case we must set it manually since it does not get
1018 * processed by OF beforehand
1020 _FDT(fdt_setprop_string(fdt
, offset
, "name", "pci"));
1021 buf
= spapr_phb_get_loc_code(sphb
, dev
);
1023 error_report("Failed setting the ibm,loc-code");
1027 err
= fdt_setprop_string(fdt
, offset
, "ibm,loc-code", buf
);
1034 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
));
1037 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1038 RESOURCE_CELLS_ADDRESS
));
1039 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1040 RESOURCE_CELLS_SIZE
));
1042 max_msi
= msi_nr_vectors_allocated(dev
);
1044 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi", max_msi
));
1046 max_msix
= dev
->msix_entries_nr
;
1048 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x", max_msix
));
1051 populate_resource_props(dev
, &rp
);
1052 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1053 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
1054 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
1059 /* create OF node for pci device and required OF DT properties */
1060 static int spapr_create_pci_child_dt(sPAPRPHBState
*phb
, PCIDevice
*dev
,
1061 void *fdt
, int node_offset
)
1064 int slot
= PCI_SLOT(dev
->devfn
);
1065 int func
= PCI_FUNC(dev
->devfn
);
1066 char nodename
[FDT_NAME_MAX
];
1069 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x,%x", slot
, func
);
1071 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x", slot
);
1073 offset
= fdt_add_subnode(fdt
, node_offset
, nodename
);
1074 ret
= spapr_populate_pci_child_dt(dev
, fdt
, offset
, phb
);
1083 static void spapr_phb_add_pci_device(sPAPRDRConnector
*drc
,
1088 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1089 DeviceState
*dev
= DEVICE(pdev
);
1091 int fdt_start_offset
= 0, fdt_size
;
1093 fdt
= create_device_tree(&fdt_size
);
1094 fdt_start_offset
= spapr_create_pci_child_dt(phb
, pdev
, fdt
, 0);
1095 if (!fdt_start_offset
) {
1096 error_setg(errp
, "Failed to create pci child device tree node");
1100 drck
->attach(drc
, DEVICE(pdev
),
1101 fdt
, fdt_start_offset
, !dev
->hotplugged
, errp
);
1108 static void spapr_phb_remove_pci_device_cb(DeviceState
*dev
, void *opaque
)
1110 /* some version guests do not wait for completion of a device
1111 * cleanup (generally done asynchronously by the kernel) before
1112 * signaling to QEMU that the device is safe, but instead sleep
1113 * for some 'safe' period of time. unfortunately on a busy host
1114 * this sleep isn't guaranteed to be long enough, resulting in
1115 * bad things like IRQ lines being left asserted during final
1116 * device removal. to deal with this we call reset just prior
1117 * to finalizing the device, which will put the device back into
1118 * an 'idle' state, as the device cleanup code expects.
1120 pci_device_reset(PCI_DEVICE(dev
));
1121 object_unparent(OBJECT(dev
));
1124 static void spapr_phb_remove_pci_device(sPAPRDRConnector
*drc
,
1129 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1131 drck
->detach(drc
, DEVICE(pdev
), spapr_phb_remove_pci_device_cb
, phb
, errp
);
1134 static sPAPRDRConnector
*spapr_phb_get_pci_func_drc(sPAPRPHBState
*phb
,
1138 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI
,
1139 (phb
->index
<< 16) |
1144 static sPAPRDRConnector
*spapr_phb_get_pci_drc(sPAPRPHBState
*phb
,
1147 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
1148 return spapr_phb_get_pci_func_drc(phb
, busnr
, pdev
->devfn
);
1151 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
1154 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1155 sPAPRDRConnectorClass
*drck
;
1161 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1162 return drck
->get_index(drc
);
1165 static void spapr_phb_hot_plug_child(HotplugHandler
*plug_handler
,
1166 DeviceState
*plugged_dev
, Error
**errp
)
1168 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1169 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1170 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1171 Error
*local_err
= NULL
;
1172 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1173 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1175 /* if DR is disabled we don't need to do anything in the case of
1176 * hotplug or coldplug callbacks
1178 if (!phb
->dr_enabled
) {
1179 /* if this is a hotplug operation initiated by the user
1180 * we need to let them know it's not enabled
1182 if (plugged_dev
->hotplugged
) {
1183 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1184 object_get_typename(OBJECT(phb
)));
1191 /* Following the QEMU convention used for PCIe multifunction
1192 * hotplug, we do not allow functions to be hotplugged to a
1193 * slot that already has function 0 present
1195 if (plugged_dev
->hotplugged
&& bus
->devices
[PCI_DEVFN(slotnr
, 0)] &&
1196 PCI_FUNC(pdev
->devfn
) != 0) {
1197 error_setg(errp
, "PCI: slot %d function 0 already ocuppied by %s,"
1198 " additional functions can no longer be exposed to guest.",
1199 slotnr
, bus
->devices
[PCI_DEVFN(slotnr
, 0)]->name
);
1203 spapr_phb_add_pci_device(drc
, phb
, pdev
, &local_err
);
1205 error_propagate(errp
, local_err
);
1209 /* If this is function 0, signal hotplug for all the device functions.
1210 * Otherwise defer sending the hotplug event.
1212 if (plugged_dev
->hotplugged
&& PCI_FUNC(pdev
->devfn
) == 0) {
1215 for (i
= 0; i
< 8; i
++) {
1216 sPAPRDRConnector
*func_drc
;
1217 sPAPRDRConnectorClass
*func_drck
;
1218 sPAPRDREntitySense state
;
1220 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1221 PCI_DEVFN(slotnr
, i
));
1222 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1223 func_drck
->entity_sense(func_drc
, &state
);
1225 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1226 spapr_hotplug_req_add_by_index(func_drc
);
1232 static void spapr_phb_hot_unplug_child(HotplugHandler
*plug_handler
,
1233 DeviceState
*plugged_dev
, Error
**errp
)
1235 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1236 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1237 sPAPRDRConnectorClass
*drck
;
1238 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1239 Error
*local_err
= NULL
;
1241 if (!phb
->dr_enabled
) {
1242 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1243 object_get_typename(OBJECT(phb
)));
1249 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1250 if (!drck
->release_pending(drc
)) {
1251 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1252 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1253 sPAPRDRConnector
*func_drc
;
1254 sPAPRDRConnectorClass
*func_drck
;
1255 sPAPRDREntitySense state
;
1258 /* ensure any other present functions are pending unplug */
1259 if (PCI_FUNC(pdev
->devfn
) == 0) {
1260 for (i
= 1; i
< 8; i
++) {
1261 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1262 PCI_DEVFN(slotnr
, i
));
1263 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1264 func_drck
->entity_sense(func_drc
, &state
);
1265 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
1266 && !func_drck
->release_pending(func_drc
)) {
1268 "PCI: slot %d, function %d still present. "
1269 "Must unplug all non-0 functions first.",
1276 spapr_phb_remove_pci_device(drc
, phb
, pdev
, &local_err
);
1278 error_propagate(errp
, local_err
);
1282 /* if this isn't func 0, defer unplug event. otherwise signal removal
1283 * for all present functions
1285 if (PCI_FUNC(pdev
->devfn
) == 0) {
1286 for (i
= 7; i
>= 0; i
--) {
1287 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1288 PCI_DEVFN(slotnr
, i
));
1289 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1290 func_drck
->entity_sense(func_drc
, &state
);
1291 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1292 spapr_hotplug_req_remove_by_index(func_drc
);
1299 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1301 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1302 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1303 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1304 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1308 uint64_t msi_window_size
= 4096;
1309 sPAPRTCETable
*tcet
;
1310 const unsigned windows_supported
=
1311 sphb
->ddw_enabled
? SPAPR_PCI_DMA_MAX_WINDOWS
: 1;
1313 if (sphb
->index
!= (uint32_t)-1) {
1314 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
1315 Error
*local_err
= NULL
;
1317 if ((sphb
->buid
!= (uint64_t)-1) || (sphb
->dma_liobn
[0] != (uint32_t)-1)
1318 || (sphb
->dma_liobn
[1] != (uint32_t)-1 && windows_supported
== 2)
1319 || (sphb
->mem_win_addr
!= (hwaddr
)-1)
1320 || (sphb
->mem64_win_addr
!= (hwaddr
)-1)
1321 || (sphb
->io_win_addr
!= (hwaddr
)-1)) {
1322 error_setg(errp
, "Either \"index\" or other parameters must"
1323 " be specified for PAPR PHB, not both");
1327 smc
->phb_placement(spapr
, sphb
->index
,
1328 &sphb
->buid
, &sphb
->io_win_addr
,
1329 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
1330 windows_supported
, sphb
->dma_liobn
, &local_err
);
1332 error_propagate(errp
, local_err
);
1337 if (sphb
->buid
== (uint64_t)-1) {
1338 error_setg(errp
, "BUID not specified for PHB");
1342 if ((sphb
->dma_liobn
[0] == (uint32_t)-1) ||
1343 ((sphb
->dma_liobn
[1] == (uint32_t)-1) && (windows_supported
> 1))) {
1344 error_setg(errp
, "LIOBN(s) not specified for PHB");
1348 if (sphb
->mem_win_addr
== (hwaddr
)-1) {
1349 error_setg(errp
, "Memory window address not specified for PHB");
1353 if (sphb
->io_win_addr
== (hwaddr
)-1) {
1354 error_setg(errp
, "IO window address not specified for PHB");
1358 if (sphb
->mem64_win_size
!= 0) {
1359 if (sphb
->mem64_win_addr
== (hwaddr
)-1) {
1361 "64-bit memory window address not specified for PHB");
1365 if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1366 error_setg(errp
, "32-bit memory window of size 0x%"HWADDR_PRIx
1367 " (max 2 GiB)", sphb
->mem_win_size
);
1371 if (sphb
->mem64_win_pciaddr
== (hwaddr
)-1) {
1372 /* 64-bit window defaults to identity mapping */
1373 sphb
->mem64_win_pciaddr
= sphb
->mem64_win_addr
;
1375 } else if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1377 * For compatibility with old configuration, if no 64-bit MMIO
1378 * window is specified, but the ordinary (32-bit) memory
1379 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1380 * window, with a 64-bit MMIO window following on immediately
1383 sphb
->mem64_win_size
= sphb
->mem_win_size
- SPAPR_PCI_MEM32_WIN_SIZE
;
1384 sphb
->mem64_win_addr
= sphb
->mem_win_addr
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1385 sphb
->mem64_win_pciaddr
=
1386 SPAPR_PCI_MEM_WIN_BUS_OFFSET
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1387 sphb
->mem_win_size
= SPAPR_PCI_MEM32_WIN_SIZE
;
1390 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1391 error_setg(errp
, "PCI host bridges must have unique BUIDs");
1395 if (sphb
->numa_node
!= -1 &&
1396 (sphb
->numa_node
>= MAX_NODES
|| !numa_info
[sphb
->numa_node
].present
)) {
1397 error_setg(errp
, "Invalid NUMA node ID for PCI host bridge");
1401 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1403 namebuf
= alloca(strlen(sphb
->dtbusname
) + 32);
1405 /* Initialize memory regions */
1406 sprintf(namebuf
, "%s.mmio", sphb
->dtbusname
);
1407 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1409 sprintf(namebuf
, "%s.mmio32-alias", sphb
->dtbusname
);
1410 memory_region_init_alias(&sphb
->mem32window
, OBJECT(sphb
),
1411 namebuf
, &sphb
->memspace
,
1412 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1413 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1414 &sphb
->mem32window
);
1416 sprintf(namebuf
, "%s.mmio64-alias", sphb
->dtbusname
);
1417 memory_region_init_alias(&sphb
->mem64window
, OBJECT(sphb
),
1418 namebuf
, &sphb
->memspace
,
1419 sphb
->mem64_win_pciaddr
, sphb
->mem64_win_size
);
1420 memory_region_add_subregion(get_system_memory(), sphb
->mem64_win_addr
,
1421 &sphb
->mem64window
);
1423 /* Initialize IO regions */
1424 sprintf(namebuf
, "%s.io", sphb
->dtbusname
);
1425 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1426 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1428 sprintf(namebuf
, "%s.io-alias", sphb
->dtbusname
);
1429 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1430 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1431 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1434 bus
= pci_register_bus(dev
, NULL
,
1435 pci_spapr_set_irq
, pci_spapr_map_irq
, sphb
,
1436 &sphb
->memspace
, &sphb
->iospace
,
1437 PCI_DEVFN(0, 0), PCI_NUM_PINS
, TYPE_PCI_BUS
);
1439 qbus_set_hotplug_handler(BUS(phb
->bus
), DEVICE(sphb
), NULL
);
1442 * Initialize PHB address space.
1443 * By default there will be at least one subregion for default
1445 * Later the guest might want to create another DMA window
1446 * which will become another memory subregion.
1448 sprintf(namebuf
, "%s.iommu-root", sphb
->dtbusname
);
1450 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1451 namebuf
, UINT64_MAX
);
1452 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1456 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1457 * we need to allocate some memory to catch those writes coming
1458 * from msi_notify()/msix_notify().
1459 * As MSIMessage:addr is going to be the same and MSIMessage:data
1460 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1463 * For KVM we want to ensure that this memory is a full page so that
1464 * our memory slot is of page size granularity.
1467 if (kvm_enabled()) {
1468 msi_window_size
= getpagesize();
1472 memory_region_init_io(&sphb
->msiwindow
, NULL
, &spapr_msi_ops
, spapr
,
1473 "msi", msi_window_size
);
1474 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1477 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1479 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1481 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1483 /* Initialize the LSI table */
1484 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1486 Error
*local_err
= NULL
;
1488 irq
= xics_spapr_alloc_block(spapr
->xics
, 1, true, false, &local_err
);
1490 error_propagate(errp
, local_err
);
1491 error_prepend(errp
, "can't allocate LSIs: ");
1495 sphb
->lsi_table
[i
].irq
= irq
;
1498 /* allocate connectors for child PCI devices */
1499 if (sphb
->dr_enabled
) {
1500 for (i
= 0; i
< PCI_SLOT_MAX
* 8; i
++) {
1501 spapr_dr_connector_new(OBJECT(phb
),
1502 SPAPR_DR_CONNECTOR_TYPE_PCI
,
1503 (sphb
->index
<< 16) | i
);
1508 for (i
= 0; i
< windows_supported
; ++i
) {
1509 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
[i
]);
1511 error_setg(errp
, "Creating window#%d failed for %s",
1512 i
, sphb
->dtbusname
);
1515 memory_region_add_subregion_overlap(&sphb
->iommu_root
, 0,
1516 spapr_tce_get_iommu(tcet
), 0);
1519 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
1522 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
1524 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
1533 void spapr_phb_dma_reset(sPAPRPHBState
*sphb
)
1536 sPAPRTCETable
*tcet
;
1538 for (i
= 0; i
< SPAPR_PCI_DMA_MAX_WINDOWS
; ++i
) {
1539 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
1541 if (tcet
&& tcet
->nb_table
) {
1542 spapr_tce_table_disable(tcet
);
1546 /* Register default 32bit DMA window */
1547 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[0]);
1548 spapr_tce_table_enable(tcet
, SPAPR_TCE_PAGE_SHIFT
, sphb
->dma_win_addr
,
1549 sphb
->dma_win_size
>> SPAPR_TCE_PAGE_SHIFT
);
1552 static void spapr_phb_reset(DeviceState
*qdev
)
1554 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(qdev
);
1556 spapr_phb_dma_reset(sphb
);
1558 /* Reset the IOMMU state */
1559 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
1561 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev
))) {
1562 spapr_phb_vfio_reset(qdev
);
1566 static Property spapr_phb_properties
[] = {
1567 DEFINE_PROP_UINT32("index", sPAPRPHBState
, index
, -1),
1568 DEFINE_PROP_UINT64("buid", sPAPRPHBState
, buid
, -1),
1569 DEFINE_PROP_UINT32("liobn", sPAPRPHBState
, dma_liobn
[0], -1),
1570 DEFINE_PROP_UINT32("liobn64", sPAPRPHBState
, dma_liobn
[1], -1),
1571 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState
, mem_win_addr
, -1),
1572 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState
, mem_win_size
,
1573 SPAPR_PCI_MEM32_WIN_SIZE
),
1574 DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState
, mem64_win_addr
, -1),
1575 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState
, mem64_win_size
,
1576 SPAPR_PCI_MEM64_WIN_SIZE
),
1577 DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState
, mem64_win_pciaddr
,
1579 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState
, io_win_addr
, -1),
1580 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState
, io_win_size
,
1581 SPAPR_PCI_IO_WIN_SIZE
),
1582 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState
, dr_enabled
,
1584 /* Default DMA window is 0..1GB */
1585 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState
, dma_win_addr
, 0),
1586 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState
, dma_win_size
, 0x40000000),
1587 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState
, dma64_win_addr
,
1588 0x800000000000000ULL
),
1589 DEFINE_PROP_BOOL("ddw", sPAPRPHBState
, ddw_enabled
, true),
1590 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState
, page_size_mask
,
1591 (1ULL << 12) | (1ULL << 16)),
1592 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState
, numa_node
, -1),
1593 DEFINE_PROP_END_OF_LIST(),
1596 static const VMStateDescription vmstate_spapr_pci_lsi
= {
1597 .name
= "spapr_pci/lsi",
1599 .minimum_version_id
= 1,
1600 .fields
= (VMStateField
[]) {
1601 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
),
1603 VMSTATE_END_OF_LIST()
1607 static const VMStateDescription vmstate_spapr_pci_msi
= {
1608 .name
= "spapr_pci/msi",
1610 .minimum_version_id
= 1,
1611 .fields
= (VMStateField
[]) {
1612 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
1613 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
1614 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
1615 VMSTATE_END_OF_LIST()
1619 static void spapr_pci_pre_save(void *opaque
)
1621 sPAPRPHBState
*sphb
= opaque
;
1622 GHashTableIter iter
;
1623 gpointer key
, value
;
1626 g_free(sphb
->msi_devs
);
1627 sphb
->msi_devs
= NULL
;
1628 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
1629 if (!sphb
->msi_devs_num
) {
1632 sphb
->msi_devs
= g_malloc(sphb
->msi_devs_num
* sizeof(spapr_pci_msi_mig
));
1634 g_hash_table_iter_init(&iter
, sphb
->msi
);
1635 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
1636 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
1637 sphb
->msi_devs
[i
].value
= *(spapr_pci_msi
*) value
;
1641 static int spapr_pci_post_load(void *opaque
, int version_id
)
1643 sPAPRPHBState
*sphb
= opaque
;
1644 gpointer key
, value
;
1647 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
1648 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
1649 sizeof(sphb
->msi_devs
[i
].key
));
1650 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
1651 sizeof(sphb
->msi_devs
[i
].value
));
1652 g_hash_table_insert(sphb
->msi
, key
, value
);
1654 g_free(sphb
->msi_devs
);
1655 sphb
->msi_devs
= NULL
;
1656 sphb
->msi_devs_num
= 0;
1661 static const VMStateDescription vmstate_spapr_pci
= {
1662 .name
= "spapr_pci",
1664 .minimum_version_id
= 2,
1665 .pre_save
= spapr_pci_pre_save
,
1666 .post_load
= spapr_pci_post_load
,
1667 .fields
= (VMStateField
[]) {
1668 VMSTATE_UINT64_EQUAL(buid
, sPAPRPHBState
),
1669 VMSTATE_UINT32_EQUAL(dma_liobn
[0], sPAPRPHBState
),
1670 VMSTATE_UINT64_EQUAL(mem_win_addr
, sPAPRPHBState
),
1671 VMSTATE_UINT64_EQUAL(mem_win_size
, sPAPRPHBState
),
1672 VMSTATE_UINT64_EQUAL(io_win_addr
, sPAPRPHBState
),
1673 VMSTATE_UINT64_EQUAL(io_win_size
, sPAPRPHBState
),
1674 VMSTATE_STRUCT_ARRAY(lsi_table
, sPAPRPHBState
, PCI_NUM_PINS
, 0,
1675 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
1676 VMSTATE_INT32(msi_devs_num
, sPAPRPHBState
),
1677 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, sPAPRPHBState
, msi_devs_num
, 0,
1678 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
1679 VMSTATE_END_OF_LIST()
1683 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
1686 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
1688 return sphb
->dtbusname
;
1691 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
1693 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
1694 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1695 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
1697 hc
->root_bus_path
= spapr_phb_root_bus_path
;
1698 dc
->realize
= spapr_phb_realize
;
1699 dc
->props
= spapr_phb_properties
;
1700 dc
->reset
= spapr_phb_reset
;
1701 dc
->vmsd
= &vmstate_spapr_pci
;
1702 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1703 hp
->plug
= spapr_phb_hot_plug_child
;
1704 hp
->unplug
= spapr_phb_hot_unplug_child
;
1707 static const TypeInfo spapr_phb_info
= {
1708 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
1709 .parent
= TYPE_PCI_HOST_BRIDGE
,
1710 .instance_size
= sizeof(sPAPRPHBState
),
1711 .class_init
= spapr_phb_class_init
,
1712 .interfaces
= (InterfaceInfo
[]) {
1713 { TYPE_HOTPLUG_HANDLER
},
1718 PCIHostState
*spapr_create_phb(sPAPRMachineState
*spapr
, int index
)
1722 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1723 qdev_prop_set_uint32(dev
, "index", index
);
1724 qdev_init_nofail(dev
);
1726 return PCI_HOST_BRIDGE(dev
);
1729 typedef struct sPAPRFDT
{
1732 sPAPRPHBState
*sphb
;
1735 static void spapr_populate_pci_devices_dt(PCIBus
*bus
, PCIDevice
*pdev
,
1739 sPAPRFDT
*p
= opaque
;
1743 offset
= spapr_create_pci_child_dt(p
->sphb
, pdev
, p
->fdt
, p
->node_off
);
1745 error_report("Failed to create pci child device tree node");
1749 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1750 PCI_HEADER_TYPE_BRIDGE
)) {
1754 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1760 s_fdt
.node_off
= offset
;
1761 s_fdt
.sphb
= p
->sphb
;
1762 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1763 spapr_populate_pci_devices_dt
,
1767 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
1770 unsigned int *bus_no
= opaque
;
1771 unsigned int primary
= *bus_no
;
1772 unsigned int subordinate
= 0xff;
1773 PCIBus
*sec_bus
= NULL
;
1775 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1776 PCI_HEADER_TYPE_BRIDGE
)) {
1781 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, primary
, 1);
1782 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
1783 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1785 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1790 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, subordinate
, 1);
1791 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1792 spapr_phb_pci_enumerate_bridge
, bus_no
);
1793 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1796 static void spapr_phb_pci_enumerate(sPAPRPHBState
*phb
)
1798 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1799 unsigned int bus_no
= 0;
1801 pci_for_each_device(bus
, pci_bus_num(bus
),
1802 spapr_phb_pci_enumerate_bridge
,
1807 int spapr_populate_pci_dt(sPAPRPHBState
*phb
,
1808 uint32_t xics_phandle
,
1811 int bus_off
, i
, j
, ret
;
1812 char nodename
[FDT_NAME_MAX
];
1813 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
1819 } QEMU_PACKED ranges
[] = {
1821 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
1822 cpu_to_be64(phb
->io_win_addr
),
1823 cpu_to_be64(memory_region_size(&phb
->iospace
)),
1826 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
1827 cpu_to_be64(phb
->mem_win_addr
),
1828 cpu_to_be64(phb
->mem_win_size
),
1831 cpu_to_be32(b_ss(3)), cpu_to_be64(phb
->mem64_win_pciaddr
),
1832 cpu_to_be64(phb
->mem64_win_addr
),
1833 cpu_to_be64(phb
->mem64_win_size
),
1836 const unsigned sizeof_ranges
=
1837 (phb
->mem64_win_size
? 3 : 2) * sizeof(ranges
[0]);
1838 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
1839 uint32_t interrupt_map_mask
[] = {
1840 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
1841 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
1842 uint32_t ddw_applicable
[] = {
1843 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW
),
1844 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW
),
1845 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW
)
1847 uint32_t ddw_extensions
[] = {
1849 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW
)
1851 uint32_t associativity
[] = {cpu_to_be32(0x4),
1855 cpu_to_be32(phb
->numa_node
)};
1856 sPAPRTCETable
*tcet
;
1857 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1860 /* Start populating the FDT */
1861 snprintf(nodename
, FDT_NAME_MAX
, "pci@%" PRIx64
, phb
->buid
);
1862 bus_off
= fdt_add_subnode(fdt
, 0, nodename
);
1867 /* Write PHB properties */
1868 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
1869 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
1870 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
1871 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
1872 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
1873 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
1874 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
1875 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
1876 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
1877 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
1878 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", XICS_IRQS_SPAPR
));
1880 /* Dynamic DMA window */
1881 if (phb
->ddw_enabled
) {
1882 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-applicable", &ddw_applicable
,
1883 sizeof(ddw_applicable
)));
1884 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-extensions",
1885 &ddw_extensions
, sizeof(ddw_extensions
)));
1888 /* Advertise NUMA via ibm,associativity */
1889 if (phb
->numa_node
!= -1) {
1890 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,associativity", associativity
,
1891 sizeof(associativity
)));
1894 /* Build the interrupt-map, this must matches what is done
1895 * in pci_spapr_map_irq
1897 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
1898 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
1899 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
1900 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
1901 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
1902 int lsi_num
= pci_spapr_swizzle(i
, j
);
1904 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
1907 irqmap
[3] = cpu_to_be32(j
+1);
1908 irqmap
[4] = cpu_to_be32(xics_phandle
);
1909 irqmap
[5] = cpu_to_be32(phb
->lsi_table
[lsi_num
].irq
);
1910 irqmap
[6] = cpu_to_be32(0x8);
1913 /* Write interrupt map */
1914 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
1915 sizeof(interrupt_map
)));
1917 tcet
= spapr_tce_find_by_liobn(phb
->dma_liobn
[0]);
1921 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
1922 tcet
->liobn
, tcet
->bus_offset
,
1923 tcet
->nb_table
<< tcet
->page_shift
);
1925 /* Walk the bridges and program the bus numbers*/
1926 spapr_phb_pci_enumerate(phb
);
1927 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
1929 /* Populate tree nodes with PCI devices attached */
1931 s_fdt
.node_off
= bus_off
;
1933 pci_for_each_device(bus
, pci_bus_num(bus
),
1934 spapr_populate_pci_devices_dt
,
1937 ret
= spapr_drc_populate_dt(fdt
, bus_off
, OBJECT(phb
),
1938 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1946 void spapr_pci_rtas_init(void)
1948 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
1949 rtas_read_pci_config
);
1950 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
1951 rtas_write_pci_config
);
1952 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
1953 rtas_ibm_read_pci_config
);
1954 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
1955 rtas_ibm_write_pci_config
);
1956 if (msi_nonbroken
) {
1957 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
1958 "ibm,query-interrupt-source-number",
1959 rtas_ibm_query_interrupt_source_number
);
1960 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
1961 rtas_ibm_change_msi
);
1964 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
1965 "ibm,set-eeh-option",
1966 rtas_ibm_set_eeh_option
);
1967 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
1968 "ibm,get-config-addr-info2",
1969 rtas_ibm_get_config_addr_info2
);
1970 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
1971 "ibm,read-slot-reset-state2",
1972 rtas_ibm_read_slot_reset_state2
);
1973 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
1974 "ibm,set-slot-reset",
1975 rtas_ibm_set_slot_reset
);
1976 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
1978 rtas_ibm_configure_pe
);
1979 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
1980 "ibm,slot-error-detail",
1981 rtas_ibm_slot_error_detail
);
1984 static void spapr_pci_register_types(void)
1986 type_register_static(&spapr_phb_info
);
1989 type_init(spapr_pci_register_types
)
1991 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
1993 bool be
= *(bool *)opaque
;
1995 if (object_dynamic_cast(OBJECT(dev
), "VGA")
1996 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
1997 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
2003 void spapr_pci_switch_vga(bool big_endian
)
2005 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
2006 sPAPRPHBState
*sphb
;
2009 * For backward compatibility with existing guests, we switch
2010 * the endianness of the VGA controller when changing the guest
2013 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
2014 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
2015 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,