| blob | e700c520674b7cebcc755bab57740713c0ac2b95 |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *
9 * Based on i386/tcg-target.c and mips/tcg-target.c
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * THE SOFTWARE.
28 */
30 #include "../tcg-pool.c.inc"
32 #ifdef CONFIG_DEBUG_TCG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "zero",
35 "ra",
36 "sp",
37 "gp",
38 "tp",
39 "t0",
40 "t1",
41 "t2",
42 "s0",
43 "s1",
44 "a0",
45 "a1",
46 "a2",
47 "a3",
48 "a4",
49 "a5",
50 "a6",
51 "a7",
52 "s2",
53 "s3",
54 "s4",
55 "s5",
56 "s6",
57 "s7",
58 "s8",
59 "s9",
60 "s10",
61 "s11",
62 "t3",
63 "t4",
64 "t5",
65 "t6"
66 };
67 #endif
69 static const int tcg_target_reg_alloc_order[] = {
70 /* Call saved registers */
71 /* TCG_REG_S0 reservered for TCG_AREG0 */
72 TCG_REG_S1,
73 TCG_REG_S2,
74 TCG_REG_S3,
75 TCG_REG_S4,
76 TCG_REG_S5,
77 TCG_REG_S6,
78 TCG_REG_S7,
79 TCG_REG_S8,
80 TCG_REG_S9,
81 TCG_REG_S10,
82 TCG_REG_S11,
84 /* Call clobbered registers */
85 TCG_REG_T0,
86 TCG_REG_T1,
87 TCG_REG_T2,
88 TCG_REG_T3,
89 TCG_REG_T4,
90 TCG_REG_T5,
91 TCG_REG_T6,
93 /* Argument registers */
94 TCG_REG_A0,
95 TCG_REG_A1,
96 TCG_REG_A2,
97 TCG_REG_A3,
98 TCG_REG_A4,
99 TCG_REG_A5,
100 TCG_REG_A6,
101 TCG_REG_A7,
102 };
104 static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_A0,
106 TCG_REG_A1,
107 TCG_REG_A2,
108 TCG_REG_A3,
109 TCG_REG_A4,
110 TCG_REG_A5,
111 TCG_REG_A6,
112 TCG_REG_A7,
113 };
115 static const int tcg_target_call_oarg_regs[] = {
116 TCG_REG_A0,
117 TCG_REG_A1,
118 };
120 #define TCG_CT_CONST_ZERO 0x100
121 #define TCG_CT_CONST_S12 0x200
122 #define TCG_CT_CONST_N12 0x400
123 #define TCG_CT_CONST_M12 0x800
125 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
126 /*
127 * For softmmu, we need to avoid conflicts with the first 5
128 * argument registers to call the helper. Some of these are
129 * also used for the tlb lookup.
130 */
131 #ifdef CONFIG_SOFTMMU
132 #define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
133 #else
134 #define SOFTMMU_RESERVE_REGS 0
135 #endif
138 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
139 {
140 if (TCG_TARGET_REG_BITS == 32) {
141 return sextract32(val, pos, len);
142 } else {
143 return sextract64(val, pos, len);
144 }
145 }
147 /* test if a constant matches the constraint */
148 static int tcg_target_const_match(tcg_target_long val, TCGType type,
149 const TCGArgConstraint *arg_ct)
150 {
151 int ct = arg_ct->ct;
152 if (ct & TCG_CT_CONST) {
153 return 1;
154 }
155 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
156 return 1;
157 }
158 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
159 return 1;
160 }
161 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
162 return 1;
163 }
164 if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
165 return 1;
166 }
167 return 0;
168 }
170 /*
171 * RISC-V Base ISA opcodes (IM)
172 */
174 typedef enum {
175 OPC_ADD = 0x33,
176 OPC_ADDI = 0x13,
177 OPC_AND = 0x7033,
178 OPC_ANDI = 0x7013,
179 OPC_AUIPC = 0x17,
180 OPC_BEQ = 0x63,
181 OPC_BGE = 0x5063,
182 OPC_BGEU = 0x7063,
183 OPC_BLT = 0x4063,
184 OPC_BLTU = 0x6063,
185 OPC_BNE = 0x1063,
186 OPC_DIV = 0x2004033,
187 OPC_DIVU = 0x2005033,
188 OPC_JAL = 0x6f,
189 OPC_JALR = 0x67,
190 OPC_LB = 0x3,
191 OPC_LBU = 0x4003,
192 OPC_LD = 0x3003,
193 OPC_LH = 0x1003,
194 OPC_LHU = 0x5003,
195 OPC_LUI = 0x37,
196 OPC_LW = 0x2003,
197 OPC_LWU = 0x6003,
198 OPC_MUL = 0x2000033,
199 OPC_MULH = 0x2001033,
200 OPC_MULHSU = 0x2002033,
201 OPC_MULHU = 0x2003033,
202 OPC_OR = 0x6033,
203 OPC_ORI = 0x6013,
204 OPC_REM = 0x2006033,
205 OPC_REMU = 0x2007033,
206 OPC_SB = 0x23,
207 OPC_SD = 0x3023,
208 OPC_SH = 0x1023,
209 OPC_SLL = 0x1033,
210 OPC_SLLI = 0x1013,
211 OPC_SLT = 0x2033,
212 OPC_SLTI = 0x2013,
213 OPC_SLTIU = 0x3013,
214 OPC_SLTU = 0x3033,
215 OPC_SRA = 0x40005033,
216 OPC_SRAI = 0x40005013,
217 OPC_SRL = 0x5033,
218 OPC_SRLI = 0x5013,
219 OPC_SUB = 0x40000033,
220 OPC_SW = 0x2023,
221 OPC_XOR = 0x4033,
222 OPC_XORI = 0x4013,
224 #if TCG_TARGET_REG_BITS == 64
225 OPC_ADDIW = 0x1b,
226 OPC_ADDW = 0x3b,
227 OPC_DIVUW = 0x200503b,
228 OPC_DIVW = 0x200403b,
229 OPC_MULW = 0x200003b,
230 OPC_REMUW = 0x200703b,
231 OPC_REMW = 0x200603b,
232 OPC_SLLIW = 0x101b,
233 OPC_SLLW = 0x103b,
234 OPC_SRAIW = 0x4000501b,
235 OPC_SRAW = 0x4000503b,
236 OPC_SRLIW = 0x501b,
237 OPC_SRLW = 0x503b,
238 OPC_SUBW = 0x4000003b,
239 #else
240 /* Simplify code throughout by defining aliases for RV32. */
241 OPC_ADDIW = OPC_ADDI,
242 OPC_ADDW = OPC_ADD,
243 OPC_DIVUW = OPC_DIVU,
244 OPC_DIVW = OPC_DIV,
245 OPC_MULW = OPC_MUL,
246 OPC_REMUW = OPC_REMU,
247 OPC_REMW = OPC_REM,
248 OPC_SLLIW = OPC_SLLI,
249 OPC_SLLW = OPC_SLL,
250 OPC_SRAIW = OPC_SRAI,
251 OPC_SRAW = OPC_SRA,
252 OPC_SRLIW = OPC_SRLI,
253 OPC_SRLW = OPC_SRL,
254 OPC_SUBW = OPC_SUB,
255 #endif
257 OPC_FENCE = 0x0000000f,
258 } RISCVInsn;
260 /*
261 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
262 */
264 /* Type-R */
266 static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
267 {
268 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
269 }
271 /* Type-I */
273 static int32_t encode_imm12(uint32_t imm)
274 {
275 return (imm & 0xfff) << 20;
276 }
278 static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
279 {
280 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
281 }
283 /* Type-S */
285 static int32_t encode_simm12(uint32_t imm)
286 {
287 int32_t ret = 0;
289 ret |= (imm & 0xFE0) << 20;
290 ret |= (imm & 0x1F) << 7;
292 return ret;
293 }
295 static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
296 {
297 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
298 }
300 /* Type-SB */
302 static int32_t encode_sbimm12(uint32_t imm)
303 {
304 int32_t ret = 0;
306 ret |= (imm & 0x1000) << 19;
307 ret |= (imm & 0x7e0) << 20;
308 ret |= (imm & 0x1e) << 7;
309 ret |= (imm & 0x800) >> 4;
311 return ret;
312 }
314 static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
315 {
316 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
317 }
319 /* Type-U */
321 static int32_t encode_uimm20(uint32_t imm)
322 {
323 return imm & 0xfffff000;
324 }
326 static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
327 {
328 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
329 }
331 /* Type-UJ */
333 static int32_t encode_ujimm20(uint32_t imm)
334 {
335 int32_t ret = 0;
337 ret |= (imm & 0x0007fe) << (21 - 1);
338 ret |= (imm & 0x000800) << (20 - 11);
339 ret |= (imm & 0x0ff000) << (12 - 12);
340 ret |= (imm & 0x100000) << (31 - 20);
342 return ret;
343 }
345 static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
346 {
347 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
348 }
350 /*
351 * RISC-V instruction emitters
352 */
354 static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
355 TCGReg rd, TCGReg rs1, TCGReg rs2)
356 {
357 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
358 }
360 static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
361 TCGReg rd, TCGReg rs1, TCGArg imm)
362 {
363 tcg_out32(s, encode_i(opc, rd, rs1, imm));
364 }
366 static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
367 TCGReg rs1, TCGReg rs2, uint32_t imm)
368 {
369 tcg_out32(s, encode_s(opc, rs1, rs2, imm));
370 }
372 static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
373 TCGReg rs1, TCGReg rs2, uint32_t imm)
374 {
375 tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
376 }
378 static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
379 TCGReg rd, uint32_t imm)
380 {
381 tcg_out32(s, encode_u(opc, rd, imm));
382 }
384 static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
385 TCGReg rd, uint32_t imm)
386 {
387 tcg_out32(s, encode_uj(opc, rd, imm));
388 }
390 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
391 {
392 int i;
393 for (i = 0; i < count; ++i) {
394 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
395 }
396 }
398 /*
399 * Relocations
400 */
402 static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
403 {
404 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
405 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
407 tcg_debug_assert((offset & 1) == 0);
408 if (offset == sextreg(offset, 0, 12)) {
409 *src_rw |= encode_sbimm12(offset);
410 return true;
411 }
413 return false;
414 }
416 static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
417 {
418 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
419 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
421 tcg_debug_assert((offset & 1) == 0);
422 if (offset == sextreg(offset, 0, 20)) {
423 *src_rw |= encode_ujimm20(offset);
424 return true;
425 }
427 return false;
428 }
430 static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
431 {
432 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
433 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
434 int32_t lo = sextreg(offset, 0, 12);
435 int32_t hi = offset - lo;
437 if (offset == hi + lo) {
438 src_rw[0] |= encode_uimm20(hi);
439 src_rw[1] |= encode_imm12(lo);
440 return true;
441 }
443 return false;
444 }
446 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
447 intptr_t value, intptr_t addend)
448 {
449 tcg_debug_assert(addend == 0);
450 switch (type) {
451 case R_RISCV_BRANCH:
452 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
453 case R_RISCV_JAL:
454 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
455 case R_RISCV_CALL:
456 return reloc_call(code_ptr, (tcg_insn_unit *)value);
457 default:
458 g_assert_not_reached();
459 }
460 }
462 /*
463 * TCG intrinsics
464 */
466 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
467 {
468 if (ret == arg) {
469 return true;
470 }
471 switch (type) {
472 case TCG_TYPE_I32:
473 case TCG_TYPE_I64:
474 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
475 break;
476 default:
477 g_assert_not_reached();
478 }
479 return true;
480 }
482 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
483 tcg_target_long val)
484 {
485 tcg_target_long lo, hi, tmp;
486 int shift, ret;
488 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
489 val = (int32_t)val;
490 }
492 lo = sextreg(val, 0, 12);
493 if (val == lo) {
494 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
495 return;
496 }
498 hi = val - lo;
499 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
500 tcg_out_opc_upper(s, OPC_LUI, rd, hi);
501 if (lo != 0) {
502 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
503 }
504 return;
505 }
507 /* We can only be here if TCG_TARGET_REG_BITS != 32 */
508 tmp = tcg_pcrel_diff(s, (void *)val);
509 if (tmp == (int32_t)tmp) {
510 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
511 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
512 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val);
513 tcg_debug_assert(ret == true);
514 return;
515 }
517 /* Look for a single 20-bit section. */
518 shift = ctz64(val);
519 tmp = val >> shift;
520 if (tmp == sextreg(tmp, 0, 20)) {
521 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
522 if (shift > 12) {
523 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
524 } else {
525 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
526 }
527 return;
528 }
530 /* Look for a few high zero bits, with lots of bits set in the middle. */
531 shift = clz64(val);
532 tmp = val << shift;
533 if (tmp == sextreg(tmp, 12, 20) << 12) {
534 tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
535 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
536 return;
537 } else if (tmp == sextreg(tmp, 0, 12)) {
538 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
539 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
540 return;
541 }
543 /* Drop into the constant pool. */
544 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
545 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
546 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
547 }
549 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
550 {
551 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
552 }
554 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
555 {
556 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
557 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
558 }
560 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
561 {
562 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
563 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
564 }
566 static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
567 {
568 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
569 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
570 }
572 static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
573 {
574 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
575 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
576 }
578 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
579 {
580 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
581 }
583 static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
584 TCGReg addr, intptr_t offset)
585 {
586 intptr_t imm12 = sextreg(offset, 0, 12);
588 if (offset != imm12) {
589 intptr_t diff = offset - (uintptr_t)s->code_ptr;
591 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
592 imm12 = sextreg(diff, 0, 12);
593 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
594 } else {
595 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
596 if (addr != TCG_REG_ZERO) {
597 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
598 }
599 }
600 addr = TCG_REG_TMP2;
601 }
603 switch (opc) {
604 case OPC_SB:
605 case OPC_SH:
606 case OPC_SW:
607 case OPC_SD:
608 tcg_out_opc_store(s, opc, addr, data, imm12);
609 break;
610 case OPC_LB:
611 case OPC_LBU:
612 case OPC_LH:
613 case OPC_LHU:
614 case OPC_LW:
615 case OPC_LWU:
616 case OPC_LD:
617 tcg_out_opc_imm(s, opc, data, addr, imm12);
618 break;
619 default:
620 g_assert_not_reached();
621 }
622 }
624 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
625 TCGReg arg1, intptr_t arg2)
626 {
627 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
628 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
629 }
631 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
632 TCGReg arg1, intptr_t arg2)
633 {
634 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
635 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
636 }
638 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
639 TCGReg base, intptr_t ofs)
640 {
641 if (val == 0) {
642 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
643 return true;
644 }
645 return false;
646 }
648 static void tcg_out_addsub2(TCGContext *s,
649 TCGReg rl, TCGReg rh,
650 TCGReg al, TCGReg ah,
651 TCGArg bl, TCGArg bh,
652 bool cbl, bool cbh, bool is_sub, bool is32bit)
653 {
654 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
655 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
656 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
657 TCGReg th = TCG_REG_TMP1;
659 /* If we have a negative constant such that negating it would
660 make the high part zero, we can (usually) eliminate one insn. */
661 if (cbl && cbh && bh == -1 && bl != 0) {
662 bl = -bl;
663 bh = 0;
664 is_sub = !is_sub;
665 }
667 /* By operating on the high part first, we get to use the final
668 carry operation to move back from the temporary. */
669 if (!cbh) {
670 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
671 } else if (bh != 0 || ah == rl) {
672 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
673 } else {
674 th = ah;
675 }
677 /* Note that tcg optimization should eliminate the bl == 0 case. */
678 if (is_sub) {
679 if (cbl) {
680 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
681 tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
682 } else {
683 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
684 tcg_out_opc_reg(s, opc_sub, rl, al, bl);
685 }
686 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
687 } else {
688 if (cbl) {
689 tcg_out_opc_imm(s, opc_addi, rl, al, bl);
690 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
691 } else if (rl == al && rl == bl) {
692 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
693 tcg_out_opc_reg(s, opc_addi, rl, al, bl);
694 } else {
695 tcg_out_opc_reg(s, opc_add, rl, al, bl);
696 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
697 rl, (rl == bl ? al : bl));
698 }
699 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
700 }
701 }
703 static const struct {
704 RISCVInsn op;
705 bool swap;
706 } tcg_brcond_to_riscv[] = {
707 [TCG_COND_EQ] = { OPC_BEQ, false },
708 [TCG_COND_NE] = { OPC_BNE, false },
709 [TCG_COND_LT] = { OPC_BLT, false },
710 [TCG_COND_GE] = { OPC_BGE, false },
711 [TCG_COND_LE] = { OPC_BGE, true },
712 [TCG_COND_GT] = { OPC_BLT, true },
713 [TCG_COND_LTU] = { OPC_BLTU, false },
714 [TCG_COND_GEU] = { OPC_BGEU, false },
715 [TCG_COND_LEU] = { OPC_BGEU, true },
716 [TCG_COND_GTU] = { OPC_BLTU, true }
717 };
719 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
720 TCGReg arg2, TCGLabel *l)
721 {
722 RISCVInsn op = tcg_brcond_to_riscv[cond].op;
724 tcg_debug_assert(op != 0);
726 if (tcg_brcond_to_riscv[cond].swap) {
727 TCGReg t = arg1;
728 arg1 = arg2;
729 arg2 = t;
730 }
732 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
733 tcg_out_opc_branch(s, op, arg1, arg2, 0);
734 }
736 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
737 TCGReg arg1, TCGReg arg2)
738 {
739 switch (cond) {
740 case TCG_COND_EQ:
741 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
742 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
743 break;
744 case TCG_COND_NE:
745 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
746 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
747 break;
748 case TCG_COND_LT:
749 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
750 break;
751 case TCG_COND_GE:
752 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
753 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
754 break;
755 case TCG_COND_LE:
756 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
757 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
758 break;
759 case TCG_COND_GT:
760 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
761 break;
762 case TCG_COND_LTU:
763 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
764 break;
765 case TCG_COND_GEU:
766 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
767 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
768 break;
769 case TCG_COND_LEU:
770 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
771 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
772 break;
773 case TCG_COND_GTU:
774 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
775 break;
776 default:
777 g_assert_not_reached();
778 break;
779 }
780 }
782 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
783 TCGReg bl, TCGReg bh, TCGLabel *l)
784 {
785 /* todo */
786 g_assert_not_reached();
787 }
789 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
790 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
791 {
792 /* todo */
793 g_assert_not_reached();
794 }
796 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
797 {
798 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
799 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
800 int ret;
802 tcg_debug_assert((offset & 1) == 0);
803 if (offset == sextreg(offset, 0, 20)) {
804 /* short jump: -2097150 to 2097152 */
805 tcg_out_opc_jump(s, OPC_JAL, link, offset);
806 } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) {
807 /* long jump: -2147483646 to 2147483648 */
808 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
809 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
810 ret = reloc_call(s->code_ptr - 2, arg);
811 tcg_debug_assert(ret == true);
812 } else if (TCG_TARGET_REG_BITS == 64) {
813 /* far jump: 64-bit */
814 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
815 tcg_target_long base = (tcg_target_long)arg - imm;
816 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
817 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
818 } else {
819 g_assert_not_reached();
820 }
821 }
823 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
824 {
825 tcg_out_call_int(s, arg, false);
826 }
828 static void tcg_out_mb(TCGContext *s, TCGArg a0)
829 {
830 tcg_insn_unit insn = OPC_FENCE;
832 if (a0 & TCG_MO_LD_LD) {
833 insn |= 0x02200000;
834 }
835 if (a0 & TCG_MO_ST_LD) {
836 insn |= 0x01200000;
837 }
838 if (a0 & TCG_MO_LD_ST) {
839 insn |= 0x02100000;
840 }
841 if (a0 & TCG_MO_ST_ST) {
842 insn |= 0x02200000;
843 }
844 tcg_out32(s, insn);
845 }
847 /*
848 * Load/store and TLB
849 */
851 #if defined(CONFIG_SOFTMMU)
852 #include "../tcg-ldst.c.inc"
854 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
855 * TCGMemOpIdx oi, uintptr_t ra)
856 */
857 static void * const qemu_ld_helpers[16] = {
858 [MO_UB] = helper_ret_ldub_mmu,
859 [MO_SB] = helper_ret_ldsb_mmu,
860 [MO_LEUW] = helper_le_lduw_mmu,
861 [MO_LESW] = helper_le_ldsw_mmu,
862 [MO_LEUL] = helper_le_ldul_mmu,
863 #if TCG_TARGET_REG_BITS == 64
864 [MO_LESL] = helper_le_ldsl_mmu,
865 #endif
866 [MO_LEQ] = helper_le_ldq_mmu,
867 [MO_BEUW] = helper_be_lduw_mmu,
868 [MO_BESW] = helper_be_ldsw_mmu,
869 [MO_BEUL] = helper_be_ldul_mmu,
870 #if TCG_TARGET_REG_BITS == 64
871 [MO_BESL] = helper_be_ldsl_mmu,
872 #endif
873 [MO_BEQ] = helper_be_ldq_mmu,
874 };
876 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
877 * uintxx_t val, TCGMemOpIdx oi,
878 * uintptr_t ra)
879 */
880 static void * const qemu_st_helpers[16] = {
881 [MO_UB] = helper_ret_stb_mmu,
882 [MO_LEUW] = helper_le_stw_mmu,
883 [MO_LEUL] = helper_le_stl_mmu,
884 [MO_LEQ] = helper_le_stq_mmu,
885 [MO_BEUW] = helper_be_stw_mmu,
886 [MO_BEUL] = helper_be_stl_mmu,
887 [MO_BEQ] = helper_be_stq_mmu,
888 };
890 /* We don't support oversize guests */
891 QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
893 /* We expect to use a 12-bit negative offset from ENV. */
894 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
895 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
897 static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
898 {
899 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
900 bool ok = reloc_jimm20(s->code_ptr - 1, target);
901 tcg_debug_assert(ok);
902 }
904 static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
905 TCGReg addrh, TCGMemOpIdx oi,
906 tcg_insn_unit **label_ptr, bool is_load)
907 {
908 MemOp opc = get_memop(oi);
909 unsigned s_bits = opc & MO_SIZE;
910 unsigned a_bits = get_alignment_bits(opc);
911 tcg_target_long compare_mask;
912 int mem_index = get_mmuidx(oi);
913 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
914 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
915 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
916 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
918 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
919 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
921 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
922 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
923 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
924 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
926 /* Load the tlb comparator and the addend. */
927 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
928 is_load ? offsetof(CPUTLBEntry, addr_read)
929 : offsetof(CPUTLBEntry, addr_write));
930 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
931 offsetof(CPUTLBEntry, addend));
933 /* We don't support unaligned accesses. */
934 if (a_bits < s_bits) {
935 a_bits = s_bits;
936 }
937 /* Clear the non-page, non-alignment bits from the address. */
938 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
939 if (compare_mask == sextreg(compare_mask, 0, 12)) {
940 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
941 } else {
942 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
943 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
944 }
946 /* Compare masked address with the TLB entry. */
947 label_ptr[0] = s->code_ptr;
948 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
950 /* TLB Hit - translate address using addend. */
951 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
952 tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
953 addrl = TCG_REG_TMP0;
954 }
955 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
956 }
958 static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
959 TCGType ext,
960 TCGReg datalo, TCGReg datahi,
961 TCGReg addrlo, TCGReg addrhi,
962 void *raddr, tcg_insn_unit **label_ptr)
963 {
964 TCGLabelQemuLdst *label = new_ldst_label(s);
966 label->is_ld = is_ld;
967 label->oi = oi;
968 label->type = ext;
969 label->datalo_reg = datalo;
970 label->datahi_reg = datahi;
971 label->addrlo_reg = addrlo;
972 label->addrhi_reg = addrhi;
973 label->raddr = tcg_splitwx_to_rx(raddr);
974 label->label_ptr[0] = label_ptr[0];
975 }
977 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
978 {
979 TCGMemOpIdx oi = l->oi;
980 MemOp opc = get_memop(oi);
981 TCGReg a0 = tcg_target_call_iarg_regs[0];
982 TCGReg a1 = tcg_target_call_iarg_regs[1];
983 TCGReg a2 = tcg_target_call_iarg_regs[2];
984 TCGReg a3 = tcg_target_call_iarg_regs[3];
986 /* We don't support oversize guests */
987 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
988 g_assert_not_reached();
989 }
991 /* resolve label address */
992 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
993 return false;
994 }
996 /* call load helper */
997 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
998 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
999 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
1000 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
1002 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1003 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
1005 tcg_out_goto(s, l->raddr);
1006 return true;
1007 }
1009 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1010 {
1011 TCGMemOpIdx oi = l->oi;
1012 MemOp opc = get_memop(oi);
1013 MemOp s_bits = opc & MO_SIZE;
1014 TCGReg a0 = tcg_target_call_iarg_regs[0];
1015 TCGReg a1 = tcg_target_call_iarg_regs[1];
1016 TCGReg a2 = tcg_target_call_iarg_regs[2];
1017 TCGReg a3 = tcg_target_call_iarg_regs[3];
1018 TCGReg a4 = tcg_target_call_iarg_regs[4];
1020 /* We don't support oversize guests */
1021 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1022 g_assert_not_reached();
1023 }
1025 /* resolve label address */
1026 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1027 return false;
1028 }
1030 /* call store helper */
1031 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1032 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1033 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
1034 switch (s_bits) {
1035 case MO_8:
1036 tcg_out_ext8u(s, a2, a2);
1037 break;
1038 case MO_16:
1039 tcg_out_ext16u(s, a2, a2);
1040 break;
1041 default:
1042 break;
1043 }
1044 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
1045 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
1047 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1049 tcg_out_goto(s, l->raddr);
1050 return true;
1051 }
1052 #endif /* CONFIG_SOFTMMU */
1054 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1055 TCGReg base, MemOp opc, bool is_64)
1056 {
1057 const MemOp bswap = opc & MO_BSWAP;
1059 /* We don't yet handle byteswapping, assert */
1060 g_assert(!bswap);
1062 switch (opc & (MO_SSIZE)) {
1063 case MO_UB:
1064 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1065 break;
1066 case MO_SB:
1067 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1068 break;
1069 case MO_UW:
1070 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1071 break;
1072 case MO_SW:
1073 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1074 break;
1075 case MO_UL:
1076 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1077 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1078 break;
1079 }
1080 /* FALLTHRU */
1081 case MO_SL:
1082 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1083 break;
1084 case MO_Q:
1085 /* Prefer to load from offset 0 first, but allow for overlap. */
1086 if (TCG_TARGET_REG_BITS == 64) {
1087 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1088 } else if (lo != base) {
1089 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1090 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1091 } else {
1092 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1093 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1094 }
1095 break;
1096 default:
1097 g_assert_not_reached();
1098 }
1099 }
1101 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1102 {
1103 TCGReg addr_regl, addr_regh __attribute__((unused));
1104 TCGReg data_regl, data_regh;
1105 TCGMemOpIdx oi;
1106 MemOp opc;
1107 #if defined(CONFIG_SOFTMMU)
1108 tcg_insn_unit *label_ptr[1];
1109 #endif
1110 TCGReg base = TCG_REG_TMP0;
1112 data_regl = *args++;
1113 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1114 addr_regl = *args++;
1115 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1116 oi = *args++;
1117 opc = get_memop(oi);
1119 #if defined(CONFIG_SOFTMMU)
1120 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
1121 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1122 add_qemu_ldst_label(s, 1, oi,
1123 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1124 data_regl, data_regh, addr_regl, addr_regh,
1125 s->code_ptr, label_ptr);
1126 #else
1127 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1128 tcg_out_ext32u(s, base, addr_regl);
1129 addr_regl = base;
1130 }
1132 if (guest_base == 0) {
1133 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1134 } else {
1135 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1136 }
1137 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1138 #endif
1139 }
1141 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1142 TCGReg base, MemOp opc)
1143 {
1144 const MemOp bswap = opc & MO_BSWAP;
1146 /* We don't yet handle byteswapping, assert */
1147 g_assert(!bswap);
1149 switch (opc & (MO_SSIZE)) {
1150 case MO_8:
1151 tcg_out_opc_store(s, OPC_SB, base, lo, 0);
1152 break;
1153 case MO_16:
1154 tcg_out_opc_store(s, OPC_SH, base, lo, 0);
1155 break;
1156 case MO_32:
1157 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1158 break;
1159 case MO_64:
1160 if (TCG_TARGET_REG_BITS == 64) {
1161 tcg_out_opc_store(s, OPC_SD, base, lo, 0);
1162 } else {
1163 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1164 tcg_out_opc_store(s, OPC_SW, base, hi, 4);
1165 }
1166 break;
1167 default:
1168 g_assert_not_reached();
1169 }
1170 }
1172 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1173 {
1174 TCGReg addr_regl, addr_regh __attribute__((unused));
1175 TCGReg data_regl, data_regh;
1176 TCGMemOpIdx oi;
1177 MemOp opc;
1178 #if defined(CONFIG_SOFTMMU)
1179 tcg_insn_unit *label_ptr[1];
1180 #endif
1181 TCGReg base = TCG_REG_TMP0;
1183 data_regl = *args++;
1184 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1185 addr_regl = *args++;
1186 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1187 oi = *args++;
1188 opc = get_memop(oi);
1190 #if defined(CONFIG_SOFTMMU)
1191 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
1192 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1193 add_qemu_ldst_label(s, 0, oi,
1194 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1195 data_regl, data_regh, addr_regl, addr_regh,
1196 s->code_ptr, label_ptr);
1197 #else
1198 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1199 tcg_out_ext32u(s, base, addr_regl);
1200 addr_regl = base;
1201 }
1203 if (guest_base == 0) {
1204 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1205 } else {
1206 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1207 }
1208 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1209 #endif
1210 }
1212 static const tcg_insn_unit *tb_ret_addr;
1214 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1215 const TCGArg *args, const int *const_args)
1216 {
1217 TCGArg a0 = args[0];
1218 TCGArg a1 = args[1];
1219 TCGArg a2 = args[2];
1220 int c2 = const_args[2];
1222 switch (opc) {
1223 case INDEX_op_exit_tb:
1224 /* Reuse the zeroing that exists for goto_ptr. */
1225 if (a0 == 0) {
1226 tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1227 } else {
1228 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1229 tcg_out_call_int(s, tb_ret_addr, true);
1230 }
1231 break;
1233 case INDEX_op_goto_tb:
1234 assert(s->tb_jmp_insn_offset == 0);
1235 /* indirect jump method */
1236 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
1237 (uintptr_t)(s->tb_jmp_target_addr + a0));
1238 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1239 set_jmp_reset_offset(s, a0);
1240 break;
1242 case INDEX_op_goto_ptr:
1243 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1244 break;
1246 case INDEX_op_br:
1247 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1248 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1249 break;
1251 case INDEX_op_ld8u_i32:
1252 case INDEX_op_ld8u_i64:
1253 tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
1254 break;
1255 case INDEX_op_ld8s_i32:
1256 case INDEX_op_ld8s_i64:
1257 tcg_out_ldst(s, OPC_LB, a0, a1, a2);
1258 break;
1259 case INDEX_op_ld16u_i32:
1260 case INDEX_op_ld16u_i64:
1261 tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
1262 break;
1263 case INDEX_op_ld16s_i32:
1264 case INDEX_op_ld16s_i64:
1265 tcg_out_ldst(s, OPC_LH, a0, a1, a2);
1266 break;
1267 case INDEX_op_ld32u_i64:
1268 tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
1269 break;
1270 case INDEX_op_ld_i32:
1271 case INDEX_op_ld32s_i64:
1272 tcg_out_ldst(s, OPC_LW, a0, a1, a2);
1273 break;
1274 case INDEX_op_ld_i64:
1275 tcg_out_ldst(s, OPC_LD, a0, a1, a2);
1276 break;
1278 case INDEX_op_st8_i32:
1279 case INDEX_op_st8_i64:
1280 tcg_out_ldst(s, OPC_SB, a0, a1, a2);
1281 break;
1282 case INDEX_op_st16_i32:
1283 case INDEX_op_st16_i64:
1284 tcg_out_ldst(s, OPC_SH, a0, a1, a2);
1285 break;
1286 case INDEX_op_st_i32:
1287 case INDEX_op_st32_i64:
1288 tcg_out_ldst(s, OPC_SW, a0, a1, a2);
1289 break;
1290 case INDEX_op_st_i64:
1291 tcg_out_ldst(s, OPC_SD, a0, a1, a2);
1292 break;
1294 case INDEX_op_add_i32:
1295 if (c2) {
1296 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
1297 } else {
1298 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
1299 }
1300 break;
1301 case INDEX_op_add_i64:
1302 if (c2) {
1303 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
1304 } else {
1305 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
1306 }
1307 break;
1309 case INDEX_op_sub_i32:
1310 if (c2) {
1311 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
1312 } else {
1313 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
1314 }
1315 break;
1316 case INDEX_op_sub_i64:
1317 if (c2) {
1318 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
1319 } else {
1320 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
1321 }
1322 break;
1324 case INDEX_op_and_i32:
1325 case INDEX_op_and_i64:
1326 if (c2) {
1327 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
1328 } else {
1329 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
1330 }
1331 break;
1333 case INDEX_op_or_i32:
1334 case INDEX_op_or_i64:
1335 if (c2) {
1336 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
1337 } else {
1338 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
1339 }
1340 break;
1342 case INDEX_op_xor_i32:
1343 case INDEX_op_xor_i64:
1344 if (c2) {
1345 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
1346 } else {
1347 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
1348 }
1349 break;
1351 case INDEX_op_not_i32:
1352 case INDEX_op_not_i64:
1353 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
1354 break;
1356 case INDEX_op_neg_i32:
1357 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
1358 break;
1359 case INDEX_op_neg_i64:
1360 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
1361 break;
1363 case INDEX_op_mul_i32:
1364 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
1365 break;
1366 case INDEX_op_mul_i64:
1367 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1368 break;
1370 case INDEX_op_div_i32:
1371 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
1372 break;
1373 case INDEX_op_div_i64:
1374 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
1375 break;
1377 case INDEX_op_divu_i32:
1378 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
1379 break;
1380 case INDEX_op_divu_i64:
1381 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
1382 break;
1384 case INDEX_op_rem_i32:
1385 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
1386 break;
1387 case INDEX_op_rem_i64:
1388 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
1389 break;
1391 case INDEX_op_remu_i32:
1392 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1393 break;
1394 case INDEX_op_remu_i64:
1395 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1396 break;
1398 case INDEX_op_shl_i32:
1399 if (c2) {
1400 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
1401 } else {
1402 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1403 }
1404 break;
1405 case INDEX_op_shl_i64:
1406 if (c2) {
1407 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
1408 } else {
1409 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1410 }
1411 break;
1413 case INDEX_op_shr_i32:
1414 if (c2) {
1415 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
1416 } else {
1417 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1418 }
1419 break;
1420 case INDEX_op_shr_i64:
1421 if (c2) {
1422 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
1423 } else {
1424 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1425 }
1426 break;
1428 case INDEX_op_sar_i32:
1429 if (c2) {
1430 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
1431 } else {
1432 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1433 }
1434 break;
1435 case INDEX_op_sar_i64:
1436 if (c2) {
1437 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
1438 } else {
1439 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1440 }
1441 break;
1443 case INDEX_op_add2_i32:
1444 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1445 const_args[4], const_args[5], false, true);
1446 break;
1447 case INDEX_op_add2_i64:
1448 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1449 const_args[4], const_args[5], false, false);
1450 break;
1451 case INDEX_op_sub2_i32:
1452 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1453 const_args[4], const_args[5], true, true);
1454 break;
1455 case INDEX_op_sub2_i64:
1456 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1457 const_args[4], const_args[5], true, false);
1458 break;
1460 case INDEX_op_brcond_i32:
1461 case INDEX_op_brcond_i64:
1462 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1463 break;
1464 case INDEX_op_brcond2_i32:
1465 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
1466 break;
1468 case INDEX_op_setcond_i32:
1469 case INDEX_op_setcond_i64:
1470 tcg_out_setcond(s, args[3], a0, a1, a2);
1471 break;
1472 case INDEX_op_setcond2_i32:
1473 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
1474 break;
1476 case INDEX_op_qemu_ld_i32:
1477 tcg_out_qemu_ld(s, args, false);
1478 break;
1479 case INDEX_op_qemu_ld_i64:
1480 tcg_out_qemu_ld(s, args, true);
1481 break;
1482 case INDEX_op_qemu_st_i32:
1483 tcg_out_qemu_st(s, args, false);
1484 break;
1485 case INDEX_op_qemu_st_i64:
1486 tcg_out_qemu_st(s, args, true);
1487 break;
1489 case INDEX_op_ext8u_i32:
1490 case INDEX_op_ext8u_i64:
1491 tcg_out_ext8u(s, a0, a1);
1492 break;
1494 case INDEX_op_ext16u_i32:
1495 case INDEX_op_ext16u_i64:
1496 tcg_out_ext16u(s, a0, a1);
1497 break;
1499 case INDEX_op_ext32u_i64:
1500 case INDEX_op_extu_i32_i64:
1501 tcg_out_ext32u(s, a0, a1);
1502 break;
1504 case INDEX_op_ext8s_i32:
1505 case INDEX_op_ext8s_i64:
1506 tcg_out_ext8s(s, a0, a1);
1507 break;
1509 case INDEX_op_ext16s_i32:
1510 case INDEX_op_ext16s_i64:
1511 tcg_out_ext16s(s, a0, a1);
1512 break;
1514 case INDEX_op_ext32s_i64:
1515 case INDEX_op_extrl_i64_i32:
1516 case INDEX_op_ext_i32_i64:
1517 tcg_out_ext32s(s, a0, a1);
1518 break;
1520 case INDEX_op_extrh_i64_i32:
1521 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
1522 break;
1524 case INDEX_op_mulsh_i32:
1525 case INDEX_op_mulsh_i64:
1526 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
1527 break;
1529 case INDEX_op_muluh_i32:
1530 case INDEX_op_muluh_i64:
1531 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
1532 break;
1534 case INDEX_op_mb:
1535 tcg_out_mb(s, a0);
1536 break;
1538 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1539 case INDEX_op_mov_i64:
1540 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1541 default:
1542 g_assert_not_reached();
1543 }
1544 }
1546 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1547 {
1548 switch (op) {
1549 case INDEX_op_goto_ptr:
1550 return C_O0_I1(r);
1552 case INDEX_op_ld8u_i32:
1553 case INDEX_op_ld8s_i32:
1554 case INDEX_op_ld16u_i32:
1555 case INDEX_op_ld16s_i32:
1556 case INDEX_op_ld_i32:
1557 case INDEX_op_not_i32:
1558 case INDEX_op_neg_i32:
1559 case INDEX_op_ld8u_i64:
1560 case INDEX_op_ld8s_i64:
1561 case INDEX_op_ld16u_i64:
1562 case INDEX_op_ld16s_i64:
1563 case INDEX_op_ld32s_i64:
1564 case INDEX_op_ld32u_i64:
1565 case INDEX_op_ld_i64:
1566 case INDEX_op_not_i64:
1567 case INDEX_op_neg_i64:
1568 case INDEX_op_ext8u_i32:
1569 case INDEX_op_ext8u_i64:
1570 case INDEX_op_ext16u_i32:
1571 case INDEX_op_ext16u_i64:
1572 case INDEX_op_ext32u_i64:
1573 case INDEX_op_extu_i32_i64:
1574 case INDEX_op_ext8s_i32:
1575 case INDEX_op_ext8s_i64:
1576 case INDEX_op_ext16s_i32:
1577 case INDEX_op_ext16s_i64:
1578 case INDEX_op_ext32s_i64:
1579 case INDEX_op_extrl_i64_i32:
1580 case INDEX_op_extrh_i64_i32:
1581 case INDEX_op_ext_i32_i64:
1582 return C_O1_I1(r, r);
1584 case INDEX_op_st8_i32:
1585 case INDEX_op_st16_i32:
1586 case INDEX_op_st_i32:
1587 case INDEX_op_st8_i64:
1588 case INDEX_op_st16_i64:
1589 case INDEX_op_st32_i64:
1590 case INDEX_op_st_i64:
1591 return C_O0_I2(rZ, r);
1593 case INDEX_op_add_i32:
1594 case INDEX_op_and_i32:
1595 case INDEX_op_or_i32:
1596 case INDEX_op_xor_i32:
1597 case INDEX_op_add_i64:
1598 case INDEX_op_and_i64:
1599 case INDEX_op_or_i64:
1600 case INDEX_op_xor_i64:
1601 return C_O1_I2(r, r, rI);
1603 case INDEX_op_sub_i32:
1604 case INDEX_op_sub_i64:
1605 return C_O1_I2(r, rZ, rN);
1607 case INDEX_op_mul_i32:
1608 case INDEX_op_mulsh_i32:
1609 case INDEX_op_muluh_i32:
1610 case INDEX_op_div_i32:
1611 case INDEX_op_divu_i32:
1612 case INDEX_op_rem_i32:
1613 case INDEX_op_remu_i32:
1614 case INDEX_op_setcond_i32:
1615 case INDEX_op_mul_i64:
1616 case INDEX_op_mulsh_i64:
1617 case INDEX_op_muluh_i64:
1618 case INDEX_op_div_i64:
1619 case INDEX_op_divu_i64:
1620 case INDEX_op_rem_i64:
1621 case INDEX_op_remu_i64:
1622 case INDEX_op_setcond_i64:
1623 return C_O1_I2(r, rZ, rZ);
1625 case INDEX_op_shl_i32:
1626 case INDEX_op_shr_i32:
1627 case INDEX_op_sar_i32:
1628 case INDEX_op_shl_i64:
1629 case INDEX_op_shr_i64:
1630 case INDEX_op_sar_i64:
1631 return C_O1_I2(r, r, ri);
1633 case INDEX_op_brcond_i32:
1634 case INDEX_op_brcond_i64:
1635 return C_O0_I2(rZ, rZ);
1637 case INDEX_op_add2_i32:
1638 case INDEX_op_add2_i64:
1639 case INDEX_op_sub2_i32:
1640 case INDEX_op_sub2_i64:
1641 return C_O2_I4(r, r, rZ, rZ, rM, rM);
1643 case INDEX_op_brcond2_i32:
1644 return C_O0_I4(rZ, rZ, rZ, rZ);
1646 case INDEX_op_setcond2_i32:
1647 return C_O1_I4(r, rZ, rZ, rZ, rZ);
1649 case INDEX_op_qemu_ld_i32:
1650 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1651 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
1652 case INDEX_op_qemu_st_i32:
1653 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1654 ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
1655 case INDEX_op_qemu_ld_i64:
1656 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
1657 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
1658 : C_O2_I2(r, r, L, L));
1659 case INDEX_op_qemu_st_i64:
1660 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
1661 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
1662 : C_O0_I4(LZ, LZ, L, L));
1664 default:
1665 g_assert_not_reached();
1666 }
1667 }
1669 static const int tcg_target_callee_save_regs[] = {
1670 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1671 TCG_REG_S1,
1672 TCG_REG_S2,
1673 TCG_REG_S3,
1674 TCG_REG_S4,
1675 TCG_REG_S5,
1676 TCG_REG_S6,
1677 TCG_REG_S7,
1678 TCG_REG_S8,
1679 TCG_REG_S9,
1680 TCG_REG_S10,
1681 TCG_REG_S11,
1682 TCG_REG_RA, /* should be last for ABI compliance */
1683 };
1685 /* Stack frame parameters. */
1686 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
1687 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
1688 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1689 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
1690 + TCG_TARGET_STACK_ALIGN - 1) \
1691 & -TCG_TARGET_STACK_ALIGN)
1692 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
1694 /* We're expecting to be able to use an immediate for frame allocation. */
1695 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
1697 /* Generate global QEMU prologue and epilogue code */
1698 static void tcg_target_qemu_prologue(TCGContext *s)
1699 {
1700 int i;
1702 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
1704 /* TB prologue */
1705 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
1706 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1707 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1708 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1709 }
1711 #if !defined(CONFIG_SOFTMMU)
1712 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1713 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1714 #endif
1716 /* Call generated code */
1717 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1718 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1720 /* Return path for goto_ptr. Set return value to 0 */
1721 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
1722 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
1724 /* TB epilogue */
1725 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
1726 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1727 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1728 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1729 }
1731 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
1732 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
1733 }
1735 static void tcg_target_init(TCGContext *s)
1736 {
1737 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
1738 if (TCG_TARGET_REG_BITS == 64) {
1739 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
1740 }
1742 tcg_target_call_clobber_regs = -1u;
1743 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
1744 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
1745 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
1746 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
1747 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
1748 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
1749 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
1750 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
1751 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
1752 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
1753 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
1754 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
1756 s->reserved_regs = 0;
1757 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
1758 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
1759 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
1760 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
1761 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
1762 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
1763 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
1764 }
1766 typedef struct {
1767 DebugFrameHeader h;
1768 uint8_t fde_def_cfa[4];
1769 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
1770 } DebugFrame;
1772 #define ELF_HOST_MACHINE EM_RISCV
1774 static const DebugFrame debug_frame = {
1775 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
1776 .h.cie.id = -1,
1777 .h.cie.version = 1,
1778 .h.cie.code_align = 1,
1779 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
1780 .h.cie.return_column = TCG_REG_RA,
1782 /* Total FDE size does not include the "len" member. */
1783 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1785 .fde_def_cfa = {
1786 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
1787 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
1788 (FRAME_SIZE >> 7)
1789 },
1790 .fde_reg_ofs = {
1791 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
1792 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
1793 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
1794 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
1795 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
1796 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
1797 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
1798 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
1799 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
1800 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
1801 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
1802 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
1803 }
1804 };
1806 void tcg_register_jit(const void *buf, size_t buf_size)
1807 {
1808 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1809 }