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Merge remote-tracking branch 'remotes/kraxel/tags/pull-ipxe-20150903-1' into staging
[qemu/ar7.git] / target-ppc / cpu.h
blob406d30896096c440f3554a80d8b3e6427d102124
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 #define TARGET_IS_BIENDIAN 1
33
34 /* Note that the official physical address space bits is 62-M where M
35 is implementation dependent. I've not looked up M for the set of
36 cpus we emulate at the system level. */
37 #define TARGET_PHYS_ADDR_SPACE_BITS 62
38
39 /* Note that the PPC environment architecture talks about 80 bit virtual
40 addresses, with segmentation. Obviously that's not all visible to a
41 single process, which is all we're concerned with here. */
42 #ifdef TARGET_ABI32
43 # define TARGET_VIRT_ADDR_SPACE_BITS 32
44 #else
45 # define TARGET_VIRT_ADDR_SPACE_BITS 64
46 #endif
47
48 #define TARGET_PAGE_BITS_64K 16
49 #define TARGET_PAGE_BITS_16M 24
50
51 #else /* defined (TARGET_PPC64) */
52 /* PowerPC 32 definitions */
53 #define TARGET_LONG_BITS 32
54
55 #if defined(TARGET_PPCEMB)
56 /* Specific definitions for PowerPC embedded */
57 /* BookE have 36 bits physical address space */
58 #if defined(CONFIG_USER_ONLY)
59 /* It looks like a lot of Linux programs assume page size
60 * is 4kB long. This is evil, but we have to deal with it...
61 */
62 #define TARGET_PAGE_BITS 12
63 #else /* defined(CONFIG_USER_ONLY) */
64 /* Pages can be 1 kB small */
65 #define TARGET_PAGE_BITS 10
66 #endif /* defined(CONFIG_USER_ONLY) */
67 #else /* defined(TARGET_PPCEMB) */
68 /* "standard" PowerPC 32 definitions */
69 #define TARGET_PAGE_BITS 12
70 #endif /* defined(TARGET_PPCEMB) */
71
72 #define TARGET_PHYS_ADDR_SPACE_BITS 36
73 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74
75 #endif /* defined (TARGET_PPC64) */
76
77 #define CPUArchState struct CPUPPCState
78
79 #include "exec/cpu-defs.h"
80
81 #include "fpu/softfloat.h"
82
83 #if defined (TARGET_PPC64)
84 #define ELF_MACHINE EM_PPC64
85 #else
86 #define ELF_MACHINE EM_PPC
87 #endif
88
89 /*****************************************************************************/
90 /* MMU model */
91 typedef enum powerpc_mmu_t powerpc_mmu_t;
92 enum powerpc_mmu_t {
93 POWERPC_MMU_UNKNOWN = 0x00000000,
94 /* Standard 32 bits PowerPC MMU */
95 POWERPC_MMU_32B = 0x00000001,
96 /* PowerPC 6xx MMU with software TLB */
97 POWERPC_MMU_SOFT_6xx = 0x00000002,
98 /* PowerPC 74xx MMU with software TLB */
99 POWERPC_MMU_SOFT_74xx = 0x00000003,
100 /* PowerPC 4xx MMU with software TLB */
101 POWERPC_MMU_SOFT_4xx = 0x00000004,
102 /* PowerPC 4xx MMU with software TLB and zones protections */
103 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
104 /* PowerPC MMU in real mode only */
105 POWERPC_MMU_REAL = 0x00000006,
106 /* Freescale MPC8xx MMU model */
107 POWERPC_MMU_MPC8xx = 0x00000007,
108 /* BookE MMU model */
109 POWERPC_MMU_BOOKE = 0x00000008,
110 /* BookE 2.06 MMU model */
111 POWERPC_MMU_BOOKE206 = 0x00000009,
112 /* PowerPC 601 MMU model (specific BATs format) */
113 POWERPC_MMU_601 = 0x0000000A,
114 #if defined(TARGET_PPC64)
115 #define POWERPC_MMU_64 0x00010000
116 #define POWERPC_MMU_1TSEG 0x00020000
117 #define POWERPC_MMU_AMR 0x00040000
118 /* 64 bits PowerPC MMU */
119 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
120 /* Architecture 2.06 variant */
121 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
122 | POWERPC_MMU_AMR | 0x00000003,
123 /* Architecture 2.06 "degraded" (no 1T segments) */
124 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
125 | 0x00000003,
126 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
127 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
128 #endif /* defined(TARGET_PPC64) */
129 };
130
131 /*****************************************************************************/
132 /* Exception model */
133 typedef enum powerpc_excp_t powerpc_excp_t;
134 enum powerpc_excp_t {
135 POWERPC_EXCP_UNKNOWN = 0,
136 /* Standard PowerPC exception model */
137 POWERPC_EXCP_STD,
138 /* PowerPC 40x exception model */
139 POWERPC_EXCP_40x,
140 /* PowerPC 601 exception model */
141 POWERPC_EXCP_601,
142 /* PowerPC 602 exception model */
143 POWERPC_EXCP_602,
144 /* PowerPC 603 exception model */
145 POWERPC_EXCP_603,
146 /* PowerPC 603e exception model */
147 POWERPC_EXCP_603E,
148 /* PowerPC G2 exception model */
149 POWERPC_EXCP_G2,
150 /* PowerPC 604 exception model */
151 POWERPC_EXCP_604,
152 /* PowerPC 7x0 exception model */
153 POWERPC_EXCP_7x0,
154 /* PowerPC 7x5 exception model */
155 POWERPC_EXCP_7x5,
156 /* PowerPC 74xx exception model */
157 POWERPC_EXCP_74xx,
158 /* BookE exception model */
159 POWERPC_EXCP_BOOKE,
160 #if defined(TARGET_PPC64)
161 /* PowerPC 970 exception model */
162 POWERPC_EXCP_970,
163 /* POWER7 exception model */
164 POWERPC_EXCP_POWER7,
165 #endif /* defined(TARGET_PPC64) */
166 };
167
168 /*****************************************************************************/
169 /* Exception vectors definitions */
170 enum {
171 POWERPC_EXCP_NONE = -1,
172 /* The 64 first entries are used by the PowerPC embedded specification */
173 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
174 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
175 POWERPC_EXCP_DSI = 2, /* Data storage exception */
176 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
177 POWERPC_EXCP_EXTERNAL = 4, /* External input */
178 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
179 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
180 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
181 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
182 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
183 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
184 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
185 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
186 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
187 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
188 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
189 /* Vectors 16 to 31 are reserved */
190 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
191 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
192 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
193 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
194 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
195 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
196 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
197 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
198 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
199 /* Vectors 42 to 63 are reserved */
200 /* Exceptions defined in the PowerPC server specification */
201 POWERPC_EXCP_RESET = 64, /* System reset exception */
202 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
203 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
204 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
205 POWERPC_EXCP_TRACE = 68, /* Trace exception */
206 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
207 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
208 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
209 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
210 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
211 /* 40x specific exceptions */
212 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
213 /* 601 specific exceptions */
214 POWERPC_EXCP_IO = 75, /* IO error exception */
215 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
216 /* 602 specific exceptions */
217 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
218 /* 602/603 specific exceptions */
219 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
220 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
221 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
222 /* Exceptions available on most PowerPC */
223 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
224 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
225 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
226 POWERPC_EXCP_SMI = 84, /* System management interrupt */
227 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
228 /* 7xx/74xx specific exceptions */
229 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
230 /* 74xx specific exceptions */
231 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
232 /* 970FX specific exceptions */
233 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
234 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
235 /* Freescale embedded cores specific exceptions */
236 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
237 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
238 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
239 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
240 /* VSX Unavailable (Power ISA 2.06 and later) */
241 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
242 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
243 /* EOL */
244 POWERPC_EXCP_NB = 96,
245 /* QEMU exceptions: used internally during code translation */
246 POWERPC_EXCP_STOP = 0x200, /* stop translation */
247 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
248 /* QEMU exceptions: special cases we want to stop translation */
249 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
250 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
251 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
252 };
253
254 /* Exceptions error codes */
255 enum {
256 /* Exception subtypes for POWERPC_EXCP_ALIGN */
257 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
258 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
259 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
260 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
261 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
262 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
263 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
264 /* FP exceptions */
265 POWERPC_EXCP_FP = 0x10,
266 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
267 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
268 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
269 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
270 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
271 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
272 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
273 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
274 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
275 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
276 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
277 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
278 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
279 /* Invalid instruction */
280 POWERPC_EXCP_INVAL = 0x20,
281 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
282 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
283 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
284 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
285 /* Privileged instruction */
286 POWERPC_EXCP_PRIV = 0x30,
287 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
288 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
289 /* Trap */
290 POWERPC_EXCP_TRAP = 0x40,
291 };
292
293 /*****************************************************************************/
294 /* Input pins model */
295 typedef enum powerpc_input_t powerpc_input_t;
296 enum powerpc_input_t {
297 PPC_FLAGS_INPUT_UNKNOWN = 0,
298 /* PowerPC 6xx bus */
299 PPC_FLAGS_INPUT_6xx,
300 /* BookE bus */
301 PPC_FLAGS_INPUT_BookE,
302 /* PowerPC 405 bus */
303 PPC_FLAGS_INPUT_405,
304 /* PowerPC 970 bus */
305 PPC_FLAGS_INPUT_970,
306 /* PowerPC POWER7 bus */
307 PPC_FLAGS_INPUT_POWER7,
308 /* PowerPC 401 bus */
309 PPC_FLAGS_INPUT_401,
310 /* Freescale RCPU bus */
311 PPC_FLAGS_INPUT_RCPU,
312 };
313
314 #define PPC_INPUT(env) (env->bus_model)
315
316 /*****************************************************************************/
317 typedef struct opc_handler_t opc_handler_t;
318
319 /*****************************************************************************/
320 /* Types used to describe some PowerPC registers */
321 typedef struct CPUPPCState CPUPPCState;
322 typedef struct DisasContext DisasContext;
323 typedef struct ppc_tb_t ppc_tb_t;
324 typedef struct ppc_spr_t ppc_spr_t;
325 typedef struct ppc_dcr_t ppc_dcr_t;
326 typedef union ppc_avr_t ppc_avr_t;
327 typedef union ppc_tlb_t ppc_tlb_t;
328
329 /* SPR access micro-ops generations callbacks */
330 struct ppc_spr_t {
331 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
332 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
333 #if !defined(CONFIG_USER_ONLY)
334 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
335 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
336 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
337 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
338 #endif
339 const char *name;
340 target_ulong default_value;
341 #ifdef CONFIG_KVM
342 /* We (ab)use the fact that all the SPRs will have ids for the
343 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
344 * don't sync this */
345 uint64_t one_reg_id;
346 #endif
347 };
348
349 /* Altivec registers (128 bits) */
350 union ppc_avr_t {
351 float32 f[4];
352 uint8_t u8[16];
353 uint16_t u16[8];
354 uint32_t u32[4];
355 int8_t s8[16];
356 int16_t s16[8];
357 int32_t s32[4];
358 uint64_t u64[2];
359 int64_t s64[2];
360 #ifdef CONFIG_INT128
361 __uint128_t u128;
362 #endif
363 };
364
365 #if !defined(CONFIG_USER_ONLY)
366 /* Software TLB cache */
367 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
368 struct ppc6xx_tlb_t {
369 target_ulong pte0;
370 target_ulong pte1;
371 target_ulong EPN;
372 };
373
374 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
375 struct ppcemb_tlb_t {
376 uint64_t RPN;
377 target_ulong EPN;
378 target_ulong PID;
379 target_ulong size;
380 uint32_t prot;
381 uint32_t attr; /* Storage attributes */
382 };
383
384 typedef struct ppcmas_tlb_t {
385 uint32_t mas8;
386 uint32_t mas1;
387 uint64_t mas2;
388 uint64_t mas7_3;
389 } ppcmas_tlb_t;
390
391 union ppc_tlb_t {
392 ppc6xx_tlb_t *tlb6;
393 ppcemb_tlb_t *tlbe;
394 ppcmas_tlb_t *tlbm;
395 };
396
397 /* possible TLB variants */
398 #define TLB_NONE 0
399 #define TLB_6XX 1
400 #define TLB_EMB 2
401 #define TLB_MAS 3
402 #endif
403
404 #define SDR_32_HTABORG 0xFFFF0000UL
405 #define SDR_32_HTABMASK 0x000001FFUL
406
407 #if defined(TARGET_PPC64)
408 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
409 #define SDR_64_HTABSIZE 0x000000000000001FULL
410 #endif /* defined(TARGET_PPC64 */
411
412 typedef struct ppc_slb_t ppc_slb_t;
413 struct ppc_slb_t {
414 uint64_t esid;
415 uint64_t vsid;
416 };
417
418 #define MAX_SLB_ENTRIES 64
419 #define SEGMENT_SHIFT_256M 28
420 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
421
422 #define SEGMENT_SHIFT_1T 40
423 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
424
425
426 /*****************************************************************************/
427 /* Machine state register bits definition */
428 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
429 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
430 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
431 #define MSR_SHV 60 /* hypervisor state hflags */
432 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
433 #define MSR_TS1 33
434 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
435 #define MSR_CM 31 /* Computation mode for BookE hflags */
436 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
437 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
438 #define MSR_GS 28 /* guest state for BookE */
439 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
440 #define MSR_VR 25 /* altivec available x hflags */
441 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
442 #define MSR_AP 23 /* Access privilege state on 602 hflags */
443 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
444 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
445 #define MSR_KEY 19 /* key bit on 603e */
446 #define MSR_POW 18 /* Power management */
447 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
448 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
449 #define MSR_ILE 16 /* Interrupt little-endian mode */
450 #define MSR_EE 15 /* External interrupt enable */
451 #define MSR_PR 14 /* Problem state hflags */
452 #define MSR_FP 13 /* Floating point available hflags */
453 #define MSR_ME 12 /* Machine check interrupt enable */
454 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
455 #define MSR_SE 10 /* Single-step trace enable x hflags */
456 #define MSR_DWE 10 /* Debug wait enable on 405 x */
457 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
458 #define MSR_BE 9 /* Branch trace enable x hflags */
459 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
460 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
461 #define MSR_AL 7 /* AL bit on POWER */
462 #define MSR_EP 6 /* Exception prefix on 601 */
463 #define MSR_IR 5 /* Instruction relocate */
464 #define MSR_DR 4 /* Data relocate */
465 #define MSR_PE 3 /* Protection enable on 403 */
466 #define MSR_PX 2 /* Protection exclusive on 403 x */
467 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
468 #define MSR_RI 1 /* Recoverable interrupt 1 */
469 #define MSR_LE 0 /* Little-endian mode 1 hflags */
470
471 #define LPCR_ILE (1 << (63-38))
472 #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
473 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
474
475 #define msr_sf ((env->msr >> MSR_SF) & 1)
476 #define msr_isf ((env->msr >> MSR_ISF) & 1)
477 #define msr_shv ((env->msr >> MSR_SHV) & 1)
478 #define msr_cm ((env->msr >> MSR_CM) & 1)
479 #define msr_icm ((env->msr >> MSR_ICM) & 1)
480 #define msr_thv ((env->msr >> MSR_THV) & 1)
481 #define msr_gs ((env->msr >> MSR_GS) & 1)
482 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
483 #define msr_vr ((env->msr >> MSR_VR) & 1)
484 #define msr_spe ((env->msr >> MSR_SPE) & 1)
485 #define msr_ap ((env->msr >> MSR_AP) & 1)
486 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
487 #define msr_sa ((env->msr >> MSR_SA) & 1)
488 #define msr_key ((env->msr >> MSR_KEY) & 1)
489 #define msr_pow ((env->msr >> MSR_POW) & 1)
490 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
491 #define msr_ce ((env->msr >> MSR_CE) & 1)
492 #define msr_ile ((env->msr >> MSR_ILE) & 1)
493 #define msr_ee ((env->msr >> MSR_EE) & 1)
494 #define msr_pr ((env->msr >> MSR_PR) & 1)
495 #define msr_fp ((env->msr >> MSR_FP) & 1)
496 #define msr_me ((env->msr >> MSR_ME) & 1)
497 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
498 #define msr_se ((env->msr >> MSR_SE) & 1)
499 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
500 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
501 #define msr_be ((env->msr >> MSR_BE) & 1)
502 #define msr_de ((env->msr >> MSR_DE) & 1)
503 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
504 #define msr_al ((env->msr >> MSR_AL) & 1)
505 #define msr_ep ((env->msr >> MSR_EP) & 1)
506 #define msr_ir ((env->msr >> MSR_IR) & 1)
507 #define msr_dr ((env->msr >> MSR_DR) & 1)
508 #define msr_pe ((env->msr >> MSR_PE) & 1)
509 #define msr_px ((env->msr >> MSR_PX) & 1)
510 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
511 #define msr_ri ((env->msr >> MSR_RI) & 1)
512 #define msr_le ((env->msr >> MSR_LE) & 1)
513 #define msr_ts ((env->msr >> MSR_TS1) & 3)
514 #define msr_tm ((env->msr >> MSR_TM) & 1)
515
516 /* Hypervisor bit is more specific */
517 #if defined(TARGET_PPC64)
518 #define MSR_HVB (1ULL << MSR_SHV)
519 #define msr_hv msr_shv
520 #else
521 #if defined(PPC_EMULATE_32BITS_HYPV)
522 #define MSR_HVB (1ULL << MSR_THV)
523 #define msr_hv msr_thv
524 #else
525 #define MSR_HVB (0ULL)
526 #define msr_hv (0)
527 #endif
528 #endif
529
530 /* Facility Status and Control (FSCR) bits */
531 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
532 #define FSCR_TAR (63 - 55) /* Target Address Register */
533 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
534 #define FSCR_IC_MASK (0xFFULL)
535 #define FSCR_IC_POS (63 - 7)
536 #define FSCR_IC_DSCR_SPR3 2
537 #define FSCR_IC_PMU 3
538 #define FSCR_IC_BHRB 4
539 #define FSCR_IC_TM 5
540 #define FSCR_IC_EBB 7
541 #define FSCR_IC_TAR 8
542
543 /* Exception state register bits definition */
544 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
545 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
546 #define ESR_PTR (1 << (63 - 38)) /* Trap */
547 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
548 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
549 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
550 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
551 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
552 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
553 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
554 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
555 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
556 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
557 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
558 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
559 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
560
561 /* Transaction EXception And Summary Register bits */
562 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
563 #define TEXASR_DISALLOWED (63 - 8)
564 #define TEXASR_NESTING_OVERFLOW (63 - 9)
565 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
566 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
567 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
568 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
569 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
570 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
571 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
572 #define TEXASR_ABORT (63 - 31)
573 #define TEXASR_SUSPENDED (63 - 32)
574 #define TEXASR_PRIVILEGE_HV (63 - 34)
575 #define TEXASR_PRIVILEGE_PR (63 - 35)
576 #define TEXASR_FAILURE_SUMMARY (63 - 36)
577 #define TEXASR_TFIAR_EXACT (63 - 37)
578 #define TEXASR_ROT (63 - 38)
579 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
580
581 enum {
582 POWERPC_FLAG_NONE = 0x00000000,
583 /* Flag for MSR bit 25 signification (VRE/SPE) */
584 POWERPC_FLAG_SPE = 0x00000001,
585 POWERPC_FLAG_VRE = 0x00000002,
586 /* Flag for MSR bit 17 signification (TGPR/CE) */
587 POWERPC_FLAG_TGPR = 0x00000004,
588 POWERPC_FLAG_CE = 0x00000008,
589 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
590 POWERPC_FLAG_SE = 0x00000010,
591 POWERPC_FLAG_DWE = 0x00000020,
592 POWERPC_FLAG_UBLE = 0x00000040,
593 /* Flag for MSR bit 9 signification (BE/DE) */
594 POWERPC_FLAG_BE = 0x00000080,
595 POWERPC_FLAG_DE = 0x00000100,
596 /* Flag for MSR bit 2 signification (PX/PMM) */
597 POWERPC_FLAG_PX = 0x00000200,
598 POWERPC_FLAG_PMM = 0x00000400,
599 /* Flag for special features */
600 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
601 POWERPC_FLAG_RTC_CLK = 0x00010000,
602 POWERPC_FLAG_BUS_CLK = 0x00020000,
603 /* Has CFAR */
604 POWERPC_FLAG_CFAR = 0x00040000,
605 /* Has VSX */
606 POWERPC_FLAG_VSX = 0x00080000,
607 /* Has Transaction Memory (ISA 2.07) */
608 POWERPC_FLAG_TM = 0x00100000,
609 };
610
611 /*****************************************************************************/
612 /* Floating point status and control register */
613 #define FPSCR_FX 31 /* Floating-point exception summary */
614 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
615 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
616 #define FPSCR_OX 28 /* Floating-point overflow exception */
617 #define FPSCR_UX 27 /* Floating-point underflow exception */
618 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
619 #define FPSCR_XX 25 /* Floating-point inexact exception */
620 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
621 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
622 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
623 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
624 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
625 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
626 #define FPSCR_FR 18 /* Floating-point fraction rounded */
627 #define FPSCR_FI 17 /* Floating-point fraction inexact */
628 #define FPSCR_C 16 /* Floating-point result class descriptor */
629 #define FPSCR_FL 15 /* Floating-point less than or negative */
630 #define FPSCR_FG 14 /* Floating-point greater than or negative */
631 #define FPSCR_FE 13 /* Floating-point equal or zero */
632 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
633 #define FPSCR_FPCC 12 /* Floating-point condition code */
634 #define FPSCR_FPRF 12 /* Floating-point result flags */
635 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
636 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
637 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
638 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
639 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
640 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
641 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
642 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
643 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
644 #define FPSCR_RN1 1
645 #define FPSCR_RN 0 /* Floating-point rounding control */
646 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
647 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
648 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
649 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
650 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
651 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
652 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
653 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
654 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
655 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
656 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
657 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
658 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
659 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
660 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
661 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
662 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
663 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
664 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
665 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
666 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
667 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
668 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
669 /* Invalid operation exception summary */
670 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
671 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
672 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
673 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
674 (1 << FPSCR_VXCVI)))
675 /* exception summary */
676 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
677 /* enabled exception summary */
678 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
679 0x1F)
680
681 /*****************************************************************************/
682 /* Vector status and control register */
683 #define VSCR_NJ 16 /* Vector non-java */
684 #define VSCR_SAT 0 /* Vector saturation */
685 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
686 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
687
688 /*****************************************************************************/
689 /* BookE e500 MMU registers */
690
691 #define MAS0_NV_SHIFT 0
692 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
693
694 #define MAS0_WQ_SHIFT 12
695 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
696 /* Write TLB entry regardless of reservation */
697 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
698 /* Write TLB entry only already in use */
699 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
700 /* Clear TLB entry */
701 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
702
703 #define MAS0_HES_SHIFT 14
704 #define MAS0_HES (1 << MAS0_HES_SHIFT)
705
706 #define MAS0_ESEL_SHIFT 16
707 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
708
709 #define MAS0_TLBSEL_SHIFT 28
710 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
711 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
712 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
713 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
714 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
715
716 #define MAS0_ATSEL_SHIFT 31
717 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
718 #define MAS0_ATSEL_TLB 0
719 #define MAS0_ATSEL_LRAT MAS0_ATSEL
720
721 #define MAS1_TSIZE_SHIFT 7
722 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
723
724 #define MAS1_TS_SHIFT 12
725 #define MAS1_TS (1 << MAS1_TS_SHIFT)
726
727 #define MAS1_IND_SHIFT 13
728 #define MAS1_IND (1 << MAS1_IND_SHIFT)
729
730 #define MAS1_TID_SHIFT 16
731 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
732
733 #define MAS1_IPROT_SHIFT 30
734 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
735
736 #define MAS1_VALID_SHIFT 31
737 #define MAS1_VALID 0x80000000
738
739 #define MAS2_EPN_SHIFT 12
740 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
741
742 #define MAS2_ACM_SHIFT 6
743 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
744
745 #define MAS2_VLE_SHIFT 5
746 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
747
748 #define MAS2_W_SHIFT 4
749 #define MAS2_W (1 << MAS2_W_SHIFT)
750
751 #define MAS2_I_SHIFT 3
752 #define MAS2_I (1 << MAS2_I_SHIFT)
753
754 #define MAS2_M_SHIFT 2
755 #define MAS2_M (1 << MAS2_M_SHIFT)
756
757 #define MAS2_G_SHIFT 1
758 #define MAS2_G (1 << MAS2_G_SHIFT)
759
760 #define MAS2_E_SHIFT 0
761 #define MAS2_E (1 << MAS2_E_SHIFT)
762
763 #define MAS3_RPN_SHIFT 12
764 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
765
766 #define MAS3_U0 0x00000200
767 #define MAS3_U1 0x00000100
768 #define MAS3_U2 0x00000080
769 #define MAS3_U3 0x00000040
770 #define MAS3_UX 0x00000020
771 #define MAS3_SX 0x00000010
772 #define MAS3_UW 0x00000008
773 #define MAS3_SW 0x00000004
774 #define MAS3_UR 0x00000002
775 #define MAS3_SR 0x00000001
776 #define MAS3_SPSIZE_SHIFT 1
777 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
778
779 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
780 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
781 #define MAS4_TIDSELD_MASK 0x00030000
782 #define MAS4_TIDSELD_PID0 0x00000000
783 #define MAS4_TIDSELD_PID1 0x00010000
784 #define MAS4_TIDSELD_PID2 0x00020000
785 #define MAS4_TIDSELD_PIDZ 0x00030000
786 #define MAS4_INDD 0x00008000 /* Default IND */
787 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
788 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
789 #define MAS4_ACMD 0x00000040
790 #define MAS4_VLED 0x00000020
791 #define MAS4_WD 0x00000010
792 #define MAS4_ID 0x00000008
793 #define MAS4_MD 0x00000004
794 #define MAS4_GD 0x00000002
795 #define MAS4_ED 0x00000001
796 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
797 #define MAS4_WIMGED_SHIFT 0
798
799 #define MAS5_SGS 0x80000000
800 #define MAS5_SLPID_MASK 0x00000fff
801
802 #define MAS6_SPID0 0x3fff0000
803 #define MAS6_SPID1 0x00007ffe
804 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
805 #define MAS6_SAS 0x00000001
806 #define MAS6_SPID MAS6_SPID0
807 #define MAS6_SIND 0x00000002 /* Indirect page */
808 #define MAS6_SIND_SHIFT 1
809 #define MAS6_SPID_MASK 0x3fff0000
810 #define MAS6_SPID_SHIFT 16
811 #define MAS6_ISIZE_MASK 0x00000f80
812 #define MAS6_ISIZE_SHIFT 7
813
814 #define MAS7_RPN 0xffffffff
815
816 #define MAS8_TGS 0x80000000
817 #define MAS8_VF 0x40000000
818 #define MAS8_TLBPID 0x00000fff
819
820 /* Bit definitions for MMUCFG */
821 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
822 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
823 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
824 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
825 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
826 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
827 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
828 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
829 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
830
831 /* Bit definitions for MMUCSR0 */
832 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
833 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
834 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
835 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
836 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
837 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
838 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
839 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
840 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
841 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
842
843 /* TLBnCFG encoding */
844 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
845 #define TLBnCFG_HES 0x00002000 /* HW select supported */
846 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
847 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
848 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
849 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
850 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
851 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
852 #define TLBnCFG_MINSIZE_SHIFT 20
853 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
854 #define TLBnCFG_MAXSIZE_SHIFT 16
855 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
856 #define TLBnCFG_ASSOC_SHIFT 24
857
858 /* TLBnPS encoding */
859 #define TLBnPS_4K 0x00000004
860 #define TLBnPS_8K 0x00000008
861 #define TLBnPS_16K 0x00000010
862 #define TLBnPS_32K 0x00000020
863 #define TLBnPS_64K 0x00000040
864 #define TLBnPS_128K 0x00000080
865 #define TLBnPS_256K 0x00000100
866 #define TLBnPS_512K 0x00000200
867 #define TLBnPS_1M 0x00000400
868 #define TLBnPS_2M 0x00000800
869 #define TLBnPS_4M 0x00001000
870 #define TLBnPS_8M 0x00002000
871 #define TLBnPS_16M 0x00004000
872 #define TLBnPS_32M 0x00008000
873 #define TLBnPS_64M 0x00010000
874 #define TLBnPS_128M 0x00020000
875 #define TLBnPS_256M 0x00040000
876 #define TLBnPS_512M 0x00080000
877 #define TLBnPS_1G 0x00100000
878 #define TLBnPS_2G 0x00200000
879 #define TLBnPS_4G 0x00400000
880 #define TLBnPS_8G 0x00800000
881 #define TLBnPS_16G 0x01000000
882 #define TLBnPS_32G 0x02000000
883 #define TLBnPS_64G 0x04000000
884 #define TLBnPS_128G 0x08000000
885 #define TLBnPS_256G 0x10000000
886
887 /* tlbilx action encoding */
888 #define TLBILX_T_ALL 0
889 #define TLBILX_T_TID 1
890 #define TLBILX_T_FULLMATCH 3
891 #define TLBILX_T_CLASS0 4
892 #define TLBILX_T_CLASS1 5
893 #define TLBILX_T_CLASS2 6
894 #define TLBILX_T_CLASS3 7
895
896 /* BookE 2.06 helper defines */
897
898 #define BOOKE206_FLUSH_TLB0 (1 << 0)
899 #define BOOKE206_FLUSH_TLB1 (1 << 1)
900 #define BOOKE206_FLUSH_TLB2 (1 << 2)
901 #define BOOKE206_FLUSH_TLB3 (1 << 3)
902
903 /* number of possible TLBs */
904 #define BOOKE206_MAX_TLBN 4
905
906 /*****************************************************************************/
907 /* Embedded.Processor Control */
908
909 #define DBELL_TYPE_SHIFT 27
910 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
911 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
912 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
913 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
914 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
915 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
916
917 #define DBELL_BRDCAST (1 << 26)
918 #define DBELL_LPIDTAG_SHIFT 14
919 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
920 #define DBELL_PIRTAG_MASK 0x3fff
921
922 /*****************************************************************************/
923 /* Segment page size information, used by recent hash MMUs
924 * The format of this structure mirrors kvm_ppc_smmu_info
925 */
926
927 #define PPC_PAGE_SIZES_MAX_SZ 8
928
929 struct ppc_one_page_size {
930 uint32_t page_shift; /* Page shift (or 0) */
931 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
932 };
933
934 struct ppc_one_seg_page_size {
935 uint32_t page_shift; /* Base page shift of segment (or 0) */
936 uint32_t slb_enc; /* SLB encoding for BookS */
937 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
938 };
939
940 struct ppc_segment_page_sizes {
941 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
942 };
943
944
945 /*****************************************************************************/
946 /* The whole PowerPC CPU context */
947 #define NB_MMU_MODES 3
948
949 #define PPC_CPU_OPCODES_LEN 0x40
950 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
951
952 struct CPUPPCState {
953 /* First are the most commonly used resources
954 * during translated code execution
955 */
956 /* general purpose registers */
957 target_ulong gpr[32];
958 /* Storage for GPR MSB, used by the SPE extension */
959 target_ulong gprh[32];
960 /* LR */
961 target_ulong lr;
962 /* CTR */
963 target_ulong ctr;
964 /* condition register */
965 uint32_t crf[8];
966 #if defined(TARGET_PPC64)
967 /* CFAR */
968 target_ulong cfar;
969 #endif
970 /* XER (with SO, OV, CA split out) */
971 target_ulong xer;
972 target_ulong so;
973 target_ulong ov;
974 target_ulong ca;
975 /* Reservation address */
976 target_ulong reserve_addr;
977 /* Reservation value */
978 target_ulong reserve_val;
979 target_ulong reserve_val2;
980 /* Reservation store address */
981 target_ulong reserve_ea;
982 /* Reserved store source register and size */
983 target_ulong reserve_info;
984
985 /* Those ones are used in supervisor mode only */
986 /* machine state register */
987 target_ulong msr;
988 /* temporary general purpose registers */
989 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
990
991 /* Floating point execution context */
992 float_status fp_status;
993 /* floating point registers */
994 float64 fpr[32];
995 /* floating point status and control register */
996 target_ulong fpscr;
997
998 /* Next instruction pointer */
999 target_ulong nip;
1000
1001 int access_type; /* when a memory exception occurs, the access
1002 type is stored here */
1003
1004 CPU_COMMON
1005
1006 /* MMU context - only relevant for full system emulation */
1007 #if !defined(CONFIG_USER_ONLY)
1008 #if defined(TARGET_PPC64)
1009 /* PowerPC 64 SLB area */
1010 ppc_slb_t slb[MAX_SLB_ENTRIES];
1011 int32_t slb_nr;
1012 #endif
1013 /* segment registers */
1014 hwaddr htab_base;
1015 /* mask used to normalize hash value to PTEG index */
1016 hwaddr htab_mask;
1017 target_ulong sr[32];
1018 /* externally stored hash table */
1019 uint8_t *external_htab;
1020 /* BATs */
1021 uint32_t nb_BATs;
1022 target_ulong DBAT[2][8];
1023 target_ulong IBAT[2][8];
1024 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1025 int32_t nb_tlb; /* Total number of TLB */
1026 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1027 int nb_ways; /* Number of ways in the TLB set */
1028 int last_way; /* Last used way used to allocate TLB in a LRU way */
1029 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1030 int nb_pids; /* Number of available PID registers */
1031 int tlb_type; /* Type of TLB we're dealing with */
1032 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1033 /* 403 dedicated access protection registers */
1034 target_ulong pb[4];
1035 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1036 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1037 #endif
1038
1039 /* Other registers */
1040 /* Special purpose registers */
1041 target_ulong spr[1024];
1042 ppc_spr_t spr_cb[1024];
1043 /* Altivec registers */
1044 ppc_avr_t avr[32];
1045 uint32_t vscr;
1046 /* VSX registers */
1047 uint64_t vsr[32];
1048 /* SPE registers */
1049 uint64_t spe_acc;
1050 uint32_t spe_fscr;
1051 /* SPE and Altivec can share a status since they will never be used
1052 * simultaneously */
1053 float_status vec_status;
1054
1055 /* Internal devices resources */
1056 /* Time base and decrementer */
1057 ppc_tb_t *tb_env;
1058 /* Device control registers */
1059 ppc_dcr_t *dcr_env;
1060
1061 int dcache_line_size;
1062 int icache_line_size;
1063
1064 /* Those resources are used during exception processing */
1065 /* CPU model definition */
1066 target_ulong msr_mask;
1067 powerpc_mmu_t mmu_model;
1068 powerpc_excp_t excp_model;
1069 powerpc_input_t bus_model;
1070 int bfd_mach;
1071 uint32_t flags;
1072 uint64_t insns_flags;
1073 uint64_t insns_flags2;
1074 #if defined(TARGET_PPC64)
1075 struct ppc_segment_page_sizes sps;
1076 #endif
1077
1078 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1079 uint64_t vpa_addr;
1080 uint64_t slb_shadow_addr, slb_shadow_size;
1081 uint64_t dtl_addr, dtl_size;
1082 #endif /* TARGET_PPC64 */
1083
1084 int error_code;
1085 uint32_t pending_interrupts;
1086 #if !defined(CONFIG_USER_ONLY)
1087 /* This is the IRQ controller, which is implementation dependent
1088 * and only relevant when emulating a complete machine.
1089 */
1090 uint32_t irq_input_state;
1091 void **irq_inputs;
1092 /* Exception vectors */
1093 target_ulong excp_vectors[POWERPC_EXCP_NB];
1094 target_ulong excp_prefix;
1095 target_ulong ivor_mask;
1096 target_ulong ivpr_mask;
1097 target_ulong hreset_vector;
1098 hwaddr mpic_iack;
1099 /* true when the external proxy facility mode is enabled */
1100 bool mpic_proxy;
1101 #endif
1102
1103 /* Those resources are used only during code translation */
1104 /* opcode handlers */
1105 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1106
1107 /* Those resources are used only in QEMU core */
1108 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1109 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1110 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1111
1112 /* Power management */
1113 int (*check_pow)(CPUPPCState *env);
1114
1115 #if !defined(CONFIG_USER_ONLY)
1116 void *load_info; /* Holds boot loading state. */
1117 #endif
1118
1119 /* booke timers */
1120
1121 /* Specifies bit locations of the Time Base used to signal a fixed timer
1122 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1123 *
1124 * 0 selects the least significant bit.
1125 * 63 selects the most significant bit.
1126 */
1127 uint8_t fit_period[4];
1128 uint8_t wdt_period[4];
1129
1130 /* Transactional memory state */
1131 target_ulong tm_gpr[32];
1132 ppc_avr_t tm_vsr[64];
1133 uint64_t tm_cr;
1134 uint64_t tm_lr;
1135 uint64_t tm_ctr;
1136 uint64_t tm_fpscr;
1137 uint64_t tm_amr;
1138 uint64_t tm_ppr;
1139 uint64_t tm_vrsave;
1140 uint32_t tm_vscr;
1141 uint64_t tm_dscr;
1142 uint64_t tm_tar;
1143 };
1144
1145 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1146 do { \
1147 env->fit_period[0] = (a_); \
1148 env->fit_period[1] = (b_); \
1149 env->fit_period[2] = (c_); \
1150 env->fit_period[3] = (d_); \
1151 } while (0)
1152
1153 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1154 do { \
1155 env->wdt_period[0] = (a_); \
1156 env->wdt_period[1] = (b_); \
1157 env->wdt_period[2] = (c_); \
1158 env->wdt_period[3] = (d_); \
1159 } while (0)
1160
1161 #include "cpu-qom.h"
1162
1163 /*****************************************************************************/
1164 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1165 void ppc_translate_init(void);
1166 void gen_update_current_nip(void *opaque);
1167 int cpu_ppc_exec (CPUState *s);
1168 /* you can call this signal handler from your SIGBUS and SIGSEGV
1169 signal handlers to inform the virtual CPU of exceptions. non zero
1170 is returned if the signal was handled by the virtual CPU. */
1171 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1172 void *puc);
1173 #if defined(CONFIG_USER_ONLY)
1174 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1175 int mmu_idx);
1176 #endif
1177
1178 #if !defined(CONFIG_USER_ONLY)
1179 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1180 #endif /* !defined(CONFIG_USER_ONLY) */
1181 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1182
1183 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1184 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1185 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
1186
1187 /* Time-base and decrementer management */
1188 #ifndef NO_CPU_IO_DEFS
1189 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1190 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1191 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1192 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1193 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1194 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1195 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1196 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1197 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1198 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1199 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1200 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1201 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1202 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1203 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1204 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1205 #if !defined(CONFIG_USER_ONLY)
1206 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1207 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1208 target_ulong load_40x_pit (CPUPPCState *env);
1209 void store_40x_pit (CPUPPCState *env, target_ulong val);
1210 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1211 void store_40x_sler (CPUPPCState *env, uint32_t val);
1212 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1213 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1214 void ppc_tlb_invalidate_all (CPUPPCState *env);
1215 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1216 #endif
1217 #endif
1218
1219 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1220
1221 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1222 {
1223 uint64_t gprv;
1224
1225 gprv = env->gpr[gprn];
1226 if (env->flags & POWERPC_FLAG_SPE) {
1227 /* If the CPU implements the SPE extension, we have to get the
1228 * high bits of the GPR from the gprh storage area
1229 */
1230 gprv &= 0xFFFFFFFFULL;
1231 gprv |= (uint64_t)env->gprh[gprn] << 32;
1232 }
1233
1234 return gprv;
1235 }
1236
1237 /* Device control registers */
1238 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1239 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1240
1241 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1242
1243 #define cpu_exec cpu_ppc_exec
1244 #define cpu_gen_code cpu_ppc_gen_code
1245 #define cpu_signal_handler cpu_ppc_signal_handler
1246 #define cpu_list ppc_cpu_list
1247
1248 /* MMU modes definitions */
1249 #define MMU_MODE0_SUFFIX _user
1250 #define MMU_MODE1_SUFFIX _kernel
1251 #define MMU_MODE2_SUFFIX _hypv
1252 #define MMU_USER_IDX 0
1253 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1254 {
1255 return env->mmu_idx;
1256 }
1257
1258 #include "exec/cpu-all.h"
1259
1260 /*****************************************************************************/
1261 /* CRF definitions */
1262 #define CRF_LT 3
1263 #define CRF_GT 2
1264 #define CRF_EQ 1
1265 #define CRF_SO 0
1266 #define CRF_CH (1 << CRF_LT)
1267 #define CRF_CL (1 << CRF_GT)
1268 #define CRF_CH_OR_CL (1 << CRF_EQ)
1269 #define CRF_CH_AND_CL (1 << CRF_SO)
1270
1271 /* XER definitions */
1272 #define XER_SO 31
1273 #define XER_OV 30
1274 #define XER_CA 29
1275 #define XER_CMP 8
1276 #define XER_BC 0
1277 #define xer_so (env->so)
1278 #define xer_ov (env->ov)
1279 #define xer_ca (env->ca)
1280 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1281 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1282
1283 /* SPR definitions */
1284 #define SPR_MQ (0x000)
1285 #define SPR_XER (0x001)
1286 #define SPR_601_VRTCU (0x004)
1287 #define SPR_601_VRTCL (0x005)
1288 #define SPR_601_UDECR (0x006)
1289 #define SPR_LR (0x008)
1290 #define SPR_CTR (0x009)
1291 #define SPR_UAMR (0x00C)
1292 #define SPR_DSCR (0x011)
1293 #define SPR_DSISR (0x012)
1294 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1295 #define SPR_601_RTCU (0x014)
1296 #define SPR_601_RTCL (0x015)
1297 #define SPR_DECR (0x016)
1298 #define SPR_SDR1 (0x019)
1299 #define SPR_SRR0 (0x01A)
1300 #define SPR_SRR1 (0x01B)
1301 #define SPR_CFAR (0x01C)
1302 #define SPR_AMR (0x01D)
1303 #define SPR_BOOKE_PID (0x030)
1304 #define SPR_BOOKE_DECAR (0x036)
1305 #define SPR_BOOKE_CSRR0 (0x03A)
1306 #define SPR_BOOKE_CSRR1 (0x03B)
1307 #define SPR_BOOKE_DEAR (0x03D)
1308 #define SPR_BOOKE_ESR (0x03E)
1309 #define SPR_BOOKE_IVPR (0x03F)
1310 #define SPR_MPC_EIE (0x050)
1311 #define SPR_MPC_EID (0x051)
1312 #define SPR_MPC_NRI (0x052)
1313 #define SPR_TFHAR (0x080)
1314 #define SPR_TFIAR (0x081)
1315 #define SPR_TEXASR (0x082)
1316 #define SPR_TEXASRU (0x083)
1317 #define SPR_UCTRL (0x088)
1318 #define SPR_MPC_CMPA (0x090)
1319 #define SPR_MPC_CMPB (0x091)
1320 #define SPR_MPC_CMPC (0x092)
1321 #define SPR_MPC_CMPD (0x093)
1322 #define SPR_MPC_ECR (0x094)
1323 #define SPR_MPC_DER (0x095)
1324 #define SPR_MPC_COUNTA (0x096)
1325 #define SPR_MPC_COUNTB (0x097)
1326 #define SPR_CTRL (0x098)
1327 #define SPR_MPC_CMPE (0x098)
1328 #define SPR_MPC_CMPF (0x099)
1329 #define SPR_FSCR (0x099)
1330 #define SPR_MPC_CMPG (0x09A)
1331 #define SPR_MPC_CMPH (0x09B)
1332 #define SPR_MPC_LCTRL1 (0x09C)
1333 #define SPR_MPC_LCTRL2 (0x09D)
1334 #define SPR_UAMOR (0x09D)
1335 #define SPR_MPC_ICTRL (0x09E)
1336 #define SPR_MPC_BAR (0x09F)
1337 #define SPR_VRSAVE (0x100)
1338 #define SPR_USPRG0 (0x100)
1339 #define SPR_USPRG1 (0x101)
1340 #define SPR_USPRG2 (0x102)
1341 #define SPR_USPRG3 (0x103)
1342 #define SPR_USPRG4 (0x104)
1343 #define SPR_USPRG5 (0x105)
1344 #define SPR_USPRG6 (0x106)
1345 #define SPR_USPRG7 (0x107)
1346 #define SPR_VTBL (0x10C)
1347 #define SPR_VTBU (0x10D)
1348 #define SPR_SPRG0 (0x110)
1349 #define SPR_SPRG1 (0x111)
1350 #define SPR_SPRG2 (0x112)
1351 #define SPR_SPRG3 (0x113)
1352 #define SPR_SPRG4 (0x114)
1353 #define SPR_SCOMC (0x114)
1354 #define SPR_SPRG5 (0x115)
1355 #define SPR_SCOMD (0x115)
1356 #define SPR_SPRG6 (0x116)
1357 #define SPR_SPRG7 (0x117)
1358 #define SPR_ASR (0x118)
1359 #define SPR_EAR (0x11A)
1360 #define SPR_TBL (0x11C)
1361 #define SPR_TBU (0x11D)
1362 #define SPR_TBU40 (0x11E)
1363 #define SPR_SVR (0x11E)
1364 #define SPR_BOOKE_PIR (0x11E)
1365 #define SPR_PVR (0x11F)
1366 #define SPR_HSPRG0 (0x130)
1367 #define SPR_BOOKE_DBSR (0x130)
1368 #define SPR_HSPRG1 (0x131)
1369 #define SPR_HDSISR (0x132)
1370 #define SPR_HDAR (0x133)
1371 #define SPR_BOOKE_EPCR (0x133)
1372 #define SPR_SPURR (0x134)
1373 #define SPR_BOOKE_DBCR0 (0x134)
1374 #define SPR_IBCR (0x135)
1375 #define SPR_PURR (0x135)
1376 #define SPR_BOOKE_DBCR1 (0x135)
1377 #define SPR_DBCR (0x136)
1378 #define SPR_HDEC (0x136)
1379 #define SPR_BOOKE_DBCR2 (0x136)
1380 #define SPR_HIOR (0x137)
1381 #define SPR_MBAR (0x137)
1382 #define SPR_RMOR (0x138)
1383 #define SPR_BOOKE_IAC1 (0x138)
1384 #define SPR_HRMOR (0x139)
1385 #define SPR_BOOKE_IAC2 (0x139)
1386 #define SPR_HSRR0 (0x13A)
1387 #define SPR_BOOKE_IAC3 (0x13A)
1388 #define SPR_HSRR1 (0x13B)
1389 #define SPR_BOOKE_IAC4 (0x13B)
1390 #define SPR_BOOKE_DAC1 (0x13C)
1391 #define SPR_LPIDR (0x13D)
1392 #define SPR_DABR2 (0x13D)
1393 #define SPR_BOOKE_DAC2 (0x13D)
1394 #define SPR_BOOKE_DVC1 (0x13E)
1395 #define SPR_LPCR (0x13E)
1396 #define SPR_BOOKE_DVC2 (0x13F)
1397 #define SPR_BOOKE_TSR (0x150)
1398 #define SPR_PCR (0x152)
1399 #define SPR_BOOKE_TCR (0x154)
1400 #define SPR_BOOKE_TLB0PS (0x158)
1401 #define SPR_BOOKE_TLB1PS (0x159)
1402 #define SPR_BOOKE_TLB2PS (0x15A)
1403 #define SPR_BOOKE_TLB3PS (0x15B)
1404 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1405 #define SPR_BOOKE_IVOR0 (0x190)
1406 #define SPR_BOOKE_IVOR1 (0x191)
1407 #define SPR_BOOKE_IVOR2 (0x192)
1408 #define SPR_BOOKE_IVOR3 (0x193)
1409 #define SPR_BOOKE_IVOR4 (0x194)
1410 #define SPR_BOOKE_IVOR5 (0x195)
1411 #define SPR_BOOKE_IVOR6 (0x196)
1412 #define SPR_BOOKE_IVOR7 (0x197)
1413 #define SPR_BOOKE_IVOR8 (0x198)
1414 #define SPR_BOOKE_IVOR9 (0x199)
1415 #define SPR_BOOKE_IVOR10 (0x19A)
1416 #define SPR_BOOKE_IVOR11 (0x19B)
1417 #define SPR_BOOKE_IVOR12 (0x19C)
1418 #define SPR_BOOKE_IVOR13 (0x19D)
1419 #define SPR_BOOKE_IVOR14 (0x19E)
1420 #define SPR_BOOKE_IVOR15 (0x19F)
1421 #define SPR_BOOKE_IVOR38 (0x1B0)
1422 #define SPR_BOOKE_IVOR39 (0x1B1)
1423 #define SPR_BOOKE_IVOR40 (0x1B2)
1424 #define SPR_BOOKE_IVOR41 (0x1B3)
1425 #define SPR_BOOKE_IVOR42 (0x1B4)
1426 #define SPR_BOOKE_GIVOR2 (0x1B8)
1427 #define SPR_BOOKE_GIVOR3 (0x1B9)
1428 #define SPR_BOOKE_GIVOR4 (0x1BA)
1429 #define SPR_BOOKE_GIVOR8 (0x1BB)
1430 #define SPR_BOOKE_GIVOR13 (0x1BC)
1431 #define SPR_BOOKE_GIVOR14 (0x1BD)
1432 #define SPR_TIR (0x1BE)
1433 #define SPR_BOOKE_SPEFSCR (0x200)
1434 #define SPR_Exxx_BBEAR (0x201)
1435 #define SPR_Exxx_BBTAR (0x202)
1436 #define SPR_Exxx_L1CFG0 (0x203)
1437 #define SPR_Exxx_L1CFG1 (0x204)
1438 #define SPR_Exxx_NPIDR (0x205)
1439 #define SPR_ATBL (0x20E)
1440 #define SPR_ATBU (0x20F)
1441 #define SPR_IBAT0U (0x210)
1442 #define SPR_BOOKE_IVOR32 (0x210)
1443 #define SPR_RCPU_MI_GRA (0x210)
1444 #define SPR_IBAT0L (0x211)
1445 #define SPR_BOOKE_IVOR33 (0x211)
1446 #define SPR_IBAT1U (0x212)
1447 #define SPR_BOOKE_IVOR34 (0x212)
1448 #define SPR_IBAT1L (0x213)
1449 #define SPR_BOOKE_IVOR35 (0x213)
1450 #define SPR_IBAT2U (0x214)
1451 #define SPR_BOOKE_IVOR36 (0x214)
1452 #define SPR_IBAT2L (0x215)
1453 #define SPR_BOOKE_IVOR37 (0x215)
1454 #define SPR_IBAT3U (0x216)
1455 #define SPR_IBAT3L (0x217)
1456 #define SPR_DBAT0U (0x218)
1457 #define SPR_RCPU_L2U_GRA (0x218)
1458 #define SPR_DBAT0L (0x219)
1459 #define SPR_DBAT1U (0x21A)
1460 #define SPR_DBAT1L (0x21B)
1461 #define SPR_DBAT2U (0x21C)
1462 #define SPR_DBAT2L (0x21D)
1463 #define SPR_DBAT3U (0x21E)
1464 #define SPR_DBAT3L (0x21F)
1465 #define SPR_IBAT4U (0x230)
1466 #define SPR_RPCU_BBCMCR (0x230)
1467 #define SPR_MPC_IC_CST (0x230)
1468 #define SPR_Exxx_CTXCR (0x230)
1469 #define SPR_IBAT4L (0x231)
1470 #define SPR_MPC_IC_ADR (0x231)
1471 #define SPR_Exxx_DBCR3 (0x231)
1472 #define SPR_IBAT5U (0x232)
1473 #define SPR_MPC_IC_DAT (0x232)
1474 #define SPR_Exxx_DBCNT (0x232)
1475 #define SPR_IBAT5L (0x233)
1476 #define SPR_IBAT6U (0x234)
1477 #define SPR_IBAT6L (0x235)
1478 #define SPR_IBAT7U (0x236)
1479 #define SPR_IBAT7L (0x237)
1480 #define SPR_DBAT4U (0x238)
1481 #define SPR_RCPU_L2U_MCR (0x238)
1482 #define SPR_MPC_DC_CST (0x238)
1483 #define SPR_Exxx_ALTCTXCR (0x238)
1484 #define SPR_DBAT4L (0x239)
1485 #define SPR_MPC_DC_ADR (0x239)
1486 #define SPR_DBAT5U (0x23A)
1487 #define SPR_BOOKE_MCSRR0 (0x23A)
1488 #define SPR_MPC_DC_DAT (0x23A)
1489 #define SPR_DBAT5L (0x23B)
1490 #define SPR_BOOKE_MCSRR1 (0x23B)
1491 #define SPR_DBAT6U (0x23C)
1492 #define SPR_BOOKE_MCSR (0x23C)
1493 #define SPR_DBAT6L (0x23D)
1494 #define SPR_Exxx_MCAR (0x23D)
1495 #define SPR_DBAT7U (0x23E)
1496 #define SPR_BOOKE_DSRR0 (0x23E)
1497 #define SPR_DBAT7L (0x23F)
1498 #define SPR_BOOKE_DSRR1 (0x23F)
1499 #define SPR_BOOKE_SPRG8 (0x25C)
1500 #define SPR_BOOKE_SPRG9 (0x25D)
1501 #define SPR_BOOKE_MAS0 (0x270)
1502 #define SPR_BOOKE_MAS1 (0x271)
1503 #define SPR_BOOKE_MAS2 (0x272)
1504 #define SPR_BOOKE_MAS3 (0x273)
1505 #define SPR_BOOKE_MAS4 (0x274)
1506 #define SPR_BOOKE_MAS5 (0x275)
1507 #define SPR_BOOKE_MAS6 (0x276)
1508 #define SPR_BOOKE_PID1 (0x279)
1509 #define SPR_BOOKE_PID2 (0x27A)
1510 #define SPR_MPC_DPDR (0x280)
1511 #define SPR_MPC_IMMR (0x288)
1512 #define SPR_BOOKE_TLB0CFG (0x2B0)
1513 #define SPR_BOOKE_TLB1CFG (0x2B1)
1514 #define SPR_BOOKE_TLB2CFG (0x2B2)
1515 #define SPR_BOOKE_TLB3CFG (0x2B3)
1516 #define SPR_BOOKE_EPR (0x2BE)
1517 #define SPR_PERF0 (0x300)
1518 #define SPR_RCPU_MI_RBA0 (0x300)
1519 #define SPR_MPC_MI_CTR (0x300)
1520 #define SPR_PERF1 (0x301)
1521 #define SPR_RCPU_MI_RBA1 (0x301)
1522 #define SPR_POWER_UMMCR2 (0x301)
1523 #define SPR_PERF2 (0x302)
1524 #define SPR_RCPU_MI_RBA2 (0x302)
1525 #define SPR_MPC_MI_AP (0x302)
1526 #define SPR_POWER_UMMCRA (0x302)
1527 #define SPR_PERF3 (0x303)
1528 #define SPR_RCPU_MI_RBA3 (0x303)
1529 #define SPR_MPC_MI_EPN (0x303)
1530 #define SPR_POWER_UPMC1 (0x303)
1531 #define SPR_PERF4 (0x304)
1532 #define SPR_POWER_UPMC2 (0x304)
1533 #define SPR_PERF5 (0x305)
1534 #define SPR_MPC_MI_TWC (0x305)
1535 #define SPR_POWER_UPMC3 (0x305)
1536 #define SPR_PERF6 (0x306)
1537 #define SPR_MPC_MI_RPN (0x306)
1538 #define SPR_POWER_UPMC4 (0x306)
1539 #define SPR_PERF7 (0x307)
1540 #define SPR_POWER_UPMC5 (0x307)
1541 #define SPR_PERF8 (0x308)
1542 #define SPR_RCPU_L2U_RBA0 (0x308)
1543 #define SPR_MPC_MD_CTR (0x308)
1544 #define SPR_POWER_UPMC6 (0x308)
1545 #define SPR_PERF9 (0x309)
1546 #define SPR_RCPU_L2U_RBA1 (0x309)
1547 #define SPR_MPC_MD_CASID (0x309)
1548 #define SPR_970_UPMC7 (0X309)
1549 #define SPR_PERFA (0x30A)
1550 #define SPR_RCPU_L2U_RBA2 (0x30A)
1551 #define SPR_MPC_MD_AP (0x30A)
1552 #define SPR_970_UPMC8 (0X30A)
1553 #define SPR_PERFB (0x30B)
1554 #define SPR_RCPU_L2U_RBA3 (0x30B)
1555 #define SPR_MPC_MD_EPN (0x30B)
1556 #define SPR_POWER_UMMCR0 (0X30B)
1557 #define SPR_PERFC (0x30C)
1558 #define SPR_MPC_MD_TWB (0x30C)
1559 #define SPR_POWER_USIAR (0X30C)
1560 #define SPR_PERFD (0x30D)
1561 #define SPR_MPC_MD_TWC (0x30D)
1562 #define SPR_POWER_USDAR (0X30D)
1563 #define SPR_PERFE (0x30E)
1564 #define SPR_MPC_MD_RPN (0x30E)
1565 #define SPR_POWER_UMMCR1 (0X30E)
1566 #define SPR_PERFF (0x30F)
1567 #define SPR_MPC_MD_TW (0x30F)
1568 #define SPR_UPERF0 (0x310)
1569 #define SPR_UPERF1 (0x311)
1570 #define SPR_POWER_MMCR2 (0x311)
1571 #define SPR_UPERF2 (0x312)
1572 #define SPR_POWER_MMCRA (0X312)
1573 #define SPR_UPERF3 (0x313)
1574 #define SPR_POWER_PMC1 (0X313)
1575 #define SPR_UPERF4 (0x314)
1576 #define SPR_POWER_PMC2 (0X314)
1577 #define SPR_UPERF5 (0x315)
1578 #define SPR_POWER_PMC3 (0X315)
1579 #define SPR_UPERF6 (0x316)
1580 #define SPR_POWER_PMC4 (0X316)
1581 #define SPR_UPERF7 (0x317)
1582 #define SPR_POWER_PMC5 (0X317)
1583 #define SPR_UPERF8 (0x318)
1584 #define SPR_POWER_PMC6 (0X318)
1585 #define SPR_UPERF9 (0x319)
1586 #define SPR_970_PMC7 (0X319)
1587 #define SPR_UPERFA (0x31A)
1588 #define SPR_970_PMC8 (0X31A)
1589 #define SPR_UPERFB (0x31B)
1590 #define SPR_POWER_MMCR0 (0X31B)
1591 #define SPR_UPERFC (0x31C)
1592 #define SPR_POWER_SIAR (0X31C)
1593 #define SPR_UPERFD (0x31D)
1594 #define SPR_POWER_SDAR (0X31D)
1595 #define SPR_UPERFE (0x31E)
1596 #define SPR_POWER_MMCR1 (0X31E)
1597 #define SPR_UPERFF (0x31F)
1598 #define SPR_RCPU_MI_RA0 (0x320)
1599 #define SPR_MPC_MI_DBCAM (0x320)
1600 #define SPR_BESCRS (0x320)
1601 #define SPR_RCPU_MI_RA1 (0x321)
1602 #define SPR_MPC_MI_DBRAM0 (0x321)
1603 #define SPR_BESCRSU (0x321)
1604 #define SPR_RCPU_MI_RA2 (0x322)
1605 #define SPR_MPC_MI_DBRAM1 (0x322)
1606 #define SPR_BESCRR (0x322)
1607 #define SPR_RCPU_MI_RA3 (0x323)
1608 #define SPR_BESCRRU (0x323)
1609 #define SPR_EBBHR (0x324)
1610 #define SPR_EBBRR (0x325)
1611 #define SPR_BESCR (0x326)
1612 #define SPR_RCPU_L2U_RA0 (0x328)
1613 #define SPR_MPC_MD_DBCAM (0x328)
1614 #define SPR_RCPU_L2U_RA1 (0x329)
1615 #define SPR_MPC_MD_DBRAM0 (0x329)
1616 #define SPR_RCPU_L2U_RA2 (0x32A)
1617 #define SPR_MPC_MD_DBRAM1 (0x32A)
1618 #define SPR_RCPU_L2U_RA3 (0x32B)
1619 #define SPR_TAR (0x32F)
1620 #define SPR_VTB (0x351)
1621 #define SPR_440_INV0 (0x370)
1622 #define SPR_440_INV1 (0x371)
1623 #define SPR_440_INV2 (0x372)
1624 #define SPR_440_INV3 (0x373)
1625 #define SPR_440_ITV0 (0x374)
1626 #define SPR_440_ITV1 (0x375)
1627 #define SPR_440_ITV2 (0x376)
1628 #define SPR_440_ITV3 (0x377)
1629 #define SPR_440_CCR1 (0x378)
1630 #define SPR_DCRIPR (0x37B)
1631 #define SPR_POWER_MMCRS (0x37E)
1632 #define SPR_PPR (0x380)
1633 #define SPR_750_GQR0 (0x390)
1634 #define SPR_440_DNV0 (0x390)
1635 #define SPR_750_GQR1 (0x391)
1636 #define SPR_440_DNV1 (0x391)
1637 #define SPR_750_GQR2 (0x392)
1638 #define SPR_440_DNV2 (0x392)
1639 #define SPR_750_GQR3 (0x393)
1640 #define SPR_440_DNV3 (0x393)
1641 #define SPR_750_GQR4 (0x394)
1642 #define SPR_440_DTV0 (0x394)
1643 #define SPR_750_GQR5 (0x395)
1644 #define SPR_440_DTV1 (0x395)
1645 #define SPR_750_GQR6 (0x396)
1646 #define SPR_440_DTV2 (0x396)
1647 #define SPR_750_GQR7 (0x397)
1648 #define SPR_440_DTV3 (0x397)
1649 #define SPR_750_THRM4 (0x398)
1650 #define SPR_750CL_HID2 (0x398)
1651 #define SPR_440_DVLIM (0x398)
1652 #define SPR_750_WPAR (0x399)
1653 #define SPR_440_IVLIM (0x399)
1654 #define SPR_750_DMAU (0x39A)
1655 #define SPR_750_DMAL (0x39B)
1656 #define SPR_440_RSTCFG (0x39B)
1657 #define SPR_BOOKE_DCDBTRL (0x39C)
1658 #define SPR_BOOKE_DCDBTRH (0x39D)
1659 #define SPR_BOOKE_ICDBTRL (0x39E)
1660 #define SPR_BOOKE_ICDBTRH (0x39F)
1661 #define SPR_74XX_UMMCR2 (0x3A0)
1662 #define SPR_7XX_UPMC5 (0x3A1)
1663 #define SPR_7XX_UPMC6 (0x3A2)
1664 #define SPR_UBAMR (0x3A7)
1665 #define SPR_7XX_UMMCR0 (0x3A8)
1666 #define SPR_7XX_UPMC1 (0x3A9)
1667 #define SPR_7XX_UPMC2 (0x3AA)
1668 #define SPR_7XX_USIAR (0x3AB)
1669 #define SPR_7XX_UMMCR1 (0x3AC)
1670 #define SPR_7XX_UPMC3 (0x3AD)
1671 #define SPR_7XX_UPMC4 (0x3AE)
1672 #define SPR_USDA (0x3AF)
1673 #define SPR_40x_ZPR (0x3B0)
1674 #define SPR_BOOKE_MAS7 (0x3B0)
1675 #define SPR_74XX_MMCR2 (0x3B0)
1676 #define SPR_7XX_PMC5 (0x3B1)
1677 #define SPR_40x_PID (0x3B1)
1678 #define SPR_7XX_PMC6 (0x3B2)
1679 #define SPR_440_MMUCR (0x3B2)
1680 #define SPR_4xx_CCR0 (0x3B3)
1681 #define SPR_BOOKE_EPLC (0x3B3)
1682 #define SPR_405_IAC3 (0x3B4)
1683 #define SPR_BOOKE_EPSC (0x3B4)
1684 #define SPR_405_IAC4 (0x3B5)
1685 #define SPR_405_DVC1 (0x3B6)
1686 #define SPR_405_DVC2 (0x3B7)
1687 #define SPR_BAMR (0x3B7)
1688 #define SPR_7XX_MMCR0 (0x3B8)
1689 #define SPR_7XX_PMC1 (0x3B9)
1690 #define SPR_40x_SGR (0x3B9)
1691 #define SPR_7XX_PMC2 (0x3BA)
1692 #define SPR_40x_DCWR (0x3BA)
1693 #define SPR_7XX_SIAR (0x3BB)
1694 #define SPR_405_SLER (0x3BB)
1695 #define SPR_7XX_MMCR1 (0x3BC)
1696 #define SPR_405_SU0R (0x3BC)
1697 #define SPR_401_SKR (0x3BC)
1698 #define SPR_7XX_PMC3 (0x3BD)
1699 #define SPR_405_DBCR1 (0x3BD)
1700 #define SPR_7XX_PMC4 (0x3BE)
1701 #define SPR_SDA (0x3BF)
1702 #define SPR_403_VTBL (0x3CC)
1703 #define SPR_403_VTBU (0x3CD)
1704 #define SPR_DMISS (0x3D0)
1705 #define SPR_DCMP (0x3D1)
1706 #define SPR_HASH1 (0x3D2)
1707 #define SPR_HASH2 (0x3D3)
1708 #define SPR_BOOKE_ICDBDR (0x3D3)
1709 #define SPR_TLBMISS (0x3D4)
1710 #define SPR_IMISS (0x3D4)
1711 #define SPR_40x_ESR (0x3D4)
1712 #define SPR_PTEHI (0x3D5)
1713 #define SPR_ICMP (0x3D5)
1714 #define SPR_40x_DEAR (0x3D5)
1715 #define SPR_PTELO (0x3D6)
1716 #define SPR_RPA (0x3D6)
1717 #define SPR_40x_EVPR (0x3D6)
1718 #define SPR_L3PM (0x3D7)
1719 #define SPR_403_CDBCR (0x3D7)
1720 #define SPR_L3ITCR0 (0x3D8)
1721 #define SPR_TCR (0x3D8)
1722 #define SPR_40x_TSR (0x3D8)
1723 #define SPR_IBR (0x3DA)
1724 #define SPR_40x_TCR (0x3DA)
1725 #define SPR_ESASRR (0x3DB)
1726 #define SPR_40x_PIT (0x3DB)
1727 #define SPR_403_TBL (0x3DC)
1728 #define SPR_403_TBU (0x3DD)
1729 #define SPR_SEBR (0x3DE)
1730 #define SPR_40x_SRR2 (0x3DE)
1731 #define SPR_SER (0x3DF)
1732 #define SPR_40x_SRR3 (0x3DF)
1733 #define SPR_L3OHCR (0x3E8)
1734 #define SPR_L3ITCR1 (0x3E9)
1735 #define SPR_L3ITCR2 (0x3EA)
1736 #define SPR_L3ITCR3 (0x3EB)
1737 #define SPR_HID0 (0x3F0)
1738 #define SPR_40x_DBSR (0x3F0)
1739 #define SPR_HID1 (0x3F1)
1740 #define SPR_IABR (0x3F2)
1741 #define SPR_40x_DBCR0 (0x3F2)
1742 #define SPR_601_HID2 (0x3F2)
1743 #define SPR_Exxx_L1CSR0 (0x3F2)
1744 #define SPR_ICTRL (0x3F3)
1745 #define SPR_HID2 (0x3F3)
1746 #define SPR_750CL_HID4 (0x3F3)
1747 #define SPR_Exxx_L1CSR1 (0x3F3)
1748 #define SPR_440_DBDR (0x3F3)
1749 #define SPR_LDSTDB (0x3F4)
1750 #define SPR_750_TDCL (0x3F4)
1751 #define SPR_40x_IAC1 (0x3F4)
1752 #define SPR_MMUCSR0 (0x3F4)
1753 #define SPR_970_HID4 (0x3F4)
1754 #define SPR_DABR (0x3F5)
1755 #define DABR_MASK (~(target_ulong)0x7)
1756 #define SPR_Exxx_BUCSR (0x3F5)
1757 #define SPR_40x_IAC2 (0x3F5)
1758 #define SPR_601_HID5 (0x3F5)
1759 #define SPR_40x_DAC1 (0x3F6)
1760 #define SPR_MSSCR0 (0x3F6)
1761 #define SPR_970_HID5 (0x3F6)
1762 #define SPR_MSSSR0 (0x3F7)
1763 #define SPR_MSSCR1 (0x3F7)
1764 #define SPR_DABRX (0x3F7)
1765 #define SPR_40x_DAC2 (0x3F7)
1766 #define SPR_MMUCFG (0x3F7)
1767 #define SPR_LDSTCR (0x3F8)
1768 #define SPR_L2PMCR (0x3F8)
1769 #define SPR_750FX_HID2 (0x3F8)
1770 #define SPR_Exxx_L1FINV0 (0x3F8)
1771 #define SPR_L2CR (0x3F9)
1772 #define SPR_L3CR (0x3FA)
1773 #define SPR_750_TDCH (0x3FA)
1774 #define SPR_IABR2 (0x3FA)
1775 #define SPR_40x_DCCR (0x3FA)
1776 #define SPR_ICTC (0x3FB)
1777 #define SPR_40x_ICCR (0x3FB)
1778 #define SPR_THRM1 (0x3FC)
1779 #define SPR_403_PBL1 (0x3FC)
1780 #define SPR_SP (0x3FD)
1781 #define SPR_THRM2 (0x3FD)
1782 #define SPR_403_PBU1 (0x3FD)
1783 #define SPR_604_HID13 (0x3FD)
1784 #define SPR_LT (0x3FE)
1785 #define SPR_THRM3 (0x3FE)
1786 #define SPR_RCPU_FPECR (0x3FE)
1787 #define SPR_403_PBL2 (0x3FE)
1788 #define SPR_PIR (0x3FF)
1789 #define SPR_403_PBU2 (0x3FF)
1790 #define SPR_601_HID15 (0x3FF)
1791 #define SPR_604_HID15 (0x3FF)
1792 #define SPR_E500_SVR (0x3FF)
1793
1794 /* Disable MAS Interrupt Updates for Hypervisor */
1795 #define EPCR_DMIUH (1 << 22)
1796 /* Disable Guest TLB Management Instructions */
1797 #define EPCR_DGTMI (1 << 23)
1798 /* Guest Interrupt Computation Mode */
1799 #define EPCR_GICM (1 << 24)
1800 /* Interrupt Computation Mode */
1801 #define EPCR_ICM (1 << 25)
1802 /* Disable Embedded Hypervisor Debug */
1803 #define EPCR_DUVD (1 << 26)
1804 /* Instruction Storage Interrupt Directed to Guest State */
1805 #define EPCR_ISIGS (1 << 27)
1806 /* Data Storage Interrupt Directed to Guest State */
1807 #define EPCR_DSIGS (1 << 28)
1808 /* Instruction TLB Error Interrupt Directed to Guest State */
1809 #define EPCR_ITLBGS (1 << 29)
1810 /* Data TLB Error Interrupt Directed to Guest State */
1811 #define EPCR_DTLBGS (1 << 30)
1812 /* External Input Interrupt Directed to Guest State */
1813 #define EPCR_EXTGS (1 << 31)
1814
1815 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1816 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1817 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1818 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1819 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1820
1821 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1822 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1823 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1824 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1825 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1826
1827 /* HID0 bits */
1828 #define HID0_DEEPNAP (1 << 24)
1829 #define HID0_DOZE (1 << 23)
1830 #define HID0_NAP (1 << 22)
1831
1832 /*****************************************************************************/
1833 /* PowerPC Instructions types definitions */
1834 enum {
1835 PPC_NONE = 0x0000000000000000ULL,
1836 /* PowerPC base instructions set */
1837 PPC_INSNS_BASE = 0x0000000000000001ULL,
1838 /* integer operations instructions */
1839 #define PPC_INTEGER PPC_INSNS_BASE
1840 /* flow control instructions */
1841 #define PPC_FLOW PPC_INSNS_BASE
1842 /* virtual memory instructions */
1843 #define PPC_MEM PPC_INSNS_BASE
1844 /* ld/st with reservation instructions */
1845 #define PPC_RES PPC_INSNS_BASE
1846 /* spr/msr access instructions */
1847 #define PPC_MISC PPC_INSNS_BASE
1848 /* Deprecated instruction sets */
1849 /* Original POWER instruction set */
1850 PPC_POWER = 0x0000000000000002ULL,
1851 /* POWER2 instruction set extension */
1852 PPC_POWER2 = 0x0000000000000004ULL,
1853 /* Power RTC support */
1854 PPC_POWER_RTC = 0x0000000000000008ULL,
1855 /* Power-to-PowerPC bridge (601) */
1856 PPC_POWER_BR = 0x0000000000000010ULL,
1857 /* 64 bits PowerPC instruction set */
1858 PPC_64B = 0x0000000000000020ULL,
1859 /* New 64 bits extensions (PowerPC 2.0x) */
1860 PPC_64BX = 0x0000000000000040ULL,
1861 /* 64 bits hypervisor extensions */
1862 PPC_64H = 0x0000000000000080ULL,
1863 /* New wait instruction (PowerPC 2.0x) */
1864 PPC_WAIT = 0x0000000000000100ULL,
1865 /* Time base mftb instruction */
1866 PPC_MFTB = 0x0000000000000200ULL,
1867
1868 /* Fixed-point unit extensions */
1869 /* PowerPC 602 specific */
1870 PPC_602_SPEC = 0x0000000000000400ULL,
1871 /* isel instruction */
1872 PPC_ISEL = 0x0000000000000800ULL,
1873 /* popcntb instruction */
1874 PPC_POPCNTB = 0x0000000000001000ULL,
1875 /* string load / store */
1876 PPC_STRING = 0x0000000000002000ULL,
1877
1878 /* Floating-point unit extensions */
1879 /* Optional floating point instructions */
1880 PPC_FLOAT = 0x0000000000010000ULL,
1881 /* New floating-point extensions (PowerPC 2.0x) */
1882 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1883 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1884 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1885 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1886 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1887 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1888 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1889
1890 /* Vector/SIMD extensions */
1891 /* Altivec support */
1892 PPC_ALTIVEC = 0x0000000001000000ULL,
1893 /* PowerPC 2.03 SPE extension */
1894 PPC_SPE = 0x0000000002000000ULL,
1895 /* PowerPC 2.03 SPE single-precision floating-point extension */
1896 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1897 /* PowerPC 2.03 SPE double-precision floating-point extension */
1898 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1899
1900 /* Optional memory control instructions */
1901 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1902 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1903 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1904 /* sync instruction */
1905 PPC_MEM_SYNC = 0x0000000080000000ULL,
1906 /* eieio instruction */
1907 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1908
1909 /* Cache control instructions */
1910 PPC_CACHE = 0x0000000200000000ULL,
1911 /* icbi instruction */
1912 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1913 /* dcbz instruction */
1914 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1915 /* dcba instruction */
1916 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1917 /* Freescale cache locking instructions */
1918 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1919
1920 /* MMU related extensions */
1921 /* external control instructions */
1922 PPC_EXTERN = 0x0000010000000000ULL,
1923 /* segment register access instructions */
1924 PPC_SEGMENT = 0x0000020000000000ULL,
1925 /* PowerPC 6xx TLB management instructions */
1926 PPC_6xx_TLB = 0x0000040000000000ULL,
1927 /* PowerPC 74xx TLB management instructions */
1928 PPC_74xx_TLB = 0x0000080000000000ULL,
1929 /* PowerPC 40x TLB management instructions */
1930 PPC_40x_TLB = 0x0000100000000000ULL,
1931 /* segment register access instructions for PowerPC 64 "bridge" */
1932 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1933 /* SLB management */
1934 PPC_SLBI = 0x0000400000000000ULL,
1935
1936 /* Embedded PowerPC dedicated instructions */
1937 PPC_WRTEE = 0x0001000000000000ULL,
1938 /* PowerPC 40x exception model */
1939 PPC_40x_EXCP = 0x0002000000000000ULL,
1940 /* PowerPC 405 Mac instructions */
1941 PPC_405_MAC = 0x0004000000000000ULL,
1942 /* PowerPC 440 specific instructions */
1943 PPC_440_SPEC = 0x0008000000000000ULL,
1944 /* BookE (embedded) PowerPC specification */
1945 PPC_BOOKE = 0x0010000000000000ULL,
1946 /* mfapidi instruction */
1947 PPC_MFAPIDI = 0x0020000000000000ULL,
1948 /* tlbiva instruction */
1949 PPC_TLBIVA = 0x0040000000000000ULL,
1950 /* tlbivax instruction */
1951 PPC_TLBIVAX = 0x0080000000000000ULL,
1952 /* PowerPC 4xx dedicated instructions */
1953 PPC_4xx_COMMON = 0x0100000000000000ULL,
1954 /* PowerPC 40x ibct instructions */
1955 PPC_40x_ICBT = 0x0200000000000000ULL,
1956 /* rfmci is not implemented in all BookE PowerPC */
1957 PPC_RFMCI = 0x0400000000000000ULL,
1958 /* rfdi instruction */
1959 PPC_RFDI = 0x0800000000000000ULL,
1960 /* DCR accesses */
1961 PPC_DCR = 0x1000000000000000ULL,
1962 /* DCR extended accesse */
1963 PPC_DCRX = 0x2000000000000000ULL,
1964 /* user-mode DCR access, implemented in PowerPC 460 */
1965 PPC_DCRUX = 0x4000000000000000ULL,
1966 /* popcntw and popcntd instructions */
1967 PPC_POPCNTWD = 0x8000000000000000ULL,
1968
1969 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1970 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1971 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1972 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1973 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1974 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1975 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1976 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1977 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1978 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1979 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1980 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1981 | PPC_CACHE | PPC_CACHE_ICBI \
1982 | PPC_CACHE_DCBZ \
1983 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1984 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1985 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1986 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1987 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1988 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1989 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1990 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1991 | PPC_POPCNTWD)
1992
1993 /* extended type values */
1994
1995 /* BookE 2.06 PowerPC specification */
1996 PPC2_BOOKE206 = 0x0000000000000001ULL,
1997 /* VSX (extensions to Altivec / VMX) */
1998 PPC2_VSX = 0x0000000000000002ULL,
1999 /* Decimal Floating Point (DFP) */
2000 PPC2_DFP = 0x0000000000000004ULL,
2001 /* Embedded.Processor Control */
2002 PPC2_PRCNTL = 0x0000000000000008ULL,
2003 /* Byte-reversed, indexed, double-word load and store */
2004 PPC2_DBRX = 0x0000000000000010ULL,
2005 /* Book I 2.05 PowerPC specification */
2006 PPC2_ISA205 = 0x0000000000000020ULL,
2007 /* VSX additions in ISA 2.07 */
2008 PPC2_VSX207 = 0x0000000000000040ULL,
2009 /* ISA 2.06B bpermd */
2010 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2011 /* ISA 2.06B divide extended variants */
2012 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2013 /* ISA 2.06B larx/stcx. instructions */
2014 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2015 /* ISA 2.06B floating point integer conversion */
2016 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2017 /* ISA 2.06B floating point test instructions */
2018 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2019 /* ISA 2.07 bctar instruction */
2020 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2021 /* ISA 2.07 load/store quadword */
2022 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2023 /* ISA 2.07 Altivec */
2024 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2025 /* PowerISA 2.07 Book3s specification */
2026 PPC2_ISA207S = 0x0000000000008000ULL,
2027 /* Double precision floating point conversion for signed integer 64 */
2028 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2029 /* Transactional Memory (ISA 2.07, Book II) */
2030 PPC2_TM = 0x0000000000020000ULL,
2031
2032 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2033 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2034 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2035 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2036 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2037 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2038 PPC2_FP_CVT_S64 | PPC2_TM)
2039 };
2040
2041 /*****************************************************************************/
2042 /* Memory access type :
2043 * may be needed for precise access rights control and precise exceptions.
2044 */
2045 enum {
2046 /* 1 bit to define user level / supervisor access */
2047 ACCESS_USER = 0x00,
2048 ACCESS_SUPER = 0x01,
2049 /* Type of instruction that generated the access */
2050 ACCESS_CODE = 0x10, /* Code fetch access */
2051 ACCESS_INT = 0x20, /* Integer load/store access */
2052 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2053 ACCESS_RES = 0x40, /* load/store with reservation */
2054 ACCESS_EXT = 0x50, /* external access */
2055 ACCESS_CACHE = 0x60, /* Cache manipulation */
2056 };
2057
2058 /* Hardware interruption sources:
2059 * all those exception can be raised simulteaneously
2060 */
2061 /* Input pins definitions */
2062 enum {
2063 /* 6xx bus input pins */
2064 PPC6xx_INPUT_HRESET = 0,
2065 PPC6xx_INPUT_SRESET = 1,
2066 PPC6xx_INPUT_CKSTP_IN = 2,
2067 PPC6xx_INPUT_MCP = 3,
2068 PPC6xx_INPUT_SMI = 4,
2069 PPC6xx_INPUT_INT = 5,
2070 PPC6xx_INPUT_TBEN = 6,
2071 PPC6xx_INPUT_WAKEUP = 7,
2072 PPC6xx_INPUT_NB,
2073 };
2074
2075 enum {
2076 /* Embedded PowerPC input pins */
2077 PPCBookE_INPUT_HRESET = 0,
2078 PPCBookE_INPUT_SRESET = 1,
2079 PPCBookE_INPUT_CKSTP_IN = 2,
2080 PPCBookE_INPUT_MCP = 3,
2081 PPCBookE_INPUT_SMI = 4,
2082 PPCBookE_INPUT_INT = 5,
2083 PPCBookE_INPUT_CINT = 6,
2084 PPCBookE_INPUT_NB,
2085 };
2086
2087 enum {
2088 /* PowerPC E500 input pins */
2089 PPCE500_INPUT_RESET_CORE = 0,
2090 PPCE500_INPUT_MCK = 1,
2091 PPCE500_INPUT_CINT = 3,
2092 PPCE500_INPUT_INT = 4,
2093 PPCE500_INPUT_DEBUG = 6,
2094 PPCE500_INPUT_NB,
2095 };
2096
2097 enum {
2098 /* PowerPC 40x input pins */
2099 PPC40x_INPUT_RESET_CORE = 0,
2100 PPC40x_INPUT_RESET_CHIP = 1,
2101 PPC40x_INPUT_RESET_SYS = 2,
2102 PPC40x_INPUT_CINT = 3,
2103 PPC40x_INPUT_INT = 4,
2104 PPC40x_INPUT_HALT = 5,
2105 PPC40x_INPUT_DEBUG = 6,
2106 PPC40x_INPUT_NB,
2107 };
2108
2109 enum {
2110 /* RCPU input pins */
2111 PPCRCPU_INPUT_PORESET = 0,
2112 PPCRCPU_INPUT_HRESET = 1,
2113 PPCRCPU_INPUT_SRESET = 2,
2114 PPCRCPU_INPUT_IRQ0 = 3,
2115 PPCRCPU_INPUT_IRQ1 = 4,
2116 PPCRCPU_INPUT_IRQ2 = 5,
2117 PPCRCPU_INPUT_IRQ3 = 6,
2118 PPCRCPU_INPUT_IRQ4 = 7,
2119 PPCRCPU_INPUT_IRQ5 = 8,
2120 PPCRCPU_INPUT_IRQ6 = 9,
2121 PPCRCPU_INPUT_IRQ7 = 10,
2122 PPCRCPU_INPUT_NB,
2123 };
2124
2125 #if defined(TARGET_PPC64)
2126 enum {
2127 /* PowerPC 970 input pins */
2128 PPC970_INPUT_HRESET = 0,
2129 PPC970_INPUT_SRESET = 1,
2130 PPC970_INPUT_CKSTP = 2,
2131 PPC970_INPUT_TBEN = 3,
2132 PPC970_INPUT_MCP = 4,
2133 PPC970_INPUT_INT = 5,
2134 PPC970_INPUT_THINT = 6,
2135 PPC970_INPUT_NB,
2136 };
2137
2138 enum {
2139 /* POWER7 input pins */
2140 POWER7_INPUT_INT = 0,
2141 /* POWER7 probably has other inputs, but we don't care about them
2142 * for any existing machine. We can wire these up when we need
2143 * them */
2144 POWER7_INPUT_NB,
2145 };
2146 #endif
2147
2148 /* Hardware exceptions definitions */
2149 enum {
2150 /* External hardware exception sources */
2151 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2152 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2153 PPC_INTERRUPT_MCK, /* Machine check exception */
2154 PPC_INTERRUPT_EXT, /* External interrupt */
2155 PPC_INTERRUPT_SMI, /* System management interrupt */
2156 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2157 PPC_INTERRUPT_DEBUG, /* External debug exception */
2158 PPC_INTERRUPT_THERM, /* Thermal exception */
2159 /* Internal hardware exception sources */
2160 PPC_INTERRUPT_DECR, /* Decrementer exception */
2161 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2162 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2163 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2164 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2165 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2166 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2167 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2168 };
2169
2170 /* Processor Compatibility mask (PCR) */
2171 enum {
2172 PCR_COMPAT_2_05 = 1ull << (63-62),
2173 PCR_COMPAT_2_06 = 1ull << (63-61),
2174 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2175 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2176 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2177 };
2178
2179 /*****************************************************************************/
2180
2181 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2182 {
2183 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2184 }
2185
2186 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2187 {
2188 env->so = (xer >> XER_SO) & 1;
2189 env->ov = (xer >> XER_OV) & 1;
2190 env->ca = (xer >> XER_CA) & 1;
2191 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2192 }
2193
2194 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2195 target_ulong *cs_base, int *flags)
2196 {
2197 *pc = env->nip;
2198 *cs_base = 0;
2199 *flags = env->hflags;
2200 }
2201
2202 #if !defined(CONFIG_USER_ONLY)
2203 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2204 {
2205 uintptr_t tlbml = (uintptr_t)tlbm;
2206 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2207
2208 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2209 }
2210
2211 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2212 {
2213 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2214 int r = tlbncfg & TLBnCFG_N_ENTRY;
2215 return r;
2216 }
2217
2218 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2219 {
2220 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2221 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2222 return r;
2223 }
2224
2225 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2226 {
2227 int id = booke206_tlbm_id(env, tlbm);
2228 int end = 0;
2229 int i;
2230
2231 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2232 end += booke206_tlb_size(env, i);
2233 if (id < end) {
2234 return i;
2235 }
2236 }
2237
2238 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2239 return 0;
2240 }
2241
2242 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2243 {
2244 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2245 int tlbid = booke206_tlbm_id(env, tlb);
2246 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2247 }
2248
2249 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2250 target_ulong ea, int way)
2251 {
2252 int r;
2253 uint32_t ways = booke206_tlb_ways(env, tlbn);
2254 int ways_bits = ctz32(ways);
2255 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2256 int i;
2257
2258 way &= ways - 1;
2259 ea >>= MAS2_EPN_SHIFT;
2260 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2261 r = (ea << ways_bits) | way;
2262
2263 if (r >= booke206_tlb_size(env, tlbn)) {
2264 return NULL;
2265 }
2266
2267 /* bump up to tlbn index */
2268 for (i = 0; i < tlbn; i++) {
2269 r += booke206_tlb_size(env, i);
2270 }
2271
2272 return &env->tlb.tlbm[r];
2273 }
2274
2275 /* returns bitmap of supported page sizes for a given TLB */
2276 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2277 {
2278 bool mav2 = false;
2279 uint32_t ret = 0;
2280
2281 if (mav2) {
2282 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2283 } else {
2284 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2285 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2286 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2287 int i;
2288 for (i = min; i <= max; i++) {
2289 ret |= (1 << (i << 1));
2290 }
2291 }
2292
2293 return ret;
2294 }
2295
2296 #endif
2297
2298 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2299 {
2300 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2301 return msr & (1ULL << MSR_CM);
2302 }
2303
2304 return msr & (1ULL << MSR_SF);
2305 }
2306
2307 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2308
2309 #include "exec/exec-all.h"
2310
2311 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2312
2313 /**
2314 * ppc_get_vcpu_dt_id:
2315 * @cs: a PowerPCCPU struct.
2316 *
2317 * Returns a device-tree ID for a CPU.
2318 */
2319 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2320
2321 /**
2322 * ppc_get_vcpu_by_dt_id:
2323 * @cpu_dt_id: a device tree id
2324 *
2325 * Searches for a CPU by @cpu_dt_id.
2326 *
2327 * Returns: a PowerPCCPU struct
2328 */
2329 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2330
2331 #endif /* !defined (__CPU_PPC_H__) */
AR7 emulation for QEMU