hw/net/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h" /* FIXME: why does this use TARGET_PAGE_ALIGN? */
  29 #include "hw/hw.h"
  30 #include "hw/sysbus.h"
  31 #include "trace.h"
  32 #include "net/net.h"
  33 #include "qemu/log.h"
  34 #include "qemu/error-report.h"
  35
  36 #include <zlib.h>
  37
  38 enum {
  39     R_SETUP = 0,
  40     R_MDIO,
  41     R_STATE0,
  42     R_COUNT0,
  43     R_STATE1,
  44     R_COUNT1,
  45     R_TXCOUNT,
  46     R_MAX
  47 };
  48
  49 enum {
  50     SETUP_PHY_RST = (1<<0),
  51 };
  52
  53 enum {
  54     MDIO_DO  = (1<<0),
  55     MDIO_DI  = (1<<1),
  56     MDIO_OE  = (1<<2),
  57     MDIO_CLK = (1<<3),
  58 };
  59
  60 enum {
  61     STATE_EMPTY   = 0,
  62     STATE_LOADED  = 1,
  63     STATE_PENDING = 2,
  64 };
  65
  66 enum {
  67     MDIO_OP_WRITE = 1,
  68     MDIO_OP_READ  = 2,
  69 };
  70
  71 enum mdio_state {
  72     MDIO_STATE_IDLE,
  73     MDIO_STATE_READING,
  74     MDIO_STATE_WRITING,
  75 };
  76
  77 enum {
  78     R_PHY_ID1  = 2,
  79     R_PHY_ID2  = 3,
  80     R_PHY_MAX  = 32
  81 };
  82
  83 #define MINIMAC2_MTU 1530
  84 #define MINIMAC2_BUFFER_SIZE 2048
  85
  86 struct MilkymistMinimac2MdioState {
  87     int last_clk;
  88     int count;
  89     uint32_t data;
  90     uint16_t data_out;
  91     int state;
  92
  93     uint8_t phy_addr;
  94     uint8_t reg_addr;
  95 };
  96 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  97
  98 #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
  99 #define MILKYMIST_MINIMAC2(obj) \
 100     OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
 101
 102 struct MilkymistMinimac2State {
 103     SysBusDevice parent_obj;
 104
 105     NICState *nic;
 106     NICConf conf;
 107     char *phy_model;
 108     MemoryRegion buffers;
 109     MemoryRegion regs_region;
 110
 111     qemu_irq rx_irq;
 112     qemu_irq tx_irq;
 113
 114     uint32_t regs[R_MAX];
 115
 116     MilkymistMinimac2MdioState mdio;
 117
 118     uint16_t phy_regs[R_PHY_MAX];
 119
 120     uint8_t *rx0_buf;
 121     uint8_t *rx1_buf;
 122     uint8_t *tx_buf;
 123 };
 124 typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 125
 126 static const uint8_t preamble_sfd[] = {
 127         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 128 };
 129
 130 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 131         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 132 {
 133     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 134
 135     /* nop */
 136 }
 137
 138 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 139         uint8_t phy_addr, uint8_t reg_addr)
 140 {
 141     uint16_t r = s->phy_regs[reg_addr];
 142
 143     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 144
 145     return r;
 146 }
 147
 148 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 149 {
 150     MilkymistMinimac2MdioState *m = &s->mdio;
 151
 152     /* detect rising clk edge */
 153     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 154         /* shift data in */
 155         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 156                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 157         m->data = (m->data << 1) | bit;
 158
 159         /* check for sync */
 160         if (m->data == 0xffffffff) {
 161             m->count = 32;
 162         }
 163
 164         if (m->count == 16) {
 165             uint8_t start = (m->data >> 14) & 0x3;
 166             uint8_t op = (m->data >> 12) & 0x3;
 167             uint8_t ta = (m->data) & 0x3;
 168
 169             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 170                 m->state = MDIO_STATE_WRITING;
 171             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 172                 m->state = MDIO_STATE_READING;
 173             } else {
 174                 m->state = MDIO_STATE_IDLE;
 175             }
 176
 177             if (m->state != MDIO_STATE_IDLE) {
 178                 m->phy_addr = (m->data >> 7) & 0x1f;
 179                 m->reg_addr = (m->data >> 2) & 0x1f;
 180             }
 181
 182             if (m->state == MDIO_STATE_READING) {
 183                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 184                         m->reg_addr);
 185             }
 186         }
 187
 188         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 189             int bit = (m->data_out & 0x8000) ? 1 : 0;
 190             m->data_out <<= 1;
 191
 192             if (bit) {
 193                 s->regs[R_MDIO] |= MDIO_DI;
 194             } else {
 195                 s->regs[R_MDIO] &= ~MDIO_DI;
 196             }
 197         }
 198
 199         if (m->count == 0 && m->state) {
 200             if (m->state == MDIO_STATE_WRITING) {
 201                 uint16_t data = m->data & 0xffff;
 202                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 203             }
 204             m->state = MDIO_STATE_IDLE;
 205         }
 206         m->count--;
 207     }
 208
 209     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 210 }
 211
 212 static size_t assemble_frame(uint8_t *buf, size_t size,
 213         const uint8_t *payload, size_t payload_size)
 214 {
 215     uint32_t crc;
 216
 217     if (size < payload_size + 12) {
 218         qemu_log_mask(LOG_GUEST_ERROR, "milkymist_minimac2: frame too big "
 219                       "(%zd bytes)\n", payload_size);
 220         return 0;
 221     }
 222
 223     /* prepend preamble and sfd */
 224     memcpy(buf, preamble_sfd, 8);
 225
 226     /* now copy the payload */
 227     memcpy(buf + 8, payload, payload_size);
 228
 229     /* pad frame if needed */
 230     if (payload_size < 60) {
 231         memset(buf + payload_size + 8, 0, 60 - payload_size);
 232         payload_size = 60;
 233     }
 234
 235     /* append fcs */
 236     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 237     memcpy(buf + payload_size + 8, &crc, 4);
 238
 239     return payload_size + 12;
 240 }
 241
 242 static void minimac2_tx(MilkymistMinimac2State *s)
 243 {
 244     uint32_t txcount = s->regs[R_TXCOUNT];
 245     uint8_t *buf = s->tx_buf;
 246
 247     if (txcount < 64) {
 248         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 249                 txcount, 64);
 250         goto err;
 251     }
 252
 253     if (txcount > MINIMAC2_MTU) {
 254         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 255                 txcount, MINIMAC2_MTU);
 256         goto err;
 257     }
 258
 259     if (memcmp(buf, preamble_sfd, 8) != 0) {
 260         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 261                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 262                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 263         goto err;
 264     }
 265
 266     trace_milkymist_minimac2_tx_frame(txcount - 12);
 267
 268     /* send packet, skipping preamble and sfd */
 269     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 270
 271     s->regs[R_TXCOUNT] = 0;
 272
 273 err:
 274     trace_milkymist_minimac2_pulse_irq_tx();
 275     qemu_irq_pulse(s->tx_irq);
 276 }
 277
 278 static void update_rx_interrupt(MilkymistMinimac2State *s)
 279 {
 280     if (s->regs[R_STATE0] == STATE_PENDING
 281             || s->regs[R_STATE1] == STATE_PENDING) {
 282         trace_milkymist_minimac2_raise_irq_rx();
 283         qemu_irq_raise(s->rx_irq);
 284     } else {
 285         trace_milkymist_minimac2_lower_irq_rx();
 286         qemu_irq_lower(s->rx_irq);
 287     }
 288 }
 289
 290 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 291 {
 292     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 293
 294     uint32_t r_count;
 295     uint32_t r_state;
 296     uint8_t *rx_buf;
 297
 298     size_t frame_size;
 299
 300     trace_milkymist_minimac2_rx_frame(buf, size);
 301
 302     /* choose appropriate slot */
 303     if (s->regs[R_STATE0] == STATE_LOADED) {
 304         r_count = R_COUNT0;
 305         r_state = R_STATE0;
 306         rx_buf = s->rx0_buf;
 307     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 308         r_count = R_COUNT1;
 309         r_state = R_STATE1;
 310         rx_buf = s->rx1_buf;
 311     } else {
 312         return 0;
 313     }
 314
 315     /* assemble frame */
 316     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 317
 318     if (frame_size == 0) {
 319         return size;
 320     }
 321
 322     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 323
 324     /* update slot */
 325     s->regs[r_count] = frame_size;
 326     s->regs[r_state] = STATE_PENDING;
 327
 328     update_rx_interrupt(s);
 329
 330     return size;
 331 }
 332
 333 static uint64_t
 334 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 335 {
 336     MilkymistMinimac2State *s = opaque;
 337     uint32_t r = 0;
 338
 339     addr >>= 2;
 340     switch (addr) {
 341     case R_SETUP:
 342     case R_MDIO:
 343     case R_STATE0:
 344     case R_COUNT0:
 345     case R_STATE1:
 346     case R_COUNT1:
 347     case R_TXCOUNT:
 348         r = s->regs[addr];
 349         break;
 350
 351     default:
 352         qemu_log_mask(LOG_GUEST_ERROR,
 353                       "milkymist_minimac2_rd%d: 0x%" HWADDR_PRIx "\n",
 354                       size, addr << 2);
 355         break;
 356     }
 357
 358     trace_milkymist_minimac2_memory_read(addr << 2, r);
 359
 360     return r;
 361 }
 362
 363 static int minimac2_can_rx(MilkymistMinimac2State *s)
 364 {
 365     if (s->regs[R_STATE0] == STATE_LOADED) {
 366         return 1;
 367     }
 368     if (s->regs[R_STATE1] == STATE_LOADED) {
 369         return 1;
 370     }
 371
 372     return 0;
 373 }
 374
 375 static void
 376 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 377                unsigned size)
 378 {
 379     MilkymistMinimac2State *s = opaque;
 380
 381     trace_milkymist_minimac2_memory_write(addr, value);
 382
 383     addr >>= 2;
 384     switch (addr) {
 385     case R_MDIO:
 386     {
 387         /* MDIO_DI is read only */
 388         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 389         s->regs[R_MDIO] = value;
 390         if (mdio_di) {
 391             s->regs[R_MDIO] |= mdio_di;
 392         } else {
 393             s->regs[R_MDIO] &= ~mdio_di;
 394         }
 395
 396         minimac2_update_mdio(s);
 397     } break;
 398     case R_TXCOUNT:
 399         s->regs[addr] = value;
 400         if (value > 0) {
 401             minimac2_tx(s);
 402         }
 403         break;
 404     case R_STATE0:
 405     case R_STATE1:
 406         s->regs[addr] = value;
 407         update_rx_interrupt(s);
 408         if (minimac2_can_rx(s)) {
 409             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 410         }
 411         break;
 412     case R_SETUP:
 413     case R_COUNT0:
 414     case R_COUNT1:
 415         s->regs[addr] = value;
 416         break;
 417
 418     default:
 419         qemu_log_mask(LOG_GUEST_ERROR,
 420                       "milkymist_minimac2_wr%d: 0x%" HWADDR_PRIx
 421                       " = 0x%" PRIx64 "\n",
 422                       size, addr << 2, value);
 423         break;
 424     }
 425 }
 426
 427 static const MemoryRegionOps minimac2_ops = {
 428     .read = minimac2_read,
 429     .write = minimac2_write,
 430     .valid = {
 431         .min_access_size = 4,
 432         .max_access_size = 4,
 433     },
 434     .endianness = DEVICE_NATIVE_ENDIAN,
 435 };
 436
 437 static void milkymist_minimac2_reset(DeviceState *d)
 438 {
 439     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 440     int i;
 441
 442     for (i = 0; i < R_MAX; i++) {
 443         s->regs[i] = 0;
 444     }
 445     for (i = 0; i < R_PHY_MAX; i++) {
 446         s->phy_regs[i] = 0;
 447     }
 448
 449     /* defaults */
 450     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 451     s->phy_regs[R_PHY_ID2] = 0x161a;
 452 }
 453
 454 static NetClientInfo net_milkymist_minimac2_info = {
 455     .type = NET_CLIENT_DRIVER_NIC,
 456     .size = sizeof(NICState),
 457     .receive = minimac2_rx,
 458 };
 459
 460 static void milkymist_minimac2_realize(DeviceState *dev, Error **errp)
 461 {
 462     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 463     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 464     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 465
 466     sysbus_init_irq(sbd, &s->rx_irq);
 467     sysbus_init_irq(sbd, &s->tx_irq);
 468
 469     memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 470                           "milkymist-minimac2", R_MAX * 4);
 471     sysbus_init_mmio(sbd, &s->regs_region);
 472
 473     /* register buffers memory */
 474     memory_region_init_ram_nomigrate(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 475                            buffers_size, &error_fatal);
 476     vmstate_register_ram_global(&s->buffers);
 477     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 478     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 479     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 480
 481     sysbus_init_mmio(sbd, &s->buffers);
 482
 483     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 484     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 485                           object_get_typename(OBJECT(dev)), dev->id, s);
 486     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 487 }
 488
 489 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 490     .name = "milkymist-minimac2-mdio",
 491     .version_id = 1,
 492     .minimum_version_id = 1,
 493     .fields = (VMStateField[]) {
 494         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 495         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 496         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 497         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 498         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 499         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 500         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 501         VMSTATE_END_OF_LIST()
 502     }
 503 };
 504
 505 static const VMStateDescription vmstate_milkymist_minimac2 = {
 506     .name = "milkymist-minimac2",
 507     .version_id = 1,
 508     .minimum_version_id = 1,
 509     .fields = (VMStateField[]) {
 510         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 511         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 512         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 513                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 514         VMSTATE_END_OF_LIST()
 515     }
 516 };
 517
 518 static Property milkymist_minimac2_properties[] = {
 519     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 520     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 521     DEFINE_PROP_END_OF_LIST(),
 522 };
 523
 524 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 525 {
 526     DeviceClass *dc = DEVICE_CLASS(klass);
 527
 528     dc->realize = milkymist_minimac2_realize;
 529     dc->reset = milkymist_minimac2_reset;
 530     dc->vmsd = &vmstate_milkymist_minimac2;
 531     dc->props = milkymist_minimac2_properties;
 532 }
 533
 534 static const TypeInfo milkymist_minimac2_info = {
 535     .name          = TYPE_MILKYMIST_MINIMAC2,
 536     .parent        = TYPE_SYS_BUS_DEVICE,
 537     .instance_size = sizeof(MilkymistMinimac2State),
 538     .class_init    = milkymist_minimac2_class_init,
 539 };
 540
 541 static void milkymist_minimac2_register_types(void)
 542 {
 543     type_register_static(&milkymist_minimac2_info);
 544 }
 545
 546 type_init(milkymist_minimac2_register_types)