2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/timer.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
35 #define DPRINTF(...) do {} while (0)
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
138 #define ERDP_EHB (1<<3)
141 typedef struct XHCITRB
{
160 PLS_COMPILANCE_MODE
= 10,
165 typedef enum TRBType
{
178 CR_CONFIGURE_ENDPOINT
,
186 CR_SET_LATENCY_TOLERANCE
,
187 CR_GET_PORT_BANDWIDTH
,
192 ER_PORT_STATUS_CHANGE
,
193 ER_BANDWIDTH_REQUEST
,
196 ER_DEVICE_NOTIFICATION
,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
204 #define CR_LINK TR_LINK
206 typedef enum TRBCCode
{
209 CC_DATA_BUFFER_ERROR
,
211 CC_USB_TRANSACTION_ERROR
,
217 CC_INVALID_STREAM_TYPE_ERROR
,
218 CC_SLOT_NOT_ENABLED_ERROR
,
219 CC_EP_NOT_ENABLED_ERROR
,
225 CC_BANDWIDTH_OVERRUN
,
226 CC_CONTEXT_STATE_ERROR
,
227 CC_NO_PING_RESPONSE_ERROR
,
228 CC_EVENT_RING_FULL_ERROR
,
229 CC_INCOMPATIBLE_DEVICE_ERROR
,
230 CC_MISSED_SERVICE_ERROR
,
231 CC_COMMAND_RING_STOPPED
,
234 CC_STOPPED_LENGTH_INVALID
,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
236 CC_ISOCH_BUFFER_OVERRUN
= 31,
239 CC_INVALID_STREAM_ID_ERROR
,
240 CC_SECONDARY_BANDWIDTH_ERROR
,
241 CC_SPLIT_TRANSACTION_ERROR
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
249 #define TRB_EV_ED (1<<2)
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
266 #define TRB_TR_DIR (1<<16)
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
276 #define TRB_LK_TC (1<<1)
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
303 typedef struct XHCIState XHCIState
;
304 typedef struct XHCIStreamContext XHCIStreamContext
;
305 typedef struct XHCIEPContext XHCIEPContext
;
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
317 typedef enum EPType
{
328 typedef struct XHCIRing
{
333 typedef struct XHCIPort
{
343 typedef struct XHCITransfer
{
351 unsigned int iso_pkts
;
354 unsigned int streamid
;
359 unsigned int trb_count
;
360 unsigned int trb_alloced
;
366 unsigned int pktsize
;
367 unsigned int cur_pkt
;
369 uint64_t mfindex_kick
;
372 struct XHCIStreamContext
{
378 struct XHCIEPContext
{
384 unsigned int next_xfer
;
385 unsigned int comp_xfer
;
386 XHCITransfer transfers
[TD_QUEUE
];
390 unsigned int max_psize
;
394 unsigned int max_pstreams
;
396 unsigned int nr_pstreams
;
397 XHCIStreamContext
*pstreams
;
399 /* iso xfer scheduling */
400 unsigned int interval
;
401 int64_t mfindex_last
;
402 QEMUTimer
*kick_timer
;
405 typedef struct XHCISlot
{
410 XHCIEPContext
* eps
[31];
413 typedef struct XHCIEvent
{
423 typedef struct XHCIInterrupter
{
428 uint32_t erstba_high
;
432 bool msix_used
, er_pcs
, er_full
;
436 unsigned int er_ep_idx
;
438 XHCIEvent ev_buffer
[EV_QUEUE
];
439 unsigned int ev_buffer_put
;
440 unsigned int ev_buffer_get
;
446 PCIDevice parent_obj
;
451 MemoryRegion mem_cap
;
452 MemoryRegion mem_oper
;
453 MemoryRegion mem_runtime
;
454 MemoryRegion mem_doorbell
;
462 uint32_t max_pstreams_mask
;
464 /* Operational Registers */
471 uint32_t dcbaap_high
;
474 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
475 XHCIPort ports
[MAXPORTS
];
476 XHCISlot slots
[MAXSLOTS
];
479 /* Runtime Registers */
480 int64_t mfindex_start
;
481 QEMUTimer
*mfwrap_timer
;
482 XHCIInterrupter intr
[MAXINTRS
];
487 #define TYPE_XHCI "nec-usb-xhci"
490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
492 typedef struct XHCIEvRingSeg
{
500 XHCI_FLAG_USE_MSI
= 1,
503 XHCI_FLAG_FORCE_PCIE_ENDCAP
,
504 XHCI_FLAG_ENABLE_STREAMS
,
507 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
508 unsigned int epid
, unsigned int streamid
);
509 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
511 static void xhci_xfer_report(XHCITransfer
*xfer
);
512 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
513 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
514 static USBEndpoint
*xhci_epid_to_usbep(XHCIState
*xhci
,
515 unsigned int slotid
, unsigned int epid
);
517 static const char *TRBType_names
[] = {
518 [TRB_RESERVED
] = "TRB_RESERVED",
519 [TR_NORMAL
] = "TR_NORMAL",
520 [TR_SETUP
] = "TR_SETUP",
521 [TR_DATA
] = "TR_DATA",
522 [TR_STATUS
] = "TR_STATUS",
523 [TR_ISOCH
] = "TR_ISOCH",
524 [TR_LINK
] = "TR_LINK",
525 [TR_EVDATA
] = "TR_EVDATA",
526 [TR_NOOP
] = "TR_NOOP",
527 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
528 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
529 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
530 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
531 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
532 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
533 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
534 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
535 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
536 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
537 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
538 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
539 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
540 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
541 [CR_NOOP
] = "CR_NOOP",
542 [ER_TRANSFER
] = "ER_TRANSFER",
543 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
544 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
545 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
546 [ER_DOORBELL
] = "ER_DOORBELL",
547 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
548 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
549 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
550 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
551 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
552 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
555 static const char *TRBCCode_names
[] = {
556 [CC_INVALID
] = "CC_INVALID",
557 [CC_SUCCESS
] = "CC_SUCCESS",
558 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
559 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
560 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
561 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
562 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
563 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
564 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
565 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
566 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
567 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
568 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
569 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
570 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
571 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
572 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
573 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
574 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
575 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
576 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
577 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
578 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
579 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
580 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
581 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
582 [CC_STOPPED
] = "CC_STOPPED",
583 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
584 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
585 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
586 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
587 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
588 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
589 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
590 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
591 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
594 static const char *ep_state_names
[] = {
595 [EP_DISABLED
] = "disabled",
596 [EP_RUNNING
] = "running",
597 [EP_HALTED
] = "halted",
598 [EP_STOPPED
] = "stopped",
599 [EP_ERROR
] = "error",
602 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
604 if (index
>= llen
|| list
[index
] == NULL
) {
610 static const char *trb_name(XHCITRB
*trb
)
612 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
613 ARRAY_SIZE(TRBType_names
));
616 static const char *event_name(XHCIEvent
*event
)
618 return lookup_name(event
->ccode
, TRBCCode_names
,
619 ARRAY_SIZE(TRBCCode_names
));
622 static const char *ep_state_name(uint32_t state
)
624 return lookup_name(state
, ep_state_names
,
625 ARRAY_SIZE(ep_state_names
));
628 static bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
630 return xhci
->flags
& (1 << bit
);
633 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
635 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
636 return (now
- xhci
->mfindex_start
) / 125000;
639 static void xhci_mfwrap_update(XHCIState
*xhci
)
641 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
642 uint32_t mfindex
, left
;
645 if ((xhci
->usbcmd
& bits
) == bits
) {
646 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
647 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
648 left
= 0x4000 - mfindex
;
649 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
651 timer_del(xhci
->mfwrap_timer
);
655 static void xhci_mfwrap_timer(void *opaque
)
657 XHCIState
*xhci
= opaque
;
658 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
660 xhci_event(xhci
, &wrap
, 0);
661 xhci_mfwrap_update(xhci
);
664 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
666 if (sizeof(dma_addr_t
) == 4) {
669 return low
| (((dma_addr_t
)high
<< 16) << 16);
673 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
675 if (sizeof(dma_addr_t
) == 4) {
676 return addr
& 0xffffffff;
682 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
683 uint32_t *buf
, size_t len
)
687 assert((len
% sizeof(uint32_t)) == 0);
689 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
691 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
692 buf
[i
] = le32_to_cpu(buf
[i
]);
696 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
697 uint32_t *buf
, size_t len
)
700 uint32_t tmp
[len
/ sizeof(uint32_t)];
702 assert((len
% sizeof(uint32_t)) == 0);
704 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
705 tmp
[i
] = cpu_to_le32(buf
[i
]);
707 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
710 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
717 switch (uport
->dev
->speed
) {
721 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
722 index
= uport
->index
+ xhci
->numports_3
;
724 index
= uport
->index
;
727 case USB_SPEED_SUPER
:
728 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
729 index
= uport
->index
;
731 index
= uport
->index
+ xhci
->numports_2
;
737 return &xhci
->ports
[index
];
740 static void xhci_intx_update(XHCIState
*xhci
)
742 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
745 if (msix_enabled(pci_dev
) ||
746 msi_enabled(pci_dev
)) {
750 if (xhci
->intr
[0].iman
& IMAN_IP
&&
751 xhci
->intr
[0].iman
& IMAN_IE
&&
752 xhci
->usbcmd
& USBCMD_INTE
) {
756 trace_usb_xhci_irq_intx(level
);
757 pci_set_irq(pci_dev
, level
);
760 static void xhci_msix_update(XHCIState
*xhci
, int v
)
762 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
765 if (!msix_enabled(pci_dev
)) {
769 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
770 if (enabled
== xhci
->intr
[v
].msix_used
) {
775 trace_usb_xhci_irq_msix_use(v
);
776 msix_vector_use(pci_dev
, v
);
777 xhci
->intr
[v
].msix_used
= true;
779 trace_usb_xhci_irq_msix_unuse(v
);
780 msix_vector_unuse(pci_dev
, v
);
781 xhci
->intr
[v
].msix_used
= false;
785 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
787 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
789 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
790 xhci
->intr
[v
].iman
|= IMAN_IP
;
791 xhci
->usbsts
|= USBSTS_EINT
;
793 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
797 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
801 if (msix_enabled(pci_dev
)) {
802 trace_usb_xhci_irq_msix(v
);
803 msix_notify(pci_dev
, v
);
807 if (msi_enabled(pci_dev
)) {
808 trace_usb_xhci_irq_msi(v
);
809 msi_notify(pci_dev
, v
);
814 trace_usb_xhci_irq_intx(1);
815 pci_irq_assert(pci_dev
);
819 static inline int xhci_running(XHCIState
*xhci
)
821 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->intr
[0].er_full
;
824 static void xhci_die(XHCIState
*xhci
)
826 xhci
->usbsts
|= USBSTS_HCE
;
827 DPRINTF("xhci: asserted controller error\n");
830 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
832 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
833 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
837 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
838 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
839 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
840 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
842 ev_trb
.control
|= TRB_C
;
844 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
846 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
847 event_name(event
), ev_trb
.parameter
,
848 ev_trb
.status
, ev_trb
.control
);
850 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
851 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
854 if (intr
->er_ep_idx
>= intr
->er_size
) {
856 intr
->er_pcs
= !intr
->er_pcs
;
860 static void xhci_events_update(XHCIState
*xhci
, int v
)
862 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
867 if (xhci
->usbsts
& USBSTS_HCH
) {
871 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
872 if (erdp
< intr
->er_start
||
873 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
874 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
875 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
876 v
, intr
->er_start
, intr
->er_size
);
880 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
881 assert(dp_idx
< intr
->er_size
);
883 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
884 * deadlocks when the ER is full. Hack it by holding off events until
885 * the driver decides to free at least half of the ring */
887 int er_free
= dp_idx
- intr
->er_ep_idx
;
889 er_free
+= intr
->er_size
;
891 if (er_free
< (intr
->er_size
/2)) {
892 DPRINTF("xhci_events_update(): event ring still "
893 "more than half full (hack)\n");
898 while (intr
->ev_buffer_put
!= intr
->ev_buffer_get
) {
899 assert(intr
->er_full
);
900 if (((intr
->er_ep_idx
+1) % intr
->er_size
) == dp_idx
) {
901 DPRINTF("xhci_events_update(): event ring full again\n");
903 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
904 xhci_write_event(xhci
, &full
, v
);
909 XHCIEvent
*event
= &intr
->ev_buffer
[intr
->ev_buffer_get
];
910 xhci_write_event(xhci
, event
, v
);
911 intr
->ev_buffer_get
++;
913 if (intr
->ev_buffer_get
== EV_QUEUE
) {
914 intr
->ev_buffer_get
= 0;
919 xhci_intr_raise(xhci
, v
);
922 if (intr
->er_full
&& intr
->ev_buffer_put
== intr
->ev_buffer_get
) {
923 DPRINTF("xhci_events_update(): event ring no longer full\n");
928 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
930 XHCIInterrupter
*intr
;
934 if (v
>= xhci
->numintrs
) {
935 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
938 intr
= &xhci
->intr
[v
];
941 DPRINTF("xhci_event(): ER full, queueing\n");
942 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
943 DPRINTF("xhci: event queue full, dropping event!\n");
946 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
947 if (intr
->ev_buffer_put
== EV_QUEUE
) {
948 intr
->ev_buffer_put
= 0;
953 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
954 if (erdp
< intr
->er_start
||
955 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
956 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
957 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
958 v
, intr
->er_start
, intr
->er_size
);
963 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
964 assert(dp_idx
< intr
->er_size
);
966 if ((intr
->er_ep_idx
+1) % intr
->er_size
== dp_idx
) {
967 DPRINTF("xhci_event(): ER full, queueing\n");
969 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
970 xhci_write_event(xhci
, &full
);
973 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
974 DPRINTF("xhci: event queue full, dropping event!\n");
977 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
978 if (intr
->ev_buffer_put
== EV_QUEUE
) {
979 intr
->ev_buffer_put
= 0;
982 xhci_write_event(xhci
, event
, v
);
985 xhci_intr_raise(xhci
, v
);
988 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
991 ring
->dequeue
= base
;
995 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
998 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
1002 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
1003 trb
->addr
= ring
->dequeue
;
1004 trb
->ccs
= ring
->ccs
;
1005 le64_to_cpus(&trb
->parameter
);
1006 le32_to_cpus(&trb
->status
);
1007 le32_to_cpus(&trb
->control
);
1009 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
1010 trb
->parameter
, trb
->status
, trb
->control
);
1012 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
1016 type
= TRB_TYPE(*trb
);
1018 if (type
!= TR_LINK
) {
1020 *addr
= ring
->dequeue
;
1022 ring
->dequeue
+= TRB_SIZE
;
1025 ring
->dequeue
= xhci_mask64(trb
->parameter
);
1026 if (trb
->control
& TRB_LK_TC
) {
1027 ring
->ccs
= !ring
->ccs
;
1033 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
1035 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
1038 dma_addr_t dequeue
= ring
->dequeue
;
1039 bool ccs
= ring
->ccs
;
1040 /* hack to bundle together the two/three TDs that make a setup transfer */
1041 bool control_td_set
= 0;
1045 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
1046 le64_to_cpus(&trb
.parameter
);
1047 le32_to_cpus(&trb
.status
);
1048 le32_to_cpus(&trb
.control
);
1050 if ((trb
.control
& TRB_C
) != ccs
) {
1054 type
= TRB_TYPE(trb
);
1056 if (type
== TR_LINK
) {
1057 dequeue
= xhci_mask64(trb
.parameter
);
1058 if (trb
.control
& TRB_LK_TC
) {
1065 dequeue
+= TRB_SIZE
;
1067 if (type
== TR_SETUP
) {
1069 } else if (type
== TR_STATUS
) {
1073 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
1079 static void xhci_er_reset(XHCIState
*xhci
, int v
)
1081 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
1084 if (intr
->erstsz
== 0) {
1090 /* cache the (sole) event ring segment location */
1091 if (intr
->erstsz
!= 1) {
1092 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1096 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1097 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
1098 le32_to_cpus(&seg
.addr_low
);
1099 le32_to_cpus(&seg
.addr_high
);
1100 le32_to_cpus(&seg
.size
);
1101 if (seg
.size
< 16 || seg
.size
> 4096) {
1102 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
1106 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1107 intr
->er_size
= seg
.size
;
1109 intr
->er_ep_idx
= 0;
1113 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1114 v
, intr
->er_start
, intr
->er_size
);
1117 static void xhci_run(XHCIState
*xhci
)
1119 trace_usb_xhci_run();
1120 xhci
->usbsts
&= ~USBSTS_HCH
;
1121 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1124 static void xhci_stop(XHCIState
*xhci
)
1126 trace_usb_xhci_stop();
1127 xhci
->usbsts
|= USBSTS_HCH
;
1128 xhci
->crcr_low
&= ~CRCR_CRR
;
1131 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
1134 XHCIStreamContext
*stctx
;
1137 stctx
= g_new0(XHCIStreamContext
, count
);
1138 for (i
= 0; i
< count
; i
++) {
1139 stctx
[i
].pctx
= base
+ i
* 16;
1145 static void xhci_reset_streams(XHCIEPContext
*epctx
)
1149 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
1150 epctx
->pstreams
[i
].sct
= -1;
1154 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
1156 assert(epctx
->pstreams
== NULL
);
1157 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
1158 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
1161 static void xhci_free_streams(XHCIEPContext
*epctx
)
1163 assert(epctx
->pstreams
!= NULL
);
1165 g_free(epctx
->pstreams
);
1166 epctx
->pstreams
= NULL
;
1167 epctx
->nr_pstreams
= 0;
1170 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
1171 unsigned int slotid
,
1173 XHCIEPContext
**epctxs
,
1177 XHCIEPContext
*epctx
;
1181 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1183 slot
= &xhci
->slots
[slotid
- 1];
1185 for (i
= 2, j
= 0; i
<= 31; i
++) {
1186 if (!(epmask
& (1u << i
))) {
1190 epctx
= slot
->eps
[i
- 1];
1191 ep
= xhci_epid_to_usbep(xhci
, slotid
, i
);
1192 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
1204 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
1207 USBEndpoint
*eps
[30];
1210 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
1212 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
1216 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
1219 XHCIEPContext
*epctxs
[30];
1220 USBEndpoint
*eps
[30];
1221 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
1223 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
1229 req_nr_streams
= epctxs
[0]->nr_pstreams
;
1230 dev_max_streams
= eps
[0]->max_streams
;
1232 for (i
= 1; i
< nr_eps
; i
++) {
1234 * HdG: I don't expect these to ever trigger, but if they do we need
1235 * to come up with another solution, ie group identical endpoints
1236 * together and make an usb_device_alloc_streams call per group.
1238 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
1239 FIXME("guest streams config not identical for all eps");
1240 return CC_RESOURCE_ERROR
;
1242 if (eps
[i
]->max_streams
!= dev_max_streams
) {
1243 FIXME("device streams config not identical for all eps");
1244 return CC_RESOURCE_ERROR
;
1249 * max-streams in both the device descriptor and in the controller is a
1250 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1251 * streams the guest will ask for 5 rounded up to the next power of 2 which
1252 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1254 * For redirected devices however this is an issue, as there we must ask
1255 * the real xhci controller to alloc streams, and the host driver for the
1256 * real xhci controller will likely disallow allocating more streams then
1257 * the device can handle.
1259 * So we limit the requested nr_streams to the maximum number the device
1262 if (req_nr_streams
> dev_max_streams
) {
1263 req_nr_streams
= dev_max_streams
;
1266 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
1268 DPRINTF("xhci: alloc streams failed\n");
1269 return CC_RESOURCE_ERROR
;
1275 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1276 unsigned int streamid
,
1279 XHCIStreamContext
*sctx
;
1281 uint32_t ctx
[2], sct
;
1283 assert(streamid
!= 0);
1285 if (streamid
>= epctx
->nr_pstreams
) {
1286 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1289 sctx
= epctx
->pstreams
+ streamid
;
1291 FIXME("secondary streams not implemented yet");
1294 if (sctx
->sct
== -1) {
1295 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1296 sct
= (ctx
[0] >> 1) & 0x07;
1297 if (epctx
->lsa
&& sct
!= 1) {
1298 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1302 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1303 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1308 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1309 XHCIStreamContext
*sctx
, uint32_t state
)
1311 XHCIRing
*ring
= NULL
;
1315 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1316 ctx
[0] &= ~EP_STATE_MASK
;
1319 /* update ring dequeue ptr */
1320 if (epctx
->nr_pstreams
) {
1323 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1325 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1326 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1327 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1330 ring
= &epctx
->ring
;
1333 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1334 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1336 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1337 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1340 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1341 if (epctx
->state
!= state
) {
1342 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1343 ep_state_name(epctx
->state
),
1344 ep_state_name(state
));
1346 epctx
->state
= state
;
1349 static void xhci_ep_kick_timer(void *opaque
)
1351 XHCIEPContext
*epctx
= opaque
;
1352 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
, 0);
1355 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1356 unsigned int slotid
,
1359 XHCIEPContext
*epctx
;
1362 epctx
= g_new0(XHCIEPContext
, 1);
1364 epctx
->slotid
= slotid
;
1367 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1368 epctx
->transfers
[i
].xhci
= xhci
;
1369 epctx
->transfers
[i
].slotid
= slotid
;
1370 epctx
->transfers
[i
].epid
= epid
;
1371 usb_packet_init(&epctx
->transfers
[i
].packet
);
1373 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1378 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1379 dma_addr_t pctx
, uint32_t *ctx
)
1383 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1385 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1387 epctx
->max_psize
= ctx
[1]>>16;
1388 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1389 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1390 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1391 if (epctx
->max_pstreams
) {
1392 xhci_alloc_streams(epctx
, dequeue
);
1394 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1395 epctx
->ring
.ccs
= ctx
[2] & 1;
1398 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1401 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1402 unsigned int epid
, dma_addr_t pctx
,
1406 XHCIEPContext
*epctx
;
1408 trace_usb_xhci_ep_enable(slotid
, epid
);
1409 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1410 assert(epid
>= 1 && epid
<= 31);
1412 slot
= &xhci
->slots
[slotid
-1];
1413 if (slot
->eps
[epid
-1]) {
1414 xhci_disable_ep(xhci
, slotid
, epid
);
1417 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1418 slot
->eps
[epid
-1] = epctx
;
1419 xhci_init_epctx(epctx
, pctx
, ctx
);
1421 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1422 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1424 epctx
->mfindex_last
= 0;
1426 epctx
->state
= EP_RUNNING
;
1427 ctx
[0] &= ~EP_STATE_MASK
;
1428 ctx
[0] |= EP_RUNNING
;
1433 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1437 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1439 xhci_xfer_report(t
);
1442 if (t
->running_async
) {
1443 usb_cancel_packet(&t
->packet
);
1444 t
->running_async
= 0;
1447 if (t
->running_retry
) {
1448 XHCIEPContext
*epctx
= t
->xhci
->slots
[t
->slotid
-1].eps
[t
->epid
-1];
1450 epctx
->retry
= NULL
;
1451 timer_del(epctx
->kick_timer
);
1453 t
->running_retry
= 0;
1461 t
->trb_count
= t
->trb_alloced
= 0;
1466 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1467 unsigned int epid
, TRBCCode report
)
1470 XHCIEPContext
*epctx
;
1471 int i
, xferi
, killed
= 0;
1472 USBEndpoint
*ep
= NULL
;
1473 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1474 assert(epid
>= 1 && epid
<= 31);
1476 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1478 slot
= &xhci
->slots
[slotid
-1];
1480 if (!slot
->eps
[epid
-1]) {
1484 epctx
= slot
->eps
[epid
-1];
1486 xferi
= epctx
->next_xfer
;
1487 for (i
= 0; i
< TD_QUEUE
; i
++) {
1488 killed
+= xhci_ep_nuke_one_xfer(&epctx
->transfers
[xferi
], report
);
1490 report
= 0; /* Only report once */
1492 epctx
->transfers
[xferi
].packet
.ep
= NULL
;
1493 xferi
= (xferi
+ 1) % TD_QUEUE
;
1496 ep
= xhci_epid_to_usbep(xhci
, slotid
, epid
);
1498 usb_device_ep_stopped(ep
->dev
, ep
);
1503 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1507 XHCIEPContext
*epctx
;
1510 trace_usb_xhci_ep_disable(slotid
, epid
);
1511 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1512 assert(epid
>= 1 && epid
<= 31);
1514 slot
= &xhci
->slots
[slotid
-1];
1516 if (!slot
->eps
[epid
-1]) {
1517 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1521 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1523 epctx
= slot
->eps
[epid
-1];
1525 if (epctx
->nr_pstreams
) {
1526 xhci_free_streams(epctx
);
1529 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1530 usb_packet_cleanup(&epctx
->transfers
[i
].packet
);
1533 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1535 timer_free(epctx
->kick_timer
);
1537 slot
->eps
[epid
-1] = NULL
;
1542 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1546 XHCIEPContext
*epctx
;
1548 trace_usb_xhci_ep_stop(slotid
, epid
);
1549 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1551 if (epid
< 1 || epid
> 31) {
1552 DPRINTF("xhci: bad ep %d\n", epid
);
1553 return CC_TRB_ERROR
;
1556 slot
= &xhci
->slots
[slotid
-1];
1558 if (!slot
->eps
[epid
-1]) {
1559 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1560 return CC_EP_NOT_ENABLED_ERROR
;
1563 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1564 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1565 "data might be lost\n");
1568 epctx
= slot
->eps
[epid
-1];
1570 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1572 if (epctx
->nr_pstreams
) {
1573 xhci_reset_streams(epctx
);
1579 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1583 XHCIEPContext
*epctx
;
1585 trace_usb_xhci_ep_reset(slotid
, epid
);
1586 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1588 if (epid
< 1 || epid
> 31) {
1589 DPRINTF("xhci: bad ep %d\n", epid
);
1590 return CC_TRB_ERROR
;
1593 slot
= &xhci
->slots
[slotid
-1];
1595 if (!slot
->eps
[epid
-1]) {
1596 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1597 return CC_EP_NOT_ENABLED_ERROR
;
1600 epctx
= slot
->eps
[epid
-1];
1602 if (epctx
->state
!= EP_HALTED
) {
1603 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1604 epid
, epctx
->state
);
1605 return CC_CONTEXT_STATE_ERROR
;
1608 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1609 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1610 "data might be lost\n");
1613 if (!xhci
->slots
[slotid
-1].uport
||
1614 !xhci
->slots
[slotid
-1].uport
->dev
||
1615 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1616 return CC_USB_TRANSACTION_ERROR
;
1619 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1621 if (epctx
->nr_pstreams
) {
1622 xhci_reset_streams(epctx
);
1628 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1629 unsigned int epid
, unsigned int streamid
,
1633 XHCIEPContext
*epctx
;
1634 XHCIStreamContext
*sctx
;
1637 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1639 if (epid
< 1 || epid
> 31) {
1640 DPRINTF("xhci: bad ep %d\n", epid
);
1641 return CC_TRB_ERROR
;
1644 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1645 dequeue
= xhci_mask64(pdequeue
);
1647 slot
= &xhci
->slots
[slotid
-1];
1649 if (!slot
->eps
[epid
-1]) {
1650 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1651 return CC_EP_NOT_ENABLED_ERROR
;
1654 epctx
= slot
->eps
[epid
-1];
1656 if (epctx
->state
!= EP_STOPPED
) {
1657 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1658 return CC_CONTEXT_STATE_ERROR
;
1661 if (epctx
->nr_pstreams
) {
1663 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1667 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1668 sctx
->ring
.ccs
= dequeue
& 1;
1671 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1672 epctx
->ring
.ccs
= dequeue
& 1;
1675 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1680 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1682 XHCIState
*xhci
= xfer
->xhci
;
1685 xfer
->int_req
= false;
1686 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1687 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1688 XHCITRB
*trb
= &xfer
->trbs
[i
];
1690 unsigned int chunk
= 0;
1692 if (trb
->control
& TRB_TR_IOC
) {
1693 xfer
->int_req
= true;
1696 switch (TRB_TYPE(*trb
)) {
1698 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1699 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1705 addr
= xhci_mask64(trb
->parameter
);
1706 chunk
= trb
->status
& 0x1ffff;
1707 if (trb
->control
& TRB_TR_IDT
) {
1708 if (chunk
> 8 || in_xfer
) {
1709 DPRINTF("xhci: invalid immediate data TRB\n");
1712 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1714 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1723 qemu_sglist_destroy(&xfer
->sgl
);
1728 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1730 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1731 qemu_sglist_destroy(&xfer
->sgl
);
1734 static void xhci_xfer_report(XHCITransfer
*xfer
)
1740 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1741 XHCIState
*xhci
= xfer
->xhci
;
1744 left
= xfer
->packet
.actual_length
;
1746 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1747 XHCITRB
*trb
= &xfer
->trbs
[i
];
1748 unsigned int chunk
= 0;
1750 switch (TRB_TYPE(*trb
)) {
1754 chunk
= trb
->status
& 0x1ffff;
1757 if (xfer
->status
== CC_SUCCESS
) {
1770 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1771 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1772 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1773 event
.slotid
= xfer
->slotid
;
1774 event
.epid
= xfer
->epid
;
1775 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1777 event
.ptr
= trb
->addr
;
1778 if (xfer
->status
== CC_SUCCESS
) {
1779 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1781 event
.ccode
= xfer
->status
;
1783 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1784 event
.ptr
= trb
->parameter
;
1785 event
.flags
|= TRB_EV_ED
;
1786 event
.length
= edtla
& 0xffffff;
1787 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1790 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1792 if (xfer
->status
!= CC_SUCCESS
) {
1797 switch (TRB_TYPE(*trb
)) {
1807 static void xhci_stall_ep(XHCITransfer
*xfer
)
1809 XHCIState
*xhci
= xfer
->xhci
;
1810 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1811 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1813 XHCIStreamContext
*sctx
;
1815 if (epctx
->nr_pstreams
) {
1816 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1820 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1821 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1822 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1824 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1825 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1826 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1830 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1831 XHCIEPContext
*epctx
);
1833 static int xhci_setup_packet(XHCITransfer
*xfer
)
1835 XHCIState
*xhci
= xfer
->xhci
;
1839 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1841 if (xfer
->packet
.ep
) {
1842 ep
= xfer
->packet
.ep
;
1844 ep
= xhci_epid_to_usbep(xhci
, xfer
->slotid
, xfer
->epid
);
1846 DPRINTF("xhci: slot %d has no device\n",
1852 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1853 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1854 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1855 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1856 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1857 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1861 static int xhci_complete_packet(XHCITransfer
*xfer
)
1863 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1864 trace_usb_xhci_xfer_async(xfer
);
1865 xfer
->running_async
= 1;
1866 xfer
->running_retry
= 0;
1869 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1870 trace_usb_xhci_xfer_nak(xfer
);
1871 xfer
->running_async
= 0;
1872 xfer
->running_retry
= 1;
1876 xfer
->running_async
= 0;
1877 xfer
->running_retry
= 0;
1879 xhci_xfer_unmap(xfer
);
1882 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1883 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1884 xfer
->status
= CC_SUCCESS
;
1885 xhci_xfer_report(xfer
);
1890 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1891 switch (xfer
->packet
.status
) {
1893 case USB_RET_IOERROR
:
1894 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1895 xhci_xfer_report(xfer
);
1896 xhci_stall_ep(xfer
);
1899 xfer
->status
= CC_STALL_ERROR
;
1900 xhci_xfer_report(xfer
);
1901 xhci_stall_ep(xfer
);
1903 case USB_RET_BABBLE
:
1904 xfer
->status
= CC_BABBLE_DETECTED
;
1905 xhci_xfer_report(xfer
);
1906 xhci_stall_ep(xfer
);
1909 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1910 xfer
->packet
.status
);
1911 FIXME("unhandled USB_RET_*");
1916 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1918 XHCITRB
*trb_setup
, *trb_status
;
1919 uint8_t bmRequestType
;
1921 trb_setup
= &xfer
->trbs
[0];
1922 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1924 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1926 /* at most one Event Data TRB allowed after STATUS */
1927 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1931 /* do some sanity checks */
1932 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1933 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1934 TRB_TYPE(*trb_setup
));
1937 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1938 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1939 TRB_TYPE(*trb_status
));
1942 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1943 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1946 if ((trb_setup
->status
& 0x1ffff) != 8) {
1947 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1948 (trb_setup
->status
& 0x1ffff));
1952 bmRequestType
= trb_setup
->parameter
;
1954 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1955 xfer
->iso_xfer
= false;
1956 xfer
->timed_xfer
= false;
1958 if (xhci_setup_packet(xfer
) < 0) {
1961 xfer
->packet
.parameter
= trb_setup
->parameter
;
1963 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1965 xhci_complete_packet(xfer
);
1966 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1967 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, 0);
1972 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1973 XHCIEPContext
*epctx
, uint64_t mfindex
)
1975 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1976 ~(epctx
->interval
-1));
1977 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1979 assert(epctx
->interval
!= 0);
1980 xfer
->mfindex_kick
= MAX(asap
, kick
);
1983 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1984 XHCIEPContext
*epctx
, uint64_t mfindex
)
1986 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1987 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1988 ~(epctx
->interval
-1));
1989 if (asap
>= epctx
->mfindex_last
&&
1990 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1991 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1993 xfer
->mfindex_kick
= asap
;
1996 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1997 & TRB_TR_FRAMEID_MASK
) << 3;
1998 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1999 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
2000 xfer
->mfindex_kick
+= 0x4000;
2005 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
2006 XHCIEPContext
*epctx
, uint64_t mfindex
)
2008 if (xfer
->mfindex_kick
> mfindex
) {
2009 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
2010 (xfer
->mfindex_kick
- mfindex
) * 125000);
2011 xfer
->running_retry
= 1;
2013 epctx
->mfindex_last
= xfer
->mfindex_kick
;
2014 timer_del(epctx
->kick_timer
);
2015 xfer
->running_retry
= 0;
2020 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
2024 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
2026 xfer
->in_xfer
= epctx
->type
>>2;
2028 switch(epctx
->type
) {
2032 xfer
->iso_xfer
= false;
2033 xfer
->timed_xfer
= true;
2034 mfindex
= xhci_mfindex_get(xhci
);
2035 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
2036 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2037 if (xfer
->running_retry
) {
2044 xfer
->iso_xfer
= false;
2045 xfer
->timed_xfer
= false;
2050 xfer
->iso_xfer
= true;
2051 xfer
->timed_xfer
= true;
2052 mfindex
= xhci_mfindex_get(xhci
);
2053 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2054 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2055 if (xfer
->running_retry
) {
2060 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
2064 if (xhci_setup_packet(xfer
) < 0) {
2067 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2069 xhci_complete_packet(xfer
);
2070 if (!xfer
->running_async
&& !xfer
->running_retry
) {
2071 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
2076 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
2078 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
2079 return xhci_submit(xhci
, xfer
, epctx
);
2082 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
2083 unsigned int epid
, unsigned int streamid
)
2085 XHCIStreamContext
*stctx
;
2086 XHCIEPContext
*epctx
;
2088 USBEndpoint
*ep
= NULL
;
2093 trace_usb_xhci_ep_kick(slotid
, epid
, streamid
);
2094 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2095 assert(epid
>= 1 && epid
<= 31);
2097 if (!xhci
->slots
[slotid
-1].enabled
) {
2098 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
2101 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
2103 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2108 /* If the device has been detached, but the guest has not noticed this
2109 yet the 2 above checks will succeed, but we must NOT continue */
2110 if (!xhci
->slots
[slotid
- 1].uport
||
2111 !xhci
->slots
[slotid
- 1].uport
->dev
||
2112 !xhci
->slots
[slotid
- 1].uport
->dev
->attached
) {
2117 XHCITransfer
*xfer
= epctx
->retry
;
2119 trace_usb_xhci_xfer_retry(xfer
);
2120 assert(xfer
->running_retry
);
2121 if (xfer
->timed_xfer
) {
2122 /* time to kick the transfer? */
2123 mfindex
= xhci_mfindex_get(xhci
);
2124 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2125 if (xfer
->running_retry
) {
2128 xfer
->timed_xfer
= 0;
2129 xfer
->running_retry
= 1;
2131 if (xfer
->iso_xfer
) {
2132 /* retry iso transfer */
2133 if (xhci_setup_packet(xfer
) < 0) {
2136 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2137 assert(xfer
->packet
.status
!= USB_RET_NAK
);
2138 xhci_complete_packet(xfer
);
2140 /* retry nak'ed transfer */
2141 if (xhci_setup_packet(xfer
) < 0) {
2144 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2145 if (xfer
->packet
.status
== USB_RET_NAK
) {
2148 xhci_complete_packet(xfer
);
2150 assert(!xfer
->running_retry
);
2151 epctx
->retry
= NULL
;
2154 if (epctx
->state
== EP_HALTED
) {
2155 DPRINTF("xhci: ep halted, not running schedule\n");
2160 if (epctx
->nr_pstreams
) {
2162 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
2163 if (stctx
== NULL
) {
2166 ring
= &stctx
->ring
;
2167 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
2169 ring
= &epctx
->ring
;
2171 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
2173 assert(ring
->dequeue
!= 0);
2176 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
2177 if (xfer
->running_async
|| xfer
->running_retry
) {
2180 length
= xhci_ring_chain_length(xhci
, ring
);
2183 } else if (length
== 0) {
2186 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
2187 xfer
->trb_count
= 0;
2188 xfer
->trb_alloced
= 0;
2193 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
2194 xfer
->trb_alloced
= length
;
2196 xfer
->trb_count
= length
;
2198 for (i
= 0; i
< length
; i
++) {
2199 assert(xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
));
2201 xfer
->streamid
= streamid
;
2204 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
2205 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2207 DPRINTF("xhci: error firing CTL transfer\n");
2210 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
2211 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2213 if (!xfer
->timed_xfer
) {
2214 DPRINTF("xhci: error firing data transfer\n");
2219 if (epctx
->state
== EP_HALTED
) {
2222 if (xfer
->running_retry
) {
2223 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2224 epctx
->retry
= xfer
;
2229 ep
= xhci_epid_to_usbep(xhci
, slotid
, epid
);
2231 usb_device_flush_ep_queue(ep
->dev
, ep
);
2235 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2237 trace_usb_xhci_slot_enable(slotid
);
2238 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2239 xhci
->slots
[slotid
-1].enabled
= 1;
2240 xhci
->slots
[slotid
-1].uport
= NULL
;
2241 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2246 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2250 trace_usb_xhci_slot_disable(slotid
);
2251 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2253 for (i
= 1; i
<= 31; i
++) {
2254 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2255 xhci_disable_ep(xhci
, slotid
, i
);
2259 xhci
->slots
[slotid
-1].enabled
= 0;
2260 xhci
->slots
[slotid
-1].addressed
= 0;
2261 xhci
->slots
[slotid
-1].uport
= NULL
;
2265 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2271 port
= (slot_ctx
[1]>>16) & 0xFF;
2272 if (port
< 1 || port
> xhci
->numports
) {
2275 port
= xhci
->ports
[port
-1].uport
->index
+1;
2276 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2277 for (i
= 0; i
< 5; i
++) {
2278 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2282 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2285 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2286 if (strcmp(uport
->path
, path
) == 0) {
2293 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2294 uint64_t pictx
, bool bsr
)
2299 dma_addr_t ictx
, octx
, dcbaap
;
2301 uint32_t ictl_ctx
[2];
2302 uint32_t slot_ctx
[4];
2303 uint32_t ep0_ctx
[5];
2307 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2309 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2310 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2311 ictx
= xhci_mask64(pictx
);
2312 octx
= xhci_mask64(poctx
);
2314 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2315 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2317 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2319 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2320 DPRINTF("xhci: invalid input context control %08x %08x\n",
2321 ictl_ctx
[0], ictl_ctx
[1]);
2322 return CC_TRB_ERROR
;
2325 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2326 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2328 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2329 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2331 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2332 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2334 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2335 if (uport
== NULL
) {
2336 DPRINTF("xhci: port not found\n");
2337 return CC_TRB_ERROR
;
2339 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2342 if (!dev
|| !dev
->attached
) {
2343 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2344 return CC_USB_TRANSACTION_ERROR
;
2347 for (i
= 0; i
< xhci
->numslots
; i
++) {
2348 if (i
== slotid
-1) {
2351 if (xhci
->slots
[i
].uport
== uport
) {
2352 DPRINTF("xhci: port %s already assigned to slot %d\n",
2354 return CC_TRB_ERROR
;
2358 slot
= &xhci
->slots
[slotid
-1];
2359 slot
->uport
= uport
;
2363 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2368 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2369 usb_device_reset(dev
);
2370 memset(&p
, 0, sizeof(p
));
2371 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2372 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2373 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2375 usb_device_handle_control(dev
, &p
,
2376 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2377 slotid
, 0, 0, NULL
);
2378 assert(p
.status
!= USB_RET_ASYNC
);
2381 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2383 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2384 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2385 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2386 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2388 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2389 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2391 xhci
->slots
[slotid
-1].addressed
= 1;
2396 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2397 uint64_t pictx
, bool dc
)
2399 dma_addr_t ictx
, octx
;
2400 uint32_t ictl_ctx
[2];
2401 uint32_t slot_ctx
[4];
2402 uint32_t islot_ctx
[4];
2407 trace_usb_xhci_slot_configure(slotid
);
2408 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2410 ictx
= xhci_mask64(pictx
);
2411 octx
= xhci
->slots
[slotid
-1].ctx
;
2413 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2414 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2417 for (i
= 2; i
<= 31; i
++) {
2418 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2419 xhci_disable_ep(xhci
, slotid
, i
);
2423 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2424 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2425 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2426 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2427 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2428 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2433 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2435 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2436 DPRINTF("xhci: invalid input context control %08x %08x\n",
2437 ictl_ctx
[0], ictl_ctx
[1]);
2438 return CC_TRB_ERROR
;
2441 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2442 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2444 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2445 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2446 return CC_CONTEXT_STATE_ERROR
;
2449 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2451 for (i
= 2; i
<= 31; i
++) {
2452 if (ictl_ctx
[0] & (1<<i
)) {
2453 xhci_disable_ep(xhci
, slotid
, i
);
2455 if (ictl_ctx
[1] & (1<<i
)) {
2456 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2457 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2458 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2459 ep_ctx
[3], ep_ctx
[4]);
2460 xhci_disable_ep(xhci
, slotid
, i
);
2461 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2462 if (res
!= CC_SUCCESS
) {
2465 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2466 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2467 ep_ctx
[3], ep_ctx
[4]);
2468 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2472 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2473 if (res
!= CC_SUCCESS
) {
2474 for (i
= 2; i
<= 31; i
++) {
2475 if (ictl_ctx
[1] & (1u << i
)) {
2476 xhci_disable_ep(xhci
, slotid
, i
);
2482 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2483 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2484 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2485 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2486 SLOT_CONTEXT_ENTRIES_SHIFT
);
2487 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2488 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2490 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2496 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2499 dma_addr_t ictx
, octx
;
2500 uint32_t ictl_ctx
[2];
2501 uint32_t iep0_ctx
[5];
2502 uint32_t ep0_ctx
[5];
2503 uint32_t islot_ctx
[4];
2504 uint32_t slot_ctx
[4];
2506 trace_usb_xhci_slot_evaluate(slotid
);
2507 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2509 ictx
= xhci_mask64(pictx
);
2510 octx
= xhci
->slots
[slotid
-1].ctx
;
2512 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2513 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2515 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2517 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2518 DPRINTF("xhci: invalid input context control %08x %08x\n",
2519 ictl_ctx
[0], ictl_ctx
[1]);
2520 return CC_TRB_ERROR
;
2523 if (ictl_ctx
[1] & 0x1) {
2524 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2526 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2527 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2529 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2531 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2532 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2533 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2534 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2536 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2537 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2539 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2542 if (ictl_ctx
[1] & 0x2) {
2543 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2545 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2546 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2547 iep0_ctx
[3], iep0_ctx
[4]);
2549 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2551 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2552 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2554 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2555 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2557 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2563 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2565 uint32_t slot_ctx
[4];
2569 trace_usb_xhci_slot_reset(slotid
);
2570 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2572 octx
= xhci
->slots
[slotid
-1].ctx
;
2574 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2576 for (i
= 2; i
<= 31; i
++) {
2577 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2578 xhci_disable_ep(xhci
, slotid
, i
);
2582 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2583 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2584 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2585 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2586 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2587 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2592 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2594 unsigned int slotid
;
2595 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2596 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2597 DPRINTF("xhci: bad slot id %d\n", slotid
);
2598 event
->ccode
= CC_TRB_ERROR
;
2600 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2601 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2602 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2608 /* cleanup slot state on usb device detach */
2609 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2613 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2614 if (xhci
->slots
[slot
].uport
== uport
) {
2618 if (slot
== xhci
->numslots
) {
2622 for (ep
= 0; ep
< 31; ep
++) {
2623 if (xhci
->slots
[slot
].eps
[ep
]) {
2624 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2627 xhci
->slots
[slot
].uport
= NULL
;
2630 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2633 uint8_t bw_ctx
[xhci
->numports
+1];
2635 DPRINTF("xhci_get_port_bandwidth()\n");
2637 ctx
= xhci_mask64(pctx
);
2639 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2641 /* TODO: actually implement real values here */
2643 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2644 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2649 static uint32_t rotl(uint32_t v
, unsigned count
)
2652 return (v
<< count
) | (v
>> (32 - count
));
2656 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2659 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2660 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2661 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2665 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2667 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
2670 dma_addr_t paddr
= xhci_mask64(addr
);
2672 pci_dma_read(pci_dev
, paddr
, &buf
, 32);
2674 memcpy(obuf
, buf
, sizeof(obuf
));
2676 if ((buf
[0] & 0xff) == 2) {
2677 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2678 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2679 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2680 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2681 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2682 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2683 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2684 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2685 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2688 pci_dma_write(pci_dev
, paddr
, &obuf
, 32);
2691 static void xhci_process_commands(XHCIState
*xhci
)
2695 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2697 unsigned int i
, slotid
= 0;
2699 DPRINTF("xhci_process_commands()\n");
2700 if (!xhci_running(xhci
)) {
2701 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2705 xhci
->crcr_low
|= CRCR_CRR
;
2707 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2710 case CR_ENABLE_SLOT
:
2711 for (i
= 0; i
< xhci
->numslots
; i
++) {
2712 if (!xhci
->slots
[i
].enabled
) {
2716 if (i
>= xhci
->numslots
) {
2717 DPRINTF("xhci: no device slots available\n");
2718 event
.ccode
= CC_NO_SLOTS_ERROR
;
2721 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2724 case CR_DISABLE_SLOT
:
2725 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2727 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2730 case CR_ADDRESS_DEVICE
:
2731 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2733 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2734 trb
.control
& TRB_CR_BSR
);
2737 case CR_CONFIGURE_ENDPOINT
:
2738 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2740 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2741 trb
.control
& TRB_CR_DC
);
2744 case CR_EVALUATE_CONTEXT
:
2745 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2747 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2750 case CR_STOP_ENDPOINT
:
2751 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2753 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2755 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2758 case CR_RESET_ENDPOINT
:
2759 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2761 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2763 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2766 case CR_SET_TR_DEQUEUE
:
2767 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2769 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2771 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2772 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2777 case CR_RESET_DEVICE
:
2778 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2780 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2783 case CR_GET_PORT_BANDWIDTH
:
2784 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2786 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2787 xhci_via_challenge(xhci
, trb
.parameter
);
2789 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2790 event
.type
= 48; /* NEC reply */
2791 event
.length
= 0x3025;
2793 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2795 uint32_t chi
= trb
.parameter
>> 32;
2796 uint32_t clo
= trb
.parameter
;
2797 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2798 event
.length
= val
& 0xFFFF;
2799 event
.epid
= val
>> 16;
2801 event
.type
= 48; /* NEC reply */
2805 trace_usb_xhci_unimplemented("command", type
);
2806 event
.ccode
= CC_TRB_ERROR
;
2809 event
.slotid
= slotid
;
2810 xhci_event(xhci
, &event
, 0);
2814 static bool xhci_port_have_device(XHCIPort
*port
)
2816 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2817 return false; /* no device present */
2819 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2820 return false; /* speed mismatch */
2825 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2827 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2828 port
->portnr
<< 24 };
2830 if ((port
->portsc
& bits
) == bits
) {
2833 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2834 port
->portsc
|= bits
;
2835 if (!xhci_running(port
->xhci
)) {
2838 xhci_event(port
->xhci
, &ev
, 0);
2841 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2843 uint32_t pls
= PLS_RX_DETECT
;
2845 port
->portsc
= PORTSC_PP
;
2846 if (!is_detach
&& xhci_port_have_device(port
)) {
2847 port
->portsc
|= PORTSC_CCS
;
2848 switch (port
->uport
->dev
->speed
) {
2850 port
->portsc
|= PORTSC_SPEED_LOW
;
2853 case USB_SPEED_FULL
:
2854 port
->portsc
|= PORTSC_SPEED_FULL
;
2857 case USB_SPEED_HIGH
:
2858 port
->portsc
|= PORTSC_SPEED_HIGH
;
2861 case USB_SPEED_SUPER
:
2862 port
->portsc
|= PORTSC_SPEED_SUPER
;
2863 port
->portsc
|= PORTSC_PED
;
2868 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2869 trace_usb_xhci_port_link(port
->portnr
, pls
);
2870 xhci_port_notify(port
, PORTSC_CSC
);
2873 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2875 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2877 if (!xhci_port_have_device(port
)) {
2881 usb_device_reset(port
->uport
->dev
);
2883 switch (port
->uport
->dev
->speed
) {
2884 case USB_SPEED_SUPER
:
2886 port
->portsc
|= PORTSC_WRC
;
2890 case USB_SPEED_FULL
:
2891 case USB_SPEED_HIGH
:
2892 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2893 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2894 port
->portsc
|= PORTSC_PED
;
2898 port
->portsc
&= ~PORTSC_PR
;
2899 xhci_port_notify(port
, PORTSC_PRC
);
2902 static void xhci_reset(DeviceState
*dev
)
2904 XHCIState
*xhci
= XHCI(dev
);
2907 trace_usb_xhci_reset();
2908 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2909 DPRINTF("xhci: reset while running!\n");
2913 xhci
->usbsts
= USBSTS_HCH
;
2916 xhci
->crcr_high
= 0;
2917 xhci
->dcbaap_low
= 0;
2918 xhci
->dcbaap_high
= 0;
2921 for (i
= 0; i
< xhci
->numslots
; i
++) {
2922 xhci_disable_slot(xhci
, i
+1);
2925 for (i
= 0; i
< xhci
->numports
; i
++) {
2926 xhci_port_update(xhci
->ports
+ i
, 0);
2929 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2930 xhci
->intr
[i
].iman
= 0;
2931 xhci
->intr
[i
].imod
= 0;
2932 xhci
->intr
[i
].erstsz
= 0;
2933 xhci
->intr
[i
].erstba_low
= 0;
2934 xhci
->intr
[i
].erstba_high
= 0;
2935 xhci
->intr
[i
].erdp_low
= 0;
2936 xhci
->intr
[i
].erdp_high
= 0;
2937 xhci
->intr
[i
].msix_used
= 0;
2939 xhci
->intr
[i
].er_ep_idx
= 0;
2940 xhci
->intr
[i
].er_pcs
= 1;
2941 xhci
->intr
[i
].er_full
= 0;
2942 xhci
->intr
[i
].ev_buffer_put
= 0;
2943 xhci
->intr
[i
].ev_buffer_get
= 0;
2946 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2947 xhci_mfwrap_update(xhci
);
2950 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2952 XHCIState
*xhci
= ptr
;
2956 case 0x00: /* HCIVERSION, CAPLENGTH */
2957 ret
= 0x01000000 | LEN_CAP
;
2959 case 0x04: /* HCSPARAMS 1 */
2960 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2961 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2963 case 0x08: /* HCSPARAMS 2 */
2966 case 0x0c: /* HCSPARAMS 3 */
2969 case 0x10: /* HCCPARAMS */
2970 if (sizeof(dma_addr_t
) == 4) {
2971 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2973 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2976 case 0x14: /* DBOFF */
2979 case 0x18: /* RTSOFF */
2983 /* extended capabilities */
2984 case 0x20: /* Supported Protocol:00 */
2985 ret
= 0x02000402; /* USB 2.0 */
2987 case 0x24: /* Supported Protocol:04 */
2988 ret
= 0x20425355; /* "USB " */
2990 case 0x28: /* Supported Protocol:08 */
2991 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2992 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2994 ret
= (xhci
->numports_2
<<8) | 1;
2997 case 0x2c: /* Supported Protocol:0c */
2998 ret
= 0x00000000; /* reserved */
3000 case 0x30: /* Supported Protocol:00 */
3001 ret
= 0x03000002; /* USB 3.0 */
3003 case 0x34: /* Supported Protocol:04 */
3004 ret
= 0x20425355; /* "USB " */
3006 case 0x38: /* Supported Protocol:08 */
3007 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3008 ret
= (xhci
->numports_3
<<8) | 1;
3010 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
3013 case 0x3c: /* Supported Protocol:0c */
3014 ret
= 0x00000000; /* reserved */
3017 trace_usb_xhci_unimplemented("cap read", reg
);
3021 trace_usb_xhci_cap_read(reg
, ret
);
3025 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
3027 XHCIPort
*port
= ptr
;
3031 case 0x00: /* PORTSC */
3034 case 0x04: /* PORTPMSC */
3035 case 0x08: /* PORTLI */
3038 case 0x0c: /* reserved */
3040 trace_usb_xhci_unimplemented("port read", reg
);
3044 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
3048 static void xhci_port_write(void *ptr
, hwaddr reg
,
3049 uint64_t val
, unsigned size
)
3051 XHCIPort
*port
= ptr
;
3052 uint32_t portsc
, notify
;
3054 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
3057 case 0x00: /* PORTSC */
3058 /* write-1-to-start bits */
3059 if (val
& PORTSC_WPR
) {
3060 xhci_port_reset(port
, true);
3063 if (val
& PORTSC_PR
) {
3064 xhci_port_reset(port
, false);
3068 portsc
= port
->portsc
;
3070 /* write-1-to-clear bits*/
3071 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
3072 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
3073 if (val
& PORTSC_LWS
) {
3074 /* overwrite PLS only when LWS=1 */
3075 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
3076 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
3079 if (old_pls
!= PLS_U0
) {
3080 set_field(&portsc
, new_pls
, PORTSC_PLS
);
3081 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
3082 notify
= PORTSC_PLC
;
3086 if (old_pls
< PLS_U3
) {
3087 set_field(&portsc
, new_pls
, PORTSC_PLS
);
3088 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
3092 /* windows does this for some reason, don't spam stderr */
3095 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3096 __func__
, old_pls
, new_pls
);
3100 /* read/write bits */
3101 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
3102 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
3103 port
->portsc
= portsc
;
3105 xhci_port_notify(port
, notify
);
3108 case 0x04: /* PORTPMSC */
3109 case 0x08: /* PORTLI */
3111 trace_usb_xhci_unimplemented("port write", reg
);
3115 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
3117 XHCIState
*xhci
= ptr
;
3121 case 0x00: /* USBCMD */
3124 case 0x04: /* USBSTS */
3127 case 0x08: /* PAGESIZE */
3130 case 0x14: /* DNCTRL */
3133 case 0x18: /* CRCR low */
3134 ret
= xhci
->crcr_low
& ~0xe;
3136 case 0x1c: /* CRCR high */
3137 ret
= xhci
->crcr_high
;
3139 case 0x30: /* DCBAAP low */
3140 ret
= xhci
->dcbaap_low
;
3142 case 0x34: /* DCBAAP high */
3143 ret
= xhci
->dcbaap_high
;
3145 case 0x38: /* CONFIG */
3149 trace_usb_xhci_unimplemented("oper read", reg
);
3153 trace_usb_xhci_oper_read(reg
, ret
);
3157 static void xhci_oper_write(void *ptr
, hwaddr reg
,
3158 uint64_t val
, unsigned size
)
3160 XHCIState
*xhci
= ptr
;
3161 DeviceState
*d
= DEVICE(ptr
);
3163 trace_usb_xhci_oper_write(reg
, val
);
3166 case 0x00: /* USBCMD */
3167 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
3169 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
3172 if (val
& USBCMD_CSS
) {
3174 xhci
->usbsts
&= ~USBSTS_SRE
;
3176 if (val
& USBCMD_CRS
) {
3178 xhci
->usbsts
|= USBSTS_SRE
;
3180 xhci
->usbcmd
= val
& 0xc0f;
3181 xhci_mfwrap_update(xhci
);
3182 if (val
& USBCMD_HCRST
) {
3185 xhci_intx_update(xhci
);
3188 case 0x04: /* USBSTS */
3189 /* these bits are write-1-to-clear */
3190 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
3191 xhci_intx_update(xhci
);
3194 case 0x14: /* DNCTRL */
3195 xhci
->dnctrl
= val
& 0xffff;
3197 case 0x18: /* CRCR low */
3198 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
3200 case 0x1c: /* CRCR high */
3201 xhci
->crcr_high
= val
;
3202 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
3203 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
3204 xhci
->crcr_low
&= ~CRCR_CRR
;
3205 xhci_event(xhci
, &event
, 0);
3206 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
3208 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
3209 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
3211 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
3213 case 0x30: /* DCBAAP low */
3214 xhci
->dcbaap_low
= val
& 0xffffffc0;
3216 case 0x34: /* DCBAAP high */
3217 xhci
->dcbaap_high
= val
;
3219 case 0x38: /* CONFIG */
3220 xhci
->config
= val
& 0xff;
3223 trace_usb_xhci_unimplemented("oper write", reg
);
3227 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
3230 XHCIState
*xhci
= ptr
;
3235 case 0x00: /* MFINDEX */
3236 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3239 trace_usb_xhci_unimplemented("runtime read", reg
);
3243 int v
= (reg
- 0x20) / 0x20;
3244 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3245 switch (reg
& 0x1f) {
3246 case 0x00: /* IMAN */
3249 case 0x04: /* IMOD */
3252 case 0x08: /* ERSTSZ */
3255 case 0x10: /* ERSTBA low */
3256 ret
= intr
->erstba_low
;
3258 case 0x14: /* ERSTBA high */
3259 ret
= intr
->erstba_high
;
3261 case 0x18: /* ERDP low */
3262 ret
= intr
->erdp_low
;
3264 case 0x1c: /* ERDP high */
3265 ret
= intr
->erdp_high
;
3270 trace_usb_xhci_runtime_read(reg
, ret
);
3274 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3275 uint64_t val
, unsigned size
)
3277 XHCIState
*xhci
= ptr
;
3278 int v
= (reg
- 0x20) / 0x20;
3279 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3280 trace_usb_xhci_runtime_write(reg
, val
);
3283 trace_usb_xhci_unimplemented("runtime write", reg
);
3287 switch (reg
& 0x1f) {
3288 case 0x00: /* IMAN */
3289 if (val
& IMAN_IP
) {
3290 intr
->iman
&= ~IMAN_IP
;
3292 intr
->iman
&= ~IMAN_IE
;
3293 intr
->iman
|= val
& IMAN_IE
;
3295 xhci_intx_update(xhci
);
3297 xhci_msix_update(xhci
, v
);
3299 case 0x04: /* IMOD */
3302 case 0x08: /* ERSTSZ */
3303 intr
->erstsz
= val
& 0xffff;
3305 case 0x10: /* ERSTBA low */
3306 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3307 intr->erstba_low = val & 0xffffffc0; */
3308 intr
->erstba_low
= val
& 0xfffffff0;
3310 case 0x14: /* ERSTBA high */
3311 intr
->erstba_high
= val
;
3312 xhci_er_reset(xhci
, v
);
3314 case 0x18: /* ERDP low */
3315 if (val
& ERDP_EHB
) {
3316 intr
->erdp_low
&= ~ERDP_EHB
;
3318 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3320 case 0x1c: /* ERDP high */
3321 intr
->erdp_high
= val
;
3322 xhci_events_update(xhci
, v
);
3325 trace_usb_xhci_unimplemented("oper write", reg
);
3329 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3332 /* doorbells always read as 0 */
3333 trace_usb_xhci_doorbell_read(reg
, 0);
3337 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3338 uint64_t val
, unsigned size
)
3340 XHCIState
*xhci
= ptr
;
3341 unsigned int epid
, streamid
;
3343 trace_usb_xhci_doorbell_write(reg
, val
);
3345 if (!xhci_running(xhci
)) {
3346 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3354 xhci_process_commands(xhci
);
3356 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3361 streamid
= (val
>> 16) & 0xffff;
3362 if (reg
> xhci
->numslots
) {
3363 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3364 } else if (epid
> 31) {
3365 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3366 (int)reg
, (uint32_t)val
);
3368 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3373 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3379 static const MemoryRegionOps xhci_cap_ops
= {
3380 .read
= xhci_cap_read
,
3381 .write
= xhci_cap_write
,
3382 .valid
.min_access_size
= 1,
3383 .valid
.max_access_size
= 4,
3384 .impl
.min_access_size
= 4,
3385 .impl
.max_access_size
= 4,
3386 .endianness
= DEVICE_LITTLE_ENDIAN
,
3389 static const MemoryRegionOps xhci_oper_ops
= {
3390 .read
= xhci_oper_read
,
3391 .write
= xhci_oper_write
,
3392 .valid
.min_access_size
= 4,
3393 .valid
.max_access_size
= 4,
3394 .endianness
= DEVICE_LITTLE_ENDIAN
,
3397 static const MemoryRegionOps xhci_port_ops
= {
3398 .read
= xhci_port_read
,
3399 .write
= xhci_port_write
,
3400 .valid
.min_access_size
= 4,
3401 .valid
.max_access_size
= 4,
3402 .endianness
= DEVICE_LITTLE_ENDIAN
,
3405 static const MemoryRegionOps xhci_runtime_ops
= {
3406 .read
= xhci_runtime_read
,
3407 .write
= xhci_runtime_write
,
3408 .valid
.min_access_size
= 4,
3409 .valid
.max_access_size
= 4,
3410 .endianness
= DEVICE_LITTLE_ENDIAN
,
3413 static const MemoryRegionOps xhci_doorbell_ops
= {
3414 .read
= xhci_doorbell_read
,
3415 .write
= xhci_doorbell_write
,
3416 .valid
.min_access_size
= 4,
3417 .valid
.max_access_size
= 4,
3418 .endianness
= DEVICE_LITTLE_ENDIAN
,
3421 static void xhci_attach(USBPort
*usbport
)
3423 XHCIState
*xhci
= usbport
->opaque
;
3424 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3426 xhci_port_update(port
, 0);
3429 static void xhci_detach(USBPort
*usbport
)
3431 XHCIState
*xhci
= usbport
->opaque
;
3432 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3434 xhci_detach_slot(xhci
, usbport
);
3435 xhci_port_update(port
, 1);
3438 static void xhci_wakeup(USBPort
*usbport
)
3440 XHCIState
*xhci
= usbport
->opaque
;
3441 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3443 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3446 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3447 xhci_port_notify(port
, PORTSC_PLC
);
3450 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3452 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3454 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3455 xhci_ep_nuke_one_xfer(xfer
, 0);
3458 xhci_complete_packet(xfer
);
3459 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
3462 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3464 USBBus
*bus
= usb_bus_from_device(child
);
3465 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3467 xhci_detach_slot(xhci
, child
->port
);
3470 static USBPortOps xhci_uport_ops
= {
3471 .attach
= xhci_attach
,
3472 .detach
= xhci_detach
,
3473 .wakeup
= xhci_wakeup
,
3474 .complete
= xhci_complete
,
3475 .child_detach
= xhci_child_detach
,
3478 static int xhci_find_epid(USBEndpoint
*ep
)
3483 if (ep
->pid
== USB_TOKEN_IN
) {
3484 return ep
->nr
* 2 + 1;
3490 static USBEndpoint
*xhci_epid_to_usbep(XHCIState
*xhci
,
3491 unsigned int slotid
, unsigned int epid
)
3493 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
3495 if (!xhci
->slots
[slotid
- 1].uport
) {
3499 return usb_ep_get(xhci
->slots
[slotid
- 1].uport
->dev
,
3500 (epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
, epid
>> 1);
3503 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3504 unsigned int stream
)
3506 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3509 DPRINTF("%s\n", __func__
);
3510 slotid
= ep
->dev
->addr
;
3511 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3512 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3515 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3518 static USBBusOps xhci_bus_ops
= {
3519 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3522 static void usb_xhci_init(XHCIState
*xhci
)
3524 DeviceState
*dev
= DEVICE(xhci
);
3526 int i
, usbports
, speedmask
;
3528 xhci
->usbsts
= USBSTS_HCH
;
3530 if (xhci
->numports_2
> MAXPORTS_2
) {
3531 xhci
->numports_2
= MAXPORTS_2
;
3533 if (xhci
->numports_3
> MAXPORTS_3
) {
3534 xhci
->numports_3
= MAXPORTS_3
;
3536 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3537 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3539 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, dev
);
3541 for (i
= 0; i
< usbports
; i
++) {
3543 if (i
< xhci
->numports_2
) {
3544 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3545 port
= &xhci
->ports
[i
+ xhci
->numports_3
];
3546 port
->portnr
= i
+ 1 + xhci
->numports_3
;
3548 port
= &xhci
->ports
[i
];
3549 port
->portnr
= i
+ 1;
3551 port
->uport
= &xhci
->uports
[i
];
3553 USB_SPEED_MASK_LOW
|
3554 USB_SPEED_MASK_FULL
|
3555 USB_SPEED_MASK_HIGH
;
3556 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3557 speedmask
|= port
->speedmask
;
3559 if (i
< xhci
->numports_3
) {
3560 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3561 port
= &xhci
->ports
[i
];
3562 port
->portnr
= i
+ 1;
3564 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3565 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3567 port
->uport
= &xhci
->uports
[i
];
3568 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3569 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3570 speedmask
|= port
->speedmask
;
3572 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3573 &xhci_uport_ops
, speedmask
);
3577 static void usb_xhci_realize(struct PCIDevice
*dev
, Error
**errp
)
3581 XHCIState
*xhci
= XHCI(dev
);
3583 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3584 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3585 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3586 dev
->config
[0x60] = 0x30; /* release number */
3588 usb_xhci_init(xhci
);
3590 if (xhci
->numintrs
> MAXINTRS
) {
3591 xhci
->numintrs
= MAXINTRS
;
3593 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3596 if (xhci
->numintrs
< 1) {
3599 if (xhci
->numslots
> MAXSLOTS
) {
3600 xhci
->numslots
= MAXSLOTS
;
3602 if (xhci
->numslots
< 1) {
3605 if (xhci_get_flag(xhci
, XHCI_FLAG_ENABLE_STREAMS
)) {
3606 xhci
->max_pstreams_mask
= 7; /* == 256 primary streams */
3608 xhci
->max_pstreams_mask
= 0;
3611 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3613 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3614 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3615 "capabilities", LEN_CAP
);
3616 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3617 "operational", 0x400);
3618 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3619 "runtime", LEN_RUNTIME
);
3620 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3621 "doorbell", LEN_DOORBELL
);
3623 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3624 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3625 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3626 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3628 for (i
= 0; i
< xhci
->numports
; i
++) {
3629 XHCIPort
*port
= &xhci
->ports
[i
];
3630 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3632 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3634 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3637 pci_register_bar(dev
, 0,
3638 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3641 if (pci_bus_is_express(dev
->bus
) ||
3642 xhci_get_flag(xhci
, XHCI_FLAG_FORCE_PCIE_ENDCAP
)) {
3643 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3647 if (xhci_get_flag(xhci
, XHCI_FLAG_USE_MSI
)) {
3648 msi_init(dev
, 0x70, xhci
->numintrs
, true, false);
3650 if (xhci_get_flag(xhci
, XHCI_FLAG_USE_MSI_X
)) {
3651 msix_init(dev
, xhci
->numintrs
,
3652 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3653 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3658 static void usb_xhci_exit(PCIDevice
*dev
)
3661 XHCIState
*xhci
= XHCI(dev
);
3663 trace_usb_xhci_exit();
3665 for (i
= 0; i
< xhci
->numslots
; i
++) {
3666 xhci_disable_slot(xhci
, i
+ 1);
3669 if (xhci
->mfwrap_timer
) {
3670 timer_del(xhci
->mfwrap_timer
);
3671 timer_free(xhci
->mfwrap_timer
);
3672 xhci
->mfwrap_timer
= NULL
;
3675 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_cap
);
3676 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_oper
);
3677 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_runtime
);
3678 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_doorbell
);
3680 for (i
= 0; i
< xhci
->numports
; i
++) {
3681 XHCIPort
*port
= &xhci
->ports
[i
];
3682 memory_region_del_subregion(&xhci
->mem
, &port
->mem
);
3685 /* destroy msix memory region */
3686 if (dev
->msix_table
&& dev
->msix_pba
3687 && dev
->msix_entry_used
) {
3688 memory_region_del_subregion(&xhci
->mem
, &dev
->msix_table_mmio
);
3689 memory_region_del_subregion(&xhci
->mem
, &dev
->msix_pba_mmio
);
3692 usb_bus_release(&xhci
->bus
);
3695 static int usb_xhci_post_load(void *opaque
, int version_id
)
3697 XHCIState
*xhci
= opaque
;
3698 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3700 XHCIEPContext
*epctx
;
3701 dma_addr_t dcbaap
, pctx
;
3702 uint32_t slot_ctx
[4];
3704 int slotid
, epid
, state
, intr
;
3706 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3708 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3709 slot
= &xhci
->slots
[slotid
-1];
3710 if (!slot
->addressed
) {
3714 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3715 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3716 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3718 /* should not happen, but may trigger on guest bugs */
3720 slot
->addressed
= 0;
3723 assert(slot
->uport
&& slot
->uport
->dev
);
3725 for (epid
= 1; epid
<= 31; epid
++) {
3726 pctx
= slot
->ctx
+ 32 * epid
;
3727 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3728 state
= ep_ctx
[0] & EP_STATE_MASK
;
3729 if (state
== EP_DISABLED
) {
3732 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3733 slot
->eps
[epid
-1] = epctx
;
3734 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3735 epctx
->state
= state
;
3736 if (state
== EP_RUNNING
) {
3737 /* kick endpoint after vmload is finished */
3738 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3743 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3744 if (xhci
->intr
[intr
].msix_used
) {
3745 msix_vector_use(pci_dev
, intr
);
3747 msix_vector_unuse(pci_dev
, intr
);
3754 static const VMStateDescription vmstate_xhci_ring
= {
3755 .name
= "xhci-ring",
3757 .fields
= (VMStateField
[]) {
3758 VMSTATE_UINT64(dequeue
, XHCIRing
),
3759 VMSTATE_BOOL(ccs
, XHCIRing
),
3760 VMSTATE_END_OF_LIST()
3764 static const VMStateDescription vmstate_xhci_port
= {
3765 .name
= "xhci-port",
3767 .fields
= (VMStateField
[]) {
3768 VMSTATE_UINT32(portsc
, XHCIPort
),
3769 VMSTATE_END_OF_LIST()
3773 static const VMStateDescription vmstate_xhci_slot
= {
3774 .name
= "xhci-slot",
3776 .fields
= (VMStateField
[]) {
3777 VMSTATE_BOOL(enabled
, XHCISlot
),
3778 VMSTATE_BOOL(addressed
, XHCISlot
),
3779 VMSTATE_END_OF_LIST()
3783 static const VMStateDescription vmstate_xhci_event
= {
3784 .name
= "xhci-event",
3786 .fields
= (VMStateField
[]) {
3787 VMSTATE_UINT32(type
, XHCIEvent
),
3788 VMSTATE_UINT32(ccode
, XHCIEvent
),
3789 VMSTATE_UINT64(ptr
, XHCIEvent
),
3790 VMSTATE_UINT32(length
, XHCIEvent
),
3791 VMSTATE_UINT32(flags
, XHCIEvent
),
3792 VMSTATE_UINT8(slotid
, XHCIEvent
),
3793 VMSTATE_UINT8(epid
, XHCIEvent
),
3794 VMSTATE_END_OF_LIST()
3798 static bool xhci_er_full(void *opaque
, int version_id
)
3800 struct XHCIInterrupter
*intr
= opaque
;
3801 return intr
->er_full
;
3804 static const VMStateDescription vmstate_xhci_intr
= {
3805 .name
= "xhci-intr",
3807 .fields
= (VMStateField
[]) {
3809 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3810 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3811 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3812 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3813 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3814 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3815 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3818 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3819 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3820 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3821 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3822 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3824 /* event queue (used if ring is full) */
3825 VMSTATE_BOOL(er_full
, XHCIInterrupter
),
3826 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3827 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3828 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3830 vmstate_xhci_event
, XHCIEvent
),
3832 VMSTATE_END_OF_LIST()
3836 static const VMStateDescription vmstate_xhci
= {
3839 .post_load
= usb_xhci_post_load
,
3840 .fields
= (VMStateField
[]) {
3841 VMSTATE_PCIE_DEVICE(parent_obj
, XHCIState
),
3842 VMSTATE_MSIX(parent_obj
, XHCIState
),
3844 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3845 vmstate_xhci_port
, XHCIPort
),
3846 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3847 vmstate_xhci_slot
, XHCISlot
),
3848 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3849 vmstate_xhci_intr
, XHCIInterrupter
),
3851 /* Operational Registers */
3852 VMSTATE_UINT32(usbcmd
, XHCIState
),
3853 VMSTATE_UINT32(usbsts
, XHCIState
),
3854 VMSTATE_UINT32(dnctrl
, XHCIState
),
3855 VMSTATE_UINT32(crcr_low
, XHCIState
),
3856 VMSTATE_UINT32(crcr_high
, XHCIState
),
3857 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3858 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3859 VMSTATE_UINT32(config
, XHCIState
),
3861 /* Runtime Registers & state */
3862 VMSTATE_INT64(mfindex_start
, XHCIState
),
3863 VMSTATE_TIMER_PTR(mfwrap_timer
, XHCIState
),
3864 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3866 VMSTATE_END_OF_LIST()
3870 static Property xhci_properties
[] = {
3871 DEFINE_PROP_BIT("msi", XHCIState
, flags
, XHCI_FLAG_USE_MSI
, true),
3872 DEFINE_PROP_BIT("msix", XHCIState
, flags
, XHCI_FLAG_USE_MSI_X
, true),
3873 DEFINE_PROP_BIT("superspeed-ports-first",
3874 XHCIState
, flags
, XHCI_FLAG_SS_FIRST
, true),
3875 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState
, flags
,
3876 XHCI_FLAG_FORCE_PCIE_ENDCAP
, false),
3877 DEFINE_PROP_BIT("streams", XHCIState
, flags
,
3878 XHCI_FLAG_ENABLE_STREAMS
, true),
3879 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3880 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3881 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3882 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3883 DEFINE_PROP_END_OF_LIST(),
3886 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3888 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3889 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3891 dc
->vmsd
= &vmstate_xhci
;
3892 dc
->props
= xhci_properties
;
3893 dc
->reset
= xhci_reset
;
3894 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3895 k
->realize
= usb_xhci_realize
;
3896 k
->exit
= usb_xhci_exit
;
3897 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3898 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3899 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3904 static const TypeInfo xhci_info
= {
3906 .parent
= TYPE_PCI_DEVICE
,
3907 .instance_size
= sizeof(XHCIState
),
3908 .class_init
= xhci_class_init
,
3911 static void xhci_register_types(void)
3913 type_register_static(&xhci_info
);
3916 type_init(xhci_register_types
)