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target/rx: CPU definitions
[qemu/ar7.git] / hw / audio / ac97.c
blob1ec87feec0cb2dc4180ea6d5368b891706bf85fa
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/audio/soundhw.h"
22 #include "audio/audio.h"
23 #include "hw/pci/pci.h"
24 #include "hw/qdev-properties.h"
25 #include "migration/vmstate.h"
26 #include "qemu/module.h"
27 #include "sysemu/dma.h"
28
29 enum {
30 AC97_Reset = 0x00,
31 AC97_Master_Volume_Mute = 0x02,
32 AC97_Headphone_Volume_Mute = 0x04,
33 AC97_Master_Volume_Mono_Mute = 0x06,
34 AC97_Master_Tone_RL = 0x08,
35 AC97_PC_BEEP_Volume_Mute = 0x0A,
36 AC97_Phone_Volume_Mute = 0x0C,
37 AC97_Mic_Volume_Mute = 0x0E,
38 AC97_Line_In_Volume_Mute = 0x10,
39 AC97_CD_Volume_Mute = 0x12,
40 AC97_Video_Volume_Mute = 0x14,
41 AC97_Aux_Volume_Mute = 0x16,
42 AC97_PCM_Out_Volume_Mute = 0x18,
43 AC97_Record_Select = 0x1A,
44 AC97_Record_Gain_Mute = 0x1C,
45 AC97_Record_Gain_Mic_Mute = 0x1E,
46 AC97_General_Purpose = 0x20,
47 AC97_3D_Control = 0x22,
48 AC97_AC_97_RESERVED = 0x24,
49 AC97_Powerdown_Ctrl_Stat = 0x26,
50 AC97_Extended_Audio_ID = 0x28,
51 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
52 AC97_PCM_Front_DAC_Rate = 0x2C,
53 AC97_PCM_Surround_DAC_Rate = 0x2E,
54 AC97_PCM_LFE_DAC_Rate = 0x30,
55 AC97_PCM_LR_ADC_Rate = 0x32,
56 AC97_MIC_ADC_Rate = 0x34,
57 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
58 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
59 AC97_Vendor_Reserved = 0x58,
60 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
61 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
62 AC97_Vendor_ID1 = 0x7c,
63 AC97_Vendor_ID2 = 0x7e
64 };
65
66 #define SOFT_VOLUME
67 #define SR_FIFOE 16 /* rwc */
68 #define SR_BCIS 8 /* rwc */
69 #define SR_LVBCI 4 /* rwc */
70 #define SR_CELV 2 /* ro */
71 #define SR_DCH 1 /* ro */
72 #define SR_VALID_MASK ((1 << 5) - 1)
73 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
74 #define SR_RO_MASK (SR_DCH | SR_CELV)
75 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
76
77 #define CR_IOCE 16 /* rw */
78 #define CR_FEIE 8 /* rw */
79 #define CR_LVBIE 4 /* rw */
80 #define CR_RR 2 /* rw */
81 #define CR_RPBM 1 /* rw */
82 #define CR_VALID_MASK ((1 << 5) - 1)
83 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
84
85 #define GC_WR 4 /* rw */
86 #define GC_CR 2 /* rw */
87 #define GC_VALID_MASK ((1 << 6) - 1)
88
89 #define GS_MD3 (1<<17) /* rw */
90 #define GS_AD3 (1<<16) /* rw */
91 #define GS_RCS (1<<15) /* rwc */
92 #define GS_B3S12 (1<<14) /* ro */
93 #define GS_B2S12 (1<<13) /* ro */
94 #define GS_B1S12 (1<<12) /* ro */
95 #define GS_S1R1 (1<<11) /* rwc */
96 #define GS_S0R1 (1<<10) /* rwc */
97 #define GS_S1CR (1<<9) /* ro */
98 #define GS_S0CR (1<<8) /* ro */
99 #define GS_MINT (1<<7) /* ro */
100 #define GS_POINT (1<<6) /* ro */
101 #define GS_PIINT (1<<5) /* ro */
102 #define GS_RSRVD ((1<<4)|(1<<3))
103 #define GS_MOINT (1<<2) /* ro */
104 #define GS_MIINT (1<<1) /* ro */
105 #define GS_GSCI 1 /* rwc */
106 #define GS_RO_MASK (GS_B3S12| \
107 GS_B2S12| \
108 GS_B1S12| \
109 GS_S1CR| \
110 GS_S0CR| \
111 GS_MINT| \
112 GS_POINT| \
113 GS_PIINT| \
114 GS_RSRVD| \
115 GS_MOINT| \
116 GS_MIINT)
117 #define GS_VALID_MASK ((1 << 18) - 1)
118 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
119
120 #define BD_IOC (1<<31)
121 #define BD_BUP (1<<30)
122
123 #define EACS_VRA 1
124 #define EACS_VRM 8
125
126 #define MUTE_SHIFT 15
127
128 #define TYPE_AC97 "AC97"
129 #define AC97(obj) \
130 OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97)
131
132 #define REC_MASK 7
133 enum {
134 REC_MIC = 0,
135 REC_CD,
136 REC_VIDEO,
137 REC_AUX,
138 REC_LINE_IN,
139 REC_STEREO_MIX,
140 REC_MONO_MIX,
141 REC_PHONE
142 };
143
144 typedef struct BD {
145 uint32_t addr;
146 uint32_t ctl_len;
147 } BD;
148
149 typedef struct AC97BusMasterRegs {
150 uint32_t bdbar; /* rw 0 */
151 uint8_t civ; /* ro 0 */
152 uint8_t lvi; /* rw 0 */
153 uint16_t sr; /* rw 1 */
154 uint16_t picb; /* ro 0 */
155 uint8_t piv; /* ro 0 */
156 uint8_t cr; /* rw 0 */
157 unsigned int bd_valid;
158 BD bd;
159 } AC97BusMasterRegs;
160
161 typedef struct AC97LinkState {
162 PCIDevice dev;
163 QEMUSoundCard card;
164 uint32_t glob_cnt;
165 uint32_t glob_sta;
166 uint32_t cas;
167 uint32_t last_samp;
168 AC97BusMasterRegs bm_regs[3];
169 uint8_t mixer_data[256];
170 SWVoiceIn *voice_pi;
171 SWVoiceOut *voice_po;
172 SWVoiceIn *voice_mc;
173 int invalid_freq[3];
174 uint8_t silence[128];
175 int bup_flag;
176 MemoryRegion io_nam;
177 MemoryRegion io_nabm;
178 } AC97LinkState;
179
180 enum {
181 BUP_SET = 1,
182 BUP_LAST = 2
183 };
184
185 #ifdef DEBUG_AC97
186 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
187 #else
188 #define dolog(...)
189 #endif
190
191 #define MKREGS(prefix, start) \
192 enum { \
193 prefix ## _BDBAR = start, \
194 prefix ## _CIV = start + 4, \
195 prefix ## _LVI = start + 5, \
196 prefix ## _SR = start + 6, \
197 prefix ## _PICB = start + 8, \
198 prefix ## _PIV = start + 10, \
199 prefix ## _CR = start + 11 \
200 }
201
202 enum {
203 PI_INDEX = 0,
204 PO_INDEX,
205 MC_INDEX,
206 LAST_INDEX
207 };
208
209 MKREGS (PI, PI_INDEX * 16);
210 MKREGS (PO, PO_INDEX * 16);
211 MKREGS (MC, MC_INDEX * 16);
212
213 enum {
214 GLOB_CNT = 0x2c,
215 GLOB_STA = 0x30,
216 CAS = 0x34
217 };
218
219 #define GET_BM(index) (((index) >> 4) & 3)
220
221 static void po_callback (void *opaque, int free);
222 static void pi_callback (void *opaque, int avail);
223 static void mc_callback (void *opaque, int avail);
224
225 static void warm_reset (AC97LinkState *s)
226 {
227 (void) s;
228 }
229
230 static void cold_reset (AC97LinkState * s)
231 {
232 (void) s;
233 }
234
235 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
236 {
237 uint8_t b[8];
238
239 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
240 r->bd_valid = 1;
241 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
242 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
243 r->picb = r->bd.ctl_len & 0xffff;
244 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
245 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
246 r->bd.ctl_len & 0xffff,
247 (r->bd.ctl_len & 0xffff) << 1);
248 }
249
250 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
251 {
252 int event = 0;
253 int level = 0;
254 uint32_t new_mask = new_sr & SR_INT_MASK;
255 uint32_t old_mask = r->sr & SR_INT_MASK;
256 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
257
258 if (new_mask ^ old_mask) {
259 /** @todo is IRQ deasserted when only one of status bits is cleared? */
260 if (!new_mask) {
261 event = 1;
262 level = 0;
263 }
264 else {
265 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
266 event = 1;
267 level = 1;
268 }
269 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
270 event = 1;
271 level = 1;
272 }
273 }
274 }
275
276 r->sr = new_sr;
277
278 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
279 r->sr & SR_BCIS, r->sr & SR_LVBCI,
280 r->sr,
281 event, level);
282
283 if (!event)
284 return;
285
286 if (level) {
287 s->glob_sta |= masks[r - s->bm_regs];
288 dolog ("set irq level=1\n");
289 pci_irq_assert(&s->dev);
290 }
291 else {
292 s->glob_sta &= ~masks[r - s->bm_regs];
293 dolog ("set irq level=0\n");
294 pci_irq_deassert(&s->dev);
295 }
296 }
297
298 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
299 {
300 switch (bm_index) {
301 case PI_INDEX:
302 AUD_set_active_in (s->voice_pi, on);
303 break;
304
305 case PO_INDEX:
306 AUD_set_active_out (s->voice_po, on);
307 break;
308
309 case MC_INDEX:
310 AUD_set_active_in (s->voice_mc, on);
311 break;
312
313 default:
314 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
315 break;
316 }
317 }
318
319 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
320 {
321 dolog ("reset_bm_regs\n");
322 r->bdbar = 0;
323 r->civ = 0;
324 r->lvi = 0;
325 /** todo do we need to do that? */
326 update_sr (s, r, SR_DCH);
327 r->picb = 0;
328 r->piv = 0;
329 r->cr = r->cr & CR_DONT_CLEAR_MASK;
330 r->bd_valid = 0;
331
332 voice_set_active (s, r - s->bm_regs, 0);
333 memset (s->silence, 0, sizeof (s->silence));
334 }
335
336 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
337 {
338 if (i + 2 > sizeof (s->mixer_data)) {
339 dolog ("mixer_store: index %d out of bounds %zd\n",
340 i, sizeof (s->mixer_data));
341 return;
342 }
343
344 s->mixer_data[i + 0] = v & 0xff;
345 s->mixer_data[i + 1] = v >> 8;
346 }
347
348 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
349 {
350 uint16_t val = 0xffff;
351
352 if (i + 2 > sizeof (s->mixer_data)) {
353 dolog ("mixer_load: index %d out of bounds %zd\n",
354 i, sizeof (s->mixer_data));
355 }
356 else {
357 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
358 }
359
360 return val;
361 }
362
363 static void open_voice (AC97LinkState *s, int index, int freq)
364 {
365 struct audsettings as;
366
367 as.freq = freq;
368 as.nchannels = 2;
369 as.fmt = AUDIO_FORMAT_S16;
370 as.endianness = 0;
371
372 if (freq > 0) {
373 s->invalid_freq[index] = 0;
374 switch (index) {
375 case PI_INDEX:
376 s->voice_pi = AUD_open_in (
377 &s->card,
378 s->voice_pi,
379 "ac97.pi",
380 s,
381 pi_callback,
382 &as
383 );
384 break;
385
386 case PO_INDEX:
387 s->voice_po = AUD_open_out (
388 &s->card,
389 s->voice_po,
390 "ac97.po",
391 s,
392 po_callback,
393 &as
394 );
395 break;
396
397 case MC_INDEX:
398 s->voice_mc = AUD_open_in (
399 &s->card,
400 s->voice_mc,
401 "ac97.mc",
402 s,
403 mc_callback,
404 &as
405 );
406 break;
407 }
408 }
409 else {
410 s->invalid_freq[index] = freq;
411 switch (index) {
412 case PI_INDEX:
413 AUD_close_in (&s->card, s->voice_pi);
414 s->voice_pi = NULL;
415 break;
416
417 case PO_INDEX:
418 AUD_close_out (&s->card, s->voice_po);
419 s->voice_po = NULL;
420 break;
421
422 case MC_INDEX:
423 AUD_close_in (&s->card, s->voice_mc);
424 s->voice_mc = NULL;
425 break;
426 }
427 }
428 }
429
430 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
431 {
432 uint16_t freq;
433
434 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
435 open_voice (s, PI_INDEX, freq);
436 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
437
438 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
439 open_voice (s, PO_INDEX, freq);
440 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
441
442 freq = mixer_load (s, AC97_MIC_ADC_Rate);
443 open_voice (s, MC_INDEX, freq);
444 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
445 }
446
447 static void get_volume (uint16_t vol, uint16_t mask, int inverse,
448 int *mute, uint8_t *lvol, uint8_t *rvol)
449 {
450 *mute = (vol >> MUTE_SHIFT) & 1;
451 *rvol = (255 * (vol & mask)) / mask;
452 *lvol = (255 * ((vol >> 8) & mask)) / mask;
453
454 if (inverse) {
455 *rvol = 255 - *rvol;
456 *lvol = 255 - *lvol;
457 }
458 }
459
460 static void update_combined_volume_out (AC97LinkState *s)
461 {
462 uint8_t lvol, rvol, plvol, prvol;
463 int mute, pmute;
464
465 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1,
466 &mute, &lvol, &rvol);
467 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1,
468 &pmute, &plvol, &prvol);
469
470 mute = mute | pmute;
471 lvol = (lvol * plvol) / 255;
472 rvol = (rvol * prvol) / 255;
473
474 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
475 }
476
477 static void update_volume_in (AC97LinkState *s)
478 {
479 uint8_t lvol, rvol;
480 int mute;
481
482 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0,
483 &mute, &lvol, &rvol);
484
485 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol);
486 }
487
488 static void set_volume (AC97LinkState *s, int index, uint32_t val)
489 {
490 switch (index) {
491 case AC97_Master_Volume_Mute:
492 val &= 0xbf3f;
493 mixer_store (s, index, val);
494 update_combined_volume_out (s);
495 break;
496 case AC97_PCM_Out_Volume_Mute:
497 val &= 0x9f1f;
498 mixer_store (s, index, val);
499 update_combined_volume_out (s);
500 break;
501 case AC97_Record_Gain_Mute:
502 val &= 0x8f0f;
503 mixer_store (s, index, val);
504 update_volume_in (s);
505 break;
506 }
507 }
508
509 static void record_select (AC97LinkState *s, uint32_t val)
510 {
511 uint8_t rs = val & REC_MASK;
512 uint8_t ls = (val >> 8) & REC_MASK;
513 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
514 }
515
516 static void mixer_reset (AC97LinkState *s)
517 {
518 uint8_t active[LAST_INDEX];
519
520 dolog ("mixer_reset\n");
521 memset (s->mixer_data, 0, sizeof (s->mixer_data));
522 memset (active, 0, sizeof (active));
523 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
524 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000);
525 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000);
526 mixer_store (s, AC97_Master_Tone_RL, 0x0000);
527 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
528 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000);
529 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000);
530 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000);
531 mixer_store (s, AC97_CD_Volume_Mute , 0x0000);
532 mixer_store (s, AC97_Video_Volume_Mute , 0x0000);
533 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000);
534 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000);
535 mixer_store (s, AC97_General_Purpose , 0x0000);
536 mixer_store (s, AC97_3D_Control , 0x0000);
537 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
538
539 /*
540 * Sigmatel 9700 (STAC9700)
541 */
542 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
543 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
544
545 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
546 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
547 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
548 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
549 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
550 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
551 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
552
553 record_select (s, 0);
554 set_volume (s, AC97_Master_Volume_Mute, 0x8000);
555 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
556 set_volume (s, AC97_Record_Gain_Mute, 0x8808);
557
558 reset_voices (s, active);
559 }
560
561 /**
562 * Native audio mixer
563 * I/O Reads
564 */
565 static uint32_t nam_readb (void *opaque, uint32_t addr)
566 {
567 AC97LinkState *s = opaque;
568 dolog ("U nam readb %#x\n", addr);
569 s->cas = 0;
570 return ~0U;
571 }
572
573 static uint32_t nam_readw (void *opaque, uint32_t addr)
574 {
575 AC97LinkState *s = opaque;
576 uint32_t val = ~0U;
577 uint32_t index = addr;
578 s->cas = 0;
579 val = mixer_load (s, index);
580 return val;
581 }
582
583 static uint32_t nam_readl (void *opaque, uint32_t addr)
584 {
585 AC97LinkState *s = opaque;
586 dolog ("U nam readl %#x\n", addr);
587 s->cas = 0;
588 return ~0U;
589 }
590
591 /**
592 * Native audio mixer
593 * I/O Writes
594 */
595 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
596 {
597 AC97LinkState *s = opaque;
598 dolog ("U nam writeb %#x <- %#x\n", addr, val);
599 s->cas = 0;
600 }
601
602 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
603 {
604 AC97LinkState *s = opaque;
605 uint32_t index = addr;
606 s->cas = 0;
607 switch (index) {
608 case AC97_Reset:
609 mixer_reset (s);
610 break;
611 case AC97_Powerdown_Ctrl_Stat:
612 val &= ~0x800f;
613 val |= mixer_load (s, index) & 0xf;
614 mixer_store (s, index, val);
615 break;
616 case AC97_PCM_Out_Volume_Mute:
617 case AC97_Master_Volume_Mute:
618 case AC97_Record_Gain_Mute:
619 set_volume (s, index, val);
620 break;
621 case AC97_Record_Select:
622 record_select (s, val);
623 break;
624 case AC97_Vendor_ID1:
625 case AC97_Vendor_ID2:
626 dolog ("Attempt to write vendor ID to %#x\n", val);
627 break;
628 case AC97_Extended_Audio_ID:
629 dolog ("Attempt to write extended audio ID to %#x\n", val);
630 break;
631 case AC97_Extended_Audio_Ctrl_Stat:
632 if (!(val & EACS_VRA)) {
633 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
634 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
635 open_voice (s, PI_INDEX, 48000);
636 open_voice (s, PO_INDEX, 48000);
637 }
638 if (!(val & EACS_VRM)) {
639 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
640 open_voice (s, MC_INDEX, 48000);
641 }
642 dolog ("Setting extended audio control to %#x\n", val);
643 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
644 break;
645 case AC97_PCM_Front_DAC_Rate:
646 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
647 mixer_store (s, index, val);
648 dolog ("Set front DAC rate to %d\n", val);
649 open_voice (s, PO_INDEX, val);
650 }
651 else {
652 dolog ("Attempt to set front DAC rate to %d, "
653 "but VRA is not set\n",
654 val);
655 }
656 break;
657 case AC97_MIC_ADC_Rate:
658 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
659 mixer_store (s, index, val);
660 dolog ("Set MIC ADC rate to %d\n", val);
661 open_voice (s, MC_INDEX, val);
662 }
663 else {
664 dolog ("Attempt to set MIC ADC rate to %d, "
665 "but VRM is not set\n",
666 val);
667 }
668 break;
669 case AC97_PCM_LR_ADC_Rate:
670 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
671 mixer_store (s, index, val);
672 dolog ("Set front LR ADC rate to %d\n", val);
673 open_voice (s, PI_INDEX, val);
674 }
675 else {
676 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
677 val);
678 }
679 break;
680 case AC97_Headphone_Volume_Mute:
681 case AC97_Master_Volume_Mono_Mute:
682 case AC97_Master_Tone_RL:
683 case AC97_PC_BEEP_Volume_Mute:
684 case AC97_Phone_Volume_Mute:
685 case AC97_Mic_Volume_Mute:
686 case AC97_Line_In_Volume_Mute:
687 case AC97_CD_Volume_Mute:
688 case AC97_Video_Volume_Mute:
689 case AC97_Aux_Volume_Mute:
690 case AC97_Record_Gain_Mic_Mute:
691 case AC97_General_Purpose:
692 case AC97_3D_Control:
693 case AC97_Sigmatel_Analog:
694 case AC97_Sigmatel_Dac2Invert:
695 /* None of the features in these regs are emulated, so they are RO */
696 break;
697 default:
698 dolog ("U nam writew %#x <- %#x\n", addr, val);
699 mixer_store (s, index, val);
700 break;
701 }
702 }
703
704 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
705 {
706 AC97LinkState *s = opaque;
707 dolog ("U nam writel %#x <- %#x\n", addr, val);
708 s->cas = 0;
709 }
710
711 /**
712 * Native audio bus master
713 * I/O Reads
714 */
715 static uint32_t nabm_readb (void *opaque, uint32_t addr)
716 {
717 AC97LinkState *s = opaque;
718 AC97BusMasterRegs *r = NULL;
719 uint32_t index = addr;
720 uint32_t val = ~0U;
721
722 switch (index) {
723 case CAS:
724 dolog ("CAS %d\n", s->cas);
725 val = s->cas;
726 s->cas = 1;
727 break;
728 case PI_CIV:
729 case PO_CIV:
730 case MC_CIV:
731 r = &s->bm_regs[GET_BM (index)];
732 val = r->civ;
733 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
734 break;
735 case PI_LVI:
736 case PO_LVI:
737 case MC_LVI:
738 r = &s->bm_regs[GET_BM (index)];
739 val = r->lvi;
740 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
741 break;
742 case PI_PIV:
743 case PO_PIV:
744 case MC_PIV:
745 r = &s->bm_regs[GET_BM (index)];
746 val = r->piv;
747 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
748 break;
749 case PI_CR:
750 case PO_CR:
751 case MC_CR:
752 r = &s->bm_regs[GET_BM (index)];
753 val = r->cr;
754 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
755 break;
756 case PI_SR:
757 case PO_SR:
758 case MC_SR:
759 r = &s->bm_regs[GET_BM (index)];
760 val = r->sr & 0xff;
761 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
762 break;
763 default:
764 dolog ("U nabm readb %#x -> %#x\n", addr, val);
765 break;
766 }
767 return val;
768 }
769
770 static uint32_t nabm_readw (void *opaque, uint32_t addr)
771 {
772 AC97LinkState *s = opaque;
773 AC97BusMasterRegs *r = NULL;
774 uint32_t index = addr;
775 uint32_t val = ~0U;
776
777 switch (index) {
778 case PI_SR:
779 case PO_SR:
780 case MC_SR:
781 r = &s->bm_regs[GET_BM (index)];
782 val = r->sr;
783 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
784 break;
785 case PI_PICB:
786 case PO_PICB:
787 case MC_PICB:
788 r = &s->bm_regs[GET_BM (index)];
789 val = r->picb;
790 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
791 break;
792 default:
793 dolog ("U nabm readw %#x -> %#x\n", addr, val);
794 break;
795 }
796 return val;
797 }
798
799 static uint32_t nabm_readl (void *opaque, uint32_t addr)
800 {
801 AC97LinkState *s = opaque;
802 AC97BusMasterRegs *r = NULL;
803 uint32_t index = addr;
804 uint32_t val = ~0U;
805
806 switch (index) {
807 case PI_BDBAR:
808 case PO_BDBAR:
809 case MC_BDBAR:
810 r = &s->bm_regs[GET_BM (index)];
811 val = r->bdbar;
812 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
813 break;
814 case PI_CIV:
815 case PO_CIV:
816 case MC_CIV:
817 r = &s->bm_regs[GET_BM (index)];
818 val = r->civ | (r->lvi << 8) | (r->sr << 16);
819 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
820 r->civ, r->lvi, r->sr);
821 break;
822 case PI_PICB:
823 case PO_PICB:
824 case MC_PICB:
825 r = &s->bm_regs[GET_BM (index)];
826 val = r->picb | (r->piv << 16) | (r->cr << 24);
827 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
828 val, r->picb, r->piv, r->cr);
829 break;
830 case GLOB_CNT:
831 val = s->glob_cnt;
832 dolog ("glob_cnt -> %#x\n", val);
833 break;
834 case GLOB_STA:
835 val = s->glob_sta | GS_S0CR;
836 dolog ("glob_sta -> %#x\n", val);
837 break;
838 default:
839 dolog ("U nabm readl %#x -> %#x\n", addr, val);
840 break;
841 }
842 return val;
843 }
844
845 /**
846 * Native audio bus master
847 * I/O Writes
848 */
849 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
850 {
851 AC97LinkState *s = opaque;
852 AC97BusMasterRegs *r = NULL;
853 uint32_t index = addr;
854 switch (index) {
855 case PI_LVI:
856 case PO_LVI:
857 case MC_LVI:
858 r = &s->bm_regs[GET_BM (index)];
859 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
860 r->sr &= ~(SR_DCH | SR_CELV);
861 r->civ = r->piv;
862 r->piv = (r->piv + 1) % 32;
863 fetch_bd (s, r);
864 }
865 r->lvi = val % 32;
866 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
867 break;
868 case PI_CR:
869 case PO_CR:
870 case MC_CR:
871 r = &s->bm_regs[GET_BM (index)];
872 if (val & CR_RR) {
873 reset_bm_regs (s, r);
874 }
875 else {
876 r->cr = val & CR_VALID_MASK;
877 if (!(r->cr & CR_RPBM)) {
878 voice_set_active (s, r - s->bm_regs, 0);
879 r->sr |= SR_DCH;
880 }
881 else {
882 r->civ = r->piv;
883 r->piv = (r->piv + 1) % 32;
884 fetch_bd (s, r);
885 r->sr &= ~SR_DCH;
886 voice_set_active (s, r - s->bm_regs, 1);
887 }
888 }
889 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
890 break;
891 case PI_SR:
892 case PO_SR:
893 case MC_SR:
894 r = &s->bm_regs[GET_BM (index)];
895 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
896 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
897 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
898 break;
899 default:
900 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
901 break;
902 }
903 }
904
905 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
906 {
907 AC97LinkState *s = opaque;
908 AC97BusMasterRegs *r = NULL;
909 uint32_t index = addr;
910 switch (index) {
911 case PI_SR:
912 case PO_SR:
913 case MC_SR:
914 r = &s->bm_regs[GET_BM (index)];
915 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
916 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
917 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
918 break;
919 default:
920 dolog ("U nabm writew %#x <- %#x\n", addr, val);
921 break;
922 }
923 }
924
925 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
926 {
927 AC97LinkState *s = opaque;
928 AC97BusMasterRegs *r = NULL;
929 uint32_t index = addr;
930 switch (index) {
931 case PI_BDBAR:
932 case PO_BDBAR:
933 case MC_BDBAR:
934 r = &s->bm_regs[GET_BM (index)];
935 r->bdbar = val & ~3;
936 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
937 GET_BM (index), val, r->bdbar);
938 break;
939 case GLOB_CNT:
940 if (val & GC_WR)
941 warm_reset (s);
942 if (val & GC_CR)
943 cold_reset (s);
944 if (!(val & (GC_WR | GC_CR)))
945 s->glob_cnt = val & GC_VALID_MASK;
946 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
947 break;
948 case GLOB_STA:
949 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
950 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
951 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
952 break;
953 default:
954 dolog ("U nabm writel %#x <- %#x\n", addr, val);
955 break;
956 }
957 }
958
959 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
960 int max, int *stop)
961 {
962 uint8_t tmpbuf[4096];
963 uint32_t addr = r->bd.addr;
964 uint32_t temp = r->picb << 1;
965 uint32_t written = 0;
966 int to_copy = 0;
967 temp = MIN (temp, max);
968
969 if (!temp) {
970 *stop = 1;
971 return 0;
972 }
973
974 while (temp) {
975 int copied;
976 to_copy = MIN (temp, sizeof (tmpbuf));
977 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
978 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
979 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
980 max, to_copy, copied);
981 if (!copied) {
982 *stop = 1;
983 break;
984 }
985 temp -= copied;
986 addr += copied;
987 written += copied;
988 }
989
990 if (!temp) {
991 if (to_copy < 4) {
992 dolog ("whoops\n");
993 s->last_samp = 0;
994 }
995 else {
996 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
997 }
998 }
999
1000 r->bd.addr = addr;
1001 return written;
1002 }
1003
1004 static void write_bup (AC97LinkState *s, int elapsed)
1005 {
1006 dolog ("write_bup\n");
1007 if (!(s->bup_flag & BUP_SET)) {
1008 if (s->bup_flag & BUP_LAST) {
1009 int i;
1010 uint8_t *p = s->silence;
1011 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1012 *(uint32_t *) p = s->last_samp;
1013 }
1014 }
1015 else {
1016 memset (s->silence, 0, sizeof (s->silence));
1017 }
1018 s->bup_flag |= BUP_SET;
1019 }
1020
1021 while (elapsed) {
1022 int temp = MIN (elapsed, sizeof (s->silence));
1023 while (temp) {
1024 int copied = AUD_write (s->voice_po, s->silence, temp);
1025 if (!copied)
1026 return;
1027 temp -= copied;
1028 elapsed -= copied;
1029 }
1030 }
1031 }
1032
1033 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1034 int max, int *stop)
1035 {
1036 uint8_t tmpbuf[4096];
1037 uint32_t addr = r->bd.addr;
1038 uint32_t temp = r->picb << 1;
1039 uint32_t nread = 0;
1040 int to_copy = 0;
1041 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1042
1043 temp = MIN (temp, max);
1044
1045 if (!temp) {
1046 *stop = 1;
1047 return 0;
1048 }
1049
1050 while (temp) {
1051 int acquired;
1052 to_copy = MIN (temp, sizeof (tmpbuf));
1053 acquired = AUD_read (voice, tmpbuf, to_copy);
1054 if (!acquired) {
1055 *stop = 1;
1056 break;
1057 }
1058 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1059 temp -= acquired;
1060 addr += acquired;
1061 nread += acquired;
1062 }
1063
1064 r->bd.addr = addr;
1065 return nread;
1066 }
1067
1068 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1069 {
1070 AC97BusMasterRegs *r = &s->bm_regs[index];
1071 int stop = 0;
1072
1073 if (s->invalid_freq[index]) {
1074 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1075 index, s->invalid_freq[index]);
1076 return;
1077 }
1078
1079 if (r->sr & SR_DCH) {
1080 if (r->cr & CR_RPBM) {
1081 switch (index) {
1082 case PO_INDEX:
1083 write_bup (s, elapsed);
1084 break;
1085 }
1086 }
1087 return;
1088 }
1089
1090 while ((elapsed >> 1) && !stop) {
1091 int temp;
1092
1093 if (!r->bd_valid) {
1094 dolog ("invalid bd\n");
1095 fetch_bd (s, r);
1096 }
1097
1098 if (!r->picb) {
1099 dolog ("fresh bd %d is empty %#x %#x\n",
1100 r->civ, r->bd.addr, r->bd.ctl_len);
1101 if (r->civ == r->lvi) {
1102 r->sr |= SR_DCH; /* CELV? */
1103 s->bup_flag = 0;
1104 break;
1105 }
1106 r->sr &= ~SR_CELV;
1107 r->civ = r->piv;
1108 r->piv = (r->piv + 1) % 32;
1109 fetch_bd (s, r);
1110 return;
1111 }
1112
1113 switch (index) {
1114 case PO_INDEX:
1115 temp = write_audio (s, r, elapsed, &stop);
1116 elapsed -= temp;
1117 r->picb -= (temp >> 1);
1118 break;
1119
1120 case PI_INDEX:
1121 case MC_INDEX:
1122 temp = read_audio (s, r, elapsed, &stop);
1123 elapsed -= temp;
1124 r->picb -= (temp >> 1);
1125 break;
1126 }
1127
1128 if (!r->picb) {
1129 uint32_t new_sr = r->sr & ~SR_CELV;
1130
1131 if (r->bd.ctl_len & BD_IOC) {
1132 new_sr |= SR_BCIS;
1133 }
1134
1135 if (r->civ == r->lvi) {
1136 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1137
1138 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1139 stop = 1;
1140 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1141 }
1142 else {
1143 r->civ = r->piv;
1144 r->piv = (r->piv + 1) % 32;
1145 fetch_bd (s, r);
1146 }
1147
1148 update_sr (s, r, new_sr);
1149 }
1150 }
1151 }
1152
1153 static void pi_callback (void *opaque, int avail)
1154 {
1155 transfer_audio (opaque, PI_INDEX, avail);
1156 }
1157
1158 static void mc_callback (void *opaque, int avail)
1159 {
1160 transfer_audio (opaque, MC_INDEX, avail);
1161 }
1162
1163 static void po_callback (void *opaque, int free)
1164 {
1165 transfer_audio (opaque, PO_INDEX, free);
1166 }
1167
1168 static const VMStateDescription vmstate_ac97_bm_regs = {
1169 .name = "ac97_bm_regs",
1170 .version_id = 1,
1171 .minimum_version_id = 1,
1172 .fields = (VMStateField[]) {
1173 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs),
1174 VMSTATE_UINT8 (civ, AC97BusMasterRegs),
1175 VMSTATE_UINT8 (lvi, AC97BusMasterRegs),
1176 VMSTATE_UINT16 (sr, AC97BusMasterRegs),
1177 VMSTATE_UINT16 (picb, AC97BusMasterRegs),
1178 VMSTATE_UINT8 (piv, AC97BusMasterRegs),
1179 VMSTATE_UINT8 (cr, AC97BusMasterRegs),
1180 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs),
1181 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs),
1182 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs),
1183 VMSTATE_END_OF_LIST ()
1184 }
1185 };
1186
1187 static int ac97_post_load (void *opaque, int version_id)
1188 {
1189 uint8_t active[LAST_INDEX];
1190 AC97LinkState *s = opaque;
1191
1192 record_select (s, mixer_load (s, AC97_Record_Select));
1193 set_volume (s, AC97_Master_Volume_Mute,
1194 mixer_load (s, AC97_Master_Volume_Mute));
1195 set_volume (s, AC97_PCM_Out_Volume_Mute,
1196 mixer_load (s, AC97_PCM_Out_Volume_Mute));
1197 set_volume (s, AC97_Record_Gain_Mute,
1198 mixer_load (s, AC97_Record_Gain_Mute));
1199
1200 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1201 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1202 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1203 reset_voices (s, active);
1204
1205 s->bup_flag = 0;
1206 s->last_samp = 0;
1207 return 0;
1208 }
1209
1210 static bool is_version_2 (void *opaque, int version_id)
1211 {
1212 return version_id == 2;
1213 }
1214
1215 static const VMStateDescription vmstate_ac97 = {
1216 .name = "ac97",
1217 .version_id = 3,
1218 .minimum_version_id = 2,
1219 .post_load = ac97_post_load,
1220 .fields = (VMStateField[]) {
1221 VMSTATE_PCI_DEVICE (dev, AC97LinkState),
1222 VMSTATE_UINT32 (glob_cnt, AC97LinkState),
1223 VMSTATE_UINT32 (glob_sta, AC97LinkState),
1224 VMSTATE_UINT32 (cas, AC97LinkState),
1225 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1,
1226 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1227 VMSTATE_BUFFER (mixer_data, AC97LinkState),
1228 VMSTATE_UNUSED_TEST (is_version_2, 3),
1229 VMSTATE_END_OF_LIST ()
1230 }
1231 };
1232
1233 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size)
1234 {
1235 if ((addr / size) > 256) {
1236 return -1;
1237 }
1238
1239 switch (size) {
1240 case 1:
1241 return nam_readb(opaque, addr);
1242 case 2:
1243 return nam_readw(opaque, addr);
1244 case 4:
1245 return nam_readl(opaque, addr);
1246 default:
1247 return -1;
1248 }
1249 }
1250
1251 static void nam_write(void *opaque, hwaddr addr, uint64_t val,
1252 unsigned size)
1253 {
1254 if ((addr / size) > 256) {
1255 return;
1256 }
1257
1258 switch (size) {
1259 case 1:
1260 nam_writeb(opaque, addr, val);
1261 break;
1262 case 2:
1263 nam_writew(opaque, addr, val);
1264 break;
1265 case 4:
1266 nam_writel(opaque, addr, val);
1267 break;
1268 }
1269 }
1270
1271 static const MemoryRegionOps ac97_io_nam_ops = {
1272 .read = nam_read,
1273 .write = nam_write,
1274 .impl = {
1275 .min_access_size = 1,
1276 .max_access_size = 4,
1277 },
1278 .endianness = DEVICE_LITTLE_ENDIAN,
1279 };
1280
1281 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size)
1282 {
1283 if ((addr / size) > 64) {
1284 return -1;
1285 }
1286
1287 switch (size) {
1288 case 1:
1289 return nabm_readb(opaque, addr);
1290 case 2:
1291 return nabm_readw(opaque, addr);
1292 case 4:
1293 return nabm_readl(opaque, addr);
1294 default:
1295 return -1;
1296 }
1297 }
1298
1299 static void nabm_write(void *opaque, hwaddr addr, uint64_t val,
1300 unsigned size)
1301 {
1302 if ((addr / size) > 64) {
1303 return;
1304 }
1305
1306 switch (size) {
1307 case 1:
1308 nabm_writeb(opaque, addr, val);
1309 break;
1310 case 2:
1311 nabm_writew(opaque, addr, val);
1312 break;
1313 case 4:
1314 nabm_writel(opaque, addr, val);
1315 break;
1316 }
1317 }
1318
1319
1320 static const MemoryRegionOps ac97_io_nabm_ops = {
1321 .read = nabm_read,
1322 .write = nabm_write,
1323 .impl = {
1324 .min_access_size = 1,
1325 .max_access_size = 4,
1326 },
1327 .endianness = DEVICE_LITTLE_ENDIAN,
1328 };
1329
1330 static void ac97_on_reset (DeviceState *dev)
1331 {
1332 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
1333
1334 reset_bm_regs (s, &s->bm_regs[0]);
1335 reset_bm_regs (s, &s->bm_regs[1]);
1336 reset_bm_regs (s, &s->bm_regs[2]);
1337
1338 /*
1339 * Reset the mixer too. The Windows XP driver seems to rely on
1340 * this. At least it wants to read the vendor id before it resets
1341 * the codec manually.
1342 */
1343 mixer_reset (s);
1344 }
1345
1346 static void ac97_realize(PCIDevice *dev, Error **errp)
1347 {
1348 AC97LinkState *s = AC97(dev);
1349 uint8_t *c = s->dev.config;
1350
1351 /* TODO: no need to override */
1352 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1353 c[PCI_COMMAND + 1] = 0x00;
1354
1355 /* TODO: */
1356 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1357 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1358
1359 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1360
1361 /* TODO set when bar is registered. no need to override. */
1362 /* nabmar native audio mixer base address rw */
1363 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1364 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1365 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1366 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1367
1368 /* TODO set when bar is registered. no need to override. */
1369 /* nabmbar native audio bus mastering base address rw */
1370 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1371 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1372 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1373 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1374
1375 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1376 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1377
1378 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
1379 "ac97-nam", 1024);
1380 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
1381 "ac97-nabm", 256);
1382 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1383 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1384 AUD_register_card ("ac97", &s->card);
1385 ac97_on_reset(DEVICE(s));
1386 }
1387
1388 static void ac97_exit(PCIDevice *dev)
1389 {
1390 AC97LinkState *s = AC97(dev);
1391
1392 AUD_close_in(&s->card, s->voice_pi);
1393 AUD_close_out(&s->card, s->voice_po);
1394 AUD_close_in(&s->card, s->voice_mc);
1395 AUD_remove_card(&s->card);
1396 }
1397
1398 static int ac97_init (PCIBus *bus)
1399 {
1400 pci_create_simple(bus, -1, TYPE_AC97);
1401 return 0;
1402 }
1403
1404 static Property ac97_properties[] = {
1405 DEFINE_AUDIO_PROPERTIES(AC97LinkState, card),
1406 DEFINE_PROP_END_OF_LIST (),
1407 };
1408
1409 static void ac97_class_init (ObjectClass *klass, void *data)
1410 {
1411 DeviceClass *dc = DEVICE_CLASS (klass);
1412 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
1413
1414 k->realize = ac97_realize;
1415 k->exit = ac97_exit;
1416 k->vendor_id = PCI_VENDOR_ID_INTEL;
1417 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
1418 k->revision = 0x01;
1419 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1420 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1421 dc->desc = "Intel 82801AA AC97 Audio";
1422 dc->vmsd = &vmstate_ac97;
1423 device_class_set_props(dc, ac97_properties);
1424 dc->reset = ac97_on_reset;
1425 }
1426
1427 static const TypeInfo ac97_info = {
1428 .name = TYPE_AC97,
1429 .parent = TYPE_PCI_DEVICE,
1430 .instance_size = sizeof (AC97LinkState),
1431 .class_init = ac97_class_init,
1432 .interfaces = (InterfaceInfo[]) {
1433 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1434 { },
1435 },
1436 };
1437
1438 static void ac97_register_types (void)
1439 {
1440 type_register_static (&ac97_info);
1441 pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init);
1442 }
1443
1444 type_init (ac97_register_types)
AR7 emulation for QEMU