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target/rx: CPU definitions
[qemu/ar7.git] / hw / arm / fsl-imx6.c
blob13f1bf23a6c7246989d0594a2d54e8c462a49873
1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/usb/imx-usb-phy.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 #include "chardev/char.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32
33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
34
35 #define NAME_SIZE 20
36
37 static void fsl_imx6_init(Object *obj)
38 {
39 MachineState *ms = MACHINE(qdev_get_machine());
40 FslIMX6State *s = FSL_IMX6(obj);
41 char name[NAME_SIZE];
42 int i;
43
44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
45 snprintf(name, NAME_SIZE, "cpu%d", i);
46 object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
47 ARM_CPU_TYPE_NAME("cortex-a9"),
48 &error_abort, NULL);
49 }
50
51 sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
52 TYPE_A9MPCORE_PRIV);
53
54 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
55
56 sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
57
58 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
59 snprintf(name, NAME_SIZE, "uart%d", i + 1);
60 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
61 TYPE_IMX_SERIAL);
62 }
63
64 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
65
66 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
67 snprintf(name, NAME_SIZE, "epit%d", i + 1);
68 sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
69 TYPE_IMX_EPIT);
70 }
71
72 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
73 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
74 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
75 TYPE_IMX_I2C);
76 }
77
78 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
79 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
80 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
81 TYPE_IMX_GPIO);
82 }
83
84 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
85 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
86 sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]),
87 TYPE_IMX_USDHC);
88 }
89
90 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
91 snprintf(name, NAME_SIZE, "usbphy%d", i);
92 sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
93 TYPE_IMX_USBPHY);
94 }
95 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
96 snprintf(name, NAME_SIZE, "usb%d", i);
97 sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
98 TYPE_CHIPIDEA);
99 }
100
101 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
102 snprintf(name, NAME_SIZE, "spi%d", i + 1);
103 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
104 TYPE_IMX_SPI);
105 }
106 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
107 snprintf(name, NAME_SIZE, "wdt%d", i);
108 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
109 TYPE_IMX2_WDT);
110 }
111
112
113 sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET);
114 }
115
116 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
117 {
118 MachineState *ms = MACHINE(qdev_get_machine());
119 FslIMX6State *s = FSL_IMX6(dev);
120 uint16_t i;
121 Error *err = NULL;
122 unsigned int smp_cpus = ms->smp.cpus;
123
124 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
125 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
126 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
127 return;
128 }
129
130 for (i = 0; i < smp_cpus; i++) {
131
132 /* On uniprocessor, the CBAR is set to 0 */
133 if (smp_cpus > 1) {
134 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
135 "reset-cbar", &error_abort);
136 }
137
138 /* All CPU but CPU 0 start in power off mode */
139 if (i) {
140 object_property_set_bool(OBJECT(&s->cpu[i]), true,
141 "start-powered-off", &error_abort);
142 }
143
144 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
145 if (err) {
146 error_propagate(errp, err);
147 return;
148 }
149 }
150
151 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
152 &error_abort);
153
154 object_property_set_int(OBJECT(&s->a9mpcore),
155 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
156 &error_abort);
157
158 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
159 if (err) {
160 error_propagate(errp, err);
161 return;
162 }
163 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
164
165 for (i = 0; i < smp_cpus; i++) {
166 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
167 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
168 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
169 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
170 }
171
172 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
173 if (err) {
174 error_propagate(errp, err);
175 return;
176 }
177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
178
179 object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
180 if (err) {
181 error_propagate(errp, err);
182 return;
183 }
184 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
185
186 /* Initialize all UARTs */
187 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
188 static const struct {
189 hwaddr addr;
190 unsigned int irq;
191 } serial_table[FSL_IMX6_NUM_UARTS] = {
192 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
193 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
194 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
195 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
196 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
197 };
198
199 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
200
201 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
202 if (err) {
203 error_propagate(errp, err);
204 return;
205 }
206
207 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
208 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
209 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
210 serial_table[i].irq));
211 }
212
213 s->gpt.ccm = IMX_CCM(&s->ccm);
214
215 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
216 if (err) {
217 error_propagate(errp, err);
218 return;
219 }
220
221 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
222 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
223 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
224 FSL_IMX6_GPT_IRQ));
225
226 /* Initialize all EPIT timers */
227 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
228 static const struct {
229 hwaddr addr;
230 unsigned int irq;
231 } epit_table[FSL_IMX6_NUM_EPITS] = {
232 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
233 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
234 };
235
236 s->epit[i].ccm = IMX_CCM(&s->ccm);
237
238 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
239 if (err) {
240 error_propagate(errp, err);
241 return;
242 }
243
244 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
245 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
246 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
247 epit_table[i].irq));
248 }
249
250 /* Initialize all I2C */
251 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
252 static const struct {
253 hwaddr addr;
254 unsigned int irq;
255 } i2c_table[FSL_IMX6_NUM_I2CS] = {
256 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
257 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
258 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
259 };
260
261 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
262 if (err) {
263 error_propagate(errp, err);
264 return;
265 }
266
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
268 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
269 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
270 i2c_table[i].irq));
271 }
272
273 /* Initialize all GPIOs */
274 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
275 static const struct {
276 hwaddr addr;
277 unsigned int irq_low;
278 unsigned int irq_high;
279 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
280 {
281 FSL_IMX6_GPIO1_ADDR,
282 FSL_IMX6_GPIO1_LOW_IRQ,
283 FSL_IMX6_GPIO1_HIGH_IRQ
284 },
285 {
286 FSL_IMX6_GPIO2_ADDR,
287 FSL_IMX6_GPIO2_LOW_IRQ,
288 FSL_IMX6_GPIO2_HIGH_IRQ
289 },
290 {
291 FSL_IMX6_GPIO3_ADDR,
292 FSL_IMX6_GPIO3_LOW_IRQ,
293 FSL_IMX6_GPIO3_HIGH_IRQ
294 },
295 {
296 FSL_IMX6_GPIO4_ADDR,
297 FSL_IMX6_GPIO4_LOW_IRQ,
298 FSL_IMX6_GPIO4_HIGH_IRQ
299 },
300 {
301 FSL_IMX6_GPIO5_ADDR,
302 FSL_IMX6_GPIO5_LOW_IRQ,
303 FSL_IMX6_GPIO5_HIGH_IRQ
304 },
305 {
306 FSL_IMX6_GPIO6_ADDR,
307 FSL_IMX6_GPIO6_LOW_IRQ,
308 FSL_IMX6_GPIO6_HIGH_IRQ
309 },
310 {
311 FSL_IMX6_GPIO7_ADDR,
312 FSL_IMX6_GPIO7_LOW_IRQ,
313 FSL_IMX6_GPIO7_HIGH_IRQ
314 },
315 };
316
317 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
318 &error_abort);
319 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
320 &error_abort);
321 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
322 if (err) {
323 error_propagate(errp, err);
324 return;
325 }
326
327 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
329 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
330 gpio_table[i].irq_low));
331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
332 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
333 gpio_table[i].irq_high));
334 }
335
336 /* Initialize all SDHC */
337 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
338 static const struct {
339 hwaddr addr;
340 unsigned int irq;
341 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
342 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
343 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
344 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
345 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
346 };
347
348 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
349 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
350 &err);
351 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
352 "capareg", &err);
353 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
354 if (err) {
355 error_propagate(errp, err);
356 return;
357 }
358 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
359 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
360 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
361 esdhc_table[i].irq));
362 }
363
364 /* USB */
365 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
366 object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
367 &error_abort);
368 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
369 FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
370 }
371 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
372 static const int FSL_IMX6_USBn_IRQ[] = {
373 FSL_IMX6_USB_OTG_IRQ,
374 FSL_IMX6_USB_HOST1_IRQ,
375 FSL_IMX6_USB_HOST2_IRQ,
376 FSL_IMX6_USB_HOST3_IRQ,
377 };
378
379 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
380 &error_abort);
381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
382 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
384 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
385 FSL_IMX6_USBn_IRQ[i]));
386 }
387
388 /* Initialize all ECSPI */
389 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
390 static const struct {
391 hwaddr addr;
392 unsigned int irq;
393 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
394 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
395 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
396 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
397 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
398 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
399 };
400
401 /* Initialize the SPI */
402 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
403 if (err) {
404 error_propagate(errp, err);
405 return;
406 }
407
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
409 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
410 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
411 spi_table[i].irq));
412 }
413
414 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
415 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
416 if (err) {
417 error_propagate(errp, err);
418 return;
419 }
420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
422 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
423 FSL_IMX6_ENET_MAC_IRQ));
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
425 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
426 FSL_IMX6_ENET_MAC_1588_IRQ));
427
428 /*
429 * Watchdog
430 */
431 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
432 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
433 FSL_IMX6_WDOG1_ADDR,
434 FSL_IMX6_WDOG2_ADDR,
435 };
436
437 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
438 &error_abort);
439
440 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
441 }
442
443 /* ROM memory */
444 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
445 FSL_IMX6_ROM_SIZE, &err);
446 if (err) {
447 error_propagate(errp, err);
448 return;
449 }
450 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
451 &s->rom);
452
453 /* CAAM memory */
454 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
455 FSL_IMX6_CAAM_MEM_SIZE, &err);
456 if (err) {
457 error_propagate(errp, err);
458 return;
459 }
460 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
461 &s->caam);
462
463 /* OCRAM memory */
464 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
465 &err);
466 if (err) {
467 error_propagate(errp, err);
468 return;
469 }
470 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
471 &s->ocram);
472
473 /* internal OCRAM (256 KB) is aliased over 1 MB */
474 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
475 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
476 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
477 &s->ocram_alias);
478 }
479
480 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
481 {
482 DeviceClass *dc = DEVICE_CLASS(oc);
483
484 dc->realize = fsl_imx6_realize;
485 dc->desc = "i.MX6 SOC";
486 /* Reason: Uses serial_hd() in the realize() function */
487 dc->user_creatable = false;
488 }
489
490 static const TypeInfo fsl_imx6_type_info = {
491 .name = TYPE_FSL_IMX6,
492 .parent = TYPE_DEVICE,
493 .instance_size = sizeof(FslIMX6State),
494 .instance_init = fsl_imx6_init,
495 .class_init = fsl_imx6_class_init,
496 };
497
498 static void fsl_imx6_register_types(void)
499 {
500 type_register_static(&fsl_imx6_type_info);
501 }
502
503 type_init(fsl_imx6_register_types)
AR7 emulation for QEMU