2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_cpu_core.h"
16 #include "hw/ppc/spapr_xive.h"
17 #include "hw/ppc/xics.h"
18 #include "hw/ppc/xics_spapr.h"
19 #include "cpu-models.h"
20 #include "sysemu/kvm.h"
24 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
26 spapr
->irq_map_nr
= nr_msis
;
27 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
30 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
36 * The 'align_mask' parameter of bitmap_find_next_zero_area()
37 * should be one less than a power of 2; 0 means no
38 * alignment. Adapt the 'align' value of the former allocator
39 * to fit the requirements of bitmap_find_next_zero_area()
43 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
45 if (irq
== spapr
->irq_map_nr
) {
46 error_setg(errp
, "can't find a free %d-IRQ block", num
);
50 bitmap_set(spapr
->irq_map
, irq
, num
);
52 return irq
+ SPAPR_IRQ_MSI
;
55 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
57 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
60 void spapr_irq_msi_reset(SpaprMachineState
*spapr
)
62 bitmap_clear(spapr
->irq_map
, 0, spapr
->irq_map_nr
);
70 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, int nr_irqs
,
73 MachineState
*machine
= MACHINE(spapr
);
75 Error
*local_err
= NULL
;
76 bool xics_kvm
= false;
79 if (machine_kernel_irqchip_allowed(machine
) &&
80 !xics_kvm_init(spapr
, &local_err
)) {
83 if (machine_kernel_irqchip_required(machine
) && !xics_kvm
) {
84 error_prepend(&local_err
,
85 "kernel_irqchip requested but unavailable: ");
86 error_propagate(errp
, local_err
);
89 error_free(local_err
);
94 xics_spapr_init(spapr
);
97 obj
= object_new(TYPE_ICS_SIMPLE
);
98 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
99 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
101 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &error_fatal
);
102 object_property_set_bool(obj
, true, "realized", &local_err
);
104 error_propagate(errp
, local_err
);
108 spapr
->ics
= ICS_BASE(obj
);
111 #define ICS_IRQ_FREE(ics, srcno) \
112 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
114 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
117 ICSState
*ics
= spapr
->ics
;
121 if (!ics_valid_irq(ics
, irq
)) {
122 error_setg(errp
, "IRQ %d is invalid", irq
);
126 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
127 error_setg(errp
, "IRQ %d is not free", irq
);
131 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
135 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
137 ICSState
*ics
= spapr
->ics
;
138 uint32_t srcno
= irq
- ics
->offset
;
141 if (ics_valid_irq(ics
, irq
)) {
142 trace_spapr_irq_free(0, irq
, num
);
143 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
144 if (ICS_IRQ_FREE(ics
, i
)) {
145 trace_spapr_irq_free_warn(0, i
);
147 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
152 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
154 ICSState
*ics
= spapr
->ics
;
155 uint32_t srcno
= irq
- ics
->offset
;
157 if (ics_valid_irq(ics
, irq
)) {
158 return spapr
->qirqs
[srcno
];
164 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
169 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
171 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
174 ics_pic_print_info(spapr
->ics
, mon
);
177 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
178 PowerPCCPU
*cpu
, Error
**errp
)
180 Error
*local_err
= NULL
;
182 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
184 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
187 error_propagate(errp
, local_err
);
191 spapr_cpu
->icp
= ICP(obj
);
194 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
196 if (!kvm_irqchip_in_kernel()) {
199 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
200 icp_resend(spapr_cpu_state(cpu
)->icp
);
206 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
208 SpaprMachineState
*spapr
= opaque
;
210 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
213 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
215 /* TODO: create the KVM XICS device */
218 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
220 return XICS_NODENAME
;
223 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
224 #define SPAPR_IRQ_XICS_NR_MSIS \
225 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
227 SpaprIrq spapr_irq_xics
= {
228 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
229 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
230 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
232 .init
= spapr_irq_init_xics
,
233 .claim
= spapr_irq_claim_xics
,
234 .free
= spapr_irq_free_xics
,
235 .qirq
= spapr_qirq_xics
,
236 .print_info
= spapr_irq_print_info_xics
,
237 .dt_populate
= spapr_dt_xics
,
238 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
239 .post_load
= spapr_irq_post_load_xics
,
240 .reset
= spapr_irq_reset_xics
,
241 .set_irq
= spapr_irq_set_irq_xics
,
242 .get_nodename
= spapr_irq_get_nodename_xics
,
248 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, int nr_irqs
,
251 MachineState
*machine
= MACHINE(spapr
);
252 uint32_t nr_servers
= spapr_max_server_number(spapr
);
256 /* KVM XIVE device not yet available */
258 if (machine_kernel_irqchip_required(machine
)) {
259 error_setg(errp
, "kernel_irqchip requested. no KVM XIVE support");
264 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
265 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
267 * 8 XIVE END structures per CPU. One for each available priority
269 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
270 qdev_init_nofail(dev
);
272 spapr
->xive
= SPAPR_XIVE(dev
);
274 /* Enable the CPU IPIs */
275 for (i
= 0; i
< nr_servers
; ++i
) {
276 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
279 spapr_xive_hcall_init(spapr
);
282 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
285 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
286 error_setg(errp
, "IRQ %d is invalid", irq
);
292 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
296 for (i
= irq
; i
< irq
+ num
; ++i
) {
297 spapr_xive_irq_free(spapr
->xive
, i
);
301 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
303 SpaprXive
*xive
= spapr
->xive
;
305 if (irq
>= xive
->nr_irqs
) {
309 /* The sPAPR machine/device should have claimed the IRQ before */
310 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
312 return spapr
->qirqs
[irq
];
315 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
321 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
323 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
326 spapr_xive_pic_print_info(spapr
->xive
, mon
);
329 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
330 PowerPCCPU
*cpu
, Error
**errp
)
332 Error
*local_err
= NULL
;
334 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
336 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
338 error_propagate(errp
, local_err
);
342 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
345 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
346 * don't beneficiate from the reset of the XIVE IRQ backend
348 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
351 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
353 return spapr_xive_post_load(spapr
->xive
, version_id
);
356 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
361 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
363 /* (TCG) Set the OS CAM line of the thread interrupt context. */
364 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
367 /* Activate the XIVE MMIOs */
368 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
371 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
373 SpaprMachineState
*spapr
= opaque
;
375 if (kvm_irqchip_in_kernel()) {
376 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
378 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
382 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
384 return spapr
->xive
->nodename
;
388 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
392 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
393 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
395 SpaprIrq spapr_irq_xive
= {
396 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
397 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
398 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
400 .init
= spapr_irq_init_xive
,
401 .claim
= spapr_irq_claim_xive
,
402 .free
= spapr_irq_free_xive
,
403 .qirq
= spapr_qirq_xive
,
404 .print_info
= spapr_irq_print_info_xive
,
405 .dt_populate
= spapr_dt_xive
,
406 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
407 .post_load
= spapr_irq_post_load_xive
,
408 .reset
= spapr_irq_reset_xive
,
409 .set_irq
= spapr_irq_set_irq_xive
,
410 .get_nodename
= spapr_irq_get_nodename_xive
,
414 * Dual XIVE and XICS IRQ backend.
416 * Both interrupt mode, XIVE and XICS, objects are created but the
417 * machine starts in legacy interrupt mode (XICS). It can be changed
418 * by the CAS negotiation process and, in that case, the new mode is
419 * activated after an extra machine reset.
423 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
426 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
428 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
429 &spapr_irq_xive
: &spapr_irq_xics
;
432 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, int nr_irqs
,
435 MachineState
*machine
= MACHINE(spapr
);
436 Error
*local_err
= NULL
;
438 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
439 error_setg(errp
, "No KVM support for the 'dual' machine");
443 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
445 error_propagate(errp
, local_err
);
449 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
451 error_propagate(errp
, local_err
);
456 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
459 Error
*local_err
= NULL
;
462 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
464 error_propagate(errp
, local_err
);
468 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
470 error_propagate(errp
, local_err
);
477 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
479 spapr_irq_xics
.free(spapr
, irq
, num
);
480 spapr_irq_xive
.free(spapr
, irq
, num
);
483 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
485 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
488 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
490 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
493 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
494 uint32_t nr_servers
, void *fdt
,
497 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
500 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
501 PowerPCCPU
*cpu
, Error
**errp
)
503 Error
*local_err
= NULL
;
505 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
507 error_propagate(errp
, local_err
);
511 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
514 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
517 * Force a reset of the XIVE backend after migration. The machine
518 * defaults to XICS at startup.
520 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
521 spapr_irq_xive
.reset(spapr
, &error_fatal
);
524 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
527 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
530 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
533 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
535 spapr_irq_current(spapr
)->reset(spapr
, errp
);
538 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
540 SpaprMachineState
*spapr
= opaque
;
542 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
545 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
547 return spapr_irq_current(spapr
)->get_nodename(spapr
);
551 * Define values in sync with the XIVE and XICS backend
553 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
554 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
556 SpaprIrq spapr_irq_dual
= {
557 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
558 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
559 .ov5
= SPAPR_OV5_XIVE_BOTH
,
561 .init
= spapr_irq_init_dual
,
562 .claim
= spapr_irq_claim_dual
,
563 .free
= spapr_irq_free_dual
,
564 .qirq
= spapr_qirq_dual
,
565 .print_info
= spapr_irq_print_info_dual
,
566 .dt_populate
= spapr_irq_dt_populate_dual
,
567 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
568 .post_load
= spapr_irq_post_load_dual
,
569 .reset
= spapr_irq_reset_dual
,
570 .set_irq
= spapr_irq_set_irq_dual
,
571 .get_nodename
= spapr_irq_get_nodename_dual
,
575 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
577 MachineState
*machine
= MACHINE(spapr
);
580 * Sanity checks on non-P9 machines. On these, XIVE is not
581 * advertised, see spapr_dt_ov5_platform_support()
583 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
584 0, spapr
->max_compat_pvr
)) {
586 * If the 'dual' interrupt mode is selected, force XICS as CAS
587 * negotiation is useless.
589 if (spapr
->irq
== &spapr_irq_dual
) {
590 spapr
->irq
= &spapr_irq_xics
;
595 * Non-P9 machines using only XIVE is a bogus setup. We have two
596 * scenarios to take into account because of the compat mode:
598 * 1. POWER7/8 machines should fail to init later on when creating
599 * the XIVE interrupt presenters because a POWER9 exception
602 * 2. POWER9 machines using the POWER8 compat mode won't fail and
603 * will let the OS boot with a partial XIVE setup : DT
604 * properties but no hcalls.
606 * To cover both and not confuse the OS, add an early failure in
609 if (spapr
->irq
== &spapr_irq_xive
) {
610 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
617 * sPAPR IRQ frontend routines for devices
619 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
621 MachineState
*machine
= MACHINE(spapr
);
622 Error
*local_err
= NULL
;
624 if (machine_kernel_irqchip_split(machine
)) {
625 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
629 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
631 "kernel_irqchip requested but only available with KVM");
635 spapr_irq_check(spapr
, &local_err
);
637 error_propagate(errp
, local_err
);
641 /* Initialize the MSI IRQ allocator. */
642 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
643 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
646 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
648 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
649 spapr
->irq
->nr_irqs
);
652 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
654 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
657 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
659 spapr
->irq
->free(spapr
, irq
, num
);
662 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
664 return spapr
->irq
->qirq(spapr
, irq
);
667 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
669 return spapr
->irq
->post_load(spapr
, version_id
);
672 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
674 if (spapr
->irq
->reset
) {
675 spapr
->irq
->reset(spapr
, errp
);
679 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
681 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
684 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
686 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
687 fdt_strerror(offset
));
691 phandle
= fdt_get_phandle(fdt
, offset
);
693 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
701 * XICS legacy routines - to deprecate one day
704 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
708 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
709 if (num
> (ics
->nr_irqs
- first
)) {
712 for (i
= first
; i
< first
+ num
; ++i
) {
713 if (!ICS_IRQ_FREE(ics
, i
)) {
717 if (i
== (first
+ num
)) {
725 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
727 ICSState
*ics
= spapr
->ics
;
733 * MSIMesage::data is used for storing VIRQ so
734 * it has to be aligned to num to support multiple
735 * MSI vectors. MSI-X is not affected by this.
736 * The hint is used for the first IRQ, the rest should
737 * be allocated continuously.
740 assert((num
== 1) || (num
== 2) || (num
== 4) ||
741 (num
== 8) || (num
== 16) || (num
== 32));
742 first
= ics_find_free_block(ics
, num
, num
);
744 first
= ics_find_free_block(ics
, num
, 1);
748 error_setg(errp
, "can't find a free %d-IRQ block", num
);
752 return first
+ ics
->offset
;
755 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
757 SpaprIrq spapr_irq_xics_legacy
= {
758 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
759 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
760 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
762 .init
= spapr_irq_init_xics
,
763 .claim
= spapr_irq_claim_xics
,
764 .free
= spapr_irq_free_xics
,
765 .qirq
= spapr_qirq_xics
,
766 .print_info
= spapr_irq_print_info_xics
,
767 .dt_populate
= spapr_dt_xics
,
768 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
769 .post_load
= spapr_irq_post_load_xics
,
770 .set_irq
= spapr_irq_set_irq_xics
,
771 .get_nodename
= spapr_irq_get_nodename_xics
,