2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "target/ppc/cpu.h"
14 #include "sysemu/cpus.h"
15 #include "sysemu/dma.h"
16 #include "hw/qdev-properties.h"
17 #include "monitor/monitor.h"
18 #include "hw/ppc/xive.h"
19 #include "hw/ppc/xive_regs.h"
22 * XIVE Thread Interrupt Management context
26 * Convert a priority number to an Interrupt Pending Buffer (IPB)
27 * register, which indicates a pending interrupt at the priority
28 * corresponding to the bit number
30 static uint8_t priority_to_ipb(uint8_t priority
)
32 return priority
> XIVE_PRIORITY_MAX
?
33 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
37 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
38 * Interrupt Priority Register (PIPR), which contains the priority of
39 * the most favored pending notification.
41 static uint8_t ipb_to_pipr(uint8_t ibp
)
43 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
46 static void ipb_update(uint8_t *regs
, uint8_t priority
)
48 regs
[TM_IPB
] |= priority_to_ipb(priority
);
49 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
52 static uint8_t exception_mask(uint8_t ring
)
60 g_assert_not_reached();
64 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
66 uint8_t *regs
= &tctx
->regs
[ring
];
67 uint8_t nsr
= regs
[TM_NSR
];
68 uint8_t mask
= exception_mask(ring
);
70 qemu_irq_lower(tctx
->output
);
72 if (regs
[TM_NSR
] & mask
) {
73 uint8_t cppr
= regs
[TM_PIPR
];
77 /* Reset the pending buffer bit */
78 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
79 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
81 /* Drop Exception bit */
82 regs
[TM_NSR
] &= ~mask
;
85 return (nsr
<< 8) | regs
[TM_CPPR
];
88 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
90 uint8_t *regs
= &tctx
->regs
[ring
];
92 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
95 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
98 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
101 g_assert_not_reached();
103 qemu_irq_raise(tctx
->output
);
107 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
109 if (cppr
> XIVE_PRIORITY_MAX
) {
113 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
115 /* CPPR has changed, check if we need to raise a pending exception */
116 xive_tctx_notify(tctx
, ring
);
120 * XIVE Thread Interrupt Management Area (TIMA)
123 static void xive_tm_set_hv_cppr(XiveTCTX
*tctx
, hwaddr offset
,
124 uint64_t value
, unsigned size
)
126 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
129 static uint64_t xive_tm_ack_hv_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
131 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
134 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX
*tctx
, hwaddr offset
,
139 ret
= tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] & TM_QW2W2_POOL_CAM
;
140 tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] &= ~TM_QW2W2_POOL_CAM
;
144 static void xive_tm_vt_push(XiveTCTX
*tctx
, hwaddr offset
,
145 uint64_t value
, unsigned size
)
147 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
150 static uint64_t xive_tm_vt_poll(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
152 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
156 * Define an access map for each page of the TIMA that we will use in
157 * the memory region ops to filter values when doing loads and stores
158 * of raw registers values
160 * Registers accessibility bits :
168 static const uint8_t xive_tm_hw_view
[] = {
169 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
170 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
171 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
172 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0,
175 static const uint8_t xive_tm_hv_view
[] = {
176 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
177 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
178 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0,
179 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0,
182 static const uint8_t xive_tm_os_view
[] = {
183 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
184 /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
185 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
186 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
189 static const uint8_t xive_tm_user_view
[] = {
190 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
191 /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
193 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
197 * Overall TIMA access map for the thread interrupt management context
200 static const uint8_t *xive_tm_views
[] = {
201 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
202 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
203 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
204 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
208 * Computes a register access mask for a given offset in the TIMA
210 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
212 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
213 uint8_t reg_offset
= offset
& 0x3F;
214 uint8_t reg_mask
= write
? 0x1 : 0x2;
218 for (i
= 0; i
< size
; i
++) {
219 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
220 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
227 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
230 uint8_t ring_offset
= offset
& 0x30;
231 uint8_t reg_offset
= offset
& 0x3F;
232 uint64_t mask
= xive_tm_mask(offset
, size
, true);
236 * Only 4 or 8 bytes stores are allowed and the User ring is
239 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
240 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
241 HWADDR_PRIx
"\n", offset
);
246 * Use the register offset for the raw values and filter out
249 for (i
= 0; i
< size
; i
++) {
250 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
252 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
258 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
260 uint8_t ring_offset
= offset
& 0x30;
261 uint8_t reg_offset
= offset
& 0x3F;
262 uint64_t mask
= xive_tm_mask(offset
, size
, false);
267 * Only 4 or 8 bytes loads are allowed and the User ring is
270 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
271 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
272 HWADDR_PRIx
"\n", offset
);
276 /* Use the register offset for the raw values */
278 for (i
= 0; i
< size
; i
++) {
279 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
282 /* filter out reserved values */
287 * The TM context is mapped twice within each page. Stores and loads
288 * to the first mapping below 2K write and read the specified values
289 * without modification. The second mapping above 2K performs specific
290 * state changes (side effects) in addition to setting/returning the
291 * interrupt management area context of the processor thread.
293 static uint64_t xive_tm_ack_os_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
295 return xive_tctx_accept(tctx
, TM_QW1_OS
);
298 static void xive_tm_set_os_cppr(XiveTCTX
*tctx
, hwaddr offset
,
299 uint64_t value
, unsigned size
)
301 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
305 * Adjust the IPB to allow a CPU to process event queues of other
306 * priorities during one physical interrupt cycle.
308 static void xive_tm_set_os_pending(XiveTCTX
*tctx
, hwaddr offset
,
309 uint64_t value
, unsigned size
)
311 ipb_update(&tctx
->regs
[TM_QW1_OS
], value
& 0xff);
312 xive_tctx_notify(tctx
, TM_QW1_OS
);
316 * Define a mapping of "special" operations depending on the TIMA page
317 * offset and the size of the operation.
319 typedef struct XiveTmOp
{
323 void (*write_handler
)(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
325 uint64_t (*read_handler
)(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
328 static const XiveTmOp xive_tm_operations
[] = {
330 * MMIOs below 2K : raw values and special operations without side
333 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
334 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
335 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
336 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
338 /* MMIOs above 2K : special operations with side effects */
339 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
340 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
341 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
342 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
343 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
346 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
348 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
349 uint32_t op_offset
= offset
& 0xFFF;
352 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
353 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
355 /* Accesses done from a more privileged TIMA page is allowed */
356 if (xto
->page_offset
>= page_offset
&&
357 xto
->op_offset
== op_offset
&&
359 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
369 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
375 * TODO: check V bit in Q[0-3]W2
379 * First, check for special operations in the 2K region
381 if (offset
& 0x800) {
382 xto
= xive_tm_find_op(offset
, size
, true);
384 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA"
385 "@%"HWADDR_PRIx
"\n", offset
);
387 xto
->write_handler(tctx
, offset
, value
, size
);
393 * Then, for special operations in the region below 2K.
395 xto
= xive_tm_find_op(offset
, size
, true);
397 xto
->write_handler(tctx
, offset
, value
, size
);
402 * Finish with raw access to the register values
404 xive_tm_raw_write(tctx
, offset
, value
, size
);
407 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
412 * TODO: check V bit in Q[0-3]W2
416 * First, check for special operations in the 2K region
418 if (offset
& 0x800) {
419 xto
= xive_tm_find_op(offset
, size
, false);
421 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
422 "@%"HWADDR_PRIx
"\n", offset
);
425 return xto
->read_handler(tctx
, offset
, size
);
429 * Then, for special operations in the region below 2K.
431 xto
= xive_tm_find_op(offset
, size
, false);
433 return xto
->read_handler(tctx
, offset
, size
);
437 * Finish with raw access to the register values
439 return xive_tm_raw_read(tctx
, offset
, size
);
442 static void xive_tm_write(void *opaque
, hwaddr offset
,
443 uint64_t value
, unsigned size
)
445 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
447 xive_tctx_tm_write(tctx
, offset
, value
, size
);
450 static uint64_t xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
452 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
454 return xive_tctx_tm_read(tctx
, offset
, size
);
457 const MemoryRegionOps xive_tm_ops
= {
458 .read
= xive_tm_read
,
459 .write
= xive_tm_write
,
460 .endianness
= DEVICE_BIG_ENDIAN
,
462 .min_access_size
= 1,
463 .max_access_size
= 8,
466 .min_access_size
= 1,
467 .max_access_size
= 8,
471 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
473 return *((uint32_t *) &ring
[TM_WORD2
]);
476 static char *xive_tctx_ring_print(uint8_t *ring
)
478 uint32_t w2
= xive_tctx_word2(ring
);
480 return g_strdup_printf("%02x %02x %02x %02x %02x "
481 "%02x %02x %02x %08x",
482 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
483 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
487 static const char * const xive_tctx_ring_names
[] = {
488 "USER", "OS", "POOL", "PHYS",
491 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
493 int cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
496 if (kvm_irqchip_in_kernel()) {
497 Error
*local_err
= NULL
;
499 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
501 error_report_err(local_err
);
506 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
509 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
510 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
511 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
512 xive_tctx_ring_names
[i
], s
);
517 static void xive_tctx_reset(void *dev
)
519 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
521 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
523 /* Set some defaults */
524 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
525 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
526 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
529 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
532 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
533 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
534 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
535 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
538 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
540 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
544 Error
*local_err
= NULL
;
546 obj
= object_property_get_link(OBJECT(dev
), "cpu", &local_err
);
548 error_propagate(errp
, local_err
);
549 error_prepend(errp
, "required link 'cpu' not found: ");
553 cpu
= POWERPC_CPU(obj
);
557 switch (PPC_INPUT(env
)) {
558 case PPC_FLAGS_INPUT_POWER9
:
559 tctx
->output
= env
->irq_inputs
[POWER9_INPUT_INT
];
563 error_setg(errp
, "XIVE interrupt controller does not support "
564 "this CPU bus model");
568 /* Connect the presenter to the VCPU (required for CPU hotplug) */
569 if (kvm_irqchip_in_kernel()) {
570 kvmppc_xive_cpu_connect(tctx
, &local_err
);
572 error_propagate(errp
, local_err
);
577 qemu_register_reset(xive_tctx_reset
, dev
);
580 static void xive_tctx_unrealize(DeviceState
*dev
, Error
**errp
)
582 qemu_unregister_reset(xive_tctx_reset
, dev
);
585 static int vmstate_xive_tctx_pre_save(void *opaque
)
587 Error
*local_err
= NULL
;
589 if (kvm_irqchip_in_kernel()) {
590 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque
), &local_err
);
592 error_report_err(local_err
);
600 static const VMStateDescription vmstate_xive_tctx
= {
601 .name
= TYPE_XIVE_TCTX
,
603 .minimum_version_id
= 1,
604 .pre_save
= vmstate_xive_tctx_pre_save
,
605 .post_load
= NULL
, /* handled by the sPAPRxive model */
606 .fields
= (VMStateField
[]) {
607 VMSTATE_BUFFER(regs
, XiveTCTX
),
608 VMSTATE_END_OF_LIST()
612 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
614 DeviceClass
*dc
= DEVICE_CLASS(klass
);
616 dc
->desc
= "XIVE Interrupt Thread Context";
617 dc
->realize
= xive_tctx_realize
;
618 dc
->unrealize
= xive_tctx_unrealize
;
619 dc
->vmsd
= &vmstate_xive_tctx
;
622 static const TypeInfo xive_tctx_info
= {
623 .name
= TYPE_XIVE_TCTX
,
624 .parent
= TYPE_DEVICE
,
625 .instance_size
= sizeof(XiveTCTX
),
626 .class_init
= xive_tctx_class_init
,
629 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
)
631 Error
*local_err
= NULL
;
634 obj
= object_new(TYPE_XIVE_TCTX
);
635 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
, &error_abort
);
637 object_property_add_const_link(obj
, "cpu", cpu
, &error_abort
);
638 object_property_set_bool(obj
, true, "realized", &local_err
);
646 object_unparent(obj
);
647 error_propagate(errp
, local_err
);
655 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
657 uint8_t old_pq
= *pq
& 0x3;
665 static bool xive_esb_trigger(uint8_t *pq
)
667 uint8_t old_pq
= *pq
& 0x3;
671 xive_esb_set(pq
, XIVE_ESB_PENDING
);
673 case XIVE_ESB_PENDING
:
674 case XIVE_ESB_QUEUED
:
675 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
678 xive_esb_set(pq
, XIVE_ESB_OFF
);
681 g_assert_not_reached();
685 static bool xive_esb_eoi(uint8_t *pq
)
687 uint8_t old_pq
= *pq
& 0x3;
691 case XIVE_ESB_PENDING
:
692 xive_esb_set(pq
, XIVE_ESB_RESET
);
694 case XIVE_ESB_QUEUED
:
695 xive_esb_set(pq
, XIVE_ESB_PENDING
);
698 xive_esb_set(pq
, XIVE_ESB_OFF
);
701 g_assert_not_reached();
706 * XIVE Interrupt Source (or IVSE)
709 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
711 assert(srcno
< xsrc
->nr_irqs
);
713 return xsrc
->status
[srcno
] & 0x3;
716 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
718 assert(srcno
< xsrc
->nr_irqs
);
720 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
724 * Returns whether the event notification should be forwarded.
726 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
728 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
730 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
734 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
742 * Returns whether the event notification should be forwarded.
744 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
748 assert(srcno
< xsrc
->nr_irqs
);
750 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
752 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
753 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
754 qemu_log_mask(LOG_GUEST_ERROR
,
755 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
762 * Returns whether the event notification should be forwarded.
764 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
768 assert(srcno
< xsrc
->nr_irqs
);
770 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
773 * LSI sources do not set the Q bit but they can still be
774 * asserted, in which case we should forward a new event
777 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
778 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
779 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
786 * Forward the source event notification to the Router
788 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
790 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
793 xnc
->notify(xsrc
->xive
, srcno
);
798 * In a two pages ESB MMIO setting, even page is the trigger page, odd
799 * page is for management
801 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
803 return !((addr
>> shift
) & 1);
806 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
808 return xive_source_esb_has_2page(xsrc
) &&
809 addr_is_even(addr
, xsrc
->esb_shift
- 1);
814 * Trigger page Management/EOI page
816 * ESB MMIO setting 2 pages 1 or 2 pages
818 * 0x000 .. 0x3FF -1 EOI and return 0|1
819 * 0x400 .. 0x7FF -1 EOI and return 0|1
820 * 0x800 .. 0xBFF -1 return PQ
821 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
822 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
823 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
824 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
826 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
828 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
829 uint32_t offset
= addr
& 0xFFF;
830 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
833 /* In a two pages ESB MMIO setting, trigger page should not be read */
834 if (xive_source_is_trigger_page(xsrc
, addr
)) {
835 qemu_log_mask(LOG_GUEST_ERROR
,
836 "XIVE: invalid load on IRQ %d trigger page at "
837 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
842 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
843 ret
= xive_source_esb_eoi(xsrc
, srcno
);
845 /* Forward the source event notification for routing */
847 xive_source_notify(xsrc
, srcno
);
851 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
852 ret
= xive_source_esb_get(xsrc
, srcno
);
855 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
856 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
857 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
858 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
859 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
862 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
871 * Trigger page Management/EOI page
873 * ESB MMIO setting 2 pages 1 or 2 pages
875 * 0x000 .. 0x3FF Trigger Trigger
876 * 0x400 .. 0x7FF Trigger EOI
877 * 0x800 .. 0xBFF Trigger undefined
878 * 0xC00 .. 0xCFF Trigger PQ=00
879 * 0xD00 .. 0xDFF Trigger PQ=01
880 * 0xE00 .. 0xDFF Trigger PQ=10
881 * 0xF00 .. 0xDFF Trigger PQ=11
883 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
884 uint64_t value
, unsigned size
)
886 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
887 uint32_t offset
= addr
& 0xFFF;
888 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
891 /* In a two pages ESB MMIO setting, trigger page only triggers */
892 if (xive_source_is_trigger_page(xsrc
, addr
)) {
893 notify
= xive_source_esb_trigger(xsrc
, srcno
);
899 notify
= xive_source_esb_trigger(xsrc
, srcno
);
902 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
903 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
904 qemu_log_mask(LOG_GUEST_ERROR
,
905 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
909 notify
= xive_source_esb_eoi(xsrc
, srcno
);
912 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
913 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
914 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
915 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
916 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
920 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
926 /* Forward the source event notification for routing */
928 xive_source_notify(xsrc
, srcno
);
932 static const MemoryRegionOps xive_source_esb_ops
= {
933 .read
= xive_source_esb_read
,
934 .write
= xive_source_esb_write
,
935 .endianness
= DEVICE_BIG_ENDIAN
,
937 .min_access_size
= 8,
938 .max_access_size
= 8,
941 .min_access_size
= 8,
942 .max_access_size
= 8,
946 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
948 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
951 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
953 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
955 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
959 notify
= xive_source_esb_trigger(xsrc
, srcno
);
963 /* Forward the source event notification for routing */
965 xive_source_notify(xsrc
, srcno
);
969 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
973 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
974 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
976 if (pq
== XIVE_ESB_OFF
) {
980 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
981 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
982 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
983 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
984 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
988 static void xive_source_reset(void *dev
)
990 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
992 /* Do not clear the LSI bitmap */
994 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
995 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
997 if (kvm_irqchip_in_kernel()) {
998 kvmppc_xive_source_reset(xsrc
, &error_fatal
);
1002 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1004 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1006 Error
*local_err
= NULL
;
1008 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1010 error_propagate(errp
, local_err
);
1011 error_prepend(errp
, "required link 'xive' not found: ");
1015 xsrc
->xive
= XIVE_NOTIFIER(obj
);
1017 if (!xsrc
->nr_irqs
) {
1018 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1022 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1023 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1024 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1025 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1026 error_setg(errp
, "Invalid ESB shift setting");
1030 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1031 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1033 if (!kvm_irqchip_in_kernel()) {
1034 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1035 &xive_source_esb_ops
, xsrc
, "xive.esb",
1036 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
1039 qemu_register_reset(xive_source_reset
, dev
);
1042 static const VMStateDescription vmstate_xive_source
= {
1043 .name
= TYPE_XIVE_SOURCE
,
1045 .minimum_version_id
= 1,
1046 .fields
= (VMStateField
[]) {
1047 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1048 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1049 VMSTATE_END_OF_LIST()
1054 * The default XIVE interrupt source setting for the ESB MMIOs is two
1055 * 64k pages without Store EOI, to be in sync with KVM.
1057 static Property xive_source_properties
[] = {
1058 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1059 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1060 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1061 DEFINE_PROP_END_OF_LIST(),
1064 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1066 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1068 dc
->desc
= "XIVE Interrupt Source";
1069 dc
->props
= xive_source_properties
;
1070 dc
->realize
= xive_source_realize
;
1071 dc
->vmsd
= &vmstate_xive_source
;
1074 static const TypeInfo xive_source_info
= {
1075 .name
= TYPE_XIVE_SOURCE
,
1076 .parent
= TYPE_DEVICE
,
1077 .instance_size
= sizeof(XiveSource
),
1078 .class_init
= xive_source_class_init
,
1085 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1087 uint64_t qaddr_base
= xive_end_qaddr(end
);
1088 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1089 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1090 uint32_t qentries
= 1 << (qsize
+ 10);
1094 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1096 monitor_printf(mon
, " [ ");
1097 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1098 for (i
= 0; i
< width
; i
++) {
1099 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1100 uint32_t qdata
= -1;
1102 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1104 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1105 HWADDR_PRIx
"\n", qaddr
);
1108 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1109 be32_to_cpu(qdata
));
1110 qindex
= (qindex
+ 1) & (qentries
- 1);
1114 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1116 uint64_t qaddr_base
= xive_end_qaddr(end
);
1117 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1118 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1119 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1120 uint32_t qentries
= 1 << (qsize
+ 10);
1122 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1123 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1125 if (!xive_end_is_valid(end
)) {
1129 monitor_printf(mon
, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
1130 "% 6d/%5d ^%d", end_idx
,
1131 xive_end_is_valid(end
) ? 'v' : '-',
1132 xive_end_is_enqueue(end
) ? 'q' : '-',
1133 xive_end_is_notify(end
) ? 'n' : '-',
1134 xive_end_is_backlog(end
) ? 'b' : '-',
1135 xive_end_is_escalate(end
) ? 'e' : '-',
1136 priority
, nvt
, qaddr_base
, qindex
, qentries
, qgen
);
1138 xive_end_queue_pic_print_info(end
, 6, mon
);
1139 monitor_printf(mon
, "]\n");
1142 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1144 uint64_t qaddr_base
= xive_end_qaddr(end
);
1145 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1146 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1147 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1149 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1150 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1151 uint32_t qentries
= 1 << (qsize
+ 10);
1153 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1154 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1155 HWADDR_PRIx
"\n", qaddr
);
1159 qindex
= (qindex
+ 1) & (qentries
- 1);
1162 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1164 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1168 * XIVE Router (aka. Virtualization Controller or IVRE)
1171 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1174 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1176 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1179 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1182 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1184 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1187 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1188 XiveEND
*end
, uint8_t word_number
)
1190 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1192 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1195 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1198 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1200 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1203 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1204 XiveNVT
*nvt
, uint8_t word_number
)
1206 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1208 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1211 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
1213 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1215 return xrc
->get_tctx(xrtr
, cs
);
1219 * By default on P9, the HW CAM line (23bits) is hardwired to :
1221 * 0x000||0b1||4Bit chip number||7Bit Thread number.
1223 * When the block grouping is enabled, the CAM line is changed to :
1225 * 4Bit chip number||0x001||7Bit Thread number.
1227 static uint32_t hw_cam_line(uint8_t chip_id
, uint8_t tid
)
1229 return 1 << 11 | (chip_id
& 0xf) << 7 | (tid
& 0x7f);
1232 static bool xive_presenter_tctx_match_hw(XiveTCTX
*tctx
,
1233 uint8_t nvt_blk
, uint32_t nvt_idx
)
1235 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1236 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1238 return hw_cam_line((pir
>> 8) & 0xf, pir
& 0x7f) ==
1239 hw_cam_line(nvt_blk
, nvt_idx
);
1243 * The thread context register words are in big-endian format.
1245 static int xive_presenter_tctx_match(XiveTCTX
*tctx
, uint8_t format
,
1246 uint8_t nvt_blk
, uint32_t nvt_idx
,
1247 bool cam_ignore
, uint32_t logic_serv
)
1249 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1250 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1251 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1252 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1253 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1256 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1257 * identifier are ignored in the "CAM" match.
1261 if (cam_ignore
== true) {
1263 * F=0 & i=1: Logical server notification (bits ignored at
1264 * the end of the NVT identifier)
1266 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1271 /* F=0 & i=0: Specific NVT notification */
1274 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1275 xive_presenter_tctx_match_hw(tctx
, nvt_blk
, nvt_idx
)) {
1276 return TM_QW3_HV_PHYS
;
1280 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1281 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1282 return TM_QW2_HV_POOL
;
1286 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1287 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1291 /* F=1 : User level Event-Based Branch (EBB) notification */
1294 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1295 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1296 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1297 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1304 typedef struct XiveTCTXMatch
{
1309 static bool xive_presenter_match(XiveRouter
*xrtr
, uint8_t format
,
1310 uint8_t nvt_blk
, uint32_t nvt_idx
,
1311 bool cam_ignore
, uint8_t priority
,
1312 uint32_t logic_serv
, XiveTCTXMatch
*match
)
1317 * TODO (PowerNV): handle chip_id overwrite of block field for
1318 * hardwired CAM compares
1322 XiveTCTX
*tctx
= xive_router_get_tctx(xrtr
, cs
);
1326 * HW checks that the CPU is enabled in the Physical Thread
1327 * Enable Register (PTER).
1331 * Check the thread context CAM lines and record matches. We
1332 * will handle CPU exception delivery later
1334 ring
= xive_presenter_tctx_match(tctx
, format
, nvt_blk
, nvt_idx
,
1335 cam_ignore
, logic_serv
);
1337 * Save the context and follow on to catch duplicates, that we
1338 * don't support yet.
1342 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
1343 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
1353 qemu_log_mask(LOG_UNIMP
, "XIVE: NVT %x/%x is not dispatched\n",
1362 * This is our simple Xive Presenter Engine model. It is merged in the
1363 * Router as it does not require an extra object.
1365 * It receives notification requests sent by the IVRE to find one
1366 * matching NVT (or more) dispatched on the processor threads. In case
1367 * of a single NVT notification, the process is abreviated and the
1368 * thread is signaled if a match is found. In case of a logical server
1369 * notification (bits ignored at the end of the NVT identifier), the
1370 * IVPE and IVRE select a winning thread using different filters. This
1371 * involves 2 or 3 exchanges on the PowerBus that the model does not
1374 * The parameters represent what is sent on the PowerBus
1376 static void xive_presenter_notify(XiveRouter
*xrtr
, uint8_t format
,
1377 uint8_t nvt_blk
, uint32_t nvt_idx
,
1378 bool cam_ignore
, uint8_t priority
,
1379 uint32_t logic_serv
)
1382 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1385 /* NVT cache lookup */
1386 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1387 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1392 if (!xive_nvt_is_valid(&nvt
)) {
1393 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1398 found
= xive_presenter_match(xrtr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1399 priority
, logic_serv
, &match
);
1401 ipb_update(&match
.tctx
->regs
[match
.ring
], priority
);
1402 xive_tctx_notify(match
.tctx
, match
.ring
);
1406 /* Record the IPB in the associated NVT structure */
1407 ipb_update((uint8_t *) &nvt
.w4
, priority
);
1408 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1411 * If no matching NVT is dispatched on a HW thread :
1412 * - update the NVT structure if backlog is activated
1413 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is
1419 * An END trigger can come from an event trigger (IPI or HW) or from
1420 * another chip. We don't model the PowerBus but the END trigger
1421 * message has the same parameters than in the function below.
1423 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1424 uint32_t end_idx
, uint32_t end_data
)
1430 /* END cache lookup */
1431 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1432 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1437 if (!xive_end_is_valid(&end
)) {
1438 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1443 if (xive_end_is_enqueue(&end
)) {
1444 xive_end_enqueue(&end
, end_data
);
1445 /* Enqueuing event data modifies the EQ toggle and index */
1446 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1450 * The W7 format depends on the F bit in W6. It defines the type
1451 * of the notification :
1453 * F=0 : single or multiple NVT notification
1454 * F=1 : User level Event-Based Branch (EBB) notification, no
1457 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1458 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1460 /* The END is masked */
1461 if (format
== 0 && priority
== 0xff) {
1466 * Check the END ESn (Event State Buffer for notification) for
1467 * even futher coalescing in the Router
1469 if (!xive_end_is_notify(&end
)) {
1470 uint8_t pq
= xive_get_field32(END_W1_ESn
, end
.w1
);
1471 bool notify
= xive_esb_trigger(&pq
);
1473 if (pq
!= xive_get_field32(END_W1_ESn
, end
.w1
)) {
1474 end
.w1
= xive_set_field32(END_W1_ESn
, end
.w1
, pq
);
1475 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1478 /* ESn[Q]=1 : end of notification */
1485 * Follows IVPE notification
1487 xive_presenter_notify(xrtr
, format
,
1488 xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
),
1489 xive_get_field32(END_W6_NVT_INDEX
, end
.w6
),
1490 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1492 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1494 /* TODO: Auto EOI. */
1497 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1499 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1500 uint8_t eas_blk
= XIVE_SRCNO_BLOCK(lisn
);
1501 uint32_t eas_idx
= XIVE_SRCNO_INDEX(lisn
);
1504 /* EAS cache lookup */
1505 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1506 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1511 * The IVRE checks the State Bit Cache at this point. We skip the
1512 * SBC lookup because the state bits of the sources are modeled
1513 * internally in QEMU.
1516 if (!xive_eas_is_valid(&eas
)) {
1517 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1521 if (xive_eas_is_masked(&eas
)) {
1522 /* Notification completed */
1527 * The event trigger becomes an END trigger
1529 xive_router_end_notify(xrtr
,
1530 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1531 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1532 xive_get_field64(EAS_END_DATA
, eas
.w
));
1535 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1537 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1538 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1540 dc
->desc
= "XIVE Router Engine";
1541 xnc
->notify
= xive_router_notify
;
1544 static const TypeInfo xive_router_info
= {
1545 .name
= TYPE_XIVE_ROUTER
,
1546 .parent
= TYPE_SYS_BUS_DEVICE
,
1548 .class_size
= sizeof(XiveRouterClass
),
1549 .class_init
= xive_router_class_init
,
1550 .interfaces
= (InterfaceInfo
[]) {
1551 { TYPE_XIVE_NOTIFIER
},
1556 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1558 if (!xive_eas_is_valid(eas
)) {
1562 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1563 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1564 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1565 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1566 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1570 * END ESB MMIO loads
1572 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1574 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1575 uint32_t offset
= addr
& 0xFFF;
1579 uint32_t end_esmask
;
1583 end_blk
= xsrc
->block_id
;
1584 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1586 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1587 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1592 if (!xive_end_is_valid(&end
)) {
1593 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1598 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1599 pq
= xive_get_field32(end_esmask
, end
.w1
);
1602 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1603 ret
= xive_esb_eoi(&pq
);
1605 /* Forward the source event notification for routing ?? */
1608 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1612 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1613 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1614 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1615 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1616 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1619 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1624 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1625 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1626 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1633 * END ESB MMIO stores are invalid
1635 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1636 uint64_t value
, unsigned size
)
1638 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1639 HWADDR_PRIx
"\n", addr
);
1642 static const MemoryRegionOps xive_end_source_ops
= {
1643 .read
= xive_end_source_read
,
1644 .write
= xive_end_source_write
,
1645 .endianness
= DEVICE_BIG_ENDIAN
,
1647 .min_access_size
= 8,
1648 .max_access_size
= 8,
1651 .min_access_size
= 8,
1652 .max_access_size
= 8,
1656 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1658 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1660 Error
*local_err
= NULL
;
1662 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1664 error_propagate(errp
, local_err
);
1665 error_prepend(errp
, "required link 'xive' not found: ");
1669 xsrc
->xrtr
= XIVE_ROUTER(obj
);
1671 if (!xsrc
->nr_ends
) {
1672 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1676 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1677 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1678 error_setg(errp
, "Invalid ESB shift setting");
1683 * Each END is assigned an even/odd pair of MMIO pages, the even page
1684 * manages the ESn field while the odd page manages the ESe field.
1686 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1687 &xive_end_source_ops
, xsrc
, "xive.end",
1688 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1691 static Property xive_end_source_properties
[] = {
1692 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
1693 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1694 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1695 DEFINE_PROP_END_OF_LIST(),
1698 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1700 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1702 dc
->desc
= "XIVE END Source";
1703 dc
->props
= xive_end_source_properties
;
1704 dc
->realize
= xive_end_source_realize
;
1707 static const TypeInfo xive_end_source_info
= {
1708 .name
= TYPE_XIVE_END_SOURCE
,
1709 .parent
= TYPE_DEVICE
,
1710 .instance_size
= sizeof(XiveENDSource
),
1711 .class_init
= xive_end_source_class_init
,
1717 static const TypeInfo xive_notifier_info
= {
1718 .name
= TYPE_XIVE_NOTIFIER
,
1719 .parent
= TYPE_INTERFACE
,
1720 .class_size
= sizeof(XiveNotifierClass
),
1723 static void xive_register_types(void)
1725 type_register_static(&xive_source_info
);
1726 type_register_static(&xive_notifier_info
);
1727 type_register_static(&xive_router_info
);
1728 type_register_static(&xive_end_source_info
);
1729 type_register_static(&xive_tctx_info
);
1732 type_init(xive_register_types
)