target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28
  29 enum {
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 104                                 int *prot, target_ulong real_address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 110     int kernel_mode = !user_mode && !supervisor_mode;
 111 #if defined(TARGET_MIPS64)
 112     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 113     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 114     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 115 #endif
 116     int ret = TLBRET_MATCH;
 117     /* effective address (modified for KVM T&E kernel segments) */
 118     target_ulong address = real_address;
 119
 120 #if 0
 121     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 122 #endif
 123
 124 #define USEG_LIMIT      0x7FFFFFFFUL
 125 #define KSEG0_BASE      0x80000000UL
 126 #define KSEG1_BASE      0xA0000000UL
 127 #define KSEG2_BASE      0xC0000000UL
 128 #define KSEG3_BASE      0xE0000000UL
 129
 130 #define KVM_KSEG0_BASE  0x40000000UL
 131 #define KVM_KSEG2_BASE  0x60000000UL
 132
 133     if (kvm_enabled()) {
 134         /* KVM T&E adds guest kernel segments in useg */
 135         if (real_address >= KVM_KSEG0_BASE) {
 136             if (real_address < KVM_KSEG2_BASE) {
 137                 /* kseg0 */
 138                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 139             } else if (real_address <= USEG_LIMIT) {
 140                 /* kseg2/3 */
 141                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 142             }
 143         }
 144     }
 145
 146     if (address <= USEG_LIMIT) {
 147         /* useg */
 148         if (env->CP0_Status & (1 << CP0St_ERL)) {
 149             *physical = address & 0xFFFFFFFF;
 150             *prot = PAGE_READ | PAGE_WRITE;
 151         } else {
 152             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 153         }
 154 #if defined(TARGET_MIPS64)
 155     } else if (address < 0x4000000000000000ULL) {
 156         /* xuseg */
 157         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 158             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 159         } else {
 160             ret = TLBRET_BADADDR;
 161         }
 162     } else if (address < 0x8000000000000000ULL) {
 163         /* xsseg */
 164         if ((supervisor_mode || kernel_mode) &&
 165             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 166             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 167         } else {
 168             ret = TLBRET_BADADDR;
 169         }
 170     } else if (address < 0xC000000000000000ULL) {
 171         /* xkphys */
 172         if (kernel_mode && KX &&
 173             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 174             *physical = address & env->PAMask;
 175             *prot = PAGE_READ | PAGE_WRITE;
 176         } else {
 177             ret = TLBRET_BADADDR;
 178         }
 179     } else if (address < 0xFFFFFFFF80000000ULL) {
 180         /* xkseg */
 181         if (kernel_mode && KX &&
 182             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 183             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 184         } else {
 185             ret = TLBRET_BADADDR;
 186         }
 187 #endif
 188     } else if (address < (int32_t)KSEG1_BASE) {
 189         /* kseg0 */
 190         if (kernel_mode) {
 191             *physical = address - (int32_t)KSEG0_BASE;
 192             *prot = PAGE_READ | PAGE_WRITE;
 193         } else {
 194             ret = TLBRET_BADADDR;
 195         }
 196     } else if (address < (int32_t)KSEG2_BASE) {
 197         /* kseg1 */
 198         if (kernel_mode) {
 199             *physical = address - (int32_t)KSEG1_BASE;
 200             *prot = PAGE_READ | PAGE_WRITE;
 201         } else {
 202             ret = TLBRET_BADADDR;
 203         }
 204     } else if (address < (int32_t)KSEG3_BASE) {
 205         /* sseg (kseg2) */
 206         if (supervisor_mode || kernel_mode) {
 207             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 208         } else {
 209             ret = TLBRET_BADADDR;
 210         }
 211     } else {
 212         /* kseg3 */
 213         /* XXX: debug segment is not emulated */
 214         if (kernel_mode) {
 215             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 216         } else {
 217             ret = TLBRET_BADADDR;
 218         }
 219     }
 220 #if 0
 221     qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
 222             address, rw, access_type, *physical, *prot, ret);
 223 #endif
 224
 225     return ret;
 226 }
 227 #endif
 228
 229 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 230                                 int rw, int tlb_error)
 231 {
 232     CPUState *cs = CPU(mips_env_get_cpu(env));
 233     int exception = 0, error_code = 0;
 234
 235     switch (tlb_error) {
 236     default:
 237     case TLBRET_BADADDR:
 238         /* Reference to kernel address from user mode or supervisor mode */
 239         /* Reference to supervisor address from user mode */
 240         if (rw)
 241             exception = EXCP_AdES;
 242         else
 243             exception = EXCP_AdEL;
 244         break;
 245     case TLBRET_NOMATCH:
 246         /* No TLB match for a mapped address */
 247         if (rw)
 248             exception = EXCP_TLBS;
 249         else
 250             exception = EXCP_TLBL;
 251         error_code = 1;
 252         break;
 253     case TLBRET_INVALID:
 254         /* TLB match with no valid bit */
 255         if (rw)
 256             exception = EXCP_TLBS;
 257         else
 258             exception = EXCP_TLBL;
 259         break;
 260     case TLBRET_DIRTY:
 261         /* TLB match but 'D' bit is cleared */
 262         exception = EXCP_LTLBL;
 263         break;
 264
 265     }
 266     /* Raise exception */
 267     env->CP0_BadVAddr = address;
 268     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 269                        ((address >> 9) & 0x007ffff0);
 270     env->CP0_EntryHi =
 271         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 272 #if defined(TARGET_MIPS64)
 273     env->CP0_EntryHi &= env->SEGMask;
 274     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 275                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 276                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 277 #endif
 278     cs->exception_index = exception;
 279     env->error_code = error_code;
 280 }
 281
 282 #if !defined(CONFIG_USER_ONLY)
 283 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 284 {
 285     MIPSCPU *cpu = MIPS_CPU(cs);
 286     hwaddr phys_addr;
 287     int prot;
 288
 289     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 290                              ACCESS_INT) != 0) {
 291         return -1;
 292     }
 293     return phys_addr;
 294 }
 295 #endif
 296
 297 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 298                               int mmu_idx)
 299 {
 300     MIPSCPU *cpu = MIPS_CPU(cs);
 301     CPUMIPSState *env = &cpu->env;
 302 #if !defined(CONFIG_USER_ONLY)
 303     hwaddr physical;
 304     int prot;
 305     int access_type;
 306 #endif
 307     int ret = 0;
 308
 309 #if 0
 310     log_cpu_state(cs, 0);
 311 #endif
 312     qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 313               __func__, env->active_tc.PC, address, rw, mmu_idx);
 314
 315     rw &= 1;
 316
 317     /* data access */
 318 #if !defined(CONFIG_USER_ONLY)
 319     /* XXX: put correct access by using cpu_restore_state()
 320        correctly */
 321     access_type = ACCESS_INT;
 322     ret = get_physical_address(env, &physical, &prot,
 323                                address, rw, access_type);
 324     qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 325              " prot %d\n",
 326              __func__, address, ret, physical, prot);
 327     if (ret == TLBRET_MATCH) {
 328         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 329                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 330                      mmu_idx, TARGET_PAGE_SIZE);
 331         ret = 0;
 332     } else if (ret < 0)
 333 #endif
 334     {
 335         raise_mmu_exception(env, address, rw, ret);
 336         ret = 1;
 337     }
 338
 339     return ret;
 340 }
 341
 342 #if !defined(CONFIG_USER_ONLY)
 343 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 344 {
 345     hwaddr physical;
 346     int prot;
 347     int access_type;
 348     int ret = 0;
 349
 350     rw &= 1;
 351
 352     /* data access */
 353     access_type = ACCESS_INT;
 354     ret = get_physical_address(env, &physical, &prot,
 355                                address, rw, access_type);
 356     if (ret != TLBRET_MATCH) {
 357         raise_mmu_exception(env, address, rw, ret);
 358         return -1LL;
 359     } else {
 360         return physical;
 361     }
 362 }
 363 #endif
 364
 365 static const char * const excp_names[EXCP_LAST + 1] = {
 366     [EXCP_RESET] = "reset",
 367     [EXCP_SRESET] = "soft reset",
 368     [EXCP_DSS] = "debug single step",
 369     [EXCP_DINT] = "debug interrupt",
 370     [EXCP_NMI] = "non-maskable interrupt",
 371     [EXCP_MCHECK] = "machine check",
 372     [EXCP_EXT_INTERRUPT] = "interrupt",
 373     [EXCP_DFWATCH] = "deferred watchpoint",
 374     [EXCP_DIB] = "debug instruction breakpoint",
 375     [EXCP_IWATCH] = "instruction fetch watchpoint",
 376     [EXCP_AdEL] = "address error load",
 377     [EXCP_AdES] = "address error store",
 378     [EXCP_TLBF] = "TLB refill",
 379     [EXCP_IBE] = "instruction bus error",
 380     [EXCP_DBp] = "debug breakpoint",
 381     [EXCP_SYSCALL] = "syscall",
 382     [EXCP_BREAK] = "break",
 383     [EXCP_CpU] = "coprocessor unusable",
 384     [EXCP_RI] = "reserved instruction",
 385     [EXCP_OVERFLOW] = "arithmetic overflow",
 386     [EXCP_TRAP] = "trap",
 387     [EXCP_FPE] = "floating point",
 388     [EXCP_DDBS] = "debug data break store",
 389     [EXCP_DWATCH] = "data watchpoint",
 390     [EXCP_LTLBL] = "TLB modify",
 391     [EXCP_TLBL] = "TLB load",
 392     [EXCP_TLBS] = "TLB store",
 393     [EXCP_DBE] = "data bus error",
 394     [EXCP_DDBL] = "debug data break load",
 395     [EXCP_THREAD] = "thread",
 396     [EXCP_MDMX] = "MDMX",
 397     [EXCP_C2E] = "precise coprocessor 2",
 398     [EXCP_CACHE] = "cache error",
 399 };
 400
 401 target_ulong exception_resume_pc (CPUMIPSState *env)
 402 {
 403     target_ulong bad_pc;
 404     target_ulong isa_mode;
 405
 406     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 407     bad_pc = env->active_tc.PC | isa_mode;
 408     if (env->hflags & MIPS_HFLAG_BMASK) {
 409         /* If the exception was raised from a delay slot, come back to
 410            the jump.  */
 411         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 412     }
 413
 414     return bad_pc;
 415 }
 416
 417 #if !defined(CONFIG_USER_ONLY)
 418 static void set_hflags_for_handler (CPUMIPSState *env)
 419 {
 420     /* Exception handlers are entered in 32-bit mode.  */
 421     env->hflags &= ~(MIPS_HFLAG_M16);
 422     /* ...except that microMIPS lets you choose.  */
 423     if (env->insn_flags & ASE_MICROMIPS) {
 424         env->hflags |= (!!(env->CP0_Config3
 425                            & (1 << CP0C3_ISA_ON_EXC))
 426                         << MIPS_HFLAG_M16_SHIFT);
 427     }
 428 }
 429 #endif
 430
 431 void mips_cpu_do_interrupt(CPUState *cs)
 432 {
 433 #if !defined(CONFIG_USER_ONLY)
 434     MIPSCPU *cpu = MIPS_CPU(cs);
 435     CPUMIPSState *env = &cpu->env;
 436     target_ulong offset;
 437     int cause = -1;
 438     const char *name;
 439
 440     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 441         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 442             name = "unknown";
 443         } else {
 444             name = excp_names[cs->exception_index];
 445         }
 446
 447         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 448                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 449     }
 450     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 451         (env->hflags & MIPS_HFLAG_DM)) {
 452         cs->exception_index = EXCP_DINT;
 453     }
 454     offset = 0x180;
 455     switch (cs->exception_index) {
 456     case EXCP_DSS:
 457         env->CP0_Debug |= 1 << CP0DB_DSS;
 458         /* Debug single step cannot be raised inside a delay slot and
 459            resume will always occur on the next instruction
 460            (but we assume the pc has always been updated during
 461            code translation). */
 462         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 463         goto enter_debug_mode;
 464     case EXCP_DINT:
 465         env->CP0_Debug |= 1 << CP0DB_DINT;
 466         goto set_DEPC;
 467     case EXCP_DIB:
 468         env->CP0_Debug |= 1 << CP0DB_DIB;
 469         goto set_DEPC;
 470     case EXCP_DBp:
 471         env->CP0_Debug |= 1 << CP0DB_DBp;
 472         goto set_DEPC;
 473     case EXCP_DDBS:
 474         env->CP0_Debug |= 1 << CP0DB_DDBS;
 475         goto set_DEPC;
 476     case EXCP_DDBL:
 477         env->CP0_Debug |= 1 << CP0DB_DDBL;
 478     set_DEPC:
 479         env->CP0_DEPC = exception_resume_pc(env);
 480         env->hflags &= ~MIPS_HFLAG_BMASK;
 481  enter_debug_mode:
 482         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 483         env->hflags &= ~(MIPS_HFLAG_KSU);
 484         /* EJTAG probe trap enable is not implemented... */
 485         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 486             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 487         env->active_tc.PC = (int32_t)0xBFC00480;
 488         set_hflags_for_handler(env);
 489         break;
 490     case EXCP_RESET:
 491         cpu_reset(CPU(cpu));
 492         break;
 493     case EXCP_SRESET:
 494         env->CP0_Status |= (1 << CP0St_SR);
 495         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 496         goto set_error_EPC;
 497     case EXCP_NMI:
 498         env->CP0_Status |= (1 << CP0St_NMI);
 499  set_error_EPC:
 500         env->CP0_ErrorEPC = exception_resume_pc(env);
 501         env->hflags &= ~MIPS_HFLAG_BMASK;
 502         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 503         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 504         env->hflags &= ~(MIPS_HFLAG_KSU);
 505         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 506             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 507         env->active_tc.PC = (int32_t)0xBFC00000;
 508         set_hflags_for_handler(env);
 509         break;
 510     case EXCP_EXT_INTERRUPT:
 511         cause = 0;
 512         if (env->CP0_Cause & (1 << CP0Ca_IV))
 513             offset = 0x200;
 514
 515         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 516             /* Vectored Interrupts.  */
 517             unsigned int spacing;
 518             unsigned int vector;
 519             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 520
 521             pending &= env->CP0_Status >> 8;
 522             /* Compute the Vector Spacing.  */
 523             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 524             spacing <<= 5;
 525
 526             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 527                 /* For VInt mode, the MIPS computes the vector internally.  */
 528                 for (vector = 7; vector > 0; vector--) {
 529                     if (pending & (1 << vector)) {
 530                         /* Found it.  */
 531                         break;
 532                     }
 533                 }
 534             } else {
 535                 /* For VEIC mode, the external interrupt controller feeds the
 536                    vector through the CP0Cause IP lines.  */
 537                 vector = pending;
 538             }
 539             offset = 0x200 + vector * spacing;
 540         }
 541         goto set_EPC;
 542     case EXCP_LTLBL:
 543         cause = 1;
 544         goto set_EPC;
 545     case EXCP_TLBL:
 546         cause = 2;
 547         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 548 #if defined(TARGET_MIPS64)
 549             int R = env->CP0_BadVAddr >> 62;
 550             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 551             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 552             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 553
 554             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 555                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 556                 offset = 0x080;
 557             else
 558 #endif
 559                 offset = 0x000;
 560         }
 561         goto set_EPC;
 562     case EXCP_TLBS:
 563         cause = 3;
 564         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 565 #if defined(TARGET_MIPS64)
 566             int R = env->CP0_BadVAddr >> 62;
 567             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 568             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 569             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 570
 571             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 572                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 573                 offset = 0x080;
 574             else
 575 #endif
 576                 offset = 0x000;
 577         }
 578         goto set_EPC;
 579     case EXCP_AdEL:
 580         cause = 4;
 581         goto set_EPC;
 582     case EXCP_AdES:
 583         cause = 5;
 584         goto set_EPC;
 585     case EXCP_IBE:
 586         cause = 6;
 587         goto set_EPC;
 588     case EXCP_DBE:
 589         cause = 7;
 590         goto set_EPC;
 591     case EXCP_SYSCALL:
 592         cause = 8;
 593         goto set_EPC;
 594     case EXCP_BREAK:
 595         cause = 9;
 596         goto set_EPC;
 597     case EXCP_RI:
 598         cause = 10;
 599         goto set_EPC;
 600     case EXCP_CpU:
 601         cause = 11;
 602         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 603                          (env->error_code << CP0Ca_CE);
 604         goto set_EPC;
 605     case EXCP_OVERFLOW:
 606         cause = 12;
 607         goto set_EPC;
 608     case EXCP_TRAP:
 609         cause = 13;
 610         goto set_EPC;
 611     case EXCP_FPE:
 612         cause = 15;
 613         goto set_EPC;
 614     case EXCP_C2E:
 615         cause = 18;
 616         goto set_EPC;
 617     case EXCP_MDMX:
 618         cause = 22;
 619         goto set_EPC;
 620     case EXCP_DWATCH:
 621         cause = 23;
 622         /* XXX: TODO: manage defered watch exceptions */
 623         goto set_EPC;
 624     case EXCP_MCHECK:
 625         cause = 24;
 626         goto set_EPC;
 627     case EXCP_THREAD:
 628         cause = 25;
 629         goto set_EPC;
 630     case EXCP_DSPDIS:
 631         cause = 26;
 632         goto set_EPC;
 633     case EXCP_CACHE:
 634         cause = 30;
 635         if (env->CP0_Status & (1 << CP0St_BEV)) {
 636             offset = 0x100;
 637         } else {
 638             offset = 0x20000100;
 639         }
 640  set_EPC:
 641         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 642             env->CP0_EPC = exception_resume_pc(env);
 643             if (env->hflags & MIPS_HFLAG_BMASK) {
 644                 env->CP0_Cause |= (1U << CP0Ca_BD);
 645             } else {
 646                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 647             }
 648             env->CP0_Status |= (1 << CP0St_EXL);
 649             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 650             env->hflags &= ~(MIPS_HFLAG_KSU);
 651         }
 652         env->hflags &= ~MIPS_HFLAG_BMASK;
 653         if (env->CP0_Status & (1 << CP0St_BEV)) {
 654             env->active_tc.PC = (int32_t)0xBFC00200;
 655         } else {
 656             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 657         }
 658         env->active_tc.PC += offset;
 659         set_hflags_for_handler(env);
 660         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 661         break;
 662     default:
 663         qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 664         printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 665         exit(1);
 666     }
 667     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 668         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 669                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 670                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 671                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 672                 env->CP0_DEPC);
 673     }
 674 #endif
 675     cs->exception_index = EXCP_NONE;
 676 }
 677
 678 #if !defined(CONFIG_USER_ONLY)
 679 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 680 {
 681     MIPSCPU *cpu = mips_env_get_cpu(env);
 682     CPUState *cs;
 683     r4k_tlb_t *tlb;
 684     target_ulong addr;
 685     target_ulong end;
 686     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 687     target_ulong mask;
 688
 689     tlb = &env->tlb->mmu.r4k.tlb[idx];
 690     /* The qemu TLB is flushed when the ASID changes, so no need to
 691        flush these entries again.  */
 692     if (tlb->G == 0 && tlb->ASID != ASID) {
 693         return;
 694     }
 695
 696     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 697         /* For tlbwr, we can shadow the discarded entry into
 698            a new (fake) TLB entry, as long as the guest can not
 699            tell that it's there.  */
 700         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 701         env->tlb->tlb_in_use++;
 702         return;
 703     }
 704
 705     /* 1k pages are not supported. */
 706     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 707     if (tlb->V0) {
 708         cs = CPU(cpu);
 709         addr = tlb->VPN & ~mask;
 710 #if defined(TARGET_MIPS64)
 711         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 712             addr |= 0x3FFFFF0000000000ULL;
 713         }
 714 #endif
 715         end = addr | (mask >> 1);
 716         while (addr < end) {
 717             tlb_flush_page(cs, addr);
 718             addr += TARGET_PAGE_SIZE;
 719         }
 720     }
 721     if (tlb->V1) {
 722         cs = CPU(cpu);
 723         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 724 #if defined(TARGET_MIPS64)
 725         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 726             addr |= 0x3FFFFF0000000000ULL;
 727         }
 728 #endif
 729         end = addr | mask;
 730         while (addr - 1 < end) {
 731             tlb_flush_page(cs, addr);
 732             addr += TARGET_PAGE_SIZE;
 733         }
 734     }
 735 }
 736 #endif