target-mips/gdbstub.c

   1 /*
   2  * MIPS gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "config.h"
  21 #include "qemu-common.h"
  22 #include "exec/gdbstub.h"
  23
  24 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  25 {
  26     MIPSCPU *cpu = MIPS_CPU(cs);
  27     CPUMIPSState *env = &cpu->env;
  28
  29     if (n < 32) {
  30         return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
  31     }
  32     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  33         if (n >= 38 && n < 70) {
  34             if (env->CP0_Status & (1 << CP0St_FR)) {
  35                 return gdb_get_regl(mem_buf,
  36                     env->active_fpu.fpr[n - 38].d);
  37             } else {
  38                 return gdb_get_regl(mem_buf,
  39                     env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
  40             }
  41         }
  42         switch (n) {
  43         case 70:
  44             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
  45         case 71:
  46             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
  47         }
  48     }
  49     switch (n) {
  50     case 32:
  51         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
  52     case 33:
  53         return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
  54     case 34:
  55         return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
  56     case 35:
  57         return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
  58     case 36:
  59         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
  60     case 37:
  61         return gdb_get_regl(mem_buf, env->active_tc.PC |
  62                                      !!(env->hflags & MIPS_HFLAG_M16));
  63     case 72:
  64         return gdb_get_regl(mem_buf, 0); /* fp */
  65     case 89:
  66         return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
  67     }
  68     if (n >= 73 && n <= 88) {
  69         /* 16 embedded regs.  */
  70         return gdb_get_regl(mem_buf, 0);
  71     }
  72
  73     return 0;
  74 }
  75
  76 /* convert MIPS rounding mode in FCR31 to IEEE library */
  77 static unsigned int ieee_rm[] = {
  78     float_round_nearest_even,
  79     float_round_to_zero,
  80     float_round_up,
  81     float_round_down
  82 };
  83 #define RESTORE_ROUNDING_MODE \
  84     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
  85                             &env->active_fpu.fp_status)
  86
  87 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  88 {
  89     MIPSCPU *cpu = MIPS_CPU(cs);
  90     CPUMIPSState *env = &cpu->env;
  91     target_ulong tmp;
  92
  93     tmp = ldtul_p(mem_buf);
  94
  95     if (n < 32) {
  96         env->active_tc.gpr[n] = tmp;
  97         return sizeof(target_ulong);
  98     }
  99     if (env->CP0_Config1 & (1 << CP0C1_FP)
 100             && n >= 38 && n < 73) {
 101         if (n < 70) {
 102             if (env->CP0_Status & (1 << CP0St_FR)) {
 103                 env->active_fpu.fpr[n - 38].d = tmp;
 104             } else {
 105                 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
 106             }
 107         }
 108         switch (n) {
 109         case 70:
 110             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
 111             /* set rounding mode */
 112             RESTORE_ROUNDING_MODE;
 113             break;
 114         case 71:
 115             env->active_fpu.fcr0 = tmp;
 116             break;
 117         }
 118         return sizeof(target_ulong);
 119     }
 120     switch (n) {
 121     case 32:
 122         env->CP0_Status = tmp;
 123         break;
 124     case 33:
 125         env->active_tc.LO[0] = tmp;
 126         break;
 127     case 34:
 128         env->active_tc.HI[0] = tmp;
 129         break;
 130     case 35:
 131         env->CP0_BadVAddr = tmp;
 132         break;
 133     case 36:
 134         env->CP0_Cause = tmp;
 135         break;
 136     case 37:
 137         env->active_tc.PC = tmp & ~(target_ulong)1;
 138         if (tmp & 1) {
 139             env->hflags |= MIPS_HFLAG_M16;
 140         } else {
 141             env->hflags &= ~(MIPS_HFLAG_M16);
 142         }
 143         break;
 144     case 72: /* fp, ignored */
 145         break;
 146     default:
 147         if (n > 89) {
 148             return 0;
 149         }
 150         /* Other registers are readonly.  Ignore writes.  */
 151         break;
 152     }
 153
 154     return sizeof(target_ulong);
 155 }