2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_cpu_core.h"
16 #include "hw/ppc/spapr_xive.h"
17 #include "hw/ppc/xics.h"
18 #include "hw/ppc/xics_spapr.h"
19 #include "cpu-models.h"
20 #include "sysemu/kvm.h"
24 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
26 spapr
->irq_map_nr
= nr_msis
;
27 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
30 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
36 * The 'align_mask' parameter of bitmap_find_next_zero_area()
37 * should be one less than a power of 2; 0 means no
38 * alignment. Adapt the 'align' value of the former allocator
39 * to fit the requirements of bitmap_find_next_zero_area()
43 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
45 if (irq
== spapr
->irq_map_nr
) {
46 error_setg(errp
, "can't find a free %d-IRQ block", num
);
50 bitmap_set(spapr
->irq_map
, irq
, num
);
52 return irq
+ SPAPR_IRQ_MSI
;
55 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
57 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
60 void spapr_irq_msi_reset(SpaprMachineState
*spapr
)
62 bitmap_clear(spapr
->irq_map
, 0, spapr
->irq_map_nr
);
70 static ICSState
*spapr_ics_create(SpaprMachineState
*spapr
,
71 int nr_irqs
, Error
**errp
)
73 Error
*local_err
= NULL
;
76 obj
= object_new(TYPE_ICS_SIMPLE
);
77 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
78 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
80 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &local_err
);
84 object_property_set_bool(obj
, true, "realized", &local_err
);
92 error_propagate(errp
, local_err
);
96 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, int nr_irqs
,
99 MachineState
*machine
= MACHINE(spapr
);
100 Error
*local_err
= NULL
;
101 bool xics_kvm
= false;
104 if (machine_kernel_irqchip_allowed(machine
) &&
105 !xics_kvm_init(spapr
, &local_err
)) {
108 if (machine_kernel_irqchip_required(machine
) && !xics_kvm
) {
109 error_prepend(&local_err
,
110 "kernel_irqchip requested but unavailable: ");
113 error_free(local_err
);
118 xics_spapr_init(spapr
);
121 spapr
->ics
= spapr_ics_create(spapr
, nr_irqs
, &local_err
);
124 error_propagate(errp
, local_err
);
127 #define ICS_IRQ_FREE(ics, srcno) \
128 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
130 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
133 ICSState
*ics
= spapr
->ics
;
137 if (!ics_valid_irq(ics
, irq
)) {
138 error_setg(errp
, "IRQ %d is invalid", irq
);
142 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
143 error_setg(errp
, "IRQ %d is not free", irq
);
147 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
151 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
153 ICSState
*ics
= spapr
->ics
;
154 uint32_t srcno
= irq
- ics
->offset
;
157 if (ics_valid_irq(ics
, irq
)) {
158 trace_spapr_irq_free(0, irq
, num
);
159 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
160 if (ICS_IRQ_FREE(ics
, i
)) {
161 trace_spapr_irq_free_warn(0, i
);
163 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
168 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
170 ICSState
*ics
= spapr
->ics
;
171 uint32_t srcno
= irq
- ics
->offset
;
173 if (ics_valid_irq(ics
, irq
)) {
174 return spapr
->qirqs
[srcno
];
180 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
185 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
187 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
190 ics_pic_print_info(spapr
->ics
, mon
);
193 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
194 PowerPCCPU
*cpu
, Error
**errp
)
196 Error
*local_err
= NULL
;
198 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
200 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
203 error_propagate(errp
, local_err
);
207 spapr_cpu
->icp
= ICP(obj
);
210 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
212 if (!kvm_irqchip_in_kernel()) {
215 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
216 icp_resend(spapr_cpu_state(cpu
)->icp
);
222 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
224 SpaprMachineState
*spapr
= opaque
;
226 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
229 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
231 /* TODO: create the KVM XICS device */
234 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
236 return XICS_NODENAME
;
239 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
240 #define SPAPR_IRQ_XICS_NR_MSIS \
241 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
243 SpaprIrq spapr_irq_xics
= {
244 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
245 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
246 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
248 .init
= spapr_irq_init_xics
,
249 .claim
= spapr_irq_claim_xics
,
250 .free
= spapr_irq_free_xics
,
251 .qirq
= spapr_qirq_xics
,
252 .print_info
= spapr_irq_print_info_xics
,
253 .dt_populate
= spapr_dt_xics
,
254 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
255 .post_load
= spapr_irq_post_load_xics
,
256 .reset
= spapr_irq_reset_xics
,
257 .set_irq
= spapr_irq_set_irq_xics
,
258 .get_nodename
= spapr_irq_get_nodename_xics
,
264 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, int nr_irqs
,
267 MachineState
*machine
= MACHINE(spapr
);
268 uint32_t nr_servers
= spapr_max_server_number(spapr
);
272 /* KVM XIVE device not yet available */
274 if (machine_kernel_irqchip_required(machine
)) {
275 error_setg(errp
, "kernel_irqchip requested. no KVM XIVE support");
280 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
281 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
283 * 8 XIVE END structures per CPU. One for each available priority
285 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
286 qdev_init_nofail(dev
);
288 spapr
->xive
= SPAPR_XIVE(dev
);
290 /* Enable the CPU IPIs */
291 for (i
= 0; i
< nr_servers
; ++i
) {
292 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
295 spapr_xive_hcall_init(spapr
);
298 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
301 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
302 error_setg(errp
, "IRQ %d is invalid", irq
);
308 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
312 for (i
= irq
; i
< irq
+ num
; ++i
) {
313 spapr_xive_irq_free(spapr
->xive
, i
);
317 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
319 SpaprXive
*xive
= spapr
->xive
;
321 if (irq
>= xive
->nr_irqs
) {
325 /* The sPAPR machine/device should have claimed the IRQ before */
326 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
328 return spapr
->qirqs
[irq
];
331 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
337 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
339 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
342 spapr_xive_pic_print_info(spapr
->xive
, mon
);
345 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
346 PowerPCCPU
*cpu
, Error
**errp
)
348 Error
*local_err
= NULL
;
350 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
352 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
354 error_propagate(errp
, local_err
);
358 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
361 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
362 * don't beneficiate from the reset of the XIVE IRQ backend
364 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
367 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
372 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
377 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
379 /* (TCG) Set the OS CAM line of the thread interrupt context. */
380 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
383 /* Activate the XIVE MMIOs */
384 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
387 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
389 SpaprMachineState
*spapr
= opaque
;
391 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
394 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
396 return spapr
->xive
->nodename
;
400 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
404 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
405 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
407 SpaprIrq spapr_irq_xive
= {
408 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
409 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
410 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
412 .init
= spapr_irq_init_xive
,
413 .claim
= spapr_irq_claim_xive
,
414 .free
= spapr_irq_free_xive
,
415 .qirq
= spapr_qirq_xive
,
416 .print_info
= spapr_irq_print_info_xive
,
417 .dt_populate
= spapr_dt_xive
,
418 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
419 .post_load
= spapr_irq_post_load_xive
,
420 .reset
= spapr_irq_reset_xive
,
421 .set_irq
= spapr_irq_set_irq_xive
,
422 .get_nodename
= spapr_irq_get_nodename_xive
,
426 * Dual XIVE and XICS IRQ backend.
428 * Both interrupt mode, XIVE and XICS, objects are created but the
429 * machine starts in legacy interrupt mode (XICS). It can be changed
430 * by the CAS negotiation process and, in that case, the new mode is
431 * activated after an extra machine reset.
435 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
438 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
440 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
441 &spapr_irq_xive
: &spapr_irq_xics
;
444 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, int nr_irqs
,
447 MachineState
*machine
= MACHINE(spapr
);
448 Error
*local_err
= NULL
;
450 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
451 error_setg(errp
, "No KVM support for the 'dual' machine");
455 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
457 error_propagate(errp
, local_err
);
461 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
463 error_propagate(errp
, local_err
);
468 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
471 Error
*local_err
= NULL
;
474 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
476 error_propagate(errp
, local_err
);
480 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
482 error_propagate(errp
, local_err
);
489 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
491 spapr_irq_xics
.free(spapr
, irq
, num
);
492 spapr_irq_xive
.free(spapr
, irq
, num
);
495 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
497 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
500 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
502 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
505 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
506 uint32_t nr_servers
, void *fdt
,
509 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
512 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
513 PowerPCCPU
*cpu
, Error
**errp
)
515 Error
*local_err
= NULL
;
517 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
519 error_propagate(errp
, local_err
);
523 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
526 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
529 * Force a reset of the XIVE backend after migration. The machine
530 * defaults to XICS at startup.
532 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
533 spapr_irq_xive
.reset(spapr
, &error_fatal
);
536 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
539 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
542 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
545 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
547 spapr_irq_current(spapr
)->reset(spapr
, errp
);
550 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
552 SpaprMachineState
*spapr
= opaque
;
554 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
557 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
559 return spapr_irq_current(spapr
)->get_nodename(spapr
);
563 * Define values in sync with the XIVE and XICS backend
565 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
566 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
568 SpaprIrq spapr_irq_dual
= {
569 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
570 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
571 .ov5
= SPAPR_OV5_XIVE_BOTH
,
573 .init
= spapr_irq_init_dual
,
574 .claim
= spapr_irq_claim_dual
,
575 .free
= spapr_irq_free_dual
,
576 .qirq
= spapr_qirq_dual
,
577 .print_info
= spapr_irq_print_info_dual
,
578 .dt_populate
= spapr_irq_dt_populate_dual
,
579 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
580 .post_load
= spapr_irq_post_load_dual
,
581 .reset
= spapr_irq_reset_dual
,
582 .set_irq
= spapr_irq_set_irq_dual
,
583 .get_nodename
= spapr_irq_get_nodename_dual
,
587 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
589 MachineState
*machine
= MACHINE(spapr
);
592 * Sanity checks on non-P9 machines. On these, XIVE is not
593 * advertised, see spapr_dt_ov5_platform_support()
595 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
596 0, spapr
->max_compat_pvr
)) {
598 * If the 'dual' interrupt mode is selected, force XICS as CAS
599 * negotiation is useless.
601 if (spapr
->irq
== &spapr_irq_dual
) {
602 spapr
->irq
= &spapr_irq_xics
;
607 * Non-P9 machines using only XIVE is a bogus setup. We have two
608 * scenarios to take into account because of the compat mode:
610 * 1. POWER7/8 machines should fail to init later on when creating
611 * the XIVE interrupt presenters because a POWER9 exception
614 * 2. POWER9 machines using the POWER8 compat mode won't fail and
615 * will let the OS boot with a partial XIVE setup : DT
616 * properties but no hcalls.
618 * To cover both and not confuse the OS, add an early failure in
621 if (spapr
->irq
== &spapr_irq_xive
) {
622 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
629 * sPAPR IRQ frontend routines for devices
631 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
633 MachineState
*machine
= MACHINE(spapr
);
634 Error
*local_err
= NULL
;
636 if (machine_kernel_irqchip_split(machine
)) {
637 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
641 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
643 "kernel_irqchip requested but only available with KVM");
647 spapr_irq_check(spapr
, &local_err
);
649 error_propagate(errp
, local_err
);
653 /* Initialize the MSI IRQ allocator. */
654 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
655 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
658 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
660 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
661 spapr
->irq
->nr_irqs
);
664 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
666 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
669 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
671 spapr
->irq
->free(spapr
, irq
, num
);
674 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
676 return spapr
->irq
->qirq(spapr
, irq
);
679 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
681 return spapr
->irq
->post_load(spapr
, version_id
);
684 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
686 if (spapr
->irq
->reset
) {
687 spapr
->irq
->reset(spapr
, errp
);
691 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
693 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
696 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
698 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
699 fdt_strerror(offset
));
703 phandle
= fdt_get_phandle(fdt
, offset
);
705 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
713 * XICS legacy routines - to deprecate one day
716 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
720 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
721 if (num
> (ics
->nr_irqs
- first
)) {
724 for (i
= first
; i
< first
+ num
; ++i
) {
725 if (!ICS_IRQ_FREE(ics
, i
)) {
729 if (i
== (first
+ num
)) {
737 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
739 ICSState
*ics
= spapr
->ics
;
745 * MSIMesage::data is used for storing VIRQ so
746 * it has to be aligned to num to support multiple
747 * MSI vectors. MSI-X is not affected by this.
748 * The hint is used for the first IRQ, the rest should
749 * be allocated continuously.
752 assert((num
== 1) || (num
== 2) || (num
== 4) ||
753 (num
== 8) || (num
== 16) || (num
== 32));
754 first
= ics_find_free_block(ics
, num
, num
);
756 first
= ics_find_free_block(ics
, num
, 1);
760 error_setg(errp
, "can't find a free %d-IRQ block", num
);
764 return first
+ ics
->offset
;
767 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
769 SpaprIrq spapr_irq_xics_legacy
= {
770 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
771 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
772 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
774 .init
= spapr_irq_init_xics
,
775 .claim
= spapr_irq_claim_xics
,
776 .free
= spapr_irq_free_xics
,
777 .qirq
= spapr_qirq_xics
,
778 .print_info
= spapr_irq_print_info_xics
,
779 .dt_populate
= spapr_dt_xics
,
780 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
781 .post_load
= spapr_irq_post_load_xics
,
782 .set_irq
= spapr_irq_set_irq_xics
,
783 .get_nodename
= spapr_irq_get_nodename_xics
,