hw/dma/puv3_dma.c

   1 /*
   2  * DMA device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14
  15 #undef DEBUG_PUV3
  16 #include "hw/unicore32/puv3.h"
  17 #include "qemu/module.h"
  18 #include "qemu/log.h"
  19
  20 #define PUV3_DMA_CH_NR          (6)
  21 #define PUV3_DMA_CH_MASK        (0xff)
  22 #define PUV3_DMA_CH(offset)     ((offset) >> 8)
  23
  24 #define TYPE_PUV3_DMA "puv3_dma"
  25 #define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
  26
  27 typedef struct PUV3DMAState {
  28     SysBusDevice parent_obj;
  29
  30     MemoryRegion iomem;
  31     uint32_t reg_CFG[PUV3_DMA_CH_NR];
  32 } PUV3DMAState;
  33
  34 static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
  35         unsigned size)
  36 {
  37     PUV3DMAState *s = opaque;
  38     uint32_t ret = 0;
  39
  40     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  41
  42     switch (offset & PUV3_DMA_CH_MASK) {
  43     case 0x10:
  44         ret = s->reg_CFG[PUV3_DMA_CH(offset)];
  45         break;
  46     default:
  47         qemu_log_mask(LOG_GUEST_ERROR,
  48                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  49                       __func__, offset);
  50     }
  51     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  52
  53     return ret;
  54 }
  55
  56 static void puv3_dma_write(void *opaque, hwaddr offset,
  57         uint64_t value, unsigned size)
  58 {
  59     PUV3DMAState *s = opaque;
  60
  61     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  62
  63     switch (offset & PUV3_DMA_CH_MASK) {
  64     case 0x10:
  65         s->reg_CFG[PUV3_DMA_CH(offset)] = value;
  66         break;
  67     default:
  68         qemu_log_mask(LOG_GUEST_ERROR,
  69                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  70                       __func__, offset);
  71     }
  72     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  73 }
  74
  75 static const MemoryRegionOps puv3_dma_ops = {
  76     .read = puv3_dma_read,
  77     .write = puv3_dma_write,
  78     .impl = {
  79         .min_access_size = 4,
  80         .max_access_size = 4,
  81     },
  82     .endianness = DEVICE_NATIVE_ENDIAN,
  83 };
  84
  85 static void puv3_dma_realize(DeviceState *dev, Error **errp)
  86 {
  87     PUV3DMAState *s = PUV3_DMA(dev);
  88     int i;
  89
  90     for (i = 0; i < PUV3_DMA_CH_NR; i++) {
  91         s->reg_CFG[i] = 0x0;
  92     }
  93
  94     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
  95             PUV3_REGS_OFFSET);
  96     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
  97 }
  98
  99 static void puv3_dma_class_init(ObjectClass *klass, void *data)
 100 {
 101     DeviceClass *dc = DEVICE_CLASS(klass);
 102
 103     dc->realize = puv3_dma_realize;
 104 }
 105
 106 static const TypeInfo puv3_dma_info = {
 107     .name = TYPE_PUV3_DMA,
 108     .parent = TYPE_SYS_BUS_DEVICE,
 109     .instance_size = sizeof(PUV3DMAState),
 110     .class_init = puv3_dma_class_init,
 111 };
 112
 113 static void puv3_dma_register_type(void)
 114 {
 115     type_register_static(&puv3_dma_info);
 116 }
 117
 118 type_init(puv3_dma_register_type)