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switch_tss fix (aka spoon OS bug)
[qemu/ar7.git] / cpu-exec.c
blob740037e4bb34166a222142a18d3428591b47e78f
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #ifndef TARGET_SPARC
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 T0 = 0;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
151 T0 = 0;
152 }
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
156 return tb;
157 }
158
159 static inline TranslationBlock *tb_find_fast(void)
160 {
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
163 unsigned int flags;
164
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
167 is executed. */
168 #if defined(TARGET_I386)
169 flags = env->hflags;
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
176 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
177 flags |= (1 << 6);
178 cs_base = 0;
179 pc = env->regs[15];
180 #elif defined(TARGET_SPARC)
181 #ifdef TARGET_SPARC64
182 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK);
195 cs_base = 0;
196 pc = env->PC;
197 #else
198 #error unsupported CPU
199 #endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 }
205 return tb;
206 }
207
208
209 /* main execution loop */
210
211 int cpu_exec(CPUState *env1)
212 {
213 int saved_T0, saved_T1;
214 #if defined(reg_T2)
215 int saved_T2;
216 #endif
217 CPUState *saved_env;
218 #if defined(TARGET_I386)
219 #ifdef reg_EAX
220 int saved_EAX;
221 #endif
222 #ifdef reg_ECX
223 int saved_ECX;
224 #endif
225 #ifdef reg_EDX
226 int saved_EDX;
227 #endif
228 #ifdef reg_EBX
229 int saved_EBX;
230 #endif
231 #ifdef reg_ESP
232 int saved_ESP;
233 #endif
234 #ifdef reg_EBP
235 int saved_EBP;
236 #endif
237 #ifdef reg_ESI
238 int saved_ESI;
239 #endif
240 #ifdef reg_EDI
241 int saved_EDI;
242 #endif
243 #elif defined(TARGET_SPARC)
244 #if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246 #endif
247 #endif
248 #ifdef __sparc__
249 int saved_i7, tmp_T0;
250 #endif
251 int ret, interrupt_request;
252 void (*gen_func)(void);
253 TranslationBlock *tb;
254 uint8_t *tc_ptr;
255
256 #if defined(TARGET_I386)
257 /* handle exit of HALTED state */
258 if (env1->hflags & HF_HALTED_MASK) {
259 /* disable halt condition */
260 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
261 (env1->eflags & IF_MASK)) {
262 env1->hflags &= ~HF_HALTED_MASK;
263 } else {
264 return EXCP_HALTED;
265 }
266 }
267 #elif defined(TARGET_PPC)
268 if (env1->halted) {
269 if (env1->msr[MSR_EE] &&
270 (env1->interrupt_request &
271 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
272 env1->halted = 0;
273 } else {
274 return EXCP_HALTED;
275 }
276 }
277 #elif defined(TARGET_SPARC)
278 if (env1->halted) {
279 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
280 (env1->psret != 0)) {
281 env1->halted = 0;
282 } else {
283 return EXCP_HALTED;
284 }
285 }
286 #elif defined(TARGET_ARM)
287 if (env1->halted) {
288 /* An interrupt wakes the CPU even if the I and F CPSR bits are
289 set. */
290 if (env1->interrupt_request
291 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
292 env1->halted = 0;
293 } else {
294 return EXCP_HALTED;
295 }
296 }
297 #elif defined(TARGET_MIPS)
298 if (env1->halted) {
299 if (env1->interrupt_request &
300 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
301 env1->halted = 0;
302 } else {
303 return EXCP_HALTED;
304 }
305 }
306 #endif
307
308 cpu_single_env = env1;
309
310 /* first we save global registers */
311 saved_env = env;
312 env = env1;
313 saved_T0 = T0;
314 saved_T1 = T1;
315 #if defined(reg_T2)
316 saved_T2 = T2;
317 #endif
318 #ifdef __sparc__
319 /* we also save i7 because longjmp may not restore it */
320 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
321 #endif
322
323 #if defined(TARGET_I386)
324 #ifdef reg_EAX
325 saved_EAX = EAX;
326 #endif
327 #ifdef reg_ECX
328 saved_ECX = ECX;
329 #endif
330 #ifdef reg_EDX
331 saved_EDX = EDX;
332 #endif
333 #ifdef reg_EBX
334 saved_EBX = EBX;
335 #endif
336 #ifdef reg_ESP
337 saved_ESP = ESP;
338 #endif
339 #ifdef reg_EBP
340 saved_EBP = EBP;
341 #endif
342 #ifdef reg_ESI
343 saved_ESI = ESI;
344 #endif
345 #ifdef reg_EDI
346 saved_EDI = EDI;
347 #endif
348
349 env_to_regs();
350 /* put eflags in CPU temporary format */
351 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
352 DF = 1 - (2 * ((env->eflags >> 10) & 1));
353 CC_OP = CC_OP_EFLAGS;
354 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
355 #elif defined(TARGET_ARM)
356 #elif defined(TARGET_SPARC)
357 #if defined(reg_REGWPTR)
358 saved_regwptr = REGWPTR;
359 #endif
360 #elif defined(TARGET_PPC)
361 #elif defined(TARGET_MIPS)
362 #else
363 #error unsupported target CPU
364 #endif
365 env->exception_index = -1;
366
367 /* prepare setjmp context for exception handling */
368 for(;;) {
369 if (setjmp(env->jmp_env) == 0) {
370 env->current_tb = NULL;
371 /* if an exception is pending, we execute it here */
372 if (env->exception_index >= 0) {
373 if (env->exception_index >= EXCP_INTERRUPT) {
374 /* exit request from the cpu execution loop */
375 ret = env->exception_index;
376 break;
377 } else if (env->user_mode_only) {
378 /* if user mode only, we simulate a fake exception
379 which will be hanlded outside the cpu execution
380 loop */
381 #if defined(TARGET_I386)
382 do_interrupt_user(env->exception_index,
383 env->exception_is_int,
384 env->error_code,
385 env->exception_next_eip);
386 #endif
387 ret = env->exception_index;
388 break;
389 } else {
390 #if defined(TARGET_I386)
391 /* simulate a real cpu exception. On i386, it can
392 trigger new exceptions, but we do not handle
393 double or triple faults yet. */
394 do_interrupt(env->exception_index,
395 env->exception_is_int,
396 env->error_code,
397 env->exception_next_eip, 0);
398 #elif defined(TARGET_PPC)
399 do_interrupt(env);
400 #elif defined(TARGET_MIPS)
401 do_interrupt(env);
402 #elif defined(TARGET_SPARC)
403 do_interrupt(env->exception_index);
404 #elif defined(TARGET_ARM)
405 do_interrupt(env);
406 #endif
407 }
408 env->exception_index = -1;
409 }
410 #ifdef USE_KQEMU
411 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
412 int ret;
413 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
414 ret = kqemu_cpu_exec(env);
415 /* put eflags in CPU temporary format */
416 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
417 DF = 1 - (2 * ((env->eflags >> 10) & 1));
418 CC_OP = CC_OP_EFLAGS;
419 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
420 if (ret == 1) {
421 /* exception */
422 longjmp(env->jmp_env, 1);
423 } else if (ret == 2) {
424 /* softmmu execution needed */
425 } else {
426 if (env->interrupt_request != 0) {
427 /* hardware interrupt will be executed just after */
428 } else {
429 /* otherwise, we restart */
430 longjmp(env->jmp_env, 1);
431 }
432 }
433 }
434 #endif
435
436 T0 = 0; /* force lookup of first TB */
437 for(;;) {
438 #ifdef __sparc__
439 /* g1 can be modified by some libc? functions */
440 tmp_T0 = T0;
441 #endif
442 interrupt_request = env->interrupt_request;
443 if (__builtin_expect(interrupt_request, 0)) {
444 #if defined(TARGET_I386)
445 /* if hardware interrupt pending, we execute it */
446 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
447 (env->eflags & IF_MASK) &&
448 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
449 int intno;
450 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
451 intno = cpu_get_pic_interrupt(env);
452 if (loglevel & CPU_LOG_TB_IN_ASM) {
453 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
454 }
455 do_interrupt(intno, 0, 0, 0, 1);
456 /* ensure that no TB jump will be modified as
457 the program flow was changed */
458 #ifdef __sparc__
459 tmp_T0 = 0;
460 #else
461 T0 = 0;
462 #endif
463 }
464 #elif defined(TARGET_PPC)
465 #if 0
466 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
467 cpu_ppc_reset(env);
468 }
469 #endif
470 if (msr_ee != 0) {
471 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
472 /* Raise it */
473 env->exception_index = EXCP_EXTERNAL;
474 env->error_code = 0;
475 do_interrupt(env);
476 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
477 #ifdef __sparc__
478 tmp_T0 = 0;
479 #else
480 T0 = 0;
481 #endif
482 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
483 /* Raise it */
484 env->exception_index = EXCP_DECR;
485 env->error_code = 0;
486 do_interrupt(env);
487 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
488 #ifdef __sparc__
489 tmp_T0 = 0;
490 #else
491 T0 = 0;
492 #endif
493 }
494 }
495 #elif defined(TARGET_MIPS)
496 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
497 (env->CP0_Status & (1 << CP0St_IE)) &&
498 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
499 !(env->hflags & MIPS_HFLAG_EXL) &&
500 !(env->hflags & MIPS_HFLAG_ERL) &&
501 !(env->hflags & MIPS_HFLAG_DM)) {
502 /* Raise it */
503 env->exception_index = EXCP_EXT_INTERRUPT;
504 env->error_code = 0;
505 do_interrupt(env);
506 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
507 #ifdef __sparc__
508 tmp_T0 = 0;
509 #else
510 T0 = 0;
511 #endif
512 }
513 #elif defined(TARGET_SPARC)
514 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
515 (env->psret != 0)) {
516 int pil = env->interrupt_index & 15;
517 int type = env->interrupt_index & 0xf0;
518
519 if (((type == TT_EXTINT) &&
520 (pil == 15 || pil > env->psrpil)) ||
521 type != TT_EXTINT) {
522 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
523 do_interrupt(env->interrupt_index);
524 env->interrupt_index = 0;
525 #ifdef __sparc__
526 tmp_T0 = 0;
527 #else
528 T0 = 0;
529 #endif
530 }
531 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
532 //do_interrupt(0, 0, 0, 0, 0);
533 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
534 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
535 env1->halted = 1;
536 return EXCP_HALTED;
537 }
538 #elif defined(TARGET_ARM)
539 if (interrupt_request & CPU_INTERRUPT_FIQ
540 && !(env->uncached_cpsr & CPSR_F)) {
541 env->exception_index = EXCP_FIQ;
542 do_interrupt(env);
543 }
544 if (interrupt_request & CPU_INTERRUPT_HARD
545 && !(env->uncached_cpsr & CPSR_I)) {
546 env->exception_index = EXCP_IRQ;
547 do_interrupt(env);
548 }
549 #endif
550 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
551 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
552 /* ensure that no TB jump will be modified as
553 the program flow was changed */
554 #ifdef __sparc__
555 tmp_T0 = 0;
556 #else
557 T0 = 0;
558 #endif
559 }
560 if (interrupt_request & CPU_INTERRUPT_EXIT) {
561 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
562 env->exception_index = EXCP_INTERRUPT;
563 cpu_loop_exit();
564 }
565 }
566 #ifdef DEBUG_EXEC
567 if ((loglevel & CPU_LOG_TB_CPU)) {
568 #if defined(TARGET_I386)
569 /* restore flags in standard format */
570 #ifdef reg_EAX
571 env->regs[R_EAX] = EAX;
572 #endif
573 #ifdef reg_EBX
574 env->regs[R_EBX] = EBX;
575 #endif
576 #ifdef reg_ECX
577 env->regs[R_ECX] = ECX;
578 #endif
579 #ifdef reg_EDX
580 env->regs[R_EDX] = EDX;
581 #endif
582 #ifdef reg_ESI
583 env->regs[R_ESI] = ESI;
584 #endif
585 #ifdef reg_EDI
586 env->regs[R_EDI] = EDI;
587 #endif
588 #ifdef reg_EBP
589 env->regs[R_EBP] = EBP;
590 #endif
591 #ifdef reg_ESP
592 env->regs[R_ESP] = ESP;
593 #endif
594 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
595 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
596 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
597 #elif defined(TARGET_ARM)
598 cpu_dump_state(env, logfile, fprintf, 0);
599 #elif defined(TARGET_SPARC)
600 REGWPTR = env->regbase + (env->cwp * 16);
601 env->regwptr = REGWPTR;
602 cpu_dump_state(env, logfile, fprintf, 0);
603 #elif defined(TARGET_PPC)
604 cpu_dump_state(env, logfile, fprintf, 0);
605 #elif defined(TARGET_MIPS)
606 cpu_dump_state(env, logfile, fprintf, 0);
607 #else
608 #error unsupported target CPU
609 #endif
610 }
611 #endif
612 tb = tb_find_fast();
613 #ifdef DEBUG_EXEC
614 if ((loglevel & CPU_LOG_EXEC)) {
615 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
616 (long)tb->tc_ptr, tb->pc,
617 lookup_symbol(tb->pc));
618 }
619 #endif
620 #ifdef __sparc__
621 T0 = tmp_T0;
622 #endif
623 /* see if we can patch the calling TB. When the TB
624 spans two pages, we cannot safely do a direct
625 jump. */
626 {
627 if (T0 != 0 &&
628 tb->page_addr[1] == -1
629 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
630 && (tb->cflags & CF_CODE_COPY) ==
631 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
632 #endif
633 ) {
634 spin_lock(&tb_lock);
635 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
636 #if defined(USE_CODE_COPY)
637 /* propagates the FP use info */
638 ((TranslationBlock *)(T0 & ~3))->cflags |=
639 (tb->cflags & CF_FP_USED);
640 #endif
641 spin_unlock(&tb_lock);
642 }
643 }
644 tc_ptr = tb->tc_ptr;
645 env->current_tb = tb;
646 /* execute the generated code */
647 gen_func = (void *)tc_ptr;
648 #if defined(__sparc__)
649 __asm__ __volatile__("call %0\n\t"
650 "mov %%o7,%%i0"
651 : /* no outputs */
652 : "r" (gen_func)
653 : "i0", "i1", "i2", "i3", "i4", "i5");
654 #elif defined(__arm__)
655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
657 "exec_loop:\n\t"
658 : /* no outputs */
659 : "r" (gen_func)
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
661 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
662 {
663 if (!(tb->cflags & CF_CODE_COPY)) {
664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
666 }
667 gen_func();
668 } else {
669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
671 }
672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
676 "\n"
677 "debug1:\n"
678 " pushl %%ebp\n"
679 " fs movl %10, %9\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
683 " pushl %%eax\n"
684 " popf\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
694 " fs jmp *%9\n"
695 "exec_loop:\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
705 " pushf\n"
706 " popl %%eax\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
709 " shrl $9, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
712 " movl $1, %%eax\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
716 " popl %%ebp\n"
717 :
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
728 "a" (gen_func),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
731 : "%ecx", "%edx"
732 );
733 }
734 }
735 #elif defined(__ia64)
736 struct fptr {
737 void *ip;
738 void *gp;
739 } fp;
740
741 fp.ip = tc_ptr;
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
744 #else
745 gen_func();
746 #endif
747 env->current_tb = NULL;
748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
753 /* do not allow linking to another block */
754 T0 = 0;
755 }
756 #endif
757 }
758 } else {
759 env_to_regs();
760 }
761 } /* for(;;) */
762
763
764 #if defined(TARGET_I386)
765 #if defined(USE_CODE_COPY)
766 if (env->native_fp_regs) {
767 save_native_fp_state(env);
768 }
769 #endif
770 /* restore flags in standard format */
771 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
772
773 /* restore global registers */
774 #ifdef reg_EAX
775 EAX = saved_EAX;
776 #endif
777 #ifdef reg_ECX
778 ECX = saved_ECX;
779 #endif
780 #ifdef reg_EDX
781 EDX = saved_EDX;
782 #endif
783 #ifdef reg_EBX
784 EBX = saved_EBX;
785 #endif
786 #ifdef reg_ESP
787 ESP = saved_ESP;
788 #endif
789 #ifdef reg_EBP
790 EBP = saved_EBP;
791 #endif
792 #ifdef reg_ESI
793 ESI = saved_ESI;
794 #endif
795 #ifdef reg_EDI
796 EDI = saved_EDI;
797 #endif
798 #elif defined(TARGET_ARM)
799 /* XXX: Save/restore host fpu exception state?. */
800 #elif defined(TARGET_SPARC)
801 #if defined(reg_REGWPTR)
802 REGWPTR = saved_regwptr;
803 #endif
804 #elif defined(TARGET_PPC)
805 #elif defined(TARGET_MIPS)
806 #else
807 #error unsupported target CPU
808 #endif
809 #ifdef __sparc__
810 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
811 #endif
812 T0 = saved_T0;
813 T1 = saved_T1;
814 #if defined(reg_T2)
815 T2 = saved_T2;
816 #endif
817 env = saved_env;
818 /* fail safe : never use cpu_single_env outside cpu_exec() */
819 cpu_single_env = NULL;
820 return ret;
821 }
822
823 /* must only be called from the generated code as an exception can be
824 generated */
825 void tb_invalidate_page_range(target_ulong start, target_ulong end)
826 {
827 /* XXX: cannot enable it yet because it yields to MMU exception
828 where NIP != read address on PowerPC */
829 #if 0
830 target_ulong phys_addr;
831 phys_addr = get_phys_addr_code(env, start);
832 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
833 #endif
834 }
835
836 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
837
838 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
839 {
840 CPUX86State *saved_env;
841
842 saved_env = env;
843 env = s;
844 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
845 selector &= 0xffff;
846 cpu_x86_load_seg_cache(env, seg_reg, selector,
847 (selector << 4), 0xffff, 0);
848 } else {
849 load_seg(seg_reg, selector);
850 }
851 env = saved_env;
852 }
853
854 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
855 {
856 CPUX86State *saved_env;
857
858 saved_env = env;
859 env = s;
860
861 helper_fsave((target_ulong)ptr, data32);
862
863 env = saved_env;
864 }
865
866 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
867 {
868 CPUX86State *saved_env;
869
870 saved_env = env;
871 env = s;
872
873 helper_frstor((target_ulong)ptr, data32);
874
875 env = saved_env;
876 }
877
878 #endif /* TARGET_I386 */
879
880 #if !defined(CONFIG_SOFTMMU)
881
882 #if defined(TARGET_I386)
883
884 /* 'pc' is the host PC at which the exception was raised. 'address' is
885 the effective address of the memory exception. 'is_write' is 1 if a
886 write caused the exception and otherwise 0'. 'old_set' is the
887 signal set which should be restored */
888 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
889 int is_write, sigset_t *old_set,
890 void *puc)
891 {
892 TranslationBlock *tb;
893 int ret;
894
895 if (cpu_single_env)
896 env = cpu_single_env; /* XXX: find a correct solution for multithread */
897 #if defined(DEBUG_SIGNAL)
898 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
899 pc, address, is_write, *(unsigned long *)old_set);
900 #endif
901 /* XXX: locking issue */
902 if (is_write && page_unprotect(address, pc, puc)) {
903 return 1;
904 }
905
906 /* see if it is an MMU fault */
907 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
908 ((env->hflags & HF_CPL_MASK) == 3), 0);
909 if (ret < 0)
910 return 0; /* not an MMU fault */
911 if (ret == 0)
912 return 1; /* the MMU fault was handled without causing real CPU fault */
913 /* now we have a real cpu fault */
914 tb = tb_find_pc(pc);
915 if (tb) {
916 /* the PC is inside the translated code. It means that we have
917 a virtual CPU fault */
918 cpu_restore_state(tb, env, pc, puc);
919 }
920 if (ret == 1) {
921 #if 0
922 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
923 env->eip, env->cr[2], env->error_code);
924 #endif
925 /* we restore the process signal mask as the sigreturn should
926 do it (XXX: use sigsetjmp) */
927 sigprocmask(SIG_SETMASK, old_set, NULL);
928 raise_exception_err(env->exception_index, env->error_code);
929 } else {
930 /* activate soft MMU for this block */
931 env->hflags |= HF_SOFTMMU_MASK;
932 cpu_resume_from_signal(env, puc);
933 }
934 /* never comes here */
935 return 1;
936 }
937
938 #elif defined(TARGET_ARM)
939 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
940 int is_write, sigset_t *old_set,
941 void *puc)
942 {
943 TranslationBlock *tb;
944 int ret;
945
946 if (cpu_single_env)
947 env = cpu_single_env; /* XXX: find a correct solution for multithread */
948 #if defined(DEBUG_SIGNAL)
949 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
950 pc, address, is_write, *(unsigned long *)old_set);
951 #endif
952 /* XXX: locking issue */
953 if (is_write && page_unprotect(address, pc, puc)) {
954 return 1;
955 }
956 /* see if it is an MMU fault */
957 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
958 if (ret < 0)
959 return 0; /* not an MMU fault */
960 if (ret == 0)
961 return 1; /* the MMU fault was handled without causing real CPU fault */
962 /* now we have a real cpu fault */
963 tb = tb_find_pc(pc);
964 if (tb) {
965 /* the PC is inside the translated code. It means that we have
966 a virtual CPU fault */
967 cpu_restore_state(tb, env, pc, puc);
968 }
969 /* we restore the process signal mask as the sigreturn should
970 do it (XXX: use sigsetjmp) */
971 sigprocmask(SIG_SETMASK, old_set, NULL);
972 cpu_loop_exit();
973 }
974 #elif defined(TARGET_SPARC)
975 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
976 int is_write, sigset_t *old_set,
977 void *puc)
978 {
979 TranslationBlock *tb;
980 int ret;
981
982 if (cpu_single_env)
983 env = cpu_single_env; /* XXX: find a correct solution for multithread */
984 #if defined(DEBUG_SIGNAL)
985 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
986 pc, address, is_write, *(unsigned long *)old_set);
987 #endif
988 /* XXX: locking issue */
989 if (is_write && page_unprotect(address, pc, puc)) {
990 return 1;
991 }
992 /* see if it is an MMU fault */
993 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
994 if (ret < 0)
995 return 0; /* not an MMU fault */
996 if (ret == 0)
997 return 1; /* the MMU fault was handled without causing real CPU fault */
998 /* now we have a real cpu fault */
999 tb = tb_find_pc(pc);
1000 if (tb) {
1001 /* the PC is inside the translated code. It means that we have
1002 a virtual CPU fault */
1003 cpu_restore_state(tb, env, pc, puc);
1004 }
1005 /* we restore the process signal mask as the sigreturn should
1006 do it (XXX: use sigsetjmp) */
1007 sigprocmask(SIG_SETMASK, old_set, NULL);
1008 cpu_loop_exit();
1009 }
1010 #elif defined (TARGET_PPC)
1011 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1012 int is_write, sigset_t *old_set,
1013 void *puc)
1014 {
1015 TranslationBlock *tb;
1016 int ret;
1017
1018 if (cpu_single_env)
1019 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1020 #if defined(DEBUG_SIGNAL)
1021 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1022 pc, address, is_write, *(unsigned long *)old_set);
1023 #endif
1024 /* XXX: locking issue */
1025 if (is_write && page_unprotect(address, pc, puc)) {
1026 return 1;
1027 }
1028
1029 /* see if it is an MMU fault */
1030 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1031 if (ret < 0)
1032 return 0; /* not an MMU fault */
1033 if (ret == 0)
1034 return 1; /* the MMU fault was handled without causing real CPU fault */
1035
1036 /* now we have a real cpu fault */
1037 tb = tb_find_pc(pc);
1038 if (tb) {
1039 /* the PC is inside the translated code. It means that we have
1040 a virtual CPU fault */
1041 cpu_restore_state(tb, env, pc, puc);
1042 }
1043 if (ret == 1) {
1044 #if 0
1045 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1046 env->nip, env->error_code, tb);
1047 #endif
1048 /* we restore the process signal mask as the sigreturn should
1049 do it (XXX: use sigsetjmp) */
1050 sigprocmask(SIG_SETMASK, old_set, NULL);
1051 do_raise_exception_err(env->exception_index, env->error_code);
1052 } else {
1053 /* activate soft MMU for this block */
1054 cpu_resume_from_signal(env, puc);
1055 }
1056 /* never comes here */
1057 return 1;
1058 }
1059
1060 #elif defined (TARGET_MIPS)
1061 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1062 int is_write, sigset_t *old_set,
1063 void *puc)
1064 {
1065 TranslationBlock *tb;
1066 int ret;
1067
1068 if (cpu_single_env)
1069 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1070 #if defined(DEBUG_SIGNAL)
1071 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1072 pc, address, is_write, *(unsigned long *)old_set);
1073 #endif
1074 /* XXX: locking issue */
1075 if (is_write && page_unprotect(address, pc, puc)) {
1076 return 1;
1077 }
1078
1079 /* see if it is an MMU fault */
1080 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1081 if (ret < 0)
1082 return 0; /* not an MMU fault */
1083 if (ret == 0)
1084 return 1; /* the MMU fault was handled without causing real CPU fault */
1085
1086 /* now we have a real cpu fault */
1087 tb = tb_find_pc(pc);
1088 if (tb) {
1089 /* the PC is inside the translated code. It means that we have
1090 a virtual CPU fault */
1091 cpu_restore_state(tb, env, pc, puc);
1092 }
1093 if (ret == 1) {
1094 #if 0
1095 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1096 env->nip, env->error_code, tb);
1097 #endif
1098 /* we restore the process signal mask as the sigreturn should
1099 do it (XXX: use sigsetjmp) */
1100 sigprocmask(SIG_SETMASK, old_set, NULL);
1101 do_raise_exception_err(env->exception_index, env->error_code);
1102 } else {
1103 /* activate soft MMU for this block */
1104 cpu_resume_from_signal(env, puc);
1105 }
1106 /* never comes here */
1107 return 1;
1108 }
1109
1110 #else
1111 #error unsupported target CPU
1112 #endif
1113
1114 #if defined(__i386__)
1115
1116 #if defined(USE_CODE_COPY)
1117 static void cpu_send_trap(unsigned long pc, int trap,
1118 struct ucontext *uc)
1119 {
1120 TranslationBlock *tb;
1121
1122 if (cpu_single_env)
1123 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1124 /* now we have a real cpu fault */
1125 tb = tb_find_pc(pc);
1126 if (tb) {
1127 /* the PC is inside the translated code. It means that we have
1128 a virtual CPU fault */
1129 cpu_restore_state(tb, env, pc, uc);
1130 }
1131 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1132 raise_exception_err(trap, env->error_code);
1133 }
1134 #endif
1135
1136 int cpu_signal_handler(int host_signum, struct siginfo *info,
1137 void *puc)
1138 {
1139 struct ucontext *uc = puc;
1140 unsigned long pc;
1141 int trapno;
1142
1143 #ifndef REG_EIP
1144 /* for glibc 2.1 */
1145 #define REG_EIP EIP
1146 #define REG_ERR ERR
1147 #define REG_TRAPNO TRAPNO
1148 #endif
1149 pc = uc->uc_mcontext.gregs[REG_EIP];
1150 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1151 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1152 if (trapno == 0x00 || trapno == 0x05) {
1153 /* send division by zero or bound exception */
1154 cpu_send_trap(pc, trapno, uc);
1155 return 1;
1156 } else
1157 #endif
1158 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1159 trapno == 0xe ?
1160 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1161 &uc->uc_sigmask, puc);
1162 }
1163
1164 #elif defined(__x86_64__)
1165
1166 int cpu_signal_handler(int host_signum, struct siginfo *info,
1167 void *puc)
1168 {
1169 struct ucontext *uc = puc;
1170 unsigned long pc;
1171
1172 pc = uc->uc_mcontext.gregs[REG_RIP];
1173 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1174 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1175 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1176 &uc->uc_sigmask, puc);
1177 }
1178
1179 #elif defined(__powerpc__)
1180
1181 /***********************************************************************
1182 * signal context platform-specific definitions
1183 * From Wine
1184 */
1185 #ifdef linux
1186 /* All Registers access - only for local access */
1187 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1188 /* Gpr Registers access */
1189 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1190 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1191 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1192 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1193 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1194 # define LR_sig(context) REG_sig(link, context) /* Link register */
1195 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1196 /* Float Registers access */
1197 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1198 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1199 /* Exception Registers access */
1200 # define DAR_sig(context) REG_sig(dar, context)
1201 # define DSISR_sig(context) REG_sig(dsisr, context)
1202 # define TRAP_sig(context) REG_sig(trap, context)
1203 #endif /* linux */
1204
1205 #ifdef __APPLE__
1206 # include <sys/ucontext.h>
1207 typedef struct ucontext SIGCONTEXT;
1208 /* All Registers access - only for local access */
1209 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1210 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1211 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1212 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1213 /* Gpr Registers access */
1214 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1215 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1216 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1217 # define CTR_sig(context) REG_sig(ctr, context)
1218 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1219 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1220 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1221 /* Float Registers access */
1222 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1223 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1224 /* Exception Registers access */
1225 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1226 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1227 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1228 #endif /* __APPLE__ */
1229
1230 int cpu_signal_handler(int host_signum, struct siginfo *info,
1231 void *puc)
1232 {
1233 struct ucontext *uc = puc;
1234 unsigned long pc;
1235 int is_write;
1236
1237 pc = IAR_sig(uc);
1238 is_write = 0;
1239 #if 0
1240 /* ppc 4xx case */
1241 if (DSISR_sig(uc) & 0x00800000)
1242 is_write = 1;
1243 #else
1244 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1245 is_write = 1;
1246 #endif
1247 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1248 is_write, &uc->uc_sigmask, puc);
1249 }
1250
1251 #elif defined(__alpha__)
1252
1253 int cpu_signal_handler(int host_signum, struct siginfo *info,
1254 void *puc)
1255 {
1256 struct ucontext *uc = puc;
1257 uint32_t *pc = uc->uc_mcontext.sc_pc;
1258 uint32_t insn = *pc;
1259 int is_write = 0;
1260
1261 /* XXX: need kernel patch to get write flag faster */
1262 switch (insn >> 26) {
1263 case 0x0d: // stw
1264 case 0x0e: // stb
1265 case 0x0f: // stq_u
1266 case 0x24: // stf
1267 case 0x25: // stg
1268 case 0x26: // sts
1269 case 0x27: // stt
1270 case 0x2c: // stl
1271 case 0x2d: // stq
1272 case 0x2e: // stl_c
1273 case 0x2f: // stq_c
1274 is_write = 1;
1275 }
1276
1277 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1278 is_write, &uc->uc_sigmask, puc);
1279 }
1280 #elif defined(__sparc__)
1281
1282 int cpu_signal_handler(int host_signum, struct siginfo *info,
1283 void *puc)
1284 {
1285 uint32_t *regs = (uint32_t *)(info + 1);
1286 void *sigmask = (regs + 20);
1287 unsigned long pc;
1288 int is_write;
1289 uint32_t insn;
1290
1291 /* XXX: is there a standard glibc define ? */
1292 pc = regs[1];
1293 /* XXX: need kernel patch to get write flag faster */
1294 is_write = 0;
1295 insn = *(uint32_t *)pc;
1296 if ((insn >> 30) == 3) {
1297 switch((insn >> 19) & 0x3f) {
1298 case 0x05: // stb
1299 case 0x06: // sth
1300 case 0x04: // st
1301 case 0x07: // std
1302 case 0x24: // stf
1303 case 0x27: // stdf
1304 case 0x25: // stfsr
1305 is_write = 1;
1306 break;
1307 }
1308 }
1309 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1310 is_write, sigmask, NULL);
1311 }
1312
1313 #elif defined(__arm__)
1314
1315 int cpu_signal_handler(int host_signum, struct siginfo *info,
1316 void *puc)
1317 {
1318 struct ucontext *uc = puc;
1319 unsigned long pc;
1320 int is_write;
1321
1322 pc = uc->uc_mcontext.gregs[R15];
1323 /* XXX: compute is_write */
1324 is_write = 0;
1325 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1326 is_write,
1327 &uc->uc_sigmask);
1328 }
1329
1330 #elif defined(__mc68000)
1331
1332 int cpu_signal_handler(int host_signum, struct siginfo *info,
1333 void *puc)
1334 {
1335 struct ucontext *uc = puc;
1336 unsigned long pc;
1337 int is_write;
1338
1339 pc = uc->uc_mcontext.gregs[16];
1340 /* XXX: compute is_write */
1341 is_write = 0;
1342 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1343 is_write,
1344 &uc->uc_sigmask, puc);
1345 }
1346
1347 #elif defined(__ia64)
1348
1349 #ifndef __ISR_VALID
1350 /* This ought to be in <bits/siginfo.h>... */
1351 # define __ISR_VALID 1
1352 # define si_flags _sifields._sigfault._si_pad0
1353 #endif
1354
1355 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1356 {
1357 struct ucontext *uc = puc;
1358 unsigned long ip;
1359 int is_write = 0;
1360
1361 ip = uc->uc_mcontext.sc_ip;
1362 switch (host_signum) {
1363 case SIGILL:
1364 case SIGFPE:
1365 case SIGSEGV:
1366 case SIGBUS:
1367 case SIGTRAP:
1368 if (info->si_code && (info->si_flags & __ISR_VALID))
1369 /* ISR.W (write-access) is bit 33: */
1370 is_write = (info->si_isr >> 33) & 1;
1371 break;
1372
1373 default:
1374 break;
1375 }
1376 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1377 is_write,
1378 &uc->uc_sigmask, puc);
1379 }
1380
1381 #elif defined(__s390__)
1382
1383 int cpu_signal_handler(int host_signum, struct siginfo *info,
1384 void *puc)
1385 {
1386 struct ucontext *uc = puc;
1387 unsigned long pc;
1388 int is_write;
1389
1390 pc = uc->uc_mcontext.psw.addr;
1391 /* XXX: compute is_write */
1392 is_write = 0;
1393 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1394 is_write,
1395 &uc->uc_sigmask, puc);
1396 }
1397
1398 #else
1399
1400 #error host CPU specific signal handler needed
1401
1402 #endif
1403
1404 #endif /* !defined(CONFIG_SOFTMMU) */
AR7 emulation for QEMU