block: Add strong_runtime_opts to BlockDriver
[qemu/ar7.git] / hw / timer / puv3_ost.c
blob3be58c7fdd7835cb38156fdfba62983f65780f13
1 /*
2 * OSTimer device simulation in PKUnity SoC
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
12 #include "hw/sysbus.h"
13 #include "hw/ptimer.h"
14 #include "qemu/main-loop.h"
16 #undef DEBUG_PUV3
17 #include "hw/unicore32/puv3.h"
19 #define TYPE_PUV3_OST "puv3_ost"
20 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
22 /* puv3 ostimer implementation. */
23 typedef struct PUV3OSTState {
24 SysBusDevice parent_obj;
26 MemoryRegion iomem;
27 QEMUBH *bh;
28 qemu_irq irq;
29 ptimer_state *ptimer;
31 uint32_t reg_OSMR0;
32 uint32_t reg_OSCR;
33 uint32_t reg_OSSR;
34 uint32_t reg_OIER;
35 } PUV3OSTState;
37 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
38 unsigned size)
40 PUV3OSTState *s = opaque;
41 uint32_t ret = 0;
43 switch (offset) {
44 case 0x10: /* Counter Register */
45 ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
46 break;
47 case 0x14: /* Status Register */
48 ret = s->reg_OSSR;
49 break;
50 case 0x1c: /* Interrupt Enable Register */
51 ret = s->reg_OIER;
52 break;
53 default:
54 DPRINTF("Bad offset %x\n", (int)offset);
56 DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
57 return ret;
60 static void puv3_ost_write(void *opaque, hwaddr offset,
61 uint64_t value, unsigned size)
63 PUV3OSTState *s = opaque;
65 DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
66 switch (offset) {
67 case 0x00: /* Match Register 0 */
68 s->reg_OSMR0 = value;
69 if (s->reg_OSMR0 > s->reg_OSCR) {
70 ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
71 } else {
72 ptimer_set_count(s->ptimer, s->reg_OSMR0 +
73 (0xffffffff - s->reg_OSCR));
75 ptimer_run(s->ptimer, 2);
76 break;
77 case 0x14: /* Status Register */
78 assert(value == 0);
79 if (s->reg_OSSR) {
80 s->reg_OSSR = value;
81 qemu_irq_lower(s->irq);
83 break;
84 case 0x1c: /* Interrupt Enable Register */
85 s->reg_OIER = value;
86 break;
87 default:
88 DPRINTF("Bad offset %x\n", (int)offset);
92 static const MemoryRegionOps puv3_ost_ops = {
93 .read = puv3_ost_read,
94 .write = puv3_ost_write,
95 .impl = {
96 .min_access_size = 4,
97 .max_access_size = 4,
99 .endianness = DEVICE_NATIVE_ENDIAN,
102 static void puv3_ost_tick(void *opaque)
104 PUV3OSTState *s = opaque;
106 DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
107 s->reg_OSCR, s->reg_OSMR0);
109 s->reg_OSCR = s->reg_OSMR0;
110 if (s->reg_OIER) {
111 s->reg_OSSR = 1;
112 qemu_irq_raise(s->irq);
116 static void puv3_ost_realize(DeviceState *dev, Error **errp)
118 PUV3OSTState *s = PUV3_OST(dev);
119 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
121 s->reg_OIER = 0;
122 s->reg_OSSR = 0;
123 s->reg_OSMR0 = 0;
124 s->reg_OSCR = 0;
126 sysbus_init_irq(sbd, &s->irq);
128 s->bh = qemu_bh_new(puv3_ost_tick, s);
129 s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
130 ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
132 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
133 PUV3_REGS_OFFSET);
134 sysbus_init_mmio(sbd, &s->iomem);
137 static void puv3_ost_class_init(ObjectClass *klass, void *data)
139 DeviceClass *dc = DEVICE_CLASS(klass);
141 dc->realize = puv3_ost_realize;
144 static const TypeInfo puv3_ost_info = {
145 .name = TYPE_PUV3_OST,
146 .parent = TYPE_SYS_BUS_DEVICE,
147 .instance_size = sizeof(PUV3OSTState),
148 .class_init = puv3_ost_class_init,
151 static void puv3_ost_register_type(void)
153 type_register_static(&puv3_ost_info);
156 type_init(puv3_ost_register_type)