2 * QEMU 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "qemu/timer.h"
27 #include "hw/timer/i8254.h"
28 #include "hw/timer/i8254_internal.h"
32 #define RW_STATE_LSB 1
33 #define RW_STATE_MSB 2
34 #define RW_STATE_WORD0 3
35 #define RW_STATE_WORD1 4
37 #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
38 #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
40 typedef struct PITClass
{
41 PITCommonClass parent_class
;
43 DeviceRealize parent_realize
;
46 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
);
48 static int pit_get_count(PITChannelState
*s
)
53 d
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->count_load_time
, PIT_FREQ
,
54 NANOSECONDS_PER_SECOND
);
60 counter
= (s
->count
- d
) & 0xffff;
63 /* XXX: may be incorrect for odd counts */
64 counter
= s
->count
- ((2 * d
) % s
->count
);
67 counter
= s
->count
- (d
% s
->count
);
73 /* val must be 0 or 1 */
74 static void pit_set_channel_gate(PITCommonState
*s
, PITChannelState
*sc
,
81 /* XXX: just disable/enable counting */
86 /* restart counting on rising edge */
87 sc
->count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
88 pit_irq_timer_update(sc
, sc
->count_load_time
);
94 /* restart counting on rising edge */
95 sc
->count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
96 pit_irq_timer_update(sc
, sc
->count_load_time
);
98 /* XXX: disable/enable counting */
104 static inline void pit_load_count(PITChannelState
*s
, int val
)
108 s
->count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
110 pit_irq_timer_update(s
, s
->count_load_time
);
113 /* if already latched, do not latch again */
114 static void pit_latch_count(PITChannelState
*s
)
116 if (!s
->count_latched
) {
117 s
->latched_count
= pit_get_count(s
);
118 s
->count_latched
= s
->rw_mode
;
122 static void pit_ioport_write(void *opaque
, hwaddr addr
,
123 uint64_t val
, unsigned size
)
125 PITCommonState
*pit
= opaque
;
133 /* read back command */
134 for(channel
= 0; channel
< 3; channel
++) {
135 s
= &pit
->channels
[channel
];
136 if (val
& (2 << channel
)) {
140 if (!(val
& 0x10) && !s
->status_latched
) {
142 /* XXX: add BCD and null count */
145 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
)) << 7) |
149 s
->status_latched
= 1;
154 s
= &pit
->channels
[channel
];
155 access
= (val
>> 4) & 3;
160 s
->read_state
= access
;
161 s
->write_state
= access
;
163 s
->mode
= (val
>> 1) & 7;
165 /* XXX: update irq timer ? */
169 s
= &pit
->channels
[addr
];
170 switch(s
->write_state
) {
173 pit_load_count(s
, val
);
176 pit_load_count(s
, val
<< 8);
179 s
->write_latch
= val
;
180 s
->write_state
= RW_STATE_WORD1
;
183 pit_load_count(s
, s
->write_latch
| (val
<< 8));
184 s
->write_state
= RW_STATE_WORD0
;
190 static uint64_t pit_ioport_read(void *opaque
, hwaddr addr
,
193 PITCommonState
*pit
= opaque
;
200 /* Mode/Command register is write only, read is ignored */
204 s
= &pit
->channels
[addr
];
205 if (s
->status_latched
) {
206 s
->status_latched
= 0;
208 } else if (s
->count_latched
) {
209 switch(s
->count_latched
) {
212 ret
= s
->latched_count
& 0xff;
213 s
->count_latched
= 0;
216 ret
= s
->latched_count
>> 8;
217 s
->count_latched
= 0;
220 ret
= s
->latched_count
& 0xff;
221 s
->count_latched
= RW_STATE_MSB
;
225 switch(s
->read_state
) {
228 count
= pit_get_count(s
);
232 count
= pit_get_count(s
);
233 ret
= (count
>> 8) & 0xff;
236 count
= pit_get_count(s
);
238 s
->read_state
= RW_STATE_WORD1
;
241 count
= pit_get_count(s
);
242 ret
= (count
>> 8) & 0xff;
243 s
->read_state
= RW_STATE_WORD0
;
250 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
)
255 if (!s
->irq_timer
|| s
->irq_disabled
) {
258 expire_time
= pit_get_next_transition_time(s
, current_time
);
259 irq_level
= pit_get_out(s
, current_time
);
260 qemu_set_irq(s
->irq
, irq_level
);
262 printf("irq_level=%d next_delay=%f\n",
264 (double)(expire_time
- current_time
) / NANOSECONDS_PER_SECOND
);
266 s
->next_transition_time
= expire_time
;
267 if (expire_time
!= -1)
268 timer_mod(s
->irq_timer
, expire_time
);
270 timer_del(s
->irq_timer
);
273 static void pit_irq_timer(void *opaque
)
275 PITChannelState
*s
= opaque
;
277 pit_irq_timer_update(s
, s
->next_transition_time
);
280 static void pit_reset(DeviceState
*dev
)
282 PITCommonState
*pit
= PIT_COMMON(dev
);
285 pit_reset_common(pit
);
287 s
= &pit
->channels
[0];
288 if (!s
->irq_disabled
) {
289 timer_mod(s
->irq_timer
, s
->next_transition_time
);
293 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
294 * reenable it when legacy mode is left again. */
295 static void pit_irq_control(void *opaque
, int n
, int enable
)
297 PITCommonState
*pit
= opaque
;
298 PITChannelState
*s
= &pit
->channels
[0];
302 pit_irq_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
305 timer_del(s
->irq_timer
);
309 static const MemoryRegionOps pit_ioport_ops
= {
310 .read
= pit_ioport_read
,
311 .write
= pit_ioport_write
,
313 .min_access_size
= 1,
314 .max_access_size
= 1,
316 .endianness
= DEVICE_LITTLE_ENDIAN
,
319 static void pit_post_load(PITCommonState
*s
)
321 PITChannelState
*sc
= &s
->channels
[0];
323 if (sc
->next_transition_time
!= -1) {
324 timer_mod(sc
->irq_timer
, sc
->next_transition_time
);
326 timer_del(sc
->irq_timer
);
330 static void pit_realizefn(DeviceState
*dev
, Error
**errp
)
332 PITCommonState
*pit
= PIT_COMMON(dev
);
333 PITClass
*pc
= PIT_GET_CLASS(dev
);
336 s
= &pit
->channels
[0];
337 /* the timer 0 is connected to an IRQ */
338 s
->irq_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, pit_irq_timer
, s
);
339 qdev_init_gpio_out(dev
, &s
->irq
, 1);
341 memory_region_init_io(&pit
->ioports
, OBJECT(pit
), &pit_ioport_ops
,
344 qdev_init_gpio_in(dev
, pit_irq_control
, 1);
346 pc
->parent_realize(dev
, errp
);
349 static Property pit_properties
[] = {
350 DEFINE_PROP_UINT32("iobase", PITCommonState
, iobase
, -1),
351 DEFINE_PROP_END_OF_LIST(),
354 static void pit_class_initfn(ObjectClass
*klass
, void *data
)
356 PITClass
*pc
= PIT_CLASS(klass
);
357 PITCommonClass
*k
= PIT_COMMON_CLASS(klass
);
358 DeviceClass
*dc
= DEVICE_CLASS(klass
);
360 device_class_set_parent_realize(dc
, pit_realizefn
, &pc
->parent_realize
);
361 k
->set_channel_gate
= pit_set_channel_gate
;
362 k
->get_channel_info
= pit_get_channel_info_common
;
363 k
->post_load
= pit_post_load
;
364 dc
->reset
= pit_reset
;
365 dc
->props
= pit_properties
;
368 static const TypeInfo pit_info
= {
370 .parent
= TYPE_PIT_COMMON
,
371 .instance_size
= sizeof(PITCommonState
),
372 .class_init
= pit_class_initfn
,
373 .class_size
= sizeof(PITClass
),
376 static void pit_register_types(void)
378 type_register_static(&pit_info
);
381 type_init(pit_register_types
)