target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31
  32 #define CPUArchState struct CPUS390XState
  33
  34 #include "exec/cpu-defs.h"
  35 #define TARGET_PAGE_BITS 12
  36
  37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  39
  40 #include "exec/cpu-all.h"
  41
  42 #include "fpu/softfloat.h"
  43
  44 #define NB_MMU_MODES 3
  45
  46 #define MMU_MODE0_SUFFIX _primary
  47 #define MMU_MODE1_SUFFIX _secondary
  48 #define MMU_MODE2_SUFFIX _home
  49
  50 #define MMU_USER_IDX 1
  51
  52 #define MAX_EXT_QUEUE 16
  53 #define MAX_IO_QUEUE 16
  54 #define MAX_MCHK_QUEUE 16
  55
  56 #define PSW_MCHK_MASK 0x0004000000000000
  57 #define PSW_IO_MASK 0x0200000000000000
  58
  59 typedef struct PSW {
  60     uint64_t mask;
  61     uint64_t addr;
  62 } PSW;
  63
  64 typedef struct ExtQueue {
  65     uint32_t code;
  66     uint32_t param;
  67     uint32_t param64;
  68 } ExtQueue;
  69
  70 typedef struct IOIntQueue {
  71     uint16_t id;
  72     uint16_t nr;
  73     uint32_t parm;
  74     uint32_t word;
  75 } IOIntQueue;
  76
  77 typedef struct MchkQueue {
  78     uint16_t type;
  79 } MchkQueue;
  80
  81 typedef struct CPUS390XState {
  82     uint64_t regs[16];     /* GP registers */
  83     CPU_DoubleU fregs[16]; /* FP registers */
  84     uint32_t aregs[16];    /* access registers */
  85
  86     uint32_t fpc;          /* floating-point control register */
  87     uint32_t cc_op;
  88
  89     float_status fpu_status; /* passed to softfloat lib */
  90
  91     /* The low part of a 128-bit return, or remainder of a divide.  */
  92     uint64_t retxl;
  93
  94     PSW psw;
  95
  96     uint64_t cc_src;
  97     uint64_t cc_dst;
  98     uint64_t cc_vr;
  99
 100     uint64_t __excp_addr;
 101     uint64_t psa;
 102
 103     uint32_t int_pgm_code;
 104     uint32_t int_pgm_ilen;
 105
 106     uint32_t int_svc_code;
 107     uint32_t int_svc_ilen;
 108
 109     uint64_t cregs[16]; /* control registers */
 110
 111     ExtQueue ext_queue[MAX_EXT_QUEUE];
 112     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 113     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 114
 115     int pending_int;
 116     int ext_index;
 117     int io_index[8];
 118     int mchk_index;
 119
 120     uint64_t ckc;
 121     uint64_t cputm;
 122     uint32_t todpr;
 123
 124     CPU_COMMON
 125
 126     /* reset does memset(0) up to here */
 127
 128     int cpu_num;
 129     uint8_t *storage_keys;
 130
 131     uint64_t tod_offset;
 132     uint64_t tod_basetime;
 133     QEMUTimer *tod_timer;
 134
 135     QEMUTimer *cpu_timer;
 136 } CPUS390XState;
 137
 138 #include "cpu-qom.h"
 139
 140 #if defined(CONFIG_USER_ONLY)
 141 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
 142 {
 143     if (newsp) {
 144         env->regs[15] = newsp;
 145     }
 146     env->regs[2] = 0;
 147 }
 148 #endif
 149
 150 /* distinguish between 24 bit and 31 bit addressing */
 151 #define HIGH_ORDER_BIT 0x80000000
 152
 153 /* Interrupt Codes */
 154 /* Program Interrupts */
 155 #define PGM_OPERATION                   0x0001
 156 #define PGM_PRIVILEGED                  0x0002
 157 #define PGM_EXECUTE                     0x0003
 158 #define PGM_PROTECTION                  0x0004
 159 #define PGM_ADDRESSING                  0x0005
 160 #define PGM_SPECIFICATION               0x0006
 161 #define PGM_DATA                        0x0007
 162 #define PGM_FIXPT_OVERFLOW              0x0008
 163 #define PGM_FIXPT_DIVIDE                0x0009
 164 #define PGM_DEC_OVERFLOW                0x000a
 165 #define PGM_DEC_DIVIDE                  0x000b
 166 #define PGM_HFP_EXP_OVERFLOW            0x000c
 167 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 168 #define PGM_HFP_SIGNIFICANCE            0x000e
 169 #define PGM_HFP_DIVIDE                  0x000f
 170 #define PGM_SEGMENT_TRANS               0x0010
 171 #define PGM_PAGE_TRANS                  0x0011
 172 #define PGM_TRANS_SPEC                  0x0012
 173 #define PGM_SPECIAL_OP                  0x0013
 174 #define PGM_OPERAND                     0x0015
 175 #define PGM_TRACE_TABLE                 0x0016
 176 #define PGM_SPACE_SWITCH                0x001c
 177 #define PGM_HFP_SQRT                    0x001d
 178 #define PGM_PC_TRANS_SPEC               0x001f
 179 #define PGM_AFX_TRANS                   0x0020
 180 #define PGM_ASX_TRANS                   0x0021
 181 #define PGM_LX_TRANS                    0x0022
 182 #define PGM_EX_TRANS                    0x0023
 183 #define PGM_PRIM_AUTH                   0x0024
 184 #define PGM_SEC_AUTH                    0x0025
 185 #define PGM_ALET_SPEC                   0x0028
 186 #define PGM_ALEN_SPEC                   0x0029
 187 #define PGM_ALE_SEQ                     0x002a
 188 #define PGM_ASTE_VALID                  0x002b
 189 #define PGM_ASTE_SEQ                    0x002c
 190 #define PGM_EXT_AUTH                    0x002d
 191 #define PGM_STACK_FULL                  0x0030
 192 #define PGM_STACK_EMPTY                 0x0031
 193 #define PGM_STACK_SPEC                  0x0032
 194 #define PGM_STACK_TYPE                  0x0033
 195 #define PGM_STACK_OP                    0x0034
 196 #define PGM_ASCE_TYPE                   0x0038
 197 #define PGM_REG_FIRST_TRANS             0x0039
 198 #define PGM_REG_SEC_TRANS               0x003a
 199 #define PGM_REG_THIRD_TRANS             0x003b
 200 #define PGM_MONITOR                     0x0040
 201 #define PGM_PER                         0x0080
 202 #define PGM_CRYPTO                      0x0119
 203
 204 /* External Interrupts */
 205 #define EXT_INTERRUPT_KEY               0x0040
 206 #define EXT_CLOCK_COMP                  0x1004
 207 #define EXT_CPU_TIMER                   0x1005
 208 #define EXT_MALFUNCTION                 0x1200
 209 #define EXT_EMERGENCY                   0x1201
 210 #define EXT_EXTERNAL_CALL               0x1202
 211 #define EXT_ETR                         0x1406
 212 #define EXT_SERVICE                     0x2401
 213 #define EXT_VIRTIO                      0x2603
 214
 215 /* PSW defines */
 216 #undef PSW_MASK_PER
 217 #undef PSW_MASK_DAT
 218 #undef PSW_MASK_IO
 219 #undef PSW_MASK_EXT
 220 #undef PSW_MASK_KEY
 221 #undef PSW_SHIFT_KEY
 222 #undef PSW_MASK_MCHECK
 223 #undef PSW_MASK_WAIT
 224 #undef PSW_MASK_PSTATE
 225 #undef PSW_MASK_ASC
 226 #undef PSW_MASK_CC
 227 #undef PSW_MASK_PM
 228 #undef PSW_MASK_64
 229
 230 #define PSW_MASK_PER            0x4000000000000000ULL
 231 #define PSW_MASK_DAT            0x0400000000000000ULL
 232 #define PSW_MASK_IO             0x0200000000000000ULL
 233 #define PSW_MASK_EXT            0x0100000000000000ULL
 234 #define PSW_MASK_KEY            0x00F0000000000000ULL
 235 #define PSW_SHIFT_KEY           56
 236 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 237 #define PSW_MASK_WAIT           0x0002000000000000ULL
 238 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 239 #define PSW_MASK_ASC            0x0000C00000000000ULL
 240 #define PSW_MASK_CC             0x0000300000000000ULL
 241 #define PSW_MASK_PM             0x00000F0000000000ULL
 242 #define PSW_MASK_64             0x0000000100000000ULL
 243 #define PSW_MASK_32             0x0000000080000000ULL
 244
 245 #undef PSW_ASC_PRIMARY
 246 #undef PSW_ASC_ACCREG
 247 #undef PSW_ASC_SECONDARY
 248 #undef PSW_ASC_HOME
 249
 250 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 251 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 252 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 253 #define PSW_ASC_HOME            0x0000C00000000000ULL
 254
 255 /* tb flags */
 256
 257 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 258 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 259 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 260 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 261 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 262 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 263 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 264 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 265 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 266 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 267 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 268 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 269 #define FLAG_MASK_32            0x00001000
 270
 271 static inline int cpu_mmu_index (CPUS390XState *env)
 272 {
 273     if (env->psw.mask & PSW_MASK_PSTATE) {
 274         return 1;
 275     }
 276
 277     return 0;
 278 }
 279
 280 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 281                                         target_ulong *cs_base, int *flags)
 282 {
 283     *pc = env->psw.addr;
 284     *cs_base = 0;
 285     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 286              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 287 }
 288
 289 /* While the PoO talks about ILC (a number between 1-3) what is actually
 290    stored in LowCore is shifted left one bit (an even between 2-6).  As
 291    this is the actual length of the insn and therefore more useful, that
 292    is what we want to pass around and manipulate.  To make sure that we
 293    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 294 static inline int get_ilen(uint8_t opc)
 295 {
 296     switch (opc >> 6) {
 297     case 0:
 298         return 2;
 299     case 1:
 300     case 2:
 301         return 4;
 302     default:
 303         return 6;
 304     }
 305 }
 306
 307 #ifndef CONFIG_USER_ONLY
 308 /* In several cases of runtime exceptions, we havn't recorded the true
 309    instruction length.  Use these codes when raising exceptions in order
 310    to re-compute the length by examining the insn in memory.  */
 311 #define ILEN_LATER       0x20
 312 #define ILEN_LATER_INC   0x21
 313 #endif
 314
 315 S390CPU *cpu_s390x_init(const char *cpu_model);
 316 void s390x_translate_init(void);
 317 int cpu_s390x_exec(CPUS390XState *s);
 318 void do_interrupt (CPUS390XState *env);
 319
 320 /* you can call this signal handler from your SIGBUS and SIGSEGV
 321    signal handlers to inform the virtual CPU of exceptions. non zero
 322    is returned if the signal was handled by the virtual CPU.  */
 323 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 324                            void *puc);
 325 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 326                                 int mmu_idx);
 327 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
 328
 329 #include "ioinst.h"
 330
 331 #ifndef CONFIG_USER_ONLY
 332 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 333                                    int is_write);
 334 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 335                                     int is_write);
 336 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 337 {
 338     hwaddr addr = 0;
 339     uint8_t reg;
 340
 341     reg = ipb >> 28;
 342     if (reg > 0) {
 343         addr = env->regs[reg];
 344     }
 345     addr += (ipb >> 16) & 0xfff;
 346
 347     return addr;
 348 }
 349
 350 void s390x_tod_timer(void *opaque);
 351 void s390x_cpu_timer(void *opaque);
 352
 353 int s390_virtio_hypercall(CPUS390XState *env);
 354
 355 #ifdef CONFIG_KVM
 356 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
 357 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
 358 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
 359                                  uint64_t parm64, int vm);
 360 #else
 361 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
 362 {
 363 }
 364
 365 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
 366                                        uint64_t token)
 367 {
 368 }
 369
 370 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
 371                                                uint32_t parm, uint64_t parm64,
 372                                                int vm)
 373 {
 374 }
 375 #endif
 376 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 377 void s390_add_running_cpu(S390CPU *cpu);
 378 unsigned s390_del_running_cpu(S390CPU *cpu);
 379
 380 /* service interrupts are floating therefore we must not pass an cpustate */
 381 void s390_sclp_extint(uint32_t parm);
 382
 383 /* from s390-virtio-bus */
 384 extern const hwaddr virtio_size;
 385
 386 #else
 387 static inline void s390_add_running_cpu(S390CPU *cpu)
 388 {
 389 }
 390
 391 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
 392 {
 393     return 0;
 394 }
 395 #endif
 396 void cpu_lock(void);
 397 void cpu_unlock(void);
 398
 399 typedef struct SubchDev SubchDev;
 400
 401 #ifndef CONFIG_USER_ONLY
 402 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 403                          uint16_t schid);
 404 bool css_subch_visible(SubchDev *sch);
 405 void css_conditional_io_interrupt(SubchDev *sch);
 406 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 407 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 408 int css_do_msch(SubchDev *sch, SCHIB *schib);
 409 int css_do_xsch(SubchDev *sch);
 410 int css_do_csch(SubchDev *sch);
 411 int css_do_hsch(SubchDev *sch);
 412 int css_do_ssch(SubchDev *sch, ORB *orb);
 413 int css_do_tsch(SubchDev *sch, IRB *irb);
 414 int css_do_stcrw(CRW *crw);
 415 int css_do_tpi(IOIntCode *int_code, int lowcore);
 416 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 417                          int rfmt, void *buf);
 418 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 419 int css_enable_mcsse(void);
 420 int css_enable_mss(void);
 421 int css_do_rsch(SubchDev *sch);
 422 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 423 bool css_present(uint8_t cssid);
 424 #else
 425 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 426                                        uint16_t schid)
 427 {
 428     return NULL;
 429 }
 430 static inline bool css_subch_visible(SubchDev *sch)
 431 {
 432     return false;
 433 }
 434 static inline void css_conditional_io_interrupt(SubchDev *sch)
 435 {
 436 }
 437 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 438 {
 439     return -ENODEV;
 440 }
 441 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 442 {
 443     return true;
 444 }
 445 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 446 {
 447     return -ENODEV;
 448 }
 449 static inline int css_do_xsch(SubchDev *sch)
 450 {
 451     return -ENODEV;
 452 }
 453 static inline int css_do_csch(SubchDev *sch)
 454 {
 455     return -ENODEV;
 456 }
 457 static inline int css_do_hsch(SubchDev *sch)
 458 {
 459     return -ENODEV;
 460 }
 461 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 462 {
 463     return -ENODEV;
 464 }
 465 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 466 {
 467     return -ENODEV;
 468 }
 469 static inline int css_do_stcrw(CRW *crw)
 470 {
 471     return 1;
 472 }
 473 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
 474 {
 475     return 0;
 476 }
 477 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 478                                        int rfmt, uint8_t l_chpid, void *buf)
 479 {
 480     return 0;
 481 }
 482 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 483 {
 484 }
 485 static inline int css_enable_mss(void)
 486 {
 487     return -EINVAL;
 488 }
 489 static inline int css_enable_mcsse(void)
 490 {
 491     return -EINVAL;
 492 }
 493 static inline int css_do_rsch(SubchDev *sch)
 494 {
 495     return -ENODEV;
 496 }
 497 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 498 {
 499     return -ENODEV;
 500 }
 501 static inline bool css_present(uint8_t cssid)
 502 {
 503     return false;
 504 }
 505 #endif
 506
 507 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
 508 {
 509     env->aregs[0] = newtls >> 32;
 510     env->aregs[1] = newtls & 0xffffffffULL;
 511 }
 512
 513 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 514 #define cpu_exec cpu_s390x_exec
 515 #define cpu_gen_code cpu_s390x_gen_code
 516 #define cpu_signal_handler cpu_s390x_signal_handler
 517
 518 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 519 #define cpu_list s390_cpu_list
 520
 521 #include "exec/exec-all.h"
 522
 523 #define EXCP_EXT 1 /* external interrupt */
 524 #define EXCP_SVC 2 /* supervisor call (syscall) */
 525 #define EXCP_PGM 3 /* program interruption */
 526 #define EXCP_IO  7 /* I/O interrupt */
 527 #define EXCP_MCHK 8 /* machine check */
 528
 529 #define INTERRUPT_EXT        (1 << 0)
 530 #define INTERRUPT_TOD        (1 << 1)
 531 #define INTERRUPT_CPUTIMER   (1 << 2)
 532 #define INTERRUPT_IO         (1 << 3)
 533 #define INTERRUPT_MCHK       (1 << 4)
 534
 535 /* Program Status Word.  */
 536 #define S390_PSWM_REGNUM 0
 537 #define S390_PSWA_REGNUM 1
 538 /* General Purpose Registers.  */
 539 #define S390_R0_REGNUM 2
 540 #define S390_R1_REGNUM 3
 541 #define S390_R2_REGNUM 4
 542 #define S390_R3_REGNUM 5
 543 #define S390_R4_REGNUM 6
 544 #define S390_R5_REGNUM 7
 545 #define S390_R6_REGNUM 8
 546 #define S390_R7_REGNUM 9
 547 #define S390_R8_REGNUM 10
 548 #define S390_R9_REGNUM 11
 549 #define S390_R10_REGNUM 12
 550 #define S390_R11_REGNUM 13
 551 #define S390_R12_REGNUM 14
 552 #define S390_R13_REGNUM 15
 553 #define S390_R14_REGNUM 16
 554 #define S390_R15_REGNUM 17
 555 /* Access Registers.  */
 556 #define S390_A0_REGNUM 18
 557 #define S390_A1_REGNUM 19
 558 #define S390_A2_REGNUM 20
 559 #define S390_A3_REGNUM 21
 560 #define S390_A4_REGNUM 22
 561 #define S390_A5_REGNUM 23
 562 #define S390_A6_REGNUM 24
 563 #define S390_A7_REGNUM 25
 564 #define S390_A8_REGNUM 26
 565 #define S390_A9_REGNUM 27
 566 #define S390_A10_REGNUM 28
 567 #define S390_A11_REGNUM 29
 568 #define S390_A12_REGNUM 30
 569 #define S390_A13_REGNUM 31
 570 #define S390_A14_REGNUM 32
 571 #define S390_A15_REGNUM 33
 572 /* Floating Point Control Word.  */
 573 #define S390_FPC_REGNUM 34
 574 /* Floating Point Registers.  */
 575 #define S390_F0_REGNUM 35
 576 #define S390_F1_REGNUM 36
 577 #define S390_F2_REGNUM 37
 578 #define S390_F3_REGNUM 38
 579 #define S390_F4_REGNUM 39
 580 #define S390_F5_REGNUM 40
 581 #define S390_F6_REGNUM 41
 582 #define S390_F7_REGNUM 42
 583 #define S390_F8_REGNUM 43
 584 #define S390_F9_REGNUM 44
 585 #define S390_F10_REGNUM 45
 586 #define S390_F11_REGNUM 46
 587 #define S390_F12_REGNUM 47
 588 #define S390_F13_REGNUM 48
 589 #define S390_F14_REGNUM 49
 590 #define S390_F15_REGNUM 50
 591 /* Total.  */
 592 #define S390_NUM_REGS 51
 593
 594 /* CC optimization */
 595
 596 enum cc_op {
 597     CC_OP_CONST0 = 0,           /* CC is 0 */
 598     CC_OP_CONST1,               /* CC is 1 */
 599     CC_OP_CONST2,               /* CC is 2 */
 600     CC_OP_CONST3,               /* CC is 3 */
 601
 602     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 603     CC_OP_STATIC,               /* CC value is env->cc_op */
 604
 605     CC_OP_NZ,                   /* env->cc_dst != 0 */
 606     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 607     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 608     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 609     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 610     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 611     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 612
 613     CC_OP_ADD_64,               /* overflow on add (64bit) */
 614     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 615     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 616     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 617     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 618     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 619     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 620     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 621
 622     CC_OP_ADD_32,               /* overflow on add (32bit) */
 623     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 624     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 625     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 626     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 627     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 628     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 629     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 630
 631     CC_OP_COMP_32,              /* complement */
 632     CC_OP_COMP_64,              /* complement */
 633
 634     CC_OP_TM_32,                /* test under mask (32bit) */
 635     CC_OP_TM_64,                /* test under mask (64bit) */
 636
 637     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 638     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 639     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 640
 641     CC_OP_ICM,                  /* insert characters under mask */
 642     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 643     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 644     CC_OP_FLOGR,                /* find leftmost one */
 645     CC_OP_MAX
 646 };
 647
 648 static const char *cc_names[] = {
 649     [CC_OP_CONST0]    = "CC_OP_CONST0",
 650     [CC_OP_CONST1]    = "CC_OP_CONST1",
 651     [CC_OP_CONST2]    = "CC_OP_CONST2",
 652     [CC_OP_CONST3]    = "CC_OP_CONST3",
 653     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 654     [CC_OP_STATIC]    = "CC_OP_STATIC",
 655     [CC_OP_NZ]        = "CC_OP_NZ",
 656     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 657     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 658     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 659     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 660     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 661     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 662     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 663     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 664     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 665     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 666     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 667     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 668     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 669     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 670     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 671     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 672     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 673     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 674     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 675     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 676     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 677     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 678     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 679     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 680     [CC_OP_TM_32]     = "CC_OP_TM_32",
 681     [CC_OP_TM_64]     = "CC_OP_TM_64",
 682     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 683     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 684     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 685     [CC_OP_ICM]       = "CC_OP_ICM",
 686     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 687     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 688     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 689 };
 690
 691 static inline const char *cc_name(int cc_op)
 692 {
 693     return cc_names[cc_op];
 694 }
 695
 696 typedef struct LowCore
 697 {
 698     /* prefix area: defined by architecture */
 699     uint32_t        ccw1[2];                  /* 0x000 */
 700     uint32_t        ccw2[4];                  /* 0x008 */
 701     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 702     uint32_t        ext_params;               /* 0x080 */
 703     uint16_t        cpu_addr;                 /* 0x084 */
 704     uint16_t        ext_int_code;             /* 0x086 */
 705     uint16_t        svc_ilen;                 /* 0x088 */
 706     uint16_t        svc_code;                 /* 0x08a */
 707     uint16_t        pgm_ilen;                 /* 0x08c */
 708     uint16_t        pgm_code;                 /* 0x08e */
 709     uint32_t        data_exc_code;            /* 0x090 */
 710     uint16_t        mon_class_num;            /* 0x094 */
 711     uint16_t        per_perc_atmid;           /* 0x096 */
 712     uint64_t        per_address;              /* 0x098 */
 713     uint8_t         exc_access_id;            /* 0x0a0 */
 714     uint8_t         per_access_id;            /* 0x0a1 */
 715     uint8_t         op_access_id;             /* 0x0a2 */
 716     uint8_t         ar_access_id;             /* 0x0a3 */
 717     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 718     uint64_t        trans_exc_code;           /* 0x0a8 */
 719     uint64_t        monitor_code;             /* 0x0b0 */
 720     uint16_t        subchannel_id;            /* 0x0b8 */
 721     uint16_t        subchannel_nr;            /* 0x0ba */
 722     uint32_t        io_int_parm;              /* 0x0bc */
 723     uint32_t        io_int_word;              /* 0x0c0 */
 724     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 725     uint32_t        stfl_fac_list;            /* 0x0c8 */
 726     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 727     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 728     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 729     uint32_t        external_damage_code;     /* 0x0f4 */
 730     uint64_t        failing_storage_address;  /* 0x0f8 */
 731     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 732     PSW             restart_old_psw;          /* 0x120 */
 733     PSW             external_old_psw;         /* 0x130 */
 734     PSW             svc_old_psw;              /* 0x140 */
 735     PSW             program_old_psw;          /* 0x150 */
 736     PSW             mcck_old_psw;             /* 0x160 */
 737     PSW             io_old_psw;               /* 0x170 */
 738     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 739     PSW             restart_psw;              /* 0x1a0 */
 740     PSW             external_new_psw;         /* 0x1b0 */
 741     PSW             svc_new_psw;              /* 0x1c0 */
 742     PSW             program_new_psw;          /* 0x1d0 */
 743     PSW             mcck_new_psw;             /* 0x1e0 */
 744     PSW             io_new_psw;               /* 0x1f0 */
 745     PSW             return_psw;               /* 0x200 */
 746     uint8_t         irb[64];                  /* 0x210 */
 747     uint64_t        sync_enter_timer;         /* 0x250 */
 748     uint64_t        async_enter_timer;        /* 0x258 */
 749     uint64_t        exit_timer;               /* 0x260 */
 750     uint64_t        last_update_timer;        /* 0x268 */
 751     uint64_t        user_timer;               /* 0x270 */
 752     uint64_t        system_timer;             /* 0x278 */
 753     uint64_t        last_update_clock;        /* 0x280 */
 754     uint64_t        steal_clock;              /* 0x288 */
 755     PSW             return_mcck_psw;          /* 0x290 */
 756     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 757     /* System info area */
 758     uint64_t        save_area[16];            /* 0xc00 */
 759     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 760     uint64_t        kernel_stack;             /* 0xd40 */
 761     uint64_t        thread_info;              /* 0xd48 */
 762     uint64_t        async_stack;              /* 0xd50 */
 763     uint64_t        kernel_asce;              /* 0xd58 */
 764     uint64_t        user_asce;                /* 0xd60 */
 765     uint64_t        panic_stack;              /* 0xd68 */
 766     uint64_t        user_exec_asce;           /* 0xd70 */
 767     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 768
 769     /* SMP info area: defined by DJB */
 770     uint64_t        clock_comparator;         /* 0xdc0 */
 771     uint64_t        ext_call_fast;            /* 0xdc8 */
 772     uint64_t        percpu_offset;            /* 0xdd0 */
 773     uint64_t        current_task;             /* 0xdd8 */
 774     uint32_t        softirq_pending;          /* 0xde0 */
 775     uint32_t        pad_0x0de4;               /* 0xde4 */
 776     uint64_t        int_clock;                /* 0xde8 */
 777     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 778
 779     /* 0xe00 is used as indicator for dump tools */
 780     /* whether the kernel died with panic() or not */
 781     uint32_t        panic_magic;              /* 0xe00 */
 782
 783     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 784
 785     /* 64 bit extparam used for pfault, diag 250 etc  */
 786     uint64_t        ext_params2;               /* 0x11B8 */
 787
 788     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 789
 790     /* System info area */
 791
 792     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 793     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 794     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 795     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 796     uint32_t        prefixreg_save_area;       /* 0x1318 */
 797     uint32_t        fpt_creg_save_area;        /* 0x131c */
 798     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 799     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 800     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 801     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 802     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 803     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 804     uint64_t        cregs_save_area[16];       /* 0x1380 */
 805
 806     /* align to the top of the prefix area */
 807
 808     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 809 } QEMU_PACKED LowCore;
 810
 811 /* STSI */
 812 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 813 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 814 #define STSI_LEVEL_1            0x0000000010000000ULL
 815 #define STSI_LEVEL_2            0x0000000020000000ULL
 816 #define STSI_LEVEL_3            0x0000000030000000ULL
 817 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 818 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 819 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 820 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 821
 822 /* Basic Machine Configuration */
 823 struct sysib_111 {
 824     uint32_t res1[8];
 825     uint8_t  manuf[16];
 826     uint8_t  type[4];
 827     uint8_t  res2[12];
 828     uint8_t  model[16];
 829     uint8_t  sequence[16];
 830     uint8_t  plant[4];
 831     uint8_t  res3[156];
 832 };
 833
 834 /* Basic Machine CPU */
 835 struct sysib_121 {
 836     uint32_t res1[80];
 837     uint8_t  sequence[16];
 838     uint8_t  plant[4];
 839     uint8_t  res2[2];
 840     uint16_t cpu_addr;
 841     uint8_t  res3[152];
 842 };
 843
 844 /* Basic Machine CPUs */
 845 struct sysib_122 {
 846     uint8_t res1[32];
 847     uint32_t capability;
 848     uint16_t total_cpus;
 849     uint16_t active_cpus;
 850     uint16_t standby_cpus;
 851     uint16_t reserved_cpus;
 852     uint16_t adjustments[2026];
 853 };
 854
 855 /* LPAR CPU */
 856 struct sysib_221 {
 857     uint32_t res1[80];
 858     uint8_t  sequence[16];
 859     uint8_t  plant[4];
 860     uint16_t cpu_id;
 861     uint16_t cpu_addr;
 862     uint8_t  res3[152];
 863 };
 864
 865 /* LPAR CPUs */
 866 struct sysib_222 {
 867     uint32_t res1[32];
 868     uint16_t lpar_num;
 869     uint8_t  res2;
 870     uint8_t  lcpuc;
 871     uint16_t total_cpus;
 872     uint16_t conf_cpus;
 873     uint16_t standby_cpus;
 874     uint16_t reserved_cpus;
 875     uint8_t  name[8];
 876     uint32_t caf;
 877     uint8_t  res3[16];
 878     uint16_t dedicated_cpus;
 879     uint16_t shared_cpus;
 880     uint8_t  res4[180];
 881 };
 882
 883 /* VM CPUs */
 884 struct sysib_322 {
 885     uint8_t  res1[31];
 886     uint8_t  count;
 887     struct {
 888         uint8_t  res2[4];
 889         uint16_t total_cpus;
 890         uint16_t conf_cpus;
 891         uint16_t standby_cpus;
 892         uint16_t reserved_cpus;
 893         uint8_t  name[8];
 894         uint32_t caf;
 895         uint8_t  cpi[16];
 896         uint8_t  res3[24];
 897     } vm[8];
 898     uint8_t res4[3552];
 899 };
 900
 901 /* MMU defines */
 902 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 903 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 904 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 905 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 906 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 907 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 908 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 909 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 910 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 911 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 912 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 913 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 914
 915 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 916 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 917 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 918 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 919 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 920 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 921 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 922
 923 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 924 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 925 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 926
 927 #define _PAGE_RO        0x200            /* HW read-only bit  */
 928 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 929
 930 #define SK_C                    (0x1 << 1)
 931 #define SK_R                    (0x1 << 2)
 932 #define SK_F                    (0x1 << 3)
 933 #define SK_ACC_MASK             (0xf << 4)
 934
 935 #define SIGP_SENSE             0x01
 936 #define SIGP_EXTERNAL_CALL     0x02
 937 #define SIGP_EMERGENCY         0x03
 938 #define SIGP_START             0x04
 939 #define SIGP_STOP              0x05
 940 #define SIGP_RESTART           0x06
 941 #define SIGP_STOP_STORE_STATUS 0x09
 942 #define SIGP_INITIAL_CPU_RESET 0x0b
 943 #define SIGP_CPU_RESET         0x0c
 944 #define SIGP_SET_PREFIX        0x0d
 945 #define SIGP_STORE_STATUS_ADDR 0x0e
 946 #define SIGP_SET_ARCH          0x12
 947
 948 /* cpu status bits */
 949 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 950 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 951 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 952 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 953 #define SIGP_STAT_STOPPED           0x00000040UL
 954 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 955 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 956 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 957 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 958 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 959
 960 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 961 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 962                   target_ulong *raddr, int *flags);
 963 int sclp_service_call(uint32_t sccb, uint64_t code);
 964 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 965                  uint64_t vr);
 966
 967 #define TARGET_HAS_ICE 1
 968
 969 /* The value of the TOD clock for 1.1.1970. */
 970 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 971
 972 /* Converts ns to s390's clock format */
 973 static inline uint64_t time2tod(uint64_t ns) {
 974     return (ns << 9) / 125;
 975 }
 976
 977 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 978                                   uint64_t param64)
 979 {
 980     CPUS390XState *env = &cpu->env;
 981
 982     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 983         /* ugh - can't queue anymore. Let's drop. */
 984         return;
 985     }
 986
 987     env->ext_index++;
 988     assert(env->ext_index < MAX_EXT_QUEUE);
 989
 990     env->ext_queue[env->ext_index].code = code;
 991     env->ext_queue[env->ext_index].param = param;
 992     env->ext_queue[env->ext_index].param64 = param64;
 993
 994     env->pending_int |= INTERRUPT_EXT;
 995     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 996 }
 997
 998 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
 999                                  uint16_t subchannel_number,
1000                                  uint32_t io_int_parm, uint32_t io_int_word)
1001 {
1002     CPUS390XState *env = &cpu->env;
1003     int isc = IO_INT_WORD_ISC(io_int_word);
1004
1005     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1006         /* ugh - can't queue anymore. Let's drop. */
1007         return;
1008     }
1009
1010     env->io_index[isc]++;
1011     assert(env->io_index[isc] < MAX_IO_QUEUE);
1012
1013     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1014     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1015     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1016     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1017
1018     env->pending_int |= INTERRUPT_IO;
1019     cpu_interrupt(env, CPU_INTERRUPT_HARD);
1020 }
1021
1022 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1023 {
1024     CPUS390XState *env = &cpu->env;
1025
1026     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1027         /* ugh - can't queue anymore. Let's drop. */
1028         return;
1029     }
1030
1031     env->mchk_index++;
1032     assert(env->mchk_index < MAX_MCHK_QUEUE);
1033
1034     env->mchk_queue[env->mchk_index].type = 1;
1035
1036     env->pending_int |= INTERRUPT_MCHK;
1037     cpu_interrupt(env, CPU_INTERRUPT_HARD);
1038 }
1039
1040 static inline bool cpu_has_work(CPUState *cpu)
1041 {
1042     S390CPU *s390_cpu = S390_CPU(cpu);
1043     CPUS390XState *env = &s390_cpu->env;
1044
1045     return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1046         (env->psw.mask & PSW_MASK_EXT);
1047 }
1048
1049 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
1050 {
1051     env->psw.addr = tb->pc;
1052 }
1053
1054 /* fpu_helper.c */
1055 uint32_t set_cc_nz_f32(float32 v);
1056 uint32_t set_cc_nz_f64(float64 v);
1057 uint32_t set_cc_nz_f128(float128 v);
1058
1059 /* misc_helper.c */
1060 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1061 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1062                                      uintptr_t retaddr);
1063
1064 #include <sysemu/kvm.h>
1065
1066 #ifdef CONFIG_KVM
1067 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1068                            uint16_t subchannel_nr, uint32_t io_int_parm,
1069                            uint32_t io_int_word);
1070 void kvm_s390_crw_mchk(S390CPU *cpu);
1071 void kvm_s390_enable_css_support(S390CPU *cpu);
1072 #else
1073 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1074                                         uint16_t subchannel_id,
1075                                         uint16_t subchannel_nr,
1076                                         uint32_t io_int_parm,
1077                                         uint32_t io_int_word)
1078 {
1079 }
1080 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1081 {
1082 }
1083 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1084 {
1085 }
1086 #endif
1087
1088 static inline void s390_io_interrupt(S390CPU *cpu,
1089                                      uint16_t subchannel_id,
1090                                      uint16_t subchannel_nr,
1091                                      uint32_t io_int_parm,
1092                                      uint32_t io_int_word)
1093 {
1094     if (kvm_enabled()) {
1095         kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1096                               io_int_word);
1097     } else {
1098         cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1099                       io_int_word);
1100     }
1101 }
1102
1103 static inline void s390_crw_mchk(S390CPU *cpu)
1104 {
1105     if (kvm_enabled()) {
1106         kvm_s390_crw_mchk(cpu);
1107     } else {
1108         cpu_inject_crw_mchk(cpu);
1109     }
1110 }
1111
1112 #endif