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target/ppc: Emulate LL/SC using cmpxchg helpers
[qemu/ar7.git] / target / ppc / translate.c
blob50b6d4dcd8b915b8103486a75b8032cec9ab4586
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93 tcg_ctx.tcg_env = cpu_env;
94
95 p = cpu_reg_names;
96 cpu_reg_names_size = sizeof(cpu_reg_names);
97
98 for (i = 0; i < 8; i++) {
99 snprintf(p, cpu_reg_names_size, "crf%d", i);
100 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
101 offsetof(CPUPPCState, crf[i]), p);
102 p += 5;
103 cpu_reg_names_size -= 5;
104 }
105
106 for (i = 0; i < 32; i++) {
107 snprintf(p, cpu_reg_names_size, "r%d", i);
108 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
109 offsetof(CPUPPCState, gpr[i]), p);
110 p += (i < 10) ? 3 : 4;
111 cpu_reg_names_size -= (i < 10) ? 3 : 4;
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
114 offsetof(CPUPPCState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "fp%d", i);
119 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, fpr[i]), p);
121 p += (i < 10) ? 4 : 5;
122 cpu_reg_names_size -= (i < 10) ? 4 : 5;
123
124 snprintf(p, cpu_reg_names_size, "avr%dH", i);
125 #ifdef HOST_WORDS_BIGENDIAN
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[0]), p);
128 #else
129 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
130 offsetof(CPUPPCState, avr[i].u64[1]), p);
131 #endif
132 p += (i < 10) ? 6 : 7;
133 cpu_reg_names_size -= (i < 10) ? 6 : 7;
134
135 snprintf(p, cpu_reg_names_size, "avr%dL", i);
136 #ifdef HOST_WORDS_BIGENDIAN
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[1]), p);
139 #else
140 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
141 offsetof(CPUPPCState, avr[i].u64[0]), p);
142 #endif
143 p += (i < 10) ? 6 : 7;
144 cpu_reg_names_size -= (i < 10) ? 6 : 7;
145 snprintf(p, cpu_reg_names_size, "vsr%d", i);
146 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
147 offsetof(CPUPPCState, vsr[i]), p);
148 p += (i < 10) ? 5 : 6;
149 cpu_reg_names_size -= (i < 10) ? 5 : 6;
150 }
151
152 cpu_nip = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, nip), "nip");
154
155 cpu_msr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, msr), "msr");
157
158 cpu_ctr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, ctr), "ctr");
160
161 cpu_lr = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, lr), "lr");
163
164 #if defined(TARGET_PPC64)
165 cpu_cfar = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, cfar), "cfar");
167 #endif
168
169 cpu_xer = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, xer), "xer");
171 cpu_so = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, so), "SO");
173 cpu_ov = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ov), "OV");
175 cpu_ca = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, ca), "CA");
177 cpu_ov32 = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, ov32), "OV32");
179 cpu_ca32 = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, ca32), "CA32");
181
182 cpu_reserve = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, reserve_addr),
184 "reserve_addr");
185 cpu_reserve_val = tcg_global_mem_new(cpu_env,
186 offsetof(CPUPPCState, reserve_val),
187 "reserve_val");
188
189 cpu_fpscr = tcg_global_mem_new(cpu_env,
190 offsetof(CPUPPCState, fpscr), "fpscr");
191
192 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
193 offsetof(CPUPPCState, access_type), "access_type");
194
195 done_init = 1;
196 }
197
198 /* internal defines */
199 struct DisasContext {
200 struct TranslationBlock *tb;
201 target_ulong nip;
202 uint32_t opcode;
203 uint32_t exception;
204 /* Routine used to access memory */
205 bool pr, hv, dr, le_mode;
206 bool lazy_tlb_flush;
207 bool need_access_type;
208 int mem_idx;
209 int access_type;
210 /* Translation flags */
211 TCGMemOp default_tcg_memop_mask;
212 #if defined(TARGET_PPC64)
213 bool sf_mode;
214 bool has_cfar;
215 #endif
216 bool fpu_enabled;
217 bool altivec_enabled;
218 bool vsx_enabled;
219 bool spe_enabled;
220 bool tm_enabled;
221 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
222 int singlestep_enabled;
223 uint64_t insns_flags;
224 uint64_t insns_flags2;
225 };
226
227 /* Return true iff byteswap is needed in a scalar memop */
228 static inline bool need_byteswap(const DisasContext *ctx)
229 {
230 #if defined(TARGET_WORDS_BIGENDIAN)
231 return ctx->le_mode;
232 #else
233 return !ctx->le_mode;
234 #endif
235 }
236
237 /* True when active word size < size of target_long. */
238 #ifdef TARGET_PPC64
239 # define NARROW_MODE(C) (!(C)->sf_mode)
240 #else
241 # define NARROW_MODE(C) 0
242 #endif
243
244 struct opc_handler_t {
245 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
246 uint32_t inval1;
247 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
248 uint32_t inval2;
249 /* instruction type */
250 uint64_t type;
251 /* extended instruction type */
252 uint64_t type2;
253 /* handler */
254 void (*handler)(DisasContext *ctx);
255 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
256 const char *oname;
257 #endif
258 #if defined(DO_PPC_STATISTICS)
259 uint64_t count;
260 #endif
261 };
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->need_access_type && ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
280 {
281 TCGv_i32 t0, t1;
282
283 /* These are all synchronous exceptions, we set the PC back to
284 * the faulting instruction
285 */
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip - 4);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
291 gen_helper_raise_exception_err(cpu_env, t0, t1);
292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295 }
296
297 static void gen_exception(DisasContext *ctx, uint32_t excp)
298 {
299 TCGv_i32 t0;
300
301 /* These are all synchronous exceptions, we set the PC back to
302 * the faulting instruction
303 */
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip - 4);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
314 target_ulong nip)
315 {
316 TCGv_i32 t0;
317
318 gen_update_nip(ctx, nip);
319 t0 = tcg_const_i32(excp);
320 gen_helper_raise_exception(cpu_env, t0);
321 tcg_temp_free_i32(t0);
322 ctx->exception = (excp);
323 }
324
325 static void gen_debug_exception(DisasContext *ctx)
326 {
327 TCGv_i32 t0;
328
329 /* These are all synchronous exceptions, we set the PC back to
330 * the faulting instruction
331 */
332 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
333 (ctx->exception != POWERPC_EXCP_SYNC)) {
334 gen_update_nip(ctx, ctx->nip);
335 }
336 t0 = tcg_const_i32(EXCP_DEBUG);
337 gen_helper_raise_exception(cpu_env, t0);
338 tcg_temp_free_i32(t0);
339 }
340
341 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
342 {
343 /* Will be converted to program check if needed */
344 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
345 }
346
347 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
348 {
349 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
350 }
351
352 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
353 {
354 /* Will be converted to program check if needed */
355 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
356 }
357
358 /* Stop translation */
359 static inline void gen_stop_exception(DisasContext *ctx)
360 {
361 gen_update_nip(ctx, ctx->nip);
362 ctx->exception = POWERPC_EXCP_STOP;
363 }
364
365 #ifndef CONFIG_USER_ONLY
366 /* No need to update nip here, as execution flow will change */
367 static inline void gen_sync_exception(DisasContext *ctx)
368 {
369 ctx->exception = POWERPC_EXCP_SYNC;
370 }
371 #endif
372
373 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
374 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
375
376 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
377 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
378
379 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
380 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
381
382 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
383 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
384
385 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
386 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
387
388 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
389 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
390
391 typedef struct opcode_t {
392 unsigned char opc1, opc2, opc3, opc4;
393 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
394 unsigned char pad[4];
395 #endif
396 opc_handler_t handler;
397 const char *oname;
398 } opcode_t;
399
400 /* Helpers for priv. check */
401 #define GEN_PRIV \
402 do { \
403 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
404 } while (0)
405
406 #if defined(CONFIG_USER_ONLY)
407 #define CHK_HV GEN_PRIV
408 #define CHK_SV GEN_PRIV
409 #define CHK_HVRM GEN_PRIV
410 #else
411 #define CHK_HV \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #define CHK_SV \
418 do { \
419 if (unlikely(ctx->pr)) { \
420 GEN_PRIV; \
421 } \
422 } while (0)
423 #define CHK_HVRM \
424 do { \
425 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
426 GEN_PRIV; \
427 } \
428 } while (0)
429 #endif
430
431 #define CHK_NONE
432
433 /*****************************************************************************/
434 /* PowerPC instructions table */
435
436 #if defined(DO_PPC_STATISTICS)
437 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
438 { \
439 .opc1 = op1, \
440 .opc2 = op2, \
441 .opc3 = op3, \
442 .opc4 = 0xff, \
443 .handler = { \
444 .inval1 = invl, \
445 .type = _typ, \
446 .type2 = _typ2, \
447 .handler = &gen_##name, \
448 .oname = stringify(name), \
449 }, \
450 .oname = stringify(name), \
451 }
452 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
453 { \
454 .opc1 = op1, \
455 .opc2 = op2, \
456 .opc3 = op3, \
457 .opc4 = 0xff, \
458 .handler = { \
459 .inval1 = invl1, \
460 .inval2 = invl2, \
461 .type = _typ, \
462 .type2 = _typ2, \
463 .handler = &gen_##name, \
464 .oname = stringify(name), \
465 }, \
466 .oname = stringify(name), \
467 }
468 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
469 { \
470 .opc1 = op1, \
471 .opc2 = op2, \
472 .opc3 = op3, \
473 .opc4 = 0xff, \
474 .handler = { \
475 .inval1 = invl, \
476 .type = _typ, \
477 .type2 = _typ2, \
478 .handler = &gen_##name, \
479 .oname = onam, \
480 }, \
481 .oname = onam, \
482 }
483 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .opc4 = op4, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .opc4 = op4, \
504 .handler = { \
505 .inval1 = invl, \
506 .type = _typ, \
507 .type2 = _typ2, \
508 .handler = &gen_##name, \
509 .oname = onam, \
510 }, \
511 .oname = onam, \
512 }
513 #else
514 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .opc4 = 0xff, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 }, \
526 .oname = stringify(name), \
527 }
528 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
529 { \
530 .opc1 = op1, \
531 .opc2 = op2, \
532 .opc3 = op3, \
533 .opc4 = 0xff, \
534 .handler = { \
535 .inval1 = invl1, \
536 .inval2 = invl2, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 }, \
541 .oname = stringify(name), \
542 }
543 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
544 { \
545 .opc1 = op1, \
546 .opc2 = op2, \
547 .opc3 = op3, \
548 .opc4 = 0xff, \
549 .handler = { \
550 .inval1 = invl, \
551 .type = _typ, \
552 .type2 = _typ2, \
553 .handler = &gen_##name, \
554 }, \
555 .oname = onam, \
556 }
557 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
558 { \
559 .opc1 = op1, \
560 .opc2 = op2, \
561 .opc3 = op3, \
562 .opc4 = op4, \
563 .handler = { \
564 .inval1 = invl, \
565 .type = _typ, \
566 .type2 = _typ2, \
567 .handler = &gen_##name, \
568 }, \
569 .oname = stringify(name), \
570 }
571 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .opc4 = op4, \
577 .handler = { \
578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = onam, \
584 }
585 #endif
586
587 /* SPR load/store helpers */
588 static inline void gen_load_spr(TCGv t, int reg)
589 {
590 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
591 }
592
593 static inline void gen_store_spr(int reg, TCGv t)
594 {
595 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
596 }
597
598 /* Invalid instruction */
599 static void gen_invalid(DisasContext *ctx)
600 {
601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
602 }
603
604 static opc_handler_t invalid_handler = {
605 .inval1 = 0xFFFFFFFF,
606 .inval2 = 0xFFFFFFFF,
607 .type = PPC_NONE,
608 .type2 = PPC_NONE,
609 .handler = gen_invalid,
610 };
611
612 /*** Integer comparison ***/
613
614 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
615 {
616 TCGv t0 = tcg_temp_new();
617 TCGv_i32 t1 = tcg_temp_new_i32();
618
619 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
620
621 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
622 tcg_gen_trunc_tl_i32(t1, t0);
623 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
624 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
625
626 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
627 tcg_gen_trunc_tl_i32(t1, t0);
628 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
629 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
630
631 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
632 tcg_gen_trunc_tl_i32(t1, t0);
633 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
634 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
635
636 tcg_temp_free(t0);
637 tcg_temp_free_i32(t1);
638 }
639
640 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
641 {
642 TCGv t0 = tcg_const_tl(arg1);
643 gen_op_cmp(arg0, t0, s, crf);
644 tcg_temp_free(t0);
645 }
646
647 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
648 {
649 TCGv t0, t1;
650 t0 = tcg_temp_new();
651 t1 = tcg_temp_new();
652 if (s) {
653 tcg_gen_ext32s_tl(t0, arg0);
654 tcg_gen_ext32s_tl(t1, arg1);
655 } else {
656 tcg_gen_ext32u_tl(t0, arg0);
657 tcg_gen_ext32u_tl(t1, arg1);
658 }
659 gen_op_cmp(t0, t1, s, crf);
660 tcg_temp_free(t1);
661 tcg_temp_free(t0);
662 }
663
664 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
665 {
666 TCGv t0 = tcg_const_tl(arg1);
667 gen_op_cmp32(arg0, t0, s, crf);
668 tcg_temp_free(t0);
669 }
670
671 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
672 {
673 if (NARROW_MODE(ctx)) {
674 gen_op_cmpi32(reg, 0, 1, 0);
675 } else {
676 gen_op_cmpi(reg, 0, 1, 0);
677 }
678 }
679
680 /* cmp */
681 static void gen_cmp(DisasContext *ctx)
682 {
683 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
684 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpi */
693 static void gen_cmpi(DisasContext *ctx)
694 {
695 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
696 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
697 1, crfD(ctx->opcode));
698 } else {
699 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
700 1, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpl */
705 static void gen_cmpl(DisasContext *ctx)
706 {
707 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
708 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* cmpli */
717 static void gen_cmpli(DisasContext *ctx)
718 {
719 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
720 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
721 0, crfD(ctx->opcode));
722 } else {
723 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
724 0, crfD(ctx->opcode));
725 }
726 }
727
728 /* cmprb - range comparison: isupper, isaplha, islower*/
729 static void gen_cmprb(DisasContext *ctx)
730 {
731 TCGv_i32 src1 = tcg_temp_new_i32();
732 TCGv_i32 src2 = tcg_temp_new_i32();
733 TCGv_i32 src2lo = tcg_temp_new_i32();
734 TCGv_i32 src2hi = tcg_temp_new_i32();
735 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
736
737 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
738 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
739
740 tcg_gen_andi_i32(src1, src1, 0xFF);
741 tcg_gen_ext8u_i32(src2lo, src2);
742 tcg_gen_shri_i32(src2, src2, 8);
743 tcg_gen_ext8u_i32(src2hi, src2);
744
745 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
747 tcg_gen_and_i32(crf, src2lo, src2hi);
748
749 if (ctx->opcode & 0x00200000) {
750 tcg_gen_shri_i32(src2, src2, 8);
751 tcg_gen_ext8u_i32(src2lo, src2);
752 tcg_gen_shri_i32(src2, src2, 8);
753 tcg_gen_ext8u_i32(src2hi, src2);
754 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
755 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
756 tcg_gen_and_i32(src2lo, src2lo, src2hi);
757 tcg_gen_or_i32(crf, crf, src2lo);
758 }
759 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
760 tcg_temp_free_i32(src1);
761 tcg_temp_free_i32(src2);
762 tcg_temp_free_i32(src2lo);
763 tcg_temp_free_i32(src2hi);
764 }
765
766 #if defined(TARGET_PPC64)
767 /* cmpeqb */
768 static void gen_cmpeqb(DisasContext *ctx)
769 {
770 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773 #endif
774
775 /* isel (PowerPC 2.03 specification) */
776 static void gen_isel(DisasContext *ctx)
777 {
778 uint32_t bi = rC(ctx->opcode);
779 uint32_t mask = 0x08 >> (bi & 0x03);
780 TCGv t0 = tcg_temp_new();
781 TCGv zr;
782
783 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
784 tcg_gen_andi_tl(t0, t0, mask);
785
786 zr = tcg_const_tl(0);
787 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
788 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
789 cpu_gpr[rB(ctx->opcode)]);
790 tcg_temp_free(zr);
791 tcg_temp_free(t0);
792 }
793
794 /* cmpb: PowerPC 2.05 specification */
795 static void gen_cmpb(DisasContext *ctx)
796 {
797 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
798 cpu_gpr[rB(ctx->opcode)]);
799 }
800
801 /*** Integer arithmetic ***/
802
803 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
804 TCGv arg1, TCGv arg2, int sub)
805 {
806 TCGv t0 = tcg_temp_new();
807
808 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
809 tcg_gen_xor_tl(t0, arg1, arg2);
810 if (sub) {
811 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
812 } else {
813 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
814 }
815 tcg_temp_free(t0);
816 if (NARROW_MODE(ctx)) {
817 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
818 if (is_isa300(ctx)) {
819 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
820 }
821 } else {
822 if (is_isa300(ctx)) {
823 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
824 }
825 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
826 }
827 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
828 }
829
830 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
831 TCGv res, TCGv arg0, TCGv arg1,
832 int sub)
833 {
834 TCGv t0;
835
836 if (!is_isa300(ctx)) {
837 return;
838 }
839
840 t0 = tcg_temp_new();
841 if (sub) {
842 tcg_gen_eqv_tl(t0, arg0, arg1);
843 } else {
844 tcg_gen_xor_tl(t0, arg0, arg1);
845 }
846 tcg_gen_xor_tl(t0, t0, res);
847 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
848 tcg_temp_free(t0);
849 }
850
851 /* Common add function */
852 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
853 TCGv arg2, bool add_ca, bool compute_ca,
854 bool compute_ov, bool compute_rc0)
855 {
856 TCGv t0 = ret;
857
858 if (compute_ca || compute_ov) {
859 t0 = tcg_temp_new();
860 }
861
862 if (compute_ca) {
863 if (NARROW_MODE(ctx)) {
864 /* Caution: a non-obvious corner case of the spec is that we
865 must produce the *entire* 64-bit addition, but produce the
866 carry into bit 32. */
867 TCGv t1 = tcg_temp_new();
868 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
869 tcg_gen_add_tl(t0, arg1, arg2);
870 if (add_ca) {
871 tcg_gen_add_tl(t0, t0, cpu_ca);
872 }
873 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
874 tcg_temp_free(t1);
875 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
876 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
877 if (is_isa300(ctx)) {
878 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
879 }
880 } else {
881 TCGv zero = tcg_const_tl(0);
882 if (add_ca) {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
884 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
885 } else {
886 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
887 }
888 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
889 tcg_temp_free(zero);
890 }
891 } else {
892 tcg_gen_add_tl(t0, arg1, arg2);
893 if (add_ca) {
894 tcg_gen_add_tl(t0, t0, cpu_ca);
895 }
896 }
897
898 if (compute_ov) {
899 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
900 }
901 if (unlikely(compute_rc0)) {
902 gen_set_Rc0(ctx, t0);
903 }
904
905 if (!TCGV_EQUAL(t0, ret)) {
906 tcg_gen_mov_tl(ret, t0);
907 tcg_temp_free(t0);
908 }
909 }
910 /* Add functions with two operands */
911 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
912 static void glue(gen_, name)(DisasContext *ctx) \
913 { \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
917 }
918 /* Add functions with one operand and one immediate */
919 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
920 add_ca, compute_ca, compute_ov) \
921 static void glue(gen_, name)(DisasContext *ctx) \
922 { \
923 TCGv t0 = tcg_const_tl(const_val); \
924 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
925 cpu_gpr[rA(ctx->opcode)], t0, \
926 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
927 tcg_temp_free(t0); \
928 }
929
930 /* add add. addo addo. */
931 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
932 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
933 /* addc addc. addco addco. */
934 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
935 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
936 /* adde adde. addeo addeo. */
937 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
938 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
939 /* addme addme. addmeo addmeo. */
940 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
941 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
942 /* addze addze. addzeo addzeo.*/
943 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
944 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
945 /* addi */
946 static void gen_addi(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* li case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
955 cpu_gpr[rA(ctx->opcode)], simm);
956 }
957 }
958 /* addic addic.*/
959 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
960 {
961 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
962 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
963 c, 0, 1, 0, compute_rc0);
964 tcg_temp_free(c);
965 }
966
967 static void gen_addic(DisasContext *ctx)
968 {
969 gen_op_addic(ctx, 0);
970 }
971
972 static void gen_addic_(DisasContext *ctx)
973 {
974 gen_op_addic(ctx, 1);
975 }
976
977 /* addis */
978 static void gen_addis(DisasContext *ctx)
979 {
980 target_long simm = SIMM(ctx->opcode);
981
982 if (rA(ctx->opcode) == 0) {
983 /* lis case */
984 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
985 } else {
986 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
987 cpu_gpr[rA(ctx->opcode)], simm << 16);
988 }
989 }
990
991 /* addpcis */
992 static void gen_addpcis(DisasContext *ctx)
993 {
994 target_long d = DX(ctx->opcode);
995
996 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
997 }
998
999 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1000 TCGv arg2, int sign, int compute_ov)
1001 {
1002 TCGv_i32 t0 = tcg_temp_new_i32();
1003 TCGv_i32 t1 = tcg_temp_new_i32();
1004 TCGv_i32 t2 = tcg_temp_new_i32();
1005 TCGv_i32 t3 = tcg_temp_new_i32();
1006
1007 tcg_gen_trunc_tl_i32(t0, arg1);
1008 tcg_gen_trunc_tl_i32(t1, arg2);
1009 if (sign) {
1010 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1012 tcg_gen_and_i32(t2, t2, t3);
1013 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1014 tcg_gen_or_i32(t2, t2, t3);
1015 tcg_gen_movi_i32(t3, 0);
1016 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1017 tcg_gen_div_i32(t3, t0, t1);
1018 tcg_gen_extu_i32_tl(ret, t3);
1019 } else {
1020 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1021 tcg_gen_movi_i32(t3, 0);
1022 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1023 tcg_gen_divu_i32(t3, t0, t1);
1024 tcg_gen_extu_i32_tl(ret, t3);
1025 }
1026 if (compute_ov) {
1027 tcg_gen_extu_i32_tl(cpu_ov, t2);
1028 if (is_isa300(ctx)) {
1029 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1030 }
1031 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1032 }
1033 tcg_temp_free_i32(t0);
1034 tcg_temp_free_i32(t1);
1035 tcg_temp_free_i32(t2);
1036 tcg_temp_free_i32(t3);
1037
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 /* Div functions */
1042 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1043 static void glue(gen_, name)(DisasContext *ctx) \
1044 { \
1045 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1047 sign, compute_ov); \
1048 }
1049 /* divwu divwu. divwuo divwuo. */
1050 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1051 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1052 /* divw divw. divwo divwo. */
1053 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1054 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1055
1056 /* div[wd]eu[o][.] */
1057 #define GEN_DIVE(name, hlpr, compute_ov) \
1058 static void gen_##name(DisasContext *ctx) \
1059 { \
1060 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1061 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1063 tcg_temp_free_i32(t0); \
1064 if (unlikely(Rc(ctx->opcode) != 0)) { \
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1066 } \
1067 }
1068
1069 GEN_DIVE(divweu, divweu, 0);
1070 GEN_DIVE(divweuo, divweu, 1);
1071 GEN_DIVE(divwe, divwe, 0);
1072 GEN_DIVE(divweo, divwe, 1);
1073
1074 #if defined(TARGET_PPC64)
1075 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1076 TCGv arg2, int sign, int compute_ov)
1077 {
1078 TCGv_i64 t0 = tcg_temp_new_i64();
1079 TCGv_i64 t1 = tcg_temp_new_i64();
1080 TCGv_i64 t2 = tcg_temp_new_i64();
1081 TCGv_i64 t3 = tcg_temp_new_i64();
1082
1083 tcg_gen_mov_i64(t0, arg1);
1084 tcg_gen_mov_i64(t1, arg2);
1085 if (sign) {
1086 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1088 tcg_gen_and_i64(t2, t2, t3);
1089 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1090 tcg_gen_or_i64(t2, t2, t3);
1091 tcg_gen_movi_i64(t3, 0);
1092 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1093 tcg_gen_div_i64(ret, t0, t1);
1094 } else {
1095 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1096 tcg_gen_movi_i64(t3, 0);
1097 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1098 tcg_gen_divu_i64(ret, t0, t1);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_mov_tl(cpu_ov, t2);
1102 if (is_isa300(ctx)) {
1103 tcg_gen_mov_tl(cpu_ov32, t2);
1104 }
1105 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1106 }
1107 tcg_temp_free_i64(t0);
1108 tcg_temp_free_i64(t1);
1109 tcg_temp_free_i64(t2);
1110 tcg_temp_free_i64(t3);
1111
1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, ret);
1114 }
1115
1116 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1117 static void glue(gen_, name)(DisasContext *ctx) \
1118 { \
1119 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1121 sign, compute_ov); \
1122 }
1123 /* divdu divdu. divduo divduo. */
1124 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1125 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1126 /* divd divd. divdo divdo. */
1127 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1128 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1129
1130 GEN_DIVE(divdeu, divdeu, 0);
1131 GEN_DIVE(divdeuo, divdeu, 1);
1132 GEN_DIVE(divde, divde, 0);
1133 GEN_DIVE(divdeo, divde, 1);
1134 #endif
1135
1136 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1137 TCGv arg2, int sign)
1138 {
1139 TCGv_i32 t0 = tcg_temp_new_i32();
1140 TCGv_i32 t1 = tcg_temp_new_i32();
1141
1142 tcg_gen_trunc_tl_i32(t0, arg1);
1143 tcg_gen_trunc_tl_i32(t1, arg2);
1144 if (sign) {
1145 TCGv_i32 t2 = tcg_temp_new_i32();
1146 TCGv_i32 t3 = tcg_temp_new_i32();
1147 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1149 tcg_gen_and_i32(t2, t2, t3);
1150 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1151 tcg_gen_or_i32(t2, t2, t3);
1152 tcg_gen_movi_i32(t3, 0);
1153 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1154 tcg_gen_rem_i32(t3, t0, t1);
1155 tcg_gen_ext_i32_tl(ret, t3);
1156 tcg_temp_free_i32(t2);
1157 tcg_temp_free_i32(t3);
1158 } else {
1159 TCGv_i32 t2 = tcg_const_i32(1);
1160 TCGv_i32 t3 = tcg_const_i32(0);
1161 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162 tcg_gen_remu_i32(t3, t0, t1);
1163 tcg_gen_extu_i32_tl(ret, t3);
1164 tcg_temp_free_i32(t2);
1165 tcg_temp_free_i32(t3);
1166 }
1167 tcg_temp_free_i32(t0);
1168 tcg_temp_free_i32(t1);
1169 }
1170
1171 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1172 static void glue(gen_, name)(DisasContext *ctx) \
1173 { \
1174 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1176 sign); \
1177 }
1178
1179 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1180 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1181
1182 #if defined(TARGET_PPC64)
1183 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1184 TCGv arg2, int sign)
1185 {
1186 TCGv_i64 t0 = tcg_temp_new_i64();
1187 TCGv_i64 t1 = tcg_temp_new_i64();
1188
1189 tcg_gen_mov_i64(t0, arg1);
1190 tcg_gen_mov_i64(t1, arg2);
1191 if (sign) {
1192 TCGv_i64 t2 = tcg_temp_new_i64();
1193 TCGv_i64 t3 = tcg_temp_new_i64();
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1196 tcg_gen_and_i64(t2, t2, t3);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1198 tcg_gen_or_i64(t2, t2, t3);
1199 tcg_gen_movi_i64(t3, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1201 tcg_gen_rem_i64(ret, t0, t1);
1202 tcg_temp_free_i64(t2);
1203 tcg_temp_free_i64(t3);
1204 } else {
1205 TCGv_i64 t2 = tcg_const_i64(1);
1206 TCGv_i64 t3 = tcg_const_i64(0);
1207 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1208 tcg_gen_remu_i64(ret, t0, t1);
1209 tcg_temp_free_i64(t2);
1210 tcg_temp_free_i64(t3);
1211 }
1212 tcg_temp_free_i64(t0);
1213 tcg_temp_free_i64(t1);
1214 }
1215
1216 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1217 static void glue(gen_, name)(DisasContext *ctx) \
1218 { \
1219 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1221 sign); \
1222 }
1223
1224 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1225 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1226 #endif
1227
1228 /* mulhw mulhw. */
1229 static void gen_mulhw(DisasContext *ctx)
1230 {
1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
1233
1234 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1236 tcg_gen_muls2_i32(t0, t1, t0, t1);
1237 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1238 tcg_temp_free_i32(t0);
1239 tcg_temp_free_i32(t1);
1240 if (unlikely(Rc(ctx->opcode) != 0))
1241 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1242 }
1243
1244 /* mulhwu mulhwu. */
1245 static void gen_mulhwu(DisasContext *ctx)
1246 {
1247 TCGv_i32 t0 = tcg_temp_new_i32();
1248 TCGv_i32 t1 = tcg_temp_new_i32();
1249
1250 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1252 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1253 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1254 tcg_temp_free_i32(t0);
1255 tcg_temp_free_i32(t1);
1256 if (unlikely(Rc(ctx->opcode) != 0))
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1258 }
1259
1260 /* mullw mullw. */
1261 static void gen_mullw(DisasContext *ctx)
1262 {
1263 #if defined(TARGET_PPC64)
1264 TCGv_i64 t0, t1;
1265 t0 = tcg_temp_new_i64();
1266 t1 = tcg_temp_new_i64();
1267 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1268 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1269 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1270 tcg_temp_free(t0);
1271 tcg_temp_free(t1);
1272 #else
1273 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1274 cpu_gpr[rB(ctx->opcode)]);
1275 #endif
1276 if (unlikely(Rc(ctx->opcode) != 0))
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1278 }
1279
1280 /* mullwo mullwo. */
1281 static void gen_mullwo(DisasContext *ctx)
1282 {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i32 t1 = tcg_temp_new_i32();
1285
1286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_muls2_i32(t0, t1, t0, t1);
1289 #if defined(TARGET_PPC64)
1290 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1291 #else
1292 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1293 #endif
1294
1295 tcg_gen_sari_i32(t0, t0, 31);
1296 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1297 tcg_gen_extu_i32_tl(cpu_ov, t0);
1298 if (is_isa300(ctx)) {
1299 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1300 }
1301 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1302
1303 tcg_temp_free_i32(t0);
1304 tcg_temp_free_i32(t1);
1305 if (unlikely(Rc(ctx->opcode) != 0))
1306 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1307 }
1308
1309 /* mulli */
1310 static void gen_mulli(DisasContext *ctx)
1311 {
1312 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1313 SIMM(ctx->opcode));
1314 }
1315
1316 #if defined(TARGET_PPC64)
1317 /* mulhd mulhd. */
1318 static void gen_mulhd(DisasContext *ctx)
1319 {
1320 TCGv lo = tcg_temp_new();
1321 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1322 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1323 tcg_temp_free(lo);
1324 if (unlikely(Rc(ctx->opcode) != 0)) {
1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1326 }
1327 }
1328
1329 /* mulhdu mulhdu. */
1330 static void gen_mulhdu(DisasContext *ctx)
1331 {
1332 TCGv lo = tcg_temp_new();
1333 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1334 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1335 tcg_temp_free(lo);
1336 if (unlikely(Rc(ctx->opcode) != 0)) {
1337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1338 }
1339 }
1340
1341 /* mulld mulld. */
1342 static void gen_mulld(DisasContext *ctx)
1343 {
1344 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1345 cpu_gpr[rB(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mulldo mulldo. */
1351 static void gen_mulldo(DisasContext *ctx)
1352 {
1353 TCGv_i64 t0 = tcg_temp_new_i64();
1354 TCGv_i64 t1 = tcg_temp_new_i64();
1355
1356 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1357 cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1359
1360 tcg_gen_sari_i64(t0, t0, 63);
1361 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1362 if (is_isa300(ctx)) {
1363 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1364 }
1365 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1366
1367 tcg_temp_free_i64(t0);
1368 tcg_temp_free_i64(t1);
1369
1370 if (unlikely(Rc(ctx->opcode) != 0)) {
1371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1372 }
1373 }
1374 #endif
1375
1376 /* Common subf function */
1377 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1378 TCGv arg2, bool add_ca, bool compute_ca,
1379 bool compute_ov, bool compute_rc0)
1380 {
1381 TCGv t0 = ret;
1382
1383 if (compute_ca || compute_ov) {
1384 t0 = tcg_temp_new();
1385 }
1386
1387 if (compute_ca) {
1388 /* dest = ~arg1 + arg2 [+ ca]. */
1389 if (NARROW_MODE(ctx)) {
1390 /* Caution: a non-obvious corner case of the spec is that we
1391 must produce the *entire* 64-bit addition, but produce the
1392 carry into bit 32. */
1393 TCGv inv1 = tcg_temp_new();
1394 TCGv t1 = tcg_temp_new();
1395 tcg_gen_not_tl(inv1, arg1);
1396 if (add_ca) {
1397 tcg_gen_add_tl(t0, arg2, cpu_ca);
1398 } else {
1399 tcg_gen_addi_tl(t0, arg2, 1);
1400 }
1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1402 tcg_gen_add_tl(t0, t0, inv1);
1403 tcg_temp_free(inv1);
1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1405 tcg_temp_free(t1);
1406 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1407 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1408 if (is_isa300(ctx)) {
1409 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1410 }
1411 } else if (add_ca) {
1412 TCGv zero, inv1 = tcg_temp_new();
1413 tcg_gen_not_tl(inv1, arg1);
1414 zero = tcg_const_tl(0);
1415 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1416 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1417 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1418 tcg_temp_free(zero);
1419 tcg_temp_free(inv1);
1420 } else {
1421 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1422 tcg_gen_sub_tl(t0, arg2, arg1);
1423 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1424 }
1425 } else if (add_ca) {
1426 /* Since we're ignoring carry-out, we can simplify the
1427 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1428 tcg_gen_sub_tl(t0, arg2, arg1);
1429 tcg_gen_add_tl(t0, t0, cpu_ca);
1430 tcg_gen_subi_tl(t0, t0, 1);
1431 } else {
1432 tcg_gen_sub_tl(t0, arg2, arg1);
1433 }
1434
1435 if (compute_ov) {
1436 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1437 }
1438 if (unlikely(compute_rc0)) {
1439 gen_set_Rc0(ctx, t0);
1440 }
1441
1442 if (!TCGV_EQUAL(t0, ret)) {
1443 tcg_gen_mov_tl(ret, t0);
1444 tcg_temp_free(t0);
1445 }
1446 }
1447 /* Sub functions with Two operands functions */
1448 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1449 static void glue(gen_, name)(DisasContext *ctx) \
1450 { \
1451 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1452 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1453 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1454 }
1455 /* Sub functions with one operand and one immediate */
1456 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1457 add_ca, compute_ca, compute_ov) \
1458 static void glue(gen_, name)(DisasContext *ctx) \
1459 { \
1460 TCGv t0 = tcg_const_tl(const_val); \
1461 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1462 cpu_gpr[rA(ctx->opcode)], t0, \
1463 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1464 tcg_temp_free(t0); \
1465 }
1466 /* subf subf. subfo subfo. */
1467 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1468 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1469 /* subfc subfc. subfco subfco. */
1470 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1471 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1472 /* subfe subfe. subfeo subfo. */
1473 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1474 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1475 /* subfme subfme. subfmeo subfmeo. */
1476 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1477 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1478 /* subfze subfze. subfzeo subfzeo.*/
1479 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1480 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1481
1482 /* subfic */
1483 static void gen_subfic(DisasContext *ctx)
1484 {
1485 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1486 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1487 c, 0, 1, 0, 0);
1488 tcg_temp_free(c);
1489 }
1490
1491 /* neg neg. nego nego. */
1492 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1493 {
1494 TCGv zero = tcg_const_tl(0);
1495 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1496 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1497 tcg_temp_free(zero);
1498 }
1499
1500 static void gen_neg(DisasContext *ctx)
1501 {
1502 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1503 if (unlikely(Rc(ctx->opcode))) {
1504 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1505 }
1506 }
1507
1508 static void gen_nego(DisasContext *ctx)
1509 {
1510 gen_op_arith_neg(ctx, 1);
1511 }
1512
1513 /*** Integer logical ***/
1514 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1515 static void glue(gen_, name)(DisasContext *ctx) \
1516 { \
1517 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1518 cpu_gpr[rB(ctx->opcode)]); \
1519 if (unlikely(Rc(ctx->opcode) != 0)) \
1520 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1521 }
1522
1523 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1524 static void glue(gen_, name)(DisasContext *ctx) \
1525 { \
1526 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1527 if (unlikely(Rc(ctx->opcode) != 0)) \
1528 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1529 }
1530
1531 /* and & and. */
1532 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1533 /* andc & andc. */
1534 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1535
1536 /* andi. */
1537 static void gen_andi_(DisasContext *ctx)
1538 {
1539 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1541 }
1542
1543 /* andis. */
1544 static void gen_andis_(DisasContext *ctx)
1545 {
1546 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1547 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1548 }
1549
1550 /* cntlzw */
1551 static void gen_cntlzw(DisasContext *ctx)
1552 {
1553 TCGv_i32 t = tcg_temp_new_i32();
1554
1555 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1556 tcg_gen_clzi_i32(t, t, 32);
1557 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1558 tcg_temp_free_i32(t);
1559
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563
1564 /* cnttzw */
1565 static void gen_cnttzw(DisasContext *ctx)
1566 {
1567 TCGv_i32 t = tcg_temp_new_i32();
1568
1569 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1570 tcg_gen_ctzi_i32(t, t, 32);
1571 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1572 tcg_temp_free_i32(t);
1573
1574 if (unlikely(Rc(ctx->opcode) != 0)) {
1575 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1576 }
1577 }
1578
1579 /* eqv & eqv. */
1580 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1581 /* extsb & extsb. */
1582 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1583 /* extsh & extsh. */
1584 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1585 /* nand & nand. */
1586 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1587 /* nor & nor. */
1588 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1589
1590 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1591 static void gen_pause(DisasContext *ctx)
1592 {
1593 TCGv_i32 t0 = tcg_const_i32(0);
1594 tcg_gen_st_i32(t0, cpu_env,
1595 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1596 tcg_temp_free_i32(t0);
1597
1598 /* Stop translation, this gives other CPUs a chance to run */
1599 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1600 }
1601 #endif /* defined(TARGET_PPC64) */
1602
1603 /* or & or. */
1604 static void gen_or(DisasContext *ctx)
1605 {
1606 int rs, ra, rb;
1607
1608 rs = rS(ctx->opcode);
1609 ra = rA(ctx->opcode);
1610 rb = rB(ctx->opcode);
1611 /* Optimisation for mr. ri case */
1612 if (rs != ra || rs != rb) {
1613 if (rs != rb)
1614 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1615 else
1616 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1617 if (unlikely(Rc(ctx->opcode) != 0))
1618 gen_set_Rc0(ctx, cpu_gpr[ra]);
1619 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1620 gen_set_Rc0(ctx, cpu_gpr[rs]);
1621 #if defined(TARGET_PPC64)
1622 } else if (rs != 0) { /* 0 is nop */
1623 int prio = 0;
1624
1625 switch (rs) {
1626 case 1:
1627 /* Set process priority to low */
1628 prio = 2;
1629 break;
1630 case 6:
1631 /* Set process priority to medium-low */
1632 prio = 3;
1633 break;
1634 case 2:
1635 /* Set process priority to normal */
1636 prio = 4;
1637 break;
1638 #if !defined(CONFIG_USER_ONLY)
1639 case 31:
1640 if (!ctx->pr) {
1641 /* Set process priority to very low */
1642 prio = 1;
1643 }
1644 break;
1645 case 5:
1646 if (!ctx->pr) {
1647 /* Set process priority to medium-hight */
1648 prio = 5;
1649 }
1650 break;
1651 case 3:
1652 if (!ctx->pr) {
1653 /* Set process priority to high */
1654 prio = 6;
1655 }
1656 break;
1657 case 7:
1658 if (ctx->hv && !ctx->pr) {
1659 /* Set process priority to very high */
1660 prio = 7;
1661 }
1662 break;
1663 #endif
1664 default:
1665 break;
1666 }
1667 if (prio) {
1668 TCGv t0 = tcg_temp_new();
1669 gen_load_spr(t0, SPR_PPR);
1670 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1671 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1672 gen_store_spr(SPR_PPR, t0);
1673 tcg_temp_free(t0);
1674 }
1675 #if !defined(CONFIG_USER_ONLY)
1676 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1677 * CPU and the kernel hangs. This applies to all encodings other
1678 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1679 * and all currently undefined.
1680 */
1681 gen_pause(ctx);
1682 #endif
1683 #endif
1684 }
1685 }
1686 /* orc & orc. */
1687 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1688
1689 /* xor & xor. */
1690 static void gen_xor(DisasContext *ctx)
1691 {
1692 /* Optimisation for "set to zero" case */
1693 if (rS(ctx->opcode) != rB(ctx->opcode))
1694 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1695 else
1696 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1697 if (unlikely(Rc(ctx->opcode) != 0))
1698 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1699 }
1700
1701 /* ori */
1702 static void gen_ori(DisasContext *ctx)
1703 {
1704 target_ulong uimm = UIMM(ctx->opcode);
1705
1706 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1707 return;
1708 }
1709 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1710 }
1711
1712 /* oris */
1713 static void gen_oris(DisasContext *ctx)
1714 {
1715 target_ulong uimm = UIMM(ctx->opcode);
1716
1717 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1718 /* NOP */
1719 return;
1720 }
1721 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1722 }
1723
1724 /* xori */
1725 static void gen_xori(DisasContext *ctx)
1726 {
1727 target_ulong uimm = UIMM(ctx->opcode);
1728
1729 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1730 /* NOP */
1731 return;
1732 }
1733 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1734 }
1735
1736 /* xoris */
1737 static void gen_xoris(DisasContext *ctx)
1738 {
1739 target_ulong uimm = UIMM(ctx->opcode);
1740
1741 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1742 /* NOP */
1743 return;
1744 }
1745 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1746 }
1747
1748 /* popcntb : PowerPC 2.03 specification */
1749 static void gen_popcntb(DisasContext *ctx)
1750 {
1751 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1752 }
1753
1754 static void gen_popcntw(DisasContext *ctx)
1755 {
1756 #if defined(TARGET_PPC64)
1757 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1758 #else
1759 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1760 #endif
1761 }
1762
1763 #if defined(TARGET_PPC64)
1764 /* popcntd: PowerPC 2.06 specification */
1765 static void gen_popcntd(DisasContext *ctx)
1766 {
1767 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1768 }
1769 #endif
1770
1771 /* prtyw: PowerPC 2.05 specification */
1772 static void gen_prtyw(DisasContext *ctx)
1773 {
1774 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1775 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1776 TCGv t0 = tcg_temp_new();
1777 tcg_gen_shri_tl(t0, rs, 16);
1778 tcg_gen_xor_tl(ra, rs, t0);
1779 tcg_gen_shri_tl(t0, ra, 8);
1780 tcg_gen_xor_tl(ra, ra, t0);
1781 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1782 tcg_temp_free(t0);
1783 }
1784
1785 #if defined(TARGET_PPC64)
1786 /* prtyd: PowerPC 2.05 specification */
1787 static void gen_prtyd(DisasContext *ctx)
1788 {
1789 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1790 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1791 TCGv t0 = tcg_temp_new();
1792 tcg_gen_shri_tl(t0, rs, 32);
1793 tcg_gen_xor_tl(ra, rs, t0);
1794 tcg_gen_shri_tl(t0, ra, 16);
1795 tcg_gen_xor_tl(ra, ra, t0);
1796 tcg_gen_shri_tl(t0, ra, 8);
1797 tcg_gen_xor_tl(ra, ra, t0);
1798 tcg_gen_andi_tl(ra, ra, 1);
1799 tcg_temp_free(t0);
1800 }
1801 #endif
1802
1803 #if defined(TARGET_PPC64)
1804 /* bpermd */
1805 static void gen_bpermd(DisasContext *ctx)
1806 {
1807 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1808 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1809 }
1810 #endif
1811
1812 #if defined(TARGET_PPC64)
1813 /* extsw & extsw. */
1814 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1815
1816 /* cntlzd */
1817 static void gen_cntlzd(DisasContext *ctx)
1818 {
1819 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1820 if (unlikely(Rc(ctx->opcode) != 0))
1821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1822 }
1823
1824 /* cnttzd */
1825 static void gen_cnttzd(DisasContext *ctx)
1826 {
1827 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1828 if (unlikely(Rc(ctx->opcode) != 0)) {
1829 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1830 }
1831 }
1832
1833 /* darn */
1834 static void gen_darn(DisasContext *ctx)
1835 {
1836 int l = L(ctx->opcode);
1837
1838 if (l == 0) {
1839 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1840 } else if (l <= 2) {
1841 /* Return 64-bit random for both CRN and RRN */
1842 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1843 } else {
1844 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1845 }
1846 }
1847 #endif
1848
1849 /*** Integer rotate ***/
1850
1851 /* rlwimi & rlwimi. */
1852 static void gen_rlwimi(DisasContext *ctx)
1853 {
1854 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1855 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1856 uint32_t sh = SH(ctx->opcode);
1857 uint32_t mb = MB(ctx->opcode);
1858 uint32_t me = ME(ctx->opcode);
1859
1860 if (sh == (31-me) && mb <= me) {
1861 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1862 } else {
1863 target_ulong mask;
1864 TCGv t1;
1865
1866 #if defined(TARGET_PPC64)
1867 mb += 32;
1868 me += 32;
1869 #endif
1870 mask = MASK(mb, me);
1871
1872 t1 = tcg_temp_new();
1873 if (mask <= 0xffffffffu) {
1874 TCGv_i32 t0 = tcg_temp_new_i32();
1875 tcg_gen_trunc_tl_i32(t0, t_rs);
1876 tcg_gen_rotli_i32(t0, t0, sh);
1877 tcg_gen_extu_i32_tl(t1, t0);
1878 tcg_temp_free_i32(t0);
1879 } else {
1880 #if defined(TARGET_PPC64)
1881 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1882 tcg_gen_rotli_i64(t1, t1, sh);
1883 #else
1884 g_assert_not_reached();
1885 #endif
1886 }
1887
1888 tcg_gen_andi_tl(t1, t1, mask);
1889 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1890 tcg_gen_or_tl(t_ra, t_ra, t1);
1891 tcg_temp_free(t1);
1892 }
1893 if (unlikely(Rc(ctx->opcode) != 0)) {
1894 gen_set_Rc0(ctx, t_ra);
1895 }
1896 }
1897
1898 /* rlwinm & rlwinm. */
1899 static void gen_rlwinm(DisasContext *ctx)
1900 {
1901 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1902 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1903 int sh = SH(ctx->opcode);
1904 int mb = MB(ctx->opcode);
1905 int me = ME(ctx->opcode);
1906 int len = me - mb + 1;
1907 int rsh = (32 - sh) & 31;
1908
1909 if (sh != 0 && len > 0 && me == (31 - sh)) {
1910 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1911 } else if (me == 31 && rsh + len <= 32) {
1912 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1913 } else {
1914 target_ulong mask;
1915 #if defined(TARGET_PPC64)
1916 mb += 32;
1917 me += 32;
1918 #endif
1919 mask = MASK(mb, me);
1920 if (sh == 0) {
1921 tcg_gen_andi_tl(t_ra, t_rs, mask);
1922 } else if (mask <= 0xffffffffu) {
1923 TCGv_i32 t0 = tcg_temp_new_i32();
1924 tcg_gen_trunc_tl_i32(t0, t_rs);
1925 tcg_gen_rotli_i32(t0, t0, sh);
1926 tcg_gen_andi_i32(t0, t0, mask);
1927 tcg_gen_extu_i32_tl(t_ra, t0);
1928 tcg_temp_free_i32(t0);
1929 } else {
1930 #if defined(TARGET_PPC64)
1931 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1932 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1933 tcg_gen_andi_i64(t_ra, t_ra, mask);
1934 #else
1935 g_assert_not_reached();
1936 #endif
1937 }
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, t_ra);
1941 }
1942 }
1943
1944 /* rlwnm & rlwnm. */
1945 static void gen_rlwnm(DisasContext *ctx)
1946 {
1947 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1948 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1949 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1950 uint32_t mb = MB(ctx->opcode);
1951 uint32_t me = ME(ctx->opcode);
1952 target_ulong mask;
1953
1954 #if defined(TARGET_PPC64)
1955 mb += 32;
1956 me += 32;
1957 #endif
1958 mask = MASK(mb, me);
1959
1960 if (mask <= 0xffffffffu) {
1961 TCGv_i32 t0 = tcg_temp_new_i32();
1962 TCGv_i32 t1 = tcg_temp_new_i32();
1963 tcg_gen_trunc_tl_i32(t0, t_rb);
1964 tcg_gen_trunc_tl_i32(t1, t_rs);
1965 tcg_gen_andi_i32(t0, t0, 0x1f);
1966 tcg_gen_rotl_i32(t1, t1, t0);
1967 tcg_gen_extu_i32_tl(t_ra, t1);
1968 tcg_temp_free_i32(t0);
1969 tcg_temp_free_i32(t1);
1970 } else {
1971 #if defined(TARGET_PPC64)
1972 TCGv_i64 t0 = tcg_temp_new_i64();
1973 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1974 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1975 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1976 tcg_temp_free_i64(t0);
1977 #else
1978 g_assert_not_reached();
1979 #endif
1980 }
1981
1982 tcg_gen_andi_tl(t_ra, t_ra, mask);
1983
1984 if (unlikely(Rc(ctx->opcode) != 0)) {
1985 gen_set_Rc0(ctx, t_ra);
1986 }
1987 }
1988
1989 #if defined(TARGET_PPC64)
1990 #define GEN_PPC64_R2(name, opc1, opc2) \
1991 static void glue(gen_, name##0)(DisasContext *ctx) \
1992 { \
1993 gen_##name(ctx, 0); \
1994 } \
1995 \
1996 static void glue(gen_, name##1)(DisasContext *ctx) \
1997 { \
1998 gen_##name(ctx, 1); \
1999 }
2000 #define GEN_PPC64_R4(name, opc1, opc2) \
2001 static void glue(gen_, name##0)(DisasContext *ctx) \
2002 { \
2003 gen_##name(ctx, 0, 0); \
2004 } \
2005 \
2006 static void glue(gen_, name##1)(DisasContext *ctx) \
2007 { \
2008 gen_##name(ctx, 0, 1); \
2009 } \
2010 \
2011 static void glue(gen_, name##2)(DisasContext *ctx) \
2012 { \
2013 gen_##name(ctx, 1, 0); \
2014 } \
2015 \
2016 static void glue(gen_, name##3)(DisasContext *ctx) \
2017 { \
2018 gen_##name(ctx, 1, 1); \
2019 }
2020
2021 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2022 {
2023 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2024 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2025 int len = me - mb + 1;
2026 int rsh = (64 - sh) & 63;
2027
2028 if (sh != 0 && len > 0 && me == (63 - sh)) {
2029 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2030 } else if (me == 63 && rsh + len <= 64) {
2031 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2032 } else {
2033 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2034 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2035 }
2036 if (unlikely(Rc(ctx->opcode) != 0)) {
2037 gen_set_Rc0(ctx, t_ra);
2038 }
2039 }
2040
2041 /* rldicl - rldicl. */
2042 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2043 {
2044 uint32_t sh, mb;
2045
2046 sh = SH(ctx->opcode) | (shn << 5);
2047 mb = MB(ctx->opcode) | (mbn << 5);
2048 gen_rldinm(ctx, mb, 63, sh);
2049 }
2050 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2051
2052 /* rldicr - rldicr. */
2053 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2054 {
2055 uint32_t sh, me;
2056
2057 sh = SH(ctx->opcode) | (shn << 5);
2058 me = MB(ctx->opcode) | (men << 5);
2059 gen_rldinm(ctx, 0, me, sh);
2060 }
2061 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2062
2063 /* rldic - rldic. */
2064 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2065 {
2066 uint32_t sh, mb;
2067
2068 sh = SH(ctx->opcode) | (shn << 5);
2069 mb = MB(ctx->opcode) | (mbn << 5);
2070 gen_rldinm(ctx, mb, 63 - sh, sh);
2071 }
2072 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2073
2074 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2075 {
2076 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2077 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2078 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2079 TCGv t0;
2080
2081 t0 = tcg_temp_new();
2082 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2083 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2084 tcg_temp_free(t0);
2085
2086 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2087 if (unlikely(Rc(ctx->opcode) != 0)) {
2088 gen_set_Rc0(ctx, t_ra);
2089 }
2090 }
2091
2092 /* rldcl - rldcl. */
2093 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2094 {
2095 uint32_t mb;
2096
2097 mb = MB(ctx->opcode) | (mbn << 5);
2098 gen_rldnm(ctx, mb, 63);
2099 }
2100 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2101
2102 /* rldcr - rldcr. */
2103 static inline void gen_rldcr(DisasContext *ctx, int men)
2104 {
2105 uint32_t me;
2106
2107 me = MB(ctx->opcode) | (men << 5);
2108 gen_rldnm(ctx, 0, me);
2109 }
2110 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2111
2112 /* rldimi - rldimi. */
2113 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2114 {
2115 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2116 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2117 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2118 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2119 uint32_t me = 63 - sh;
2120
2121 if (mb <= me) {
2122 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2123 } else {
2124 target_ulong mask = MASK(mb, me);
2125 TCGv t1 = tcg_temp_new();
2126
2127 tcg_gen_rotli_tl(t1, t_rs, sh);
2128 tcg_gen_andi_tl(t1, t1, mask);
2129 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2130 tcg_gen_or_tl(t_ra, t_ra, t1);
2131 tcg_temp_free(t1);
2132 }
2133 if (unlikely(Rc(ctx->opcode) != 0)) {
2134 gen_set_Rc0(ctx, t_ra);
2135 }
2136 }
2137 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2138 #endif
2139
2140 /*** Integer shift ***/
2141
2142 /* slw & slw. */
2143 static void gen_slw(DisasContext *ctx)
2144 {
2145 TCGv t0, t1;
2146
2147 t0 = tcg_temp_new();
2148 /* AND rS with a mask that is 0 when rB >= 0x20 */
2149 #if defined(TARGET_PPC64)
2150 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2151 tcg_gen_sari_tl(t0, t0, 0x3f);
2152 #else
2153 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2154 tcg_gen_sari_tl(t0, t0, 0x1f);
2155 #endif
2156 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2157 t1 = tcg_temp_new();
2158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2159 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2160 tcg_temp_free(t1);
2161 tcg_temp_free(t0);
2162 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2163 if (unlikely(Rc(ctx->opcode) != 0))
2164 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2165 }
2166
2167 /* sraw & sraw. */
2168 static void gen_sraw(DisasContext *ctx)
2169 {
2170 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2171 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2172 if (unlikely(Rc(ctx->opcode) != 0))
2173 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2174 }
2175
2176 /* srawi & srawi. */
2177 static void gen_srawi(DisasContext *ctx)
2178 {
2179 int sh = SH(ctx->opcode);
2180 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2181 TCGv src = cpu_gpr[rS(ctx->opcode)];
2182 if (sh == 0) {
2183 tcg_gen_ext32s_tl(dst, src);
2184 tcg_gen_movi_tl(cpu_ca, 0);
2185 } else {
2186 TCGv t0;
2187 tcg_gen_ext32s_tl(dst, src);
2188 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2189 t0 = tcg_temp_new();
2190 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2191 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2192 tcg_temp_free(t0);
2193 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2194 tcg_gen_sari_tl(dst, dst, sh);
2195 }
2196 if (unlikely(Rc(ctx->opcode) != 0)) {
2197 gen_set_Rc0(ctx, dst);
2198 }
2199 }
2200
2201 /* srw & srw. */
2202 static void gen_srw(DisasContext *ctx)
2203 {
2204 TCGv t0, t1;
2205
2206 t0 = tcg_temp_new();
2207 /* AND rS with a mask that is 0 when rB >= 0x20 */
2208 #if defined(TARGET_PPC64)
2209 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2210 tcg_gen_sari_tl(t0, t0, 0x3f);
2211 #else
2212 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2213 tcg_gen_sari_tl(t0, t0, 0x1f);
2214 #endif
2215 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2216 tcg_gen_ext32u_tl(t0, t0);
2217 t1 = tcg_temp_new();
2218 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2219 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2220 tcg_temp_free(t1);
2221 tcg_temp_free(t0);
2222 if (unlikely(Rc(ctx->opcode) != 0))
2223 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2224 }
2225
2226 #if defined(TARGET_PPC64)
2227 /* sld & sld. */
2228 static void gen_sld(DisasContext *ctx)
2229 {
2230 TCGv t0, t1;
2231
2232 t0 = tcg_temp_new();
2233 /* AND rS with a mask that is 0 when rB >= 0x40 */
2234 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2235 tcg_gen_sari_tl(t0, t0, 0x3f);
2236 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2237 t1 = tcg_temp_new();
2238 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2239 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2240 tcg_temp_free(t1);
2241 tcg_temp_free(t0);
2242 if (unlikely(Rc(ctx->opcode) != 0))
2243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2244 }
2245
2246 /* srad & srad. */
2247 static void gen_srad(DisasContext *ctx)
2248 {
2249 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2250 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2251 if (unlikely(Rc(ctx->opcode) != 0))
2252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2253 }
2254 /* sradi & sradi. */
2255 static inline void gen_sradi(DisasContext *ctx, int n)
2256 {
2257 int sh = SH(ctx->opcode) + (n << 5);
2258 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2259 TCGv src = cpu_gpr[rS(ctx->opcode)];
2260 if (sh == 0) {
2261 tcg_gen_mov_tl(dst, src);
2262 tcg_gen_movi_tl(cpu_ca, 0);
2263 } else {
2264 TCGv t0;
2265 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2266 t0 = tcg_temp_new();
2267 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2268 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2269 tcg_temp_free(t0);
2270 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2271 tcg_gen_sari_tl(dst, src, sh);
2272 }
2273 if (unlikely(Rc(ctx->opcode) != 0)) {
2274 gen_set_Rc0(ctx, dst);
2275 }
2276 }
2277
2278 static void gen_sradi0(DisasContext *ctx)
2279 {
2280 gen_sradi(ctx, 0);
2281 }
2282
2283 static void gen_sradi1(DisasContext *ctx)
2284 {
2285 gen_sradi(ctx, 1);
2286 }
2287
2288 /* extswsli & extswsli. */
2289 static inline void gen_extswsli(DisasContext *ctx, int n)
2290 {
2291 int sh = SH(ctx->opcode) + (n << 5);
2292 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2293 TCGv src = cpu_gpr[rS(ctx->opcode)];
2294
2295 tcg_gen_ext32s_tl(dst, src);
2296 tcg_gen_shli_tl(dst, dst, sh);
2297 if (unlikely(Rc(ctx->opcode) != 0)) {
2298 gen_set_Rc0(ctx, dst);
2299 }
2300 }
2301
2302 static void gen_extswsli0(DisasContext *ctx)
2303 {
2304 gen_extswsli(ctx, 0);
2305 }
2306
2307 static void gen_extswsli1(DisasContext *ctx)
2308 {
2309 gen_extswsli(ctx, 1);
2310 }
2311
2312 /* srd & srd. */
2313 static void gen_srd(DisasContext *ctx)
2314 {
2315 TCGv t0, t1;
2316
2317 t0 = tcg_temp_new();
2318 /* AND rS with a mask that is 0 when rB >= 0x40 */
2319 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2320 tcg_gen_sari_tl(t0, t0, 0x3f);
2321 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2322 t1 = tcg_temp_new();
2323 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2324 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2325 tcg_temp_free(t1);
2326 tcg_temp_free(t0);
2327 if (unlikely(Rc(ctx->opcode) != 0))
2328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2329 }
2330 #endif
2331
2332 /*** Addressing modes ***/
2333 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2334 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2335 target_long maskl)
2336 {
2337 target_long simm = SIMM(ctx->opcode);
2338
2339 simm &= ~maskl;
2340 if (rA(ctx->opcode) == 0) {
2341 if (NARROW_MODE(ctx)) {
2342 simm = (uint32_t)simm;
2343 }
2344 tcg_gen_movi_tl(EA, simm);
2345 } else if (likely(simm != 0)) {
2346 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2347 if (NARROW_MODE(ctx)) {
2348 tcg_gen_ext32u_tl(EA, EA);
2349 }
2350 } else {
2351 if (NARROW_MODE(ctx)) {
2352 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2353 } else {
2354 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2355 }
2356 }
2357 }
2358
2359 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2360 {
2361 if (rA(ctx->opcode) == 0) {
2362 if (NARROW_MODE(ctx)) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2364 } else {
2365 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2366 }
2367 } else {
2368 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2369 if (NARROW_MODE(ctx)) {
2370 tcg_gen_ext32u_tl(EA, EA);
2371 }
2372 }
2373 }
2374
2375 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2376 {
2377 if (rA(ctx->opcode) == 0) {
2378 tcg_gen_movi_tl(EA, 0);
2379 } else if (NARROW_MODE(ctx)) {
2380 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2381 } else {
2382 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2383 }
2384 }
2385
2386 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2387 target_long val)
2388 {
2389 tcg_gen_addi_tl(ret, arg1, val);
2390 if (NARROW_MODE(ctx)) {
2391 tcg_gen_ext32u_tl(ret, ret);
2392 }
2393 }
2394
2395 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2396 {
2397 TCGLabel *l1 = gen_new_label();
2398 TCGv t0 = tcg_temp_new();
2399 TCGv_i32 t1, t2;
2400 tcg_gen_andi_tl(t0, EA, mask);
2401 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2402 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2403 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2404 gen_update_nip(ctx, ctx->nip - 4);
2405 gen_helper_raise_exception_err(cpu_env, t1, t2);
2406 tcg_temp_free_i32(t1);
2407 tcg_temp_free_i32(t2);
2408 gen_set_label(l1);
2409 tcg_temp_free(t0);
2410 }
2411
2412 static inline void gen_align_no_le(DisasContext *ctx)
2413 {
2414 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2415 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2416 }
2417
2418 /*** Integer load ***/
2419 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2420 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2421
2422 #define GEN_QEMU_LOAD_TL(ldop, op) \
2423 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2424 TCGv val, \
2425 TCGv addr) \
2426 { \
2427 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2428 }
2429
2430 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2431 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2432 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2433 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2434 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2435
2436 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2437 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2438
2439 #define GEN_QEMU_LOAD_64(ldop, op) \
2440 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2441 TCGv_i64 val, \
2442 TCGv addr) \
2443 { \
2444 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2445 }
2446
2447 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2448 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2449 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2450 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2451 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2452
2453 #if defined(TARGET_PPC64)
2454 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2455 #endif
2456
2457 #define GEN_QEMU_STORE_TL(stop, op) \
2458 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2459 TCGv val, \
2460 TCGv addr) \
2461 { \
2462 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2463 }
2464
2465 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2466 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2467 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2468
2469 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2470 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2471
2472 #define GEN_QEMU_STORE_64(stop, op) \
2473 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2474 TCGv_i64 val, \
2475 TCGv addr) \
2476 { \
2477 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2478 }
2479
2480 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2481 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2482 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2483 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2484
2485 #if defined(TARGET_PPC64)
2486 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2487 #endif
2488
2489 #define GEN_LD(name, ldop, opc, type) \
2490 static void glue(gen_, name)(DisasContext *ctx) \
2491 { \
2492 TCGv EA; \
2493 gen_set_access_type(ctx, ACCESS_INT); \
2494 EA = tcg_temp_new(); \
2495 gen_addr_imm_index(ctx, EA, 0); \
2496 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2497 tcg_temp_free(EA); \
2498 }
2499
2500 #define GEN_LDU(name, ldop, opc, type) \
2501 static void glue(gen_, name##u)(DisasContext *ctx) \
2502 { \
2503 TCGv EA; \
2504 if (unlikely(rA(ctx->opcode) == 0 || \
2505 rA(ctx->opcode) == rD(ctx->opcode))) { \
2506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2507 return; \
2508 } \
2509 gen_set_access_type(ctx, ACCESS_INT); \
2510 EA = tcg_temp_new(); \
2511 if (type == PPC_64B) \
2512 gen_addr_imm_index(ctx, EA, 0x03); \
2513 else \
2514 gen_addr_imm_index(ctx, EA, 0); \
2515 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2516 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2517 tcg_temp_free(EA); \
2518 }
2519
2520 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2521 static void glue(gen_, name##ux)(DisasContext *ctx) \
2522 { \
2523 TCGv EA; \
2524 if (unlikely(rA(ctx->opcode) == 0 || \
2525 rA(ctx->opcode) == rD(ctx->opcode))) { \
2526 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2527 return; \
2528 } \
2529 gen_set_access_type(ctx, ACCESS_INT); \
2530 EA = tcg_temp_new(); \
2531 gen_addr_reg_index(ctx, EA); \
2532 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2533 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2534 tcg_temp_free(EA); \
2535 }
2536
2537 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2538 static void glue(gen_, name##x)(DisasContext *ctx) \
2539 { \
2540 TCGv EA; \
2541 chk; \
2542 gen_set_access_type(ctx, ACCESS_INT); \
2543 EA = tcg_temp_new(); \
2544 gen_addr_reg_index(ctx, EA); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_temp_free(EA); \
2547 }
2548
2549 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2550 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2551
2552 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2553 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2554
2555 #define GEN_LDS(name, ldop, op, type) \
2556 GEN_LD(name, ldop, op | 0x20, type); \
2557 GEN_LDU(name, ldop, op | 0x21, type); \
2558 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2559 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2560
2561 /* lbz lbzu lbzux lbzx */
2562 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2563 /* lha lhau lhaux lhax */
2564 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2565 /* lhz lhzu lhzux lhzx */
2566 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2567 /* lwz lwzu lwzux lwzx */
2568 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2569 #if defined(TARGET_PPC64)
2570 /* lwaux */
2571 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2572 /* lwax */
2573 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2574 /* ldux */
2575 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2576 /* ldx */
2577 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2578
2579 /* CI load/store variants */
2580 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2581 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2582 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2583 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2584
2585 static void gen_ld(DisasContext *ctx)
2586 {
2587 TCGv EA;
2588 if (Rc(ctx->opcode)) {
2589 if (unlikely(rA(ctx->opcode) == 0 ||
2590 rA(ctx->opcode) == rD(ctx->opcode))) {
2591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2592 return;
2593 }
2594 }
2595 gen_set_access_type(ctx, ACCESS_INT);
2596 EA = tcg_temp_new();
2597 gen_addr_imm_index(ctx, EA, 0x03);
2598 if (ctx->opcode & 0x02) {
2599 /* lwa (lwau is undefined) */
2600 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2601 } else {
2602 /* ld - ldu */
2603 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2604 }
2605 if (Rc(ctx->opcode))
2606 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2607 tcg_temp_free(EA);
2608 }
2609
2610 /* lq */
2611 static void gen_lq(DisasContext *ctx)
2612 {
2613 int ra, rd;
2614 TCGv EA;
2615
2616 /* lq is a legal user mode instruction starting in ISA 2.07 */
2617 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2618 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2619
2620 if (!legal_in_user_mode && ctx->pr) {
2621 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2622 return;
2623 }
2624
2625 if (!le_is_supported && ctx->le_mode) {
2626 gen_align_no_le(ctx);
2627 return;
2628 }
2629 ra = rA(ctx->opcode);
2630 rd = rD(ctx->opcode);
2631 if (unlikely((rd & 1) || rd == ra)) {
2632 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2633 return;
2634 }
2635
2636 gen_set_access_type(ctx, ACCESS_INT);
2637 EA = tcg_temp_new();
2638 gen_addr_imm_index(ctx, EA, 0x0F);
2639
2640 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2641 necessary 64-bit byteswap already. */
2642 if (unlikely(ctx->le_mode)) {
2643 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2644 gen_addr_add(ctx, EA, EA, 8);
2645 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2646 } else {
2647 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2648 gen_addr_add(ctx, EA, EA, 8);
2649 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2650 }
2651 tcg_temp_free(EA);
2652 }
2653 #endif
2654
2655 /*** Integer store ***/
2656 #define GEN_ST(name, stop, opc, type) \
2657 static void glue(gen_, name)(DisasContext *ctx) \
2658 { \
2659 TCGv EA; \
2660 gen_set_access_type(ctx, ACCESS_INT); \
2661 EA = tcg_temp_new(); \
2662 gen_addr_imm_index(ctx, EA, 0); \
2663 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2664 tcg_temp_free(EA); \
2665 }
2666
2667 #define GEN_STU(name, stop, opc, type) \
2668 static void glue(gen_, stop##u)(DisasContext *ctx) \
2669 { \
2670 TCGv EA; \
2671 if (unlikely(rA(ctx->opcode) == 0)) { \
2672 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2673 return; \
2674 } \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 if (type == PPC_64B) \
2678 gen_addr_imm_index(ctx, EA, 0x03); \
2679 else \
2680 gen_addr_imm_index(ctx, EA, 0); \
2681 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2683 tcg_temp_free(EA); \
2684 }
2685
2686 #define GEN_STUX(name, stop, opc2, opc3, type) \
2687 static void glue(gen_, name##ux)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 if (unlikely(rA(ctx->opcode) == 0)) { \
2691 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2692 return; \
2693 } \
2694 gen_set_access_type(ctx, ACCESS_INT); \
2695 EA = tcg_temp_new(); \
2696 gen_addr_reg_index(ctx, EA); \
2697 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2700 }
2701
2702 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2703 static void glue(gen_, name##x)(DisasContext *ctx) \
2704 { \
2705 TCGv EA; \
2706 chk; \
2707 gen_set_access_type(ctx, ACCESS_INT); \
2708 EA = tcg_temp_new(); \
2709 gen_addr_reg_index(ctx, EA); \
2710 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2711 tcg_temp_free(EA); \
2712 }
2713 #define GEN_STX(name, stop, opc2, opc3, type) \
2714 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2715
2716 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2717 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2718
2719 #define GEN_STS(name, stop, op, type) \
2720 GEN_ST(name, stop, op | 0x20, type); \
2721 GEN_STU(name, stop, op | 0x21, type); \
2722 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2723 GEN_STX(name, stop, 0x17, op | 0x00, type)
2724
2725 /* stb stbu stbux stbx */
2726 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2727 /* sth sthu sthux sthx */
2728 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2729 /* stw stwu stwux stwx */
2730 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2731 #if defined(TARGET_PPC64)
2732 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2733 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2734 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2735 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2736 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2737 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2738
2739 static void gen_std(DisasContext *ctx)
2740 {
2741 int rs;
2742 TCGv EA;
2743
2744 rs = rS(ctx->opcode);
2745 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2746 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2747 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2748
2749 if (!(ctx->insns_flags & PPC_64BX)) {
2750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2751 }
2752
2753 if (!legal_in_user_mode && ctx->pr) {
2754 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2755 return;
2756 }
2757
2758 if (!le_is_supported && ctx->le_mode) {
2759 gen_align_no_le(ctx);
2760 return;
2761 }
2762
2763 if (unlikely(rs & 1)) {
2764 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2765 return;
2766 }
2767 gen_set_access_type(ctx, ACCESS_INT);
2768 EA = tcg_temp_new();
2769 gen_addr_imm_index(ctx, EA, 0x03);
2770
2771 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2772 necessary 64-bit byteswap already. */
2773 if (unlikely(ctx->le_mode)) {
2774 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2775 gen_addr_add(ctx, EA, EA, 8);
2776 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2777 } else {
2778 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2779 gen_addr_add(ctx, EA, EA, 8);
2780 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2781 }
2782 tcg_temp_free(EA);
2783 } else {
2784 /* std / stdu*/
2785 if (Rc(ctx->opcode)) {
2786 if (unlikely(rA(ctx->opcode) == 0)) {
2787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2788 return;
2789 }
2790 }
2791 gen_set_access_type(ctx, ACCESS_INT);
2792 EA = tcg_temp_new();
2793 gen_addr_imm_index(ctx, EA, 0x03);
2794 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2795 if (Rc(ctx->opcode))
2796 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2797 tcg_temp_free(EA);
2798 }
2799 }
2800 #endif
2801 /*** Integer load and store with byte reverse ***/
2802
2803 /* lhbrx */
2804 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2805
2806 /* lwbrx */
2807 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2808
2809 #if defined(TARGET_PPC64)
2810 /* ldbrx */
2811 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2812 /* stdbrx */
2813 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2814 #endif /* TARGET_PPC64 */
2815
2816 /* sthbrx */
2817 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2818 /* stwbrx */
2819 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2820
2821 /*** Integer load and store multiple ***/
2822
2823 /* lmw */
2824 static void gen_lmw(DisasContext *ctx)
2825 {
2826 TCGv t0;
2827 TCGv_i32 t1;
2828
2829 if (ctx->le_mode) {
2830 gen_align_no_le(ctx);
2831 return;
2832 }
2833 gen_set_access_type(ctx, ACCESS_INT);
2834 t0 = tcg_temp_new();
2835 t1 = tcg_const_i32(rD(ctx->opcode));
2836 gen_addr_imm_index(ctx, t0, 0);
2837 gen_helper_lmw(cpu_env, t0, t1);
2838 tcg_temp_free(t0);
2839 tcg_temp_free_i32(t1);
2840 }
2841
2842 /* stmw */
2843 static void gen_stmw(DisasContext *ctx)
2844 {
2845 TCGv t0;
2846 TCGv_i32 t1;
2847
2848 if (ctx->le_mode) {
2849 gen_align_no_le(ctx);
2850 return;
2851 }
2852 gen_set_access_type(ctx, ACCESS_INT);
2853 t0 = tcg_temp_new();
2854 t1 = tcg_const_i32(rS(ctx->opcode));
2855 gen_addr_imm_index(ctx, t0, 0);
2856 gen_helper_stmw(cpu_env, t0, t1);
2857 tcg_temp_free(t0);
2858 tcg_temp_free_i32(t1);
2859 }
2860
2861 /*** Integer load and store strings ***/
2862
2863 /* lswi */
2864 /* PowerPC32 specification says we must generate an exception if
2865 * rA is in the range of registers to be loaded.
2866 * In an other hand, IBM says this is valid, but rA won't be loaded.
2867 * For now, I'll follow the spec...
2868 */
2869 static void gen_lswi(DisasContext *ctx)
2870 {
2871 TCGv t0;
2872 TCGv_i32 t1, t2;
2873 int nb = NB(ctx->opcode);
2874 int start = rD(ctx->opcode);
2875 int ra = rA(ctx->opcode);
2876 int nr;
2877
2878 if (ctx->le_mode) {
2879 gen_align_no_le(ctx);
2880 return;
2881 }
2882 if (nb == 0)
2883 nb = 32;
2884 nr = (nb + 3) / 4;
2885 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2886 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2887 return;
2888 }
2889 gen_set_access_type(ctx, ACCESS_INT);
2890 t0 = tcg_temp_new();
2891 gen_addr_register(ctx, t0);
2892 t1 = tcg_const_i32(nb);
2893 t2 = tcg_const_i32(start);
2894 gen_helper_lsw(cpu_env, t0, t1, t2);
2895 tcg_temp_free(t0);
2896 tcg_temp_free_i32(t1);
2897 tcg_temp_free_i32(t2);
2898 }
2899
2900 /* lswx */
2901 static void gen_lswx(DisasContext *ctx)
2902 {
2903 TCGv t0;
2904 TCGv_i32 t1, t2, t3;
2905
2906 if (ctx->le_mode) {
2907 gen_align_no_le(ctx);
2908 return;
2909 }
2910 gen_set_access_type(ctx, ACCESS_INT);
2911 t0 = tcg_temp_new();
2912 gen_addr_reg_index(ctx, t0);
2913 t1 = tcg_const_i32(rD(ctx->opcode));
2914 t2 = tcg_const_i32(rA(ctx->opcode));
2915 t3 = tcg_const_i32(rB(ctx->opcode));
2916 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2917 tcg_temp_free(t0);
2918 tcg_temp_free_i32(t1);
2919 tcg_temp_free_i32(t2);
2920 tcg_temp_free_i32(t3);
2921 }
2922
2923 /* stswi */
2924 static void gen_stswi(DisasContext *ctx)
2925 {
2926 TCGv t0;
2927 TCGv_i32 t1, t2;
2928 int nb = NB(ctx->opcode);
2929
2930 if (ctx->le_mode) {
2931 gen_align_no_le(ctx);
2932 return;
2933 }
2934 gen_set_access_type(ctx, ACCESS_INT);
2935 t0 = tcg_temp_new();
2936 gen_addr_register(ctx, t0);
2937 if (nb == 0)
2938 nb = 32;
2939 t1 = tcg_const_i32(nb);
2940 t2 = tcg_const_i32(rS(ctx->opcode));
2941 gen_helper_stsw(cpu_env, t0, t1, t2);
2942 tcg_temp_free(t0);
2943 tcg_temp_free_i32(t1);
2944 tcg_temp_free_i32(t2);
2945 }
2946
2947 /* stswx */
2948 static void gen_stswx(DisasContext *ctx)
2949 {
2950 TCGv t0;
2951 TCGv_i32 t1, t2;
2952
2953 if (ctx->le_mode) {
2954 gen_align_no_le(ctx);
2955 return;
2956 }
2957 gen_set_access_type(ctx, ACCESS_INT);
2958 t0 = tcg_temp_new();
2959 gen_addr_reg_index(ctx, t0);
2960 t1 = tcg_temp_new_i32();
2961 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2962 tcg_gen_andi_i32(t1, t1, 0x7F);
2963 t2 = tcg_const_i32(rS(ctx->opcode));
2964 gen_helper_stsw(cpu_env, t0, t1, t2);
2965 tcg_temp_free(t0);
2966 tcg_temp_free_i32(t1);
2967 tcg_temp_free_i32(t2);
2968 }
2969
2970 /*** Memory synchronisation ***/
2971 /* eieio */
2972 static void gen_eieio(DisasContext *ctx)
2973 {
2974 }
2975
2976 #if !defined(CONFIG_USER_ONLY)
2977 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2978 {
2979 TCGv_i32 t;
2980 TCGLabel *l;
2981
2982 if (!ctx->lazy_tlb_flush) {
2983 return;
2984 }
2985 l = gen_new_label();
2986 t = tcg_temp_new_i32();
2987 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2988 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2989 if (global) {
2990 gen_helper_check_tlb_flush_global(cpu_env);
2991 } else {
2992 gen_helper_check_tlb_flush_local(cpu_env);
2993 }
2994 gen_set_label(l);
2995 tcg_temp_free_i32(t);
2996 }
2997 #else
2998 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
2999 #endif
3000
3001 /* isync */
3002 static void gen_isync(DisasContext *ctx)
3003 {
3004 /*
3005 * We need to check for a pending TLB flush. This can only happen in
3006 * kernel mode however so check MSR_PR
3007 */
3008 if (!ctx->pr) {
3009 gen_check_tlb_flush(ctx, false);
3010 }
3011 gen_stop_exception(ctx);
3012 }
3013
3014 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3015
3016 #define LARX(name, memop) \
3017 static void gen_##name(DisasContext *ctx) \
3018 { \
3019 TCGv t0; \
3020 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3021 int len = MEMOP_GET_SIZE(memop); \
3022 gen_set_access_type(ctx, ACCESS_RES); \
3023 t0 = tcg_temp_local_new(); \
3024 gen_addr_reg_index(ctx, t0); \
3025 if ((len) > 1) { \
3026 gen_check_align(ctx, t0, (len)-1); \
3027 } \
3028 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3029 tcg_gen_mov_tl(cpu_reserve, t0); \
3030 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3031 tcg_temp_free(t0); \
3032 }
3033
3034 /* lwarx */
3035 LARX(lbarx, DEF_MEMOP(MO_UB))
3036 LARX(lharx, DEF_MEMOP(MO_UW))
3037 LARX(lwarx, DEF_MEMOP(MO_UL))
3038
3039 #define LD_ATOMIC(name, memop, tp, op, eop) \
3040 static void gen_##name(DisasContext *ctx) \
3041 { \
3042 int len = MEMOP_GET_SIZE(memop); \
3043 uint32_t gpr_FC = FC(ctx->opcode); \
3044 TCGv EA = tcg_temp_local_new(); \
3045 TCGv_##tp t0, t1; \
3046 \
3047 gen_addr_register(ctx, EA); \
3048 if (len > 1) { \
3049 gen_check_align(ctx, EA, len - 1); \
3050 } \
3051 t0 = tcg_temp_new_##tp(); \
3052 t1 = tcg_temp_new_##tp(); \
3053 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3054 \
3055 switch (gpr_FC) { \
3056 case 0: /* Fetch and add */ \
3057 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3058 break; \
3059 case 1: /* Fetch and xor */ \
3060 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3061 break; \
3062 case 2: /* Fetch and or */ \
3063 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3064 break; \
3065 case 3: /* Fetch and 'and' */ \
3066 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3067 break; \
3068 case 8: /* Swap */ \
3069 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3070 break; \
3071 case 4: /* Fetch and max unsigned */ \
3072 case 5: /* Fetch and max signed */ \
3073 case 6: /* Fetch and min unsigned */ \
3074 case 7: /* Fetch and min signed */ \
3075 case 16: /* compare and swap not equal */ \
3076 case 24: /* Fetch and increment bounded */ \
3077 case 25: /* Fetch and increment equal */ \
3078 case 28: /* Fetch and decrement bounded */ \
3079 gen_invalid(ctx); \
3080 break; \
3081 default: \
3082 /* invoke data storage error handler */ \
3083 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3084 } \
3085 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3086 tcg_temp_free_##tp(t0); \
3087 tcg_temp_free_##tp(t1); \
3088 tcg_temp_free(EA); \
3089 }
3090
3091 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3092 #if defined(TARGET_PPC64)
3093 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3094 #endif
3095
3096 #define ST_ATOMIC(name, memop, tp, op) \
3097 static void gen_##name(DisasContext *ctx) \
3098 { \
3099 int len = MEMOP_GET_SIZE(memop); \
3100 uint32_t gpr_FC = FC(ctx->opcode); \
3101 TCGv EA = tcg_temp_local_new(); \
3102 TCGv_##tp t0, t1; \
3103 \
3104 gen_addr_register(ctx, EA); \
3105 if (len > 1) { \
3106 gen_check_align(ctx, EA, len - 1); \
3107 } \
3108 t0 = tcg_temp_new_##tp(); \
3109 t1 = tcg_temp_new_##tp(); \
3110 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3111 \
3112 switch (gpr_FC) { \
3113 case 0: /* add and Store */ \
3114 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3115 break; \
3116 case 1: /* xor and Store */ \
3117 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3118 break; \
3119 case 2: /* Or and Store */ \
3120 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3121 break; \
3122 case 3: /* 'and' and Store */ \
3123 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3124 break; \
3125 case 4: /* Store max unsigned */ \
3126 case 5: /* Store max signed */ \
3127 case 6: /* Store min unsigned */ \
3128 case 7: /* Store min signed */ \
3129 case 24: /* Store twin */ \
3130 gen_invalid(ctx); \
3131 break; \
3132 default: \
3133 /* invoke data storage error handler */ \
3134 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3135 } \
3136 tcg_temp_free_##tp(t0); \
3137 tcg_temp_free_##tp(t1); \
3138 tcg_temp_free(EA); \
3139 }
3140
3141 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3142 #if defined(TARGET_PPC64)
3143 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3144 #endif
3145
3146 #if defined(CONFIG_USER_ONLY)
3147 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3148 int reg, int memop)
3149 {
3150 TCGv t0 = tcg_temp_new();
3151
3152 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3153 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3154 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3155 tcg_temp_free(t0);
3156 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3157 }
3158 #else
3159 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3160 int reg, int memop)
3161 {
3162 TCGLabel *l1 = gen_new_label();
3163 TCGLabel *l2 = gen_new_label();
3164 TCGv t0;
3165
3166 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3167
3168 t0 = tcg_temp_new();
3169 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3170 cpu_gpr[reg], ctx->mem_idx,
3171 DEF_MEMOP(memop) | MO_ALIGN);
3172 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3173 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3174 tcg_gen_or_tl(t0, t0, cpu_so);
3175 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3176 tcg_temp_free(t0);
3177 tcg_gen_br(l2);
3178
3179 gen_set_label(l1);
3180 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3181
3182 gen_set_label(l2);
3183 tcg_gen_movi_tl(cpu_reserve, -1);
3184 }
3185 #endif
3186
3187 #define STCX(name, memop) \
3188 static void gen_##name(DisasContext *ctx) \
3189 { \
3190 TCGv t0; \
3191 int len = MEMOP_GET_SIZE(memop); \
3192 gen_set_access_type(ctx, ACCESS_RES); \
3193 t0 = tcg_temp_local_new(); \
3194 gen_addr_reg_index(ctx, t0); \
3195 if (len > 1) { \
3196 gen_check_align(ctx, t0, (len) - 1); \
3197 } \
3198 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3199 tcg_temp_free(t0); \
3200 }
3201
3202 STCX(stbcx_, DEF_MEMOP(MO_UB))
3203 STCX(sthcx_, DEF_MEMOP(MO_UW))
3204 STCX(stwcx_, DEF_MEMOP(MO_UL))
3205
3206 #if defined(TARGET_PPC64)
3207 /* ldarx */
3208 LARX(ldarx, DEF_MEMOP(MO_Q))
3209 /* stdcx. */
3210 STCX(stdcx_, DEF_MEMOP(MO_Q))
3211
3212 /* lqarx */
3213 static void gen_lqarx(DisasContext *ctx)
3214 {
3215 TCGv EA;
3216 int rd = rD(ctx->opcode);
3217 TCGv gpr1, gpr2;
3218
3219 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3220 (rd == rB(ctx->opcode)))) {
3221 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3222 return;
3223 }
3224
3225 gen_set_access_type(ctx, ACCESS_RES);
3226 EA = tcg_temp_local_new();
3227 gen_addr_reg_index(ctx, EA);
3228 gen_check_align(ctx, EA, 15);
3229 if (unlikely(ctx->le_mode)) {
3230 gpr1 = cpu_gpr[rd+1];
3231 gpr2 = cpu_gpr[rd];
3232 } else {
3233 gpr1 = cpu_gpr[rd];
3234 gpr2 = cpu_gpr[rd+1];
3235 }
3236 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3237 tcg_gen_mov_tl(cpu_reserve, EA);
3238 gen_addr_add(ctx, EA, EA, 8);
3239 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3240
3241 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3242 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3243 tcg_temp_free(EA);
3244 }
3245
3246 /* stqcx. */
3247 static void gen_stqcx_(DisasContext *ctx)
3248 {
3249 TCGv EA;
3250 int reg = rS(ctx->opcode);
3251 int len = 16;
3252 #if !defined(CONFIG_USER_ONLY)
3253 TCGLabel *l1;
3254 TCGv gpr1, gpr2;
3255 #endif
3256
3257 if (unlikely((rD(ctx->opcode) & 1))) {
3258 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3259 return;
3260 }
3261 gen_set_access_type(ctx, ACCESS_RES);
3262 EA = tcg_temp_local_new();
3263 gen_addr_reg_index(ctx, EA);
3264 if (len > 1) {
3265 gen_check_align(ctx, EA, (len) - 1);
3266 }
3267
3268 #if defined(CONFIG_USER_ONLY)
3269 gen_conditional_store(ctx, EA, reg, 16);
3270 #else
3271 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3272 l1 = gen_new_label();
3273 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3274 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3275
3276 if (unlikely(ctx->le_mode)) {
3277 gpr1 = cpu_gpr[reg + 1];
3278 gpr2 = cpu_gpr[reg];
3279 } else {
3280 gpr1 = cpu_gpr[reg];
3281 gpr2 = cpu_gpr[reg + 1];
3282 }
3283 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3284 gen_addr_add(ctx, EA, EA, 8);
3285 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3286
3287 gen_set_label(l1);
3288 tcg_gen_movi_tl(cpu_reserve, -1);
3289 #endif
3290 tcg_temp_free(EA);
3291 }
3292
3293 #endif /* defined(TARGET_PPC64) */
3294
3295 /* sync */
3296 static void gen_sync(DisasContext *ctx)
3297 {
3298 uint32_t l = (ctx->opcode >> 21) & 3;
3299
3300 /*
3301 * We may need to check for a pending TLB flush.
3302 *
3303 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3304 *
3305 * Additionally, this can only happen in kernel mode however so
3306 * check MSR_PR as well.
3307 */
3308 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3309 gen_check_tlb_flush(ctx, true);
3310 }
3311 }
3312
3313 /* wait */
3314 static void gen_wait(DisasContext *ctx)
3315 {
3316 TCGv_i32 t0 = tcg_const_i32(1);
3317 tcg_gen_st_i32(t0, cpu_env,
3318 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3319 tcg_temp_free_i32(t0);
3320 /* Stop translation, as the CPU is supposed to sleep from now */
3321 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3322 }
3323
3324 #if defined(TARGET_PPC64)
3325 static void gen_doze(DisasContext *ctx)
3326 {
3327 #if defined(CONFIG_USER_ONLY)
3328 GEN_PRIV;
3329 #else
3330 TCGv_i32 t;
3331
3332 CHK_HV;
3333 t = tcg_const_i32(PPC_PM_DOZE);
3334 gen_helper_pminsn(cpu_env, t);
3335 tcg_temp_free_i32(t);
3336 gen_stop_exception(ctx);
3337 #endif /* defined(CONFIG_USER_ONLY) */
3338 }
3339
3340 static void gen_nap(DisasContext *ctx)
3341 {
3342 #if defined(CONFIG_USER_ONLY)
3343 GEN_PRIV;
3344 #else
3345 TCGv_i32 t;
3346
3347 CHK_HV;
3348 t = tcg_const_i32(PPC_PM_NAP);
3349 gen_helper_pminsn(cpu_env, t);
3350 tcg_temp_free_i32(t);
3351 gen_stop_exception(ctx);
3352 #endif /* defined(CONFIG_USER_ONLY) */
3353 }
3354
3355 static void gen_stop(DisasContext *ctx)
3356 {
3357 gen_nap(ctx);
3358 }
3359
3360 static void gen_sleep(DisasContext *ctx)
3361 {
3362 #if defined(CONFIG_USER_ONLY)
3363 GEN_PRIV;
3364 #else
3365 TCGv_i32 t;
3366
3367 CHK_HV;
3368 t = tcg_const_i32(PPC_PM_SLEEP);
3369 gen_helper_pminsn(cpu_env, t);
3370 tcg_temp_free_i32(t);
3371 gen_stop_exception(ctx);
3372 #endif /* defined(CONFIG_USER_ONLY) */
3373 }
3374
3375 static void gen_rvwinkle(DisasContext *ctx)
3376 {
3377 #if defined(CONFIG_USER_ONLY)
3378 GEN_PRIV;
3379 #else
3380 TCGv_i32 t;
3381
3382 CHK_HV;
3383 t = tcg_const_i32(PPC_PM_RVWINKLE);
3384 gen_helper_pminsn(cpu_env, t);
3385 tcg_temp_free_i32(t);
3386 gen_stop_exception(ctx);
3387 #endif /* defined(CONFIG_USER_ONLY) */
3388 }
3389 #endif /* #if defined(TARGET_PPC64) */
3390
3391 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3392 {
3393 #if defined(TARGET_PPC64)
3394 if (ctx->has_cfar)
3395 tcg_gen_movi_tl(cpu_cfar, nip);
3396 #endif
3397 }
3398
3399 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3400 {
3401 if (unlikely(ctx->singlestep_enabled)) {
3402 return false;
3403 }
3404
3405 #ifndef CONFIG_USER_ONLY
3406 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3407 #else
3408 return true;
3409 #endif
3410 }
3411
3412 /*** Branch ***/
3413 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3414 {
3415 if (NARROW_MODE(ctx)) {
3416 dest = (uint32_t) dest;
3417 }
3418 if (use_goto_tb(ctx, dest)) {
3419 tcg_gen_goto_tb(n);
3420 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3421 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3422 } else {
3423 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3424 if (unlikely(ctx->singlestep_enabled)) {
3425 if ((ctx->singlestep_enabled &
3426 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3427 (ctx->exception == POWERPC_EXCP_BRANCH ||
3428 ctx->exception == POWERPC_EXCP_TRACE)) {
3429 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3430 }
3431 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3432 gen_debug_exception(ctx);
3433 }
3434 }
3435 tcg_gen_exit_tb(0);
3436 }
3437 }
3438
3439 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3440 {
3441 if (NARROW_MODE(ctx)) {
3442 nip = (uint32_t)nip;
3443 }
3444 tcg_gen_movi_tl(cpu_lr, nip);
3445 }
3446
3447 /* b ba bl bla */
3448 static void gen_b(DisasContext *ctx)
3449 {
3450 target_ulong li, target;
3451
3452 ctx->exception = POWERPC_EXCP_BRANCH;
3453 /* sign extend LI */
3454 li = LI(ctx->opcode);
3455 li = (li ^ 0x02000000) - 0x02000000;
3456 if (likely(AA(ctx->opcode) == 0)) {
3457 target = ctx->nip + li - 4;
3458 } else {
3459 target = li;
3460 }
3461 if (LK(ctx->opcode)) {
3462 gen_setlr(ctx, ctx->nip);
3463 }
3464 gen_update_cfar(ctx, ctx->nip - 4);
3465 gen_goto_tb(ctx, 0, target);
3466 }
3467
3468 #define BCOND_IM 0
3469 #define BCOND_LR 1
3470 #define BCOND_CTR 2
3471 #define BCOND_TAR 3
3472
3473 static inline void gen_bcond(DisasContext *ctx, int type)
3474 {
3475 uint32_t bo = BO(ctx->opcode);
3476 TCGLabel *l1;
3477 TCGv target;
3478
3479 ctx->exception = POWERPC_EXCP_BRANCH;
3480 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3481 target = tcg_temp_local_new();
3482 if (type == BCOND_CTR)
3483 tcg_gen_mov_tl(target, cpu_ctr);
3484 else if (type == BCOND_TAR)
3485 gen_load_spr(target, SPR_TAR);
3486 else
3487 tcg_gen_mov_tl(target, cpu_lr);
3488 } else {
3489 TCGV_UNUSED(target);
3490 }
3491 if (LK(ctx->opcode))
3492 gen_setlr(ctx, ctx->nip);
3493 l1 = gen_new_label();
3494 if ((bo & 0x4) == 0) {
3495 /* Decrement and test CTR */
3496 TCGv temp = tcg_temp_new();
3497 if (unlikely(type == BCOND_CTR)) {
3498 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3499 return;
3500 }
3501 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3502 if (NARROW_MODE(ctx)) {
3503 tcg_gen_ext32u_tl(temp, cpu_ctr);
3504 } else {
3505 tcg_gen_mov_tl(temp, cpu_ctr);
3506 }
3507 if (bo & 0x2) {
3508 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3509 } else {
3510 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3511 }
3512 tcg_temp_free(temp);
3513 }
3514 if ((bo & 0x10) == 0) {
3515 /* Test CR */
3516 uint32_t bi = BI(ctx->opcode);
3517 uint32_t mask = 0x08 >> (bi & 0x03);
3518 TCGv_i32 temp = tcg_temp_new_i32();
3519
3520 if (bo & 0x8) {
3521 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3522 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3523 } else {
3524 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3525 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3526 }
3527 tcg_temp_free_i32(temp);
3528 }
3529 gen_update_cfar(ctx, ctx->nip - 4);
3530 if (type == BCOND_IM) {
3531 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3532 if (likely(AA(ctx->opcode) == 0)) {
3533 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3534 } else {
3535 gen_goto_tb(ctx, 0, li);
3536 }
3537 if ((bo & 0x14) != 0x14) {
3538 gen_set_label(l1);
3539 gen_goto_tb(ctx, 1, ctx->nip);
3540 }
3541 } else {
3542 if (NARROW_MODE(ctx)) {
3543 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3544 } else {
3545 tcg_gen_andi_tl(cpu_nip, target, ~3);
3546 }
3547 tcg_gen_exit_tb(0);
3548 if ((bo & 0x14) != 0x14) {
3549 gen_set_label(l1);
3550 gen_update_nip(ctx, ctx->nip);
3551 tcg_gen_exit_tb(0);
3552 }
3553 }
3554 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3555 tcg_temp_free(target);
3556 }
3557 }
3558
3559 static void gen_bc(DisasContext *ctx)
3560 {
3561 gen_bcond(ctx, BCOND_IM);
3562 }
3563
3564 static void gen_bcctr(DisasContext *ctx)
3565 {
3566 gen_bcond(ctx, BCOND_CTR);
3567 }
3568
3569 static void gen_bclr(DisasContext *ctx)
3570 {
3571 gen_bcond(ctx, BCOND_LR);
3572 }
3573
3574 static void gen_bctar(DisasContext *ctx)
3575 {
3576 gen_bcond(ctx, BCOND_TAR);
3577 }
3578
3579 /*** Condition register logical ***/
3580 #define GEN_CRLOGIC(name, tcg_op, opc) \
3581 static void glue(gen_, name)(DisasContext *ctx) \
3582 { \
3583 uint8_t bitmask; \
3584 int sh; \
3585 TCGv_i32 t0, t1; \
3586 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3587 t0 = tcg_temp_new_i32(); \
3588 if (sh > 0) \
3589 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3590 else if (sh < 0) \
3591 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3592 else \
3593 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3594 t1 = tcg_temp_new_i32(); \
3595 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3596 if (sh > 0) \
3597 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3598 else if (sh < 0) \
3599 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3600 else \
3601 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3602 tcg_op(t0, t0, t1); \
3603 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3604 tcg_gen_andi_i32(t0, t0, bitmask); \
3605 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3606 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3607 tcg_temp_free_i32(t0); \
3608 tcg_temp_free_i32(t1); \
3609 }
3610
3611 /* crand */
3612 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3613 /* crandc */
3614 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3615 /* creqv */
3616 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3617 /* crnand */
3618 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3619 /* crnor */
3620 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3621 /* cror */
3622 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3623 /* crorc */
3624 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3625 /* crxor */
3626 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3627
3628 /* mcrf */
3629 static void gen_mcrf(DisasContext *ctx)
3630 {
3631 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3632 }
3633
3634 /*** System linkage ***/
3635
3636 /* rfi (supervisor only) */
3637 static void gen_rfi(DisasContext *ctx)
3638 {
3639 #if defined(CONFIG_USER_ONLY)
3640 GEN_PRIV;
3641 #else
3642 /* This instruction doesn't exist anymore on 64-bit server
3643 * processors compliant with arch 2.x
3644 */
3645 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3646 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3647 return;
3648 }
3649 /* Restore CPU state */
3650 CHK_SV;
3651 gen_update_cfar(ctx, ctx->nip - 4);
3652 gen_helper_rfi(cpu_env);
3653 gen_sync_exception(ctx);
3654 #endif
3655 }
3656
3657 #if defined(TARGET_PPC64)
3658 static void gen_rfid(DisasContext *ctx)
3659 {
3660 #if defined(CONFIG_USER_ONLY)
3661 GEN_PRIV;
3662 #else
3663 /* Restore CPU state */
3664 CHK_SV;
3665 gen_update_cfar(ctx, ctx->nip - 4);
3666 gen_helper_rfid(cpu_env);
3667 gen_sync_exception(ctx);
3668 #endif
3669 }
3670
3671 static void gen_hrfid(DisasContext *ctx)
3672 {
3673 #if defined(CONFIG_USER_ONLY)
3674 GEN_PRIV;
3675 #else
3676 /* Restore CPU state */
3677 CHK_HV;
3678 gen_helper_hrfid(cpu_env);
3679 gen_sync_exception(ctx);
3680 #endif
3681 }
3682 #endif
3683
3684 /* sc */
3685 #if defined(CONFIG_USER_ONLY)
3686 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3687 #else
3688 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3689 #endif
3690 static void gen_sc(DisasContext *ctx)
3691 {
3692 uint32_t lev;
3693
3694 lev = (ctx->opcode >> 5) & 0x7F;
3695 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3696 }
3697
3698 /*** Trap ***/
3699
3700 /* Check for unconditional traps (always or never) */
3701 static bool check_unconditional_trap(DisasContext *ctx)
3702 {
3703 /* Trap never */
3704 if (TO(ctx->opcode) == 0) {
3705 return true;
3706 }
3707 /* Trap always */
3708 if (TO(ctx->opcode) == 31) {
3709 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3710 return true;
3711 }
3712 return false;
3713 }
3714
3715 /* tw */
3716 static void gen_tw(DisasContext *ctx)
3717 {
3718 TCGv_i32 t0;
3719
3720 if (check_unconditional_trap(ctx)) {
3721 return;
3722 }
3723 t0 = tcg_const_i32(TO(ctx->opcode));
3724 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3725 t0);
3726 tcg_temp_free_i32(t0);
3727 }
3728
3729 /* twi */
3730 static void gen_twi(DisasContext *ctx)
3731 {
3732 TCGv t0;
3733 TCGv_i32 t1;
3734
3735 if (check_unconditional_trap(ctx)) {
3736 return;
3737 }
3738 t0 = tcg_const_tl(SIMM(ctx->opcode));
3739 t1 = tcg_const_i32(TO(ctx->opcode));
3740 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3741 tcg_temp_free(t0);
3742 tcg_temp_free_i32(t1);
3743 }
3744
3745 #if defined(TARGET_PPC64)
3746 /* td */
3747 static void gen_td(DisasContext *ctx)
3748 {
3749 TCGv_i32 t0;
3750
3751 if (check_unconditional_trap(ctx)) {
3752 return;
3753 }
3754 t0 = tcg_const_i32(TO(ctx->opcode));
3755 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3756 t0);
3757 tcg_temp_free_i32(t0);
3758 }
3759
3760 /* tdi */
3761 static void gen_tdi(DisasContext *ctx)
3762 {
3763 TCGv t0;
3764 TCGv_i32 t1;
3765
3766 if (check_unconditional_trap(ctx)) {
3767 return;
3768 }
3769 t0 = tcg_const_tl(SIMM(ctx->opcode));
3770 t1 = tcg_const_i32(TO(ctx->opcode));
3771 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3772 tcg_temp_free(t0);
3773 tcg_temp_free_i32(t1);
3774 }
3775 #endif
3776
3777 /*** Processor control ***/
3778
3779 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3780 {
3781 TCGv t0 = tcg_temp_new();
3782 TCGv t1 = tcg_temp_new();
3783 TCGv t2 = tcg_temp_new();
3784 tcg_gen_mov_tl(dst, cpu_xer);
3785 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3786 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3787 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3788 tcg_gen_or_tl(t0, t0, t1);
3789 tcg_gen_or_tl(dst, dst, t2);
3790 tcg_gen_or_tl(dst, dst, t0);
3791 if (is_isa300(ctx)) {
3792 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3793 tcg_gen_or_tl(dst, dst, t0);
3794 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3795 tcg_gen_or_tl(dst, dst, t0);
3796 }
3797 tcg_temp_free(t0);
3798 tcg_temp_free(t1);
3799 tcg_temp_free(t2);
3800 }
3801
3802 static void gen_write_xer(TCGv src)
3803 {
3804 /* Write all flags, while reading back check for isa300 */
3805 tcg_gen_andi_tl(cpu_xer, src,
3806 ~((1u << XER_SO) |
3807 (1u << XER_OV) | (1u << XER_OV32) |
3808 (1u << XER_CA) | (1u << XER_CA32)));
3809 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3810 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3811 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3812 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3813 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3814 }
3815
3816 /* mcrxr */
3817 static void gen_mcrxr(DisasContext *ctx)
3818 {
3819 TCGv_i32 t0 = tcg_temp_new_i32();
3820 TCGv_i32 t1 = tcg_temp_new_i32();
3821 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3822
3823 tcg_gen_trunc_tl_i32(t0, cpu_so);
3824 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3825 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3826 tcg_gen_shli_i32(t0, t0, 3);
3827 tcg_gen_shli_i32(t1, t1, 2);
3828 tcg_gen_shli_i32(dst, dst, 1);
3829 tcg_gen_or_i32(dst, dst, t0);
3830 tcg_gen_or_i32(dst, dst, t1);
3831 tcg_temp_free_i32(t0);
3832 tcg_temp_free_i32(t1);
3833
3834 tcg_gen_movi_tl(cpu_so, 0);
3835 tcg_gen_movi_tl(cpu_ov, 0);
3836 tcg_gen_movi_tl(cpu_ca, 0);
3837 }
3838
3839 #ifdef TARGET_PPC64
3840 /* mcrxrx */
3841 static void gen_mcrxrx(DisasContext *ctx)
3842 {
3843 TCGv t0 = tcg_temp_new();
3844 TCGv t1 = tcg_temp_new();
3845 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3846
3847 /* copy OV and OV32 */
3848 tcg_gen_shli_tl(t0, cpu_ov, 1);
3849 tcg_gen_or_tl(t0, t0, cpu_ov32);
3850 tcg_gen_shli_tl(t0, t0, 2);
3851 /* copy CA and CA32 */
3852 tcg_gen_shli_tl(t1, cpu_ca, 1);
3853 tcg_gen_or_tl(t1, t1, cpu_ca32);
3854 tcg_gen_or_tl(t0, t0, t1);
3855 tcg_gen_trunc_tl_i32(dst, t0);
3856 tcg_temp_free(t0);
3857 tcg_temp_free(t1);
3858 }
3859 #endif
3860
3861 /* mfcr mfocrf */
3862 static void gen_mfcr(DisasContext *ctx)
3863 {
3864 uint32_t crm, crn;
3865
3866 if (likely(ctx->opcode & 0x00100000)) {
3867 crm = CRM(ctx->opcode);
3868 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3869 crn = ctz32 (crm);
3870 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3871 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3872 cpu_gpr[rD(ctx->opcode)], crn * 4);
3873 }
3874 } else {
3875 TCGv_i32 t0 = tcg_temp_new_i32();
3876 tcg_gen_mov_i32(t0, cpu_crf[0]);
3877 tcg_gen_shli_i32(t0, t0, 4);
3878 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3879 tcg_gen_shli_i32(t0, t0, 4);
3880 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3881 tcg_gen_shli_i32(t0, t0, 4);
3882 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3883 tcg_gen_shli_i32(t0, t0, 4);
3884 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3885 tcg_gen_shli_i32(t0, t0, 4);
3886 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3887 tcg_gen_shli_i32(t0, t0, 4);
3888 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3889 tcg_gen_shli_i32(t0, t0, 4);
3890 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3891 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3892 tcg_temp_free_i32(t0);
3893 }
3894 }
3895
3896 /* mfmsr */
3897 static void gen_mfmsr(DisasContext *ctx)
3898 {
3899 CHK_SV;
3900 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3901 }
3902
3903 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3904 {
3905 #if 0
3906 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3907 printf("ERROR: try to access SPR %d !\n", sprn);
3908 #endif
3909 }
3910 #define SPR_NOACCESS (&spr_noaccess)
3911
3912 /* mfspr */
3913 static inline void gen_op_mfspr(DisasContext *ctx)
3914 {
3915 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3916 uint32_t sprn = SPR(ctx->opcode);
3917
3918 #if defined(CONFIG_USER_ONLY)
3919 read_cb = ctx->spr_cb[sprn].uea_read;
3920 #else
3921 if (ctx->pr) {
3922 read_cb = ctx->spr_cb[sprn].uea_read;
3923 } else if (ctx->hv) {
3924 read_cb = ctx->spr_cb[sprn].hea_read;
3925 } else {
3926 read_cb = ctx->spr_cb[sprn].oea_read;
3927 }
3928 #endif
3929 if (likely(read_cb != NULL)) {
3930 if (likely(read_cb != SPR_NOACCESS)) {
3931 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3932 } else {
3933 /* Privilege exception */
3934 /* This is a hack to avoid warnings when running Linux:
3935 * this OS breaks the PowerPC virtualisation model,
3936 * allowing userland application to read the PVR
3937 */
3938 if (sprn != SPR_PVR) {
3939 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3940 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3941 if (qemu_log_separate()) {
3942 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3943 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3944 }
3945 }
3946 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3947 }
3948 } else {
3949 /* ISA 2.07 defines these as no-ops */
3950 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3951 (sprn >= 808 && sprn <= 811)) {
3952 /* This is a nop */
3953 return;
3954 }
3955 /* Not defined */
3956 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3957 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3958 if (qemu_log_separate()) {
3959 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3960 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3961 }
3962
3963 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3964 * it can generate a priv, a hv emu or a no-op
3965 */
3966 if (sprn & 0x10) {
3967 if (ctx->pr) {
3968 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3969 }
3970 } else {
3971 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3972 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3973 }
3974 }
3975 }
3976 }
3977
3978 static void gen_mfspr(DisasContext *ctx)
3979 {
3980 gen_op_mfspr(ctx);
3981 }
3982
3983 /* mftb */
3984 static void gen_mftb(DisasContext *ctx)
3985 {
3986 gen_op_mfspr(ctx);
3987 }
3988
3989 /* mtcrf mtocrf*/
3990 static void gen_mtcrf(DisasContext *ctx)
3991 {
3992 uint32_t crm, crn;
3993
3994 crm = CRM(ctx->opcode);
3995 if (likely((ctx->opcode & 0x00100000))) {
3996 if (crm && ((crm & (crm - 1)) == 0)) {
3997 TCGv_i32 temp = tcg_temp_new_i32();
3998 crn = ctz32 (crm);
3999 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4000 tcg_gen_shri_i32(temp, temp, crn * 4);
4001 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4002 tcg_temp_free_i32(temp);
4003 }
4004 } else {
4005 TCGv_i32 temp = tcg_temp_new_i32();
4006 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4007 for (crn = 0 ; crn < 8 ; crn++) {
4008 if (crm & (1 << crn)) {
4009 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4010 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4011 }
4012 }
4013 tcg_temp_free_i32(temp);
4014 }
4015 }
4016
4017 /* mtmsr */
4018 #if defined(TARGET_PPC64)
4019 static void gen_mtmsrd(DisasContext *ctx)
4020 {
4021 CHK_SV;
4022
4023 #if !defined(CONFIG_USER_ONLY)
4024 if (ctx->opcode & 0x00010000) {
4025 /* Special form that does not need any synchronisation */
4026 TCGv t0 = tcg_temp_new();
4027 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4028 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4029 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4030 tcg_temp_free(t0);
4031 } else {
4032 /* XXX: we need to update nip before the store
4033 * if we enter power saving mode, we will exit the loop
4034 * directly from ppc_store_msr
4035 */
4036 gen_update_nip(ctx, ctx->nip);
4037 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4038 /* Must stop the translation as machine state (may have) changed */
4039 /* Note that mtmsr is not always defined as context-synchronizing */
4040 gen_stop_exception(ctx);
4041 }
4042 #endif /* !defined(CONFIG_USER_ONLY) */
4043 }
4044 #endif /* defined(TARGET_PPC64) */
4045
4046 static void gen_mtmsr(DisasContext *ctx)
4047 {
4048 CHK_SV;
4049
4050 #if !defined(CONFIG_USER_ONLY)
4051 if (ctx->opcode & 0x00010000) {
4052 /* Special form that does not need any synchronisation */
4053 TCGv t0 = tcg_temp_new();
4054 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4055 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4056 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4057 tcg_temp_free(t0);
4058 } else {
4059 TCGv msr = tcg_temp_new();
4060
4061 /* XXX: we need to update nip before the store
4062 * if we enter power saving mode, we will exit the loop
4063 * directly from ppc_store_msr
4064 */
4065 gen_update_nip(ctx, ctx->nip);
4066 #if defined(TARGET_PPC64)
4067 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4068 #else
4069 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4070 #endif
4071 gen_helper_store_msr(cpu_env, msr);
4072 tcg_temp_free(msr);
4073 /* Must stop the translation as machine state (may have) changed */
4074 /* Note that mtmsr is not always defined as context-synchronizing */
4075 gen_stop_exception(ctx);
4076 }
4077 #endif
4078 }
4079
4080 /* mtspr */
4081 static void gen_mtspr(DisasContext *ctx)
4082 {
4083 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4084 uint32_t sprn = SPR(ctx->opcode);
4085
4086 #if defined(CONFIG_USER_ONLY)
4087 write_cb = ctx->spr_cb[sprn].uea_write;
4088 #else
4089 if (ctx->pr) {
4090 write_cb = ctx->spr_cb[sprn].uea_write;
4091 } else if (ctx->hv) {
4092 write_cb = ctx->spr_cb[sprn].hea_write;
4093 } else {
4094 write_cb = ctx->spr_cb[sprn].oea_write;
4095 }
4096 #endif
4097 if (likely(write_cb != NULL)) {
4098 if (likely(write_cb != SPR_NOACCESS)) {
4099 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4100 } else {
4101 /* Privilege exception */
4102 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4103 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4104 if (qemu_log_separate()) {
4105 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4106 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4107 }
4108 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4109 }
4110 } else {
4111 /* ISA 2.07 defines these as no-ops */
4112 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4113 (sprn >= 808 && sprn <= 811)) {
4114 /* This is a nop */
4115 return;
4116 }
4117
4118 /* Not defined */
4119 if (qemu_log_separate()) {
4120 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4121 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4122 }
4123 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4124 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4125
4126
4127 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4128 * it can generate a priv, a hv emu or a no-op
4129 */
4130 if (sprn & 0x10) {
4131 if (ctx->pr) {
4132 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4133 }
4134 } else {
4135 if (ctx->pr || sprn == 0) {
4136 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4137 }
4138 }
4139 }
4140 }
4141
4142 #if defined(TARGET_PPC64)
4143 /* setb */
4144 static void gen_setb(DisasContext *ctx)
4145 {
4146 TCGv_i32 t0 = tcg_temp_new_i32();
4147 TCGv_i32 t8 = tcg_temp_new_i32();
4148 TCGv_i32 tm1 = tcg_temp_new_i32();
4149 int crf = crfS(ctx->opcode);
4150
4151 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4152 tcg_gen_movi_i32(t8, 8);
4153 tcg_gen_movi_i32(tm1, -1);
4154 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4155 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4156
4157 tcg_temp_free_i32(t0);
4158 tcg_temp_free_i32(t8);
4159 tcg_temp_free_i32(tm1);
4160 }
4161 #endif
4162
4163 /*** Cache management ***/
4164
4165 /* dcbf */
4166 static void gen_dcbf(DisasContext *ctx)
4167 {
4168 /* XXX: specification says this is treated as a load by the MMU */
4169 TCGv t0;
4170 gen_set_access_type(ctx, ACCESS_CACHE);
4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
4173 gen_qemu_ld8u(ctx, t0, t0);
4174 tcg_temp_free(t0);
4175 }
4176
4177 /* dcbi (Supervisor only) */
4178 static void gen_dcbi(DisasContext *ctx)
4179 {
4180 #if defined(CONFIG_USER_ONLY)
4181 GEN_PRIV;
4182 #else
4183 TCGv EA, val;
4184
4185 CHK_SV;
4186 EA = tcg_temp_new();
4187 gen_set_access_type(ctx, ACCESS_CACHE);
4188 gen_addr_reg_index(ctx, EA);
4189 val = tcg_temp_new();
4190 /* XXX: specification says this should be treated as a store by the MMU */
4191 gen_qemu_ld8u(ctx, val, EA);
4192 gen_qemu_st8(ctx, val, EA);
4193 tcg_temp_free(val);
4194 tcg_temp_free(EA);
4195 #endif /* defined(CONFIG_USER_ONLY) */
4196 }
4197
4198 /* dcdst */
4199 static void gen_dcbst(DisasContext *ctx)
4200 {
4201 /* XXX: specification say this is treated as a load by the MMU */
4202 TCGv t0;
4203 gen_set_access_type(ctx, ACCESS_CACHE);
4204 t0 = tcg_temp_new();
4205 gen_addr_reg_index(ctx, t0);
4206 gen_qemu_ld8u(ctx, t0, t0);
4207 tcg_temp_free(t0);
4208 }
4209
4210 /* dcbt */
4211 static void gen_dcbt(DisasContext *ctx)
4212 {
4213 /* interpreted as no-op */
4214 /* XXX: specification say this is treated as a load by the MMU
4215 * but does not generate any exception
4216 */
4217 }
4218
4219 /* dcbtst */
4220 static void gen_dcbtst(DisasContext *ctx)
4221 {
4222 /* interpreted as no-op */
4223 /* XXX: specification say this is treated as a load by the MMU
4224 * but does not generate any exception
4225 */
4226 }
4227
4228 /* dcbtls */
4229 static void gen_dcbtls(DisasContext *ctx)
4230 {
4231 /* Always fails locking the cache */
4232 TCGv t0 = tcg_temp_new();
4233 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4234 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4235 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4236 tcg_temp_free(t0);
4237 }
4238
4239 /* dcbz */
4240 static void gen_dcbz(DisasContext *ctx)
4241 {
4242 TCGv tcgv_addr;
4243 TCGv_i32 tcgv_op;
4244
4245 gen_set_access_type(ctx, ACCESS_CACHE);
4246 tcgv_addr = tcg_temp_new();
4247 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4248 gen_addr_reg_index(ctx, tcgv_addr);
4249 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4250 tcg_temp_free(tcgv_addr);
4251 tcg_temp_free_i32(tcgv_op);
4252 }
4253
4254 /* dst / dstt */
4255 static void gen_dst(DisasContext *ctx)
4256 {
4257 if (rA(ctx->opcode) == 0) {
4258 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4259 } else {
4260 /* interpreted as no-op */
4261 }
4262 }
4263
4264 /* dstst /dststt */
4265 static void gen_dstst(DisasContext *ctx)
4266 {
4267 if (rA(ctx->opcode) == 0) {
4268 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4269 } else {
4270 /* interpreted as no-op */
4271 }
4272
4273 }
4274
4275 /* dss / dssall */
4276 static void gen_dss(DisasContext *ctx)
4277 {
4278 /* interpreted as no-op */
4279 }
4280
4281 /* icbi */
4282 static void gen_icbi(DisasContext *ctx)
4283 {
4284 TCGv t0;
4285 gen_set_access_type(ctx, ACCESS_CACHE);
4286 t0 = tcg_temp_new();
4287 gen_addr_reg_index(ctx, t0);
4288 gen_helper_icbi(cpu_env, t0);
4289 tcg_temp_free(t0);
4290 }
4291
4292 /* Optional: */
4293 /* dcba */
4294 static void gen_dcba(DisasContext *ctx)
4295 {
4296 /* interpreted as no-op */
4297 /* XXX: specification say this is treated as a store by the MMU
4298 * but does not generate any exception
4299 */
4300 }
4301
4302 /*** Segment register manipulation ***/
4303 /* Supervisor only: */
4304
4305 /* mfsr */
4306 static void gen_mfsr(DisasContext *ctx)
4307 {
4308 #if defined(CONFIG_USER_ONLY)
4309 GEN_PRIV;
4310 #else
4311 TCGv t0;
4312
4313 CHK_SV;
4314 t0 = tcg_const_tl(SR(ctx->opcode));
4315 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4316 tcg_temp_free(t0);
4317 #endif /* defined(CONFIG_USER_ONLY) */
4318 }
4319
4320 /* mfsrin */
4321 static void gen_mfsrin(DisasContext *ctx)
4322 {
4323 #if defined(CONFIG_USER_ONLY)
4324 GEN_PRIV;
4325 #else
4326 TCGv t0;
4327
4328 CHK_SV;
4329 t0 = tcg_temp_new();
4330 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4331 tcg_gen_andi_tl(t0, t0, 0xF);
4332 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4333 tcg_temp_free(t0);
4334 #endif /* defined(CONFIG_USER_ONLY) */
4335 }
4336
4337 /* mtsr */
4338 static void gen_mtsr(DisasContext *ctx)
4339 {
4340 #if defined(CONFIG_USER_ONLY)
4341 GEN_PRIV;
4342 #else
4343 TCGv t0;
4344
4345 CHK_SV;
4346 t0 = tcg_const_tl(SR(ctx->opcode));
4347 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4348 tcg_temp_free(t0);
4349 #endif /* defined(CONFIG_USER_ONLY) */
4350 }
4351
4352 /* mtsrin */
4353 static void gen_mtsrin(DisasContext *ctx)
4354 {
4355 #if defined(CONFIG_USER_ONLY)
4356 GEN_PRIV;
4357 #else
4358 TCGv t0;
4359 CHK_SV;
4360
4361 t0 = tcg_temp_new();
4362 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4363 tcg_gen_andi_tl(t0, t0, 0xF);
4364 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4365 tcg_temp_free(t0);
4366 #endif /* defined(CONFIG_USER_ONLY) */
4367 }
4368
4369 #if defined(TARGET_PPC64)
4370 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4371
4372 /* mfsr */
4373 static void gen_mfsr_64b(DisasContext *ctx)
4374 {
4375 #if defined(CONFIG_USER_ONLY)
4376 GEN_PRIV;
4377 #else
4378 TCGv t0;
4379
4380 CHK_SV;
4381 t0 = tcg_const_tl(SR(ctx->opcode));
4382 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4383 tcg_temp_free(t0);
4384 #endif /* defined(CONFIG_USER_ONLY) */
4385 }
4386
4387 /* mfsrin */
4388 static void gen_mfsrin_64b(DisasContext *ctx)
4389 {
4390 #if defined(CONFIG_USER_ONLY)
4391 GEN_PRIV;
4392 #else
4393 TCGv t0;
4394
4395 CHK_SV;
4396 t0 = tcg_temp_new();
4397 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4398 tcg_gen_andi_tl(t0, t0, 0xF);
4399 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4400 tcg_temp_free(t0);
4401 #endif /* defined(CONFIG_USER_ONLY) */
4402 }
4403
4404 /* mtsr */
4405 static void gen_mtsr_64b(DisasContext *ctx)
4406 {
4407 #if defined(CONFIG_USER_ONLY)
4408 GEN_PRIV;
4409 #else
4410 TCGv t0;
4411
4412 CHK_SV;
4413 t0 = tcg_const_tl(SR(ctx->opcode));
4414 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4415 tcg_temp_free(t0);
4416 #endif /* defined(CONFIG_USER_ONLY) */
4417 }
4418
4419 /* mtsrin */
4420 static void gen_mtsrin_64b(DisasContext *ctx)
4421 {
4422 #if defined(CONFIG_USER_ONLY)
4423 GEN_PRIV;
4424 #else
4425 TCGv t0;
4426
4427 CHK_SV;
4428 t0 = tcg_temp_new();
4429 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4430 tcg_gen_andi_tl(t0, t0, 0xF);
4431 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4432 tcg_temp_free(t0);
4433 #endif /* defined(CONFIG_USER_ONLY) */
4434 }
4435
4436 /* slbmte */
4437 static void gen_slbmte(DisasContext *ctx)
4438 {
4439 #if defined(CONFIG_USER_ONLY)
4440 GEN_PRIV;
4441 #else
4442 CHK_SV;
4443
4444 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4445 cpu_gpr[rS(ctx->opcode)]);
4446 #endif /* defined(CONFIG_USER_ONLY) */
4447 }
4448
4449 static void gen_slbmfee(DisasContext *ctx)
4450 {
4451 #if defined(CONFIG_USER_ONLY)
4452 GEN_PRIV;
4453 #else
4454 CHK_SV;
4455
4456 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4457 cpu_gpr[rB(ctx->opcode)]);
4458 #endif /* defined(CONFIG_USER_ONLY) */
4459 }
4460
4461 static void gen_slbmfev(DisasContext *ctx)
4462 {
4463 #if defined(CONFIG_USER_ONLY)
4464 GEN_PRIV;
4465 #else
4466 CHK_SV;
4467
4468 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4469 cpu_gpr[rB(ctx->opcode)]);
4470 #endif /* defined(CONFIG_USER_ONLY) */
4471 }
4472
4473 static void gen_slbfee_(DisasContext *ctx)
4474 {
4475 #if defined(CONFIG_USER_ONLY)
4476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4477 #else
4478 TCGLabel *l1, *l2;
4479
4480 if (unlikely(ctx->pr)) {
4481 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4482 return;
4483 }
4484 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4485 cpu_gpr[rB(ctx->opcode)]);
4486 l1 = gen_new_label();
4487 l2 = gen_new_label();
4488 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4489 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4490 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4491 tcg_gen_br(l2);
4492 gen_set_label(l1);
4493 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4494 gen_set_label(l2);
4495 #endif
4496 }
4497 #endif /* defined(TARGET_PPC64) */
4498
4499 /*** Lookaside buffer management ***/
4500 /* Optional & supervisor only: */
4501
4502 /* tlbia */
4503 static void gen_tlbia(DisasContext *ctx)
4504 {
4505 #if defined(CONFIG_USER_ONLY)
4506 GEN_PRIV;
4507 #else
4508 CHK_HV;
4509
4510 gen_helper_tlbia(cpu_env);
4511 #endif /* defined(CONFIG_USER_ONLY) */
4512 }
4513
4514 /* tlbiel */
4515 static void gen_tlbiel(DisasContext *ctx)
4516 {
4517 #if defined(CONFIG_USER_ONLY)
4518 GEN_PRIV;
4519 #else
4520 CHK_SV;
4521
4522 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4523 #endif /* defined(CONFIG_USER_ONLY) */
4524 }
4525
4526 /* tlbie */
4527 static void gen_tlbie(DisasContext *ctx)
4528 {
4529 #if defined(CONFIG_USER_ONLY)
4530 GEN_PRIV;
4531 #else
4532 TCGv_i32 t1;
4533 CHK_HV;
4534
4535 if (NARROW_MODE(ctx)) {
4536 TCGv t0 = tcg_temp_new();
4537 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4538 gen_helper_tlbie(cpu_env, t0);
4539 tcg_temp_free(t0);
4540 } else {
4541 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4542 }
4543 t1 = tcg_temp_new_i32();
4544 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4545 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4546 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4547 tcg_temp_free_i32(t1);
4548 #endif /* defined(CONFIG_USER_ONLY) */
4549 }
4550
4551 /* tlbsync */
4552 static void gen_tlbsync(DisasContext *ctx)
4553 {
4554 #if defined(CONFIG_USER_ONLY)
4555 GEN_PRIV;
4556 #else
4557 CHK_HV;
4558
4559 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4560 if (ctx->insns_flags & PPC_BOOKE) {
4561 gen_check_tlb_flush(ctx, true);
4562 }
4563 #endif /* defined(CONFIG_USER_ONLY) */
4564 }
4565
4566 #if defined(TARGET_PPC64)
4567 /* slbia */
4568 static void gen_slbia(DisasContext *ctx)
4569 {
4570 #if defined(CONFIG_USER_ONLY)
4571 GEN_PRIV;
4572 #else
4573 CHK_SV;
4574
4575 gen_helper_slbia(cpu_env);
4576 #endif /* defined(CONFIG_USER_ONLY) */
4577 }
4578
4579 /* slbie */
4580 static void gen_slbie(DisasContext *ctx)
4581 {
4582 #if defined(CONFIG_USER_ONLY)
4583 GEN_PRIV;
4584 #else
4585 CHK_SV;
4586
4587 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4588 #endif /* defined(CONFIG_USER_ONLY) */
4589 }
4590
4591 /* slbieg */
4592 static void gen_slbieg(DisasContext *ctx)
4593 {
4594 #if defined(CONFIG_USER_ONLY)
4595 GEN_PRIV;
4596 #else
4597 CHK_SV;
4598
4599 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4600 #endif /* defined(CONFIG_USER_ONLY) */
4601 }
4602
4603 /* slbsync */
4604 static void gen_slbsync(DisasContext *ctx)
4605 {
4606 #if defined(CONFIG_USER_ONLY)
4607 GEN_PRIV;
4608 #else
4609 CHK_SV;
4610 gen_check_tlb_flush(ctx, true);
4611 #endif /* defined(CONFIG_USER_ONLY) */
4612 }
4613
4614 #endif /* defined(TARGET_PPC64) */
4615
4616 /*** External control ***/
4617 /* Optional: */
4618
4619 /* eciwx */
4620 static void gen_eciwx(DisasContext *ctx)
4621 {
4622 TCGv t0;
4623 /* Should check EAR[E] ! */
4624 gen_set_access_type(ctx, ACCESS_EXT);
4625 t0 = tcg_temp_new();
4626 gen_addr_reg_index(ctx, t0);
4627 gen_check_align(ctx, t0, 0x03);
4628 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4629 tcg_temp_free(t0);
4630 }
4631
4632 /* ecowx */
4633 static void gen_ecowx(DisasContext *ctx)
4634 {
4635 TCGv t0;
4636 /* Should check EAR[E] ! */
4637 gen_set_access_type(ctx, ACCESS_EXT);
4638 t0 = tcg_temp_new();
4639 gen_addr_reg_index(ctx, t0);
4640 gen_check_align(ctx, t0, 0x03);
4641 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4642 tcg_temp_free(t0);
4643 }
4644
4645 /* PowerPC 601 specific instructions */
4646
4647 /* abs - abs. */
4648 static void gen_abs(DisasContext *ctx)
4649 {
4650 TCGLabel *l1 = gen_new_label();
4651 TCGLabel *l2 = gen_new_label();
4652 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4653 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4654 tcg_gen_br(l2);
4655 gen_set_label(l1);
4656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4657 gen_set_label(l2);
4658 if (unlikely(Rc(ctx->opcode) != 0))
4659 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4660 }
4661
4662 /* abso - abso. */
4663 static void gen_abso(DisasContext *ctx)
4664 {
4665 TCGLabel *l1 = gen_new_label();
4666 TCGLabel *l2 = gen_new_label();
4667 TCGLabel *l3 = gen_new_label();
4668 /* Start with XER OV disabled, the most likely case */
4669 tcg_gen_movi_tl(cpu_ov, 0);
4670 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4671 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4672 tcg_gen_movi_tl(cpu_ov, 1);
4673 tcg_gen_movi_tl(cpu_so, 1);
4674 tcg_gen_br(l2);
4675 gen_set_label(l1);
4676 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_br(l3);
4678 gen_set_label(l2);
4679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4680 gen_set_label(l3);
4681 if (unlikely(Rc(ctx->opcode) != 0))
4682 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4683 }
4684
4685 /* clcs */
4686 static void gen_clcs(DisasContext *ctx)
4687 {
4688 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4689 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4690 tcg_temp_free_i32(t0);
4691 /* Rc=1 sets CR0 to an undefined state */
4692 }
4693
4694 /* div - div. */
4695 static void gen_div(DisasContext *ctx)
4696 {
4697 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4698 cpu_gpr[rB(ctx->opcode)]);
4699 if (unlikely(Rc(ctx->opcode) != 0))
4700 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4701 }
4702
4703 /* divo - divo. */
4704 static void gen_divo(DisasContext *ctx)
4705 {
4706 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4707 cpu_gpr[rB(ctx->opcode)]);
4708 if (unlikely(Rc(ctx->opcode) != 0))
4709 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4710 }
4711
4712 /* divs - divs. */
4713 static void gen_divs(DisasContext *ctx)
4714 {
4715 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4716 cpu_gpr[rB(ctx->opcode)]);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4719 }
4720
4721 /* divso - divso. */
4722 static void gen_divso(DisasContext *ctx)
4723 {
4724 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4725 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4726 if (unlikely(Rc(ctx->opcode) != 0))
4727 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4728 }
4729
4730 /* doz - doz. */
4731 static void gen_doz(DisasContext *ctx)
4732 {
4733 TCGLabel *l1 = gen_new_label();
4734 TCGLabel *l2 = gen_new_label();
4735 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4736 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4737 tcg_gen_br(l2);
4738 gen_set_label(l1);
4739 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4740 gen_set_label(l2);
4741 if (unlikely(Rc(ctx->opcode) != 0))
4742 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4743 }
4744
4745 /* dozo - dozo. */
4746 static void gen_dozo(DisasContext *ctx)
4747 {
4748 TCGLabel *l1 = gen_new_label();
4749 TCGLabel *l2 = gen_new_label();
4750 TCGv t0 = tcg_temp_new();
4751 TCGv t1 = tcg_temp_new();
4752 TCGv t2 = tcg_temp_new();
4753 /* Start with XER OV disabled, the most likely case */
4754 tcg_gen_movi_tl(cpu_ov, 0);
4755 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4756 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4757 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4758 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4759 tcg_gen_andc_tl(t1, t1, t2);
4760 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4761 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4762 tcg_gen_movi_tl(cpu_ov, 1);
4763 tcg_gen_movi_tl(cpu_so, 1);
4764 tcg_gen_br(l2);
4765 gen_set_label(l1);
4766 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4767 gen_set_label(l2);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
4770 tcg_temp_free(t2);
4771 if (unlikely(Rc(ctx->opcode) != 0))
4772 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4773 }
4774
4775 /* dozi */
4776 static void gen_dozi(DisasContext *ctx)
4777 {
4778 target_long simm = SIMM(ctx->opcode);
4779 TCGLabel *l1 = gen_new_label();
4780 TCGLabel *l2 = gen_new_label();
4781 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4782 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4783 tcg_gen_br(l2);
4784 gen_set_label(l1);
4785 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4786 gen_set_label(l2);
4787 if (unlikely(Rc(ctx->opcode) != 0))
4788 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4789 }
4790
4791 /* lscbx - lscbx. */
4792 static void gen_lscbx(DisasContext *ctx)
4793 {
4794 TCGv t0 = tcg_temp_new();
4795 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4796 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4797 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4798
4799 gen_addr_reg_index(ctx, t0);
4800 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4801 tcg_temp_free_i32(t1);
4802 tcg_temp_free_i32(t2);
4803 tcg_temp_free_i32(t3);
4804 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4805 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4806 if (unlikely(Rc(ctx->opcode) != 0))
4807 gen_set_Rc0(ctx, t0);
4808 tcg_temp_free(t0);
4809 }
4810
4811 /* maskg - maskg. */
4812 static void gen_maskg(DisasContext *ctx)
4813 {
4814 TCGLabel *l1 = gen_new_label();
4815 TCGv t0 = tcg_temp_new();
4816 TCGv t1 = tcg_temp_new();
4817 TCGv t2 = tcg_temp_new();
4818 TCGv t3 = tcg_temp_new();
4819 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4820 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4821 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4822 tcg_gen_addi_tl(t2, t0, 1);
4823 tcg_gen_shr_tl(t2, t3, t2);
4824 tcg_gen_shr_tl(t3, t3, t1);
4825 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4826 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4827 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4828 gen_set_label(l1);
4829 tcg_temp_free(t0);
4830 tcg_temp_free(t1);
4831 tcg_temp_free(t2);
4832 tcg_temp_free(t3);
4833 if (unlikely(Rc(ctx->opcode) != 0))
4834 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4835 }
4836
4837 /* maskir - maskir. */
4838 static void gen_maskir(DisasContext *ctx)
4839 {
4840 TCGv t0 = tcg_temp_new();
4841 TCGv t1 = tcg_temp_new();
4842 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4843 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4844 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 tcg_temp_free(t0);
4846 tcg_temp_free(t1);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4849 }
4850
4851 /* mul - mul. */
4852 static void gen_mul(DisasContext *ctx)
4853 {
4854 TCGv_i64 t0 = tcg_temp_new_i64();
4855 TCGv_i64 t1 = tcg_temp_new_i64();
4856 TCGv t2 = tcg_temp_new();
4857 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4858 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4859 tcg_gen_mul_i64(t0, t0, t1);
4860 tcg_gen_trunc_i64_tl(t2, t0);
4861 gen_store_spr(SPR_MQ, t2);
4862 tcg_gen_shri_i64(t1, t0, 32);
4863 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4864 tcg_temp_free_i64(t0);
4865 tcg_temp_free_i64(t1);
4866 tcg_temp_free(t2);
4867 if (unlikely(Rc(ctx->opcode) != 0))
4868 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4869 }
4870
4871 /* mulo - mulo. */
4872 static void gen_mulo(DisasContext *ctx)
4873 {
4874 TCGLabel *l1 = gen_new_label();
4875 TCGv_i64 t0 = tcg_temp_new_i64();
4876 TCGv_i64 t1 = tcg_temp_new_i64();
4877 TCGv t2 = tcg_temp_new();
4878 /* Start with XER OV disabled, the most likely case */
4879 tcg_gen_movi_tl(cpu_ov, 0);
4880 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4881 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4882 tcg_gen_mul_i64(t0, t0, t1);
4883 tcg_gen_trunc_i64_tl(t2, t0);
4884 gen_store_spr(SPR_MQ, t2);
4885 tcg_gen_shri_i64(t1, t0, 32);
4886 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4887 tcg_gen_ext32s_i64(t1, t0);
4888 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4889 tcg_gen_movi_tl(cpu_ov, 1);
4890 tcg_gen_movi_tl(cpu_so, 1);
4891 gen_set_label(l1);
4892 tcg_temp_free_i64(t0);
4893 tcg_temp_free_i64(t1);
4894 tcg_temp_free(t2);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4897 }
4898
4899 /* nabs - nabs. */
4900 static void gen_nabs(DisasContext *ctx)
4901 {
4902 TCGLabel *l1 = gen_new_label();
4903 TCGLabel *l2 = gen_new_label();
4904 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4905 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4906 tcg_gen_br(l2);
4907 gen_set_label(l1);
4908 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4909 gen_set_label(l2);
4910 if (unlikely(Rc(ctx->opcode) != 0))
4911 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4912 }
4913
4914 /* nabso - nabso. */
4915 static void gen_nabso(DisasContext *ctx)
4916 {
4917 TCGLabel *l1 = gen_new_label();
4918 TCGLabel *l2 = gen_new_label();
4919 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4920 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4921 tcg_gen_br(l2);
4922 gen_set_label(l1);
4923 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4924 gen_set_label(l2);
4925 /* nabs never overflows */
4926 tcg_gen_movi_tl(cpu_ov, 0);
4927 if (unlikely(Rc(ctx->opcode) != 0))
4928 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4929 }
4930
4931 /* rlmi - rlmi. */
4932 static void gen_rlmi(DisasContext *ctx)
4933 {
4934 uint32_t mb = MB(ctx->opcode);
4935 uint32_t me = ME(ctx->opcode);
4936 TCGv t0 = tcg_temp_new();
4937 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4938 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4939 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4940 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4941 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4942 tcg_temp_free(t0);
4943 if (unlikely(Rc(ctx->opcode) != 0))
4944 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4945 }
4946
4947 /* rrib - rrib. */
4948 static void gen_rrib(DisasContext *ctx)
4949 {
4950 TCGv t0 = tcg_temp_new();
4951 TCGv t1 = tcg_temp_new();
4952 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4953 tcg_gen_movi_tl(t1, 0x80000000);
4954 tcg_gen_shr_tl(t1, t1, t0);
4955 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4956 tcg_gen_and_tl(t0, t0, t1);
4957 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4958 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4959 tcg_temp_free(t0);
4960 tcg_temp_free(t1);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963 }
4964
4965 /* sle - sle. */
4966 static void gen_sle(DisasContext *ctx)
4967 {
4968 TCGv t0 = tcg_temp_new();
4969 TCGv t1 = tcg_temp_new();
4970 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4971 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4972 tcg_gen_subfi_tl(t1, 32, t1);
4973 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4974 tcg_gen_or_tl(t1, t0, t1);
4975 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4976 gen_store_spr(SPR_MQ, t1);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
4979 if (unlikely(Rc(ctx->opcode) != 0))
4980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4981 }
4982
4983 /* sleq - sleq. */
4984 static void gen_sleq(DisasContext *ctx)
4985 {
4986 TCGv t0 = tcg_temp_new();
4987 TCGv t1 = tcg_temp_new();
4988 TCGv t2 = tcg_temp_new();
4989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4990 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4991 tcg_gen_shl_tl(t2, t2, t0);
4992 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4993 gen_load_spr(t1, SPR_MQ);
4994 gen_store_spr(SPR_MQ, t0);
4995 tcg_gen_and_tl(t0, t0, t2);
4996 tcg_gen_andc_tl(t1, t1, t2);
4997 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 tcg_temp_free(t2);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5003 }
5004
5005 /* sliq - sliq. */
5006 static void gen_sliq(DisasContext *ctx)
5007 {
5008 int sh = SH(ctx->opcode);
5009 TCGv t0 = tcg_temp_new();
5010 TCGv t1 = tcg_temp_new();
5011 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5012 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* slliq - slliq. */
5023 static void gen_slliq(DisasContext *ctx)
5024 {
5025 int sh = SH(ctx->opcode);
5026 TCGv t0 = tcg_temp_new();
5027 TCGv t1 = tcg_temp_new();
5028 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5029 gen_load_spr(t1, SPR_MQ);
5030 gen_store_spr(SPR_MQ, t0);
5031 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5032 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* sllq - sllq. */
5041 static void gen_sllq(DisasContext *ctx)
5042 {
5043 TCGLabel *l1 = gen_new_label();
5044 TCGLabel *l2 = gen_new_label();
5045 TCGv t0 = tcg_temp_local_new();
5046 TCGv t1 = tcg_temp_local_new();
5047 TCGv t2 = tcg_temp_local_new();
5048 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5050 tcg_gen_shl_tl(t1, t1, t2);
5051 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5053 gen_load_spr(t0, SPR_MQ);
5054 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5055 tcg_gen_br(l2);
5056 gen_set_label(l1);
5057 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5058 gen_load_spr(t2, SPR_MQ);
5059 tcg_gen_andc_tl(t1, t2, t1);
5060 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5061 gen_set_label(l2);
5062 tcg_temp_free(t0);
5063 tcg_temp_free(t1);
5064 tcg_temp_free(t2);
5065 if (unlikely(Rc(ctx->opcode) != 0))
5066 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5067 }
5068
5069 /* slq - slq. */
5070 static void gen_slq(DisasContext *ctx)
5071 {
5072 TCGLabel *l1 = gen_new_label();
5073 TCGv t0 = tcg_temp_new();
5074 TCGv t1 = tcg_temp_new();
5075 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5076 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5077 tcg_gen_subfi_tl(t1, 32, t1);
5078 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5079 tcg_gen_or_tl(t1, t0, t1);
5080 gen_store_spr(SPR_MQ, t1);
5081 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5082 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5083 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5084 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5085 gen_set_label(l1);
5086 tcg_temp_free(t0);
5087 tcg_temp_free(t1);
5088 if (unlikely(Rc(ctx->opcode) != 0))
5089 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5090 }
5091
5092 /* sraiq - sraiq. */
5093 static void gen_sraiq(DisasContext *ctx)
5094 {
5095 int sh = SH(ctx->opcode);
5096 TCGLabel *l1 = gen_new_label();
5097 TCGv t0 = tcg_temp_new();
5098 TCGv t1 = tcg_temp_new();
5099 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5100 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5101 tcg_gen_or_tl(t0, t0, t1);
5102 gen_store_spr(SPR_MQ, t0);
5103 tcg_gen_movi_tl(cpu_ca, 0);
5104 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5105 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5106 tcg_gen_movi_tl(cpu_ca, 1);
5107 gen_set_label(l1);
5108 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5109 tcg_temp_free(t0);
5110 tcg_temp_free(t1);
5111 if (unlikely(Rc(ctx->opcode) != 0))
5112 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5113 }
5114
5115 /* sraq - sraq. */
5116 static void gen_sraq(DisasContext *ctx)
5117 {
5118 TCGLabel *l1 = gen_new_label();
5119 TCGLabel *l2 = gen_new_label();
5120 TCGv t0 = tcg_temp_new();
5121 TCGv t1 = tcg_temp_local_new();
5122 TCGv t2 = tcg_temp_local_new();
5123 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5124 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5125 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5126 tcg_gen_subfi_tl(t2, 32, t2);
5127 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5128 tcg_gen_or_tl(t0, t0, t2);
5129 gen_store_spr(SPR_MQ, t0);
5130 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5131 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5132 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5133 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5134 gen_set_label(l1);
5135 tcg_temp_free(t0);
5136 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5137 tcg_gen_movi_tl(cpu_ca, 0);
5138 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5139 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5140 tcg_gen_movi_tl(cpu_ca, 1);
5141 gen_set_label(l2);
5142 tcg_temp_free(t1);
5143 tcg_temp_free(t2);
5144 if (unlikely(Rc(ctx->opcode) != 0))
5145 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5146 }
5147
5148 /* sre - sre. */
5149 static void gen_sre(DisasContext *ctx)
5150 {
5151 TCGv t0 = tcg_temp_new();
5152 TCGv t1 = tcg_temp_new();
5153 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5154 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5155 tcg_gen_subfi_tl(t1, 32, t1);
5156 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5157 tcg_gen_or_tl(t1, t0, t1);
5158 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5159 gen_store_spr(SPR_MQ, t1);
5160 tcg_temp_free(t0);
5161 tcg_temp_free(t1);
5162 if (unlikely(Rc(ctx->opcode) != 0))
5163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5164 }
5165
5166 /* srea - srea. */
5167 static void gen_srea(DisasContext *ctx)
5168 {
5169 TCGv t0 = tcg_temp_new();
5170 TCGv t1 = tcg_temp_new();
5171 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5172 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5173 gen_store_spr(SPR_MQ, t0);
5174 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5175 tcg_temp_free(t0);
5176 tcg_temp_free(t1);
5177 if (unlikely(Rc(ctx->opcode) != 0))
5178 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5179 }
5180
5181 /* sreq */
5182 static void gen_sreq(DisasContext *ctx)
5183 {
5184 TCGv t0 = tcg_temp_new();
5185 TCGv t1 = tcg_temp_new();
5186 TCGv t2 = tcg_temp_new();
5187 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5188 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5189 tcg_gen_shr_tl(t1, t1, t0);
5190 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5191 gen_load_spr(t2, SPR_MQ);
5192 gen_store_spr(SPR_MQ, t0);
5193 tcg_gen_and_tl(t0, t0, t1);
5194 tcg_gen_andc_tl(t2, t2, t1);
5195 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5196 tcg_temp_free(t0);
5197 tcg_temp_free(t1);
5198 tcg_temp_free(t2);
5199 if (unlikely(Rc(ctx->opcode) != 0))
5200 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5201 }
5202
5203 /* sriq */
5204 static void gen_sriq(DisasContext *ctx)
5205 {
5206 int sh = SH(ctx->opcode);
5207 TCGv t0 = tcg_temp_new();
5208 TCGv t1 = tcg_temp_new();
5209 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5210 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5211 tcg_gen_or_tl(t1, t0, t1);
5212 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5213 gen_store_spr(SPR_MQ, t1);
5214 tcg_temp_free(t0);
5215 tcg_temp_free(t1);
5216 if (unlikely(Rc(ctx->opcode) != 0))
5217 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5218 }
5219
5220 /* srliq */
5221 static void gen_srliq(DisasContext *ctx)
5222 {
5223 int sh = SH(ctx->opcode);
5224 TCGv t0 = tcg_temp_new();
5225 TCGv t1 = tcg_temp_new();
5226 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5227 gen_load_spr(t1, SPR_MQ);
5228 gen_store_spr(SPR_MQ, t0);
5229 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5230 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5231 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5232 tcg_temp_free(t0);
5233 tcg_temp_free(t1);
5234 if (unlikely(Rc(ctx->opcode) != 0))
5235 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5236 }
5237
5238 /* srlq */
5239 static void gen_srlq(DisasContext *ctx)
5240 {
5241 TCGLabel *l1 = gen_new_label();
5242 TCGLabel *l2 = gen_new_label();
5243 TCGv t0 = tcg_temp_local_new();
5244 TCGv t1 = tcg_temp_local_new();
5245 TCGv t2 = tcg_temp_local_new();
5246 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5247 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5248 tcg_gen_shr_tl(t2, t1, t2);
5249 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5250 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5251 gen_load_spr(t0, SPR_MQ);
5252 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5253 tcg_gen_br(l2);
5254 gen_set_label(l1);
5255 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5256 tcg_gen_and_tl(t0, t0, t2);
5257 gen_load_spr(t1, SPR_MQ);
5258 tcg_gen_andc_tl(t1, t1, t2);
5259 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5260 gen_set_label(l2);
5261 tcg_temp_free(t0);
5262 tcg_temp_free(t1);
5263 tcg_temp_free(t2);
5264 if (unlikely(Rc(ctx->opcode) != 0))
5265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5266 }
5267
5268 /* srq */
5269 static void gen_srq(DisasContext *ctx)
5270 {
5271 TCGLabel *l1 = gen_new_label();
5272 TCGv t0 = tcg_temp_new();
5273 TCGv t1 = tcg_temp_new();
5274 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5275 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5276 tcg_gen_subfi_tl(t1, 32, t1);
5277 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5278 tcg_gen_or_tl(t1, t0, t1);
5279 gen_store_spr(SPR_MQ, t1);
5280 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5281 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5282 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5283 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5284 gen_set_label(l1);
5285 tcg_temp_free(t0);
5286 tcg_temp_free(t1);
5287 if (unlikely(Rc(ctx->opcode) != 0))
5288 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5289 }
5290
5291 /* PowerPC 602 specific instructions */
5292
5293 /* dsa */
5294 static void gen_dsa(DisasContext *ctx)
5295 {
5296 /* XXX: TODO */
5297 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5298 }
5299
5300 /* esa */
5301 static void gen_esa(DisasContext *ctx)
5302 {
5303 /* XXX: TODO */
5304 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5305 }
5306
5307 /* mfrom */
5308 static void gen_mfrom(DisasContext *ctx)
5309 {
5310 #if defined(CONFIG_USER_ONLY)
5311 GEN_PRIV;
5312 #else
5313 CHK_SV;
5314 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5315 #endif /* defined(CONFIG_USER_ONLY) */
5316 }
5317
5318 /* 602 - 603 - G2 TLB management */
5319
5320 /* tlbld */
5321 static void gen_tlbld_6xx(DisasContext *ctx)
5322 {
5323 #if defined(CONFIG_USER_ONLY)
5324 GEN_PRIV;
5325 #else
5326 CHK_SV;
5327 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5328 #endif /* defined(CONFIG_USER_ONLY) */
5329 }
5330
5331 /* tlbli */
5332 static void gen_tlbli_6xx(DisasContext *ctx)
5333 {
5334 #if defined(CONFIG_USER_ONLY)
5335 GEN_PRIV;
5336 #else
5337 CHK_SV;
5338 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5339 #endif /* defined(CONFIG_USER_ONLY) */
5340 }
5341
5342 /* 74xx TLB management */
5343
5344 /* tlbld */
5345 static void gen_tlbld_74xx(DisasContext *ctx)
5346 {
5347 #if defined(CONFIG_USER_ONLY)
5348 GEN_PRIV;
5349 #else
5350 CHK_SV;
5351 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5352 #endif /* defined(CONFIG_USER_ONLY) */
5353 }
5354
5355 /* tlbli */
5356 static void gen_tlbli_74xx(DisasContext *ctx)
5357 {
5358 #if defined(CONFIG_USER_ONLY)
5359 GEN_PRIV;
5360 #else
5361 CHK_SV;
5362 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5363 #endif /* defined(CONFIG_USER_ONLY) */
5364 }
5365
5366 /* POWER instructions not in PowerPC 601 */
5367
5368 /* clf */
5369 static void gen_clf(DisasContext *ctx)
5370 {
5371 /* Cache line flush: implemented as no-op */
5372 }
5373
5374 /* cli */
5375 static void gen_cli(DisasContext *ctx)
5376 {
5377 #if defined(CONFIG_USER_ONLY)
5378 GEN_PRIV;
5379 #else
5380 /* Cache line invalidate: privileged and treated as no-op */
5381 CHK_SV;
5382 #endif /* defined(CONFIG_USER_ONLY) */
5383 }
5384
5385 /* dclst */
5386 static void gen_dclst(DisasContext *ctx)
5387 {
5388 /* Data cache line store: treated as no-op */
5389 }
5390
5391 static void gen_mfsri(DisasContext *ctx)
5392 {
5393 #if defined(CONFIG_USER_ONLY)
5394 GEN_PRIV;
5395 #else
5396 int ra = rA(ctx->opcode);
5397 int rd = rD(ctx->opcode);
5398 TCGv t0;
5399
5400 CHK_SV;
5401 t0 = tcg_temp_new();
5402 gen_addr_reg_index(ctx, t0);
5403 tcg_gen_shri_tl(t0, t0, 28);
5404 tcg_gen_andi_tl(t0, t0, 0xF);
5405 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5406 tcg_temp_free(t0);
5407 if (ra != 0 && ra != rd)
5408 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5409 #endif /* defined(CONFIG_USER_ONLY) */
5410 }
5411
5412 static void gen_rac(DisasContext *ctx)
5413 {
5414 #if defined(CONFIG_USER_ONLY)
5415 GEN_PRIV;
5416 #else
5417 TCGv t0;
5418
5419 CHK_SV;
5420 t0 = tcg_temp_new();
5421 gen_addr_reg_index(ctx, t0);
5422 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5423 tcg_temp_free(t0);
5424 #endif /* defined(CONFIG_USER_ONLY) */
5425 }
5426
5427 static void gen_rfsvc(DisasContext *ctx)
5428 {
5429 #if defined(CONFIG_USER_ONLY)
5430 GEN_PRIV;
5431 #else
5432 CHK_SV;
5433
5434 gen_helper_rfsvc(cpu_env);
5435 gen_sync_exception(ctx);
5436 #endif /* defined(CONFIG_USER_ONLY) */
5437 }
5438
5439 /* svc is not implemented for now */
5440
5441 /* BookE specific instructions */
5442
5443 /* XXX: not implemented on 440 ? */
5444 static void gen_mfapidi(DisasContext *ctx)
5445 {
5446 /* XXX: TODO */
5447 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5448 }
5449
5450 /* XXX: not implemented on 440 ? */
5451 static void gen_tlbiva(DisasContext *ctx)
5452 {
5453 #if defined(CONFIG_USER_ONLY)
5454 GEN_PRIV;
5455 #else
5456 TCGv t0;
5457
5458 CHK_SV;
5459 t0 = tcg_temp_new();
5460 gen_addr_reg_index(ctx, t0);
5461 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5462 tcg_temp_free(t0);
5463 #endif /* defined(CONFIG_USER_ONLY) */
5464 }
5465
5466 /* All 405 MAC instructions are translated here */
5467 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5468 int ra, int rb, int rt, int Rc)
5469 {
5470 TCGv t0, t1;
5471
5472 t0 = tcg_temp_local_new();
5473 t1 = tcg_temp_local_new();
5474
5475 switch (opc3 & 0x0D) {
5476 case 0x05:
5477 /* macchw - macchw. - macchwo - macchwo. */
5478 /* macchws - macchws. - macchwso - macchwso. */
5479 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5480 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5481 /* mulchw - mulchw. */
5482 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5483 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5484 tcg_gen_ext16s_tl(t1, t1);
5485 break;
5486 case 0x04:
5487 /* macchwu - macchwu. - macchwuo - macchwuo. */
5488 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5489 /* mulchwu - mulchwu. */
5490 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5491 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5492 tcg_gen_ext16u_tl(t1, t1);
5493 break;
5494 case 0x01:
5495 /* machhw - machhw. - machhwo - machhwo. */
5496 /* machhws - machhws. - machhwso - machhwso. */
5497 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5498 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5499 /* mulhhw - mulhhw. */
5500 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5501 tcg_gen_ext16s_tl(t0, t0);
5502 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5503 tcg_gen_ext16s_tl(t1, t1);
5504 break;
5505 case 0x00:
5506 /* machhwu - machhwu. - machhwuo - machhwuo. */
5507 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5508 /* mulhhwu - mulhhwu. */
5509 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5510 tcg_gen_ext16u_tl(t0, t0);
5511 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5512 tcg_gen_ext16u_tl(t1, t1);
5513 break;
5514 case 0x0D:
5515 /* maclhw - maclhw. - maclhwo - maclhwo. */
5516 /* maclhws - maclhws. - maclhwso - maclhwso. */
5517 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5518 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5519 /* mullhw - mullhw. */
5520 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5521 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5522 break;
5523 case 0x0C:
5524 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5525 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5526 /* mullhwu - mullhwu. */
5527 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5528 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5529 break;
5530 }
5531 if (opc2 & 0x04) {
5532 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5533 tcg_gen_mul_tl(t1, t0, t1);
5534 if (opc2 & 0x02) {
5535 /* nmultiply-and-accumulate (0x0E) */
5536 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5537 } else {
5538 /* multiply-and-accumulate (0x0C) */
5539 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5540 }
5541
5542 if (opc3 & 0x12) {
5543 /* Check overflow and/or saturate */
5544 TCGLabel *l1 = gen_new_label();
5545
5546 if (opc3 & 0x10) {
5547 /* Start with XER OV disabled, the most likely case */
5548 tcg_gen_movi_tl(cpu_ov, 0);
5549 }
5550 if (opc3 & 0x01) {
5551 /* Signed */
5552 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5553 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5554 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5555 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5556 if (opc3 & 0x02) {
5557 /* Saturate */
5558 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5559 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5560 }
5561 } else {
5562 /* Unsigned */
5563 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5564 if (opc3 & 0x02) {
5565 /* Saturate */
5566 tcg_gen_movi_tl(t0, UINT32_MAX);
5567 }
5568 }
5569 if (opc3 & 0x10) {
5570 /* Check overflow */
5571 tcg_gen_movi_tl(cpu_ov, 1);
5572 tcg_gen_movi_tl(cpu_so, 1);
5573 }
5574 gen_set_label(l1);
5575 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5576 }
5577 } else {
5578 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5579 }
5580 tcg_temp_free(t0);
5581 tcg_temp_free(t1);
5582 if (unlikely(Rc) != 0) {
5583 /* Update Rc0 */
5584 gen_set_Rc0(ctx, cpu_gpr[rt]);
5585 }
5586 }
5587
5588 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5589 static void glue(gen_, name)(DisasContext *ctx) \
5590 { \
5591 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5592 rD(ctx->opcode), Rc(ctx->opcode)); \
5593 }
5594
5595 /* macchw - macchw. */
5596 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5597 /* macchwo - macchwo. */
5598 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5599 /* macchws - macchws. */
5600 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5601 /* macchwso - macchwso. */
5602 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5603 /* macchwsu - macchwsu. */
5604 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5605 /* macchwsuo - macchwsuo. */
5606 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5607 /* macchwu - macchwu. */
5608 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5609 /* macchwuo - macchwuo. */
5610 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5611 /* machhw - machhw. */
5612 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5613 /* machhwo - machhwo. */
5614 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5615 /* machhws - machhws. */
5616 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5617 /* machhwso - machhwso. */
5618 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5619 /* machhwsu - machhwsu. */
5620 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5621 /* machhwsuo - machhwsuo. */
5622 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5623 /* machhwu - machhwu. */
5624 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5625 /* machhwuo - machhwuo. */
5626 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5627 /* maclhw - maclhw. */
5628 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5629 /* maclhwo - maclhwo. */
5630 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5631 /* maclhws - maclhws. */
5632 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5633 /* maclhwso - maclhwso. */
5634 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5635 /* maclhwu - maclhwu. */
5636 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5637 /* maclhwuo - maclhwuo. */
5638 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5639 /* maclhwsu - maclhwsu. */
5640 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5641 /* maclhwsuo - maclhwsuo. */
5642 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5643 /* nmacchw - nmacchw. */
5644 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5645 /* nmacchwo - nmacchwo. */
5646 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5647 /* nmacchws - nmacchws. */
5648 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5649 /* nmacchwso - nmacchwso. */
5650 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5651 /* nmachhw - nmachhw. */
5652 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5653 /* nmachhwo - nmachhwo. */
5654 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5655 /* nmachhws - nmachhws. */
5656 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5657 /* nmachhwso - nmachhwso. */
5658 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5659 /* nmaclhw - nmaclhw. */
5660 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5661 /* nmaclhwo - nmaclhwo. */
5662 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5663 /* nmaclhws - nmaclhws. */
5664 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5665 /* nmaclhwso - nmaclhwso. */
5666 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5667
5668 /* mulchw - mulchw. */
5669 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5670 /* mulchwu - mulchwu. */
5671 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5672 /* mulhhw - mulhhw. */
5673 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5674 /* mulhhwu - mulhhwu. */
5675 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5676 /* mullhw - mullhw. */
5677 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5678 /* mullhwu - mullhwu. */
5679 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5680
5681 /* mfdcr */
5682 static void gen_mfdcr(DisasContext *ctx)
5683 {
5684 #if defined(CONFIG_USER_ONLY)
5685 GEN_PRIV;
5686 #else
5687 TCGv dcrn;
5688
5689 CHK_SV;
5690 dcrn = tcg_const_tl(SPR(ctx->opcode));
5691 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5692 tcg_temp_free(dcrn);
5693 #endif /* defined(CONFIG_USER_ONLY) */
5694 }
5695
5696 /* mtdcr */
5697 static void gen_mtdcr(DisasContext *ctx)
5698 {
5699 #if defined(CONFIG_USER_ONLY)
5700 GEN_PRIV;
5701 #else
5702 TCGv dcrn;
5703
5704 CHK_SV;
5705 dcrn = tcg_const_tl(SPR(ctx->opcode));
5706 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5707 tcg_temp_free(dcrn);
5708 #endif /* defined(CONFIG_USER_ONLY) */
5709 }
5710
5711 /* mfdcrx */
5712 /* XXX: not implemented on 440 ? */
5713 static void gen_mfdcrx(DisasContext *ctx)
5714 {
5715 #if defined(CONFIG_USER_ONLY)
5716 GEN_PRIV;
5717 #else
5718 CHK_SV;
5719 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5720 cpu_gpr[rA(ctx->opcode)]);
5721 /* Note: Rc update flag set leads to undefined state of Rc0 */
5722 #endif /* defined(CONFIG_USER_ONLY) */
5723 }
5724
5725 /* mtdcrx */
5726 /* XXX: not implemented on 440 ? */
5727 static void gen_mtdcrx(DisasContext *ctx)
5728 {
5729 #if defined(CONFIG_USER_ONLY)
5730 GEN_PRIV;
5731 #else
5732 CHK_SV;
5733 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5734 cpu_gpr[rS(ctx->opcode)]);
5735 /* Note: Rc update flag set leads to undefined state of Rc0 */
5736 #endif /* defined(CONFIG_USER_ONLY) */
5737 }
5738
5739 /* mfdcrux (PPC 460) : user-mode access to DCR */
5740 static void gen_mfdcrux(DisasContext *ctx)
5741 {
5742 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5743 cpu_gpr[rA(ctx->opcode)]);
5744 /* Note: Rc update flag set leads to undefined state of Rc0 */
5745 }
5746
5747 /* mtdcrux (PPC 460) : user-mode access to DCR */
5748 static void gen_mtdcrux(DisasContext *ctx)
5749 {
5750 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5751 cpu_gpr[rS(ctx->opcode)]);
5752 /* Note: Rc update flag set leads to undefined state of Rc0 */
5753 }
5754
5755 /* dccci */
5756 static void gen_dccci(DisasContext *ctx)
5757 {
5758 CHK_SV;
5759 /* interpreted as no-op */
5760 }
5761
5762 /* dcread */
5763 static void gen_dcread(DisasContext *ctx)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 GEN_PRIV;
5767 #else
5768 TCGv EA, val;
5769
5770 CHK_SV;
5771 gen_set_access_type(ctx, ACCESS_CACHE);
5772 EA = tcg_temp_new();
5773 gen_addr_reg_index(ctx, EA);
5774 val = tcg_temp_new();
5775 gen_qemu_ld32u(ctx, val, EA);
5776 tcg_temp_free(val);
5777 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5778 tcg_temp_free(EA);
5779 #endif /* defined(CONFIG_USER_ONLY) */
5780 }
5781
5782 /* icbt */
5783 static void gen_icbt_40x(DisasContext *ctx)
5784 {
5785 /* interpreted as no-op */
5786 /* XXX: specification say this is treated as a load by the MMU
5787 * but does not generate any exception
5788 */
5789 }
5790
5791 /* iccci */
5792 static void gen_iccci(DisasContext *ctx)
5793 {
5794 CHK_SV;
5795 /* interpreted as no-op */
5796 }
5797
5798 /* icread */
5799 static void gen_icread(DisasContext *ctx)
5800 {
5801 CHK_SV;
5802 /* interpreted as no-op */
5803 }
5804
5805 /* rfci (supervisor only) */
5806 static void gen_rfci_40x(DisasContext *ctx)
5807 {
5808 #if defined(CONFIG_USER_ONLY)
5809 GEN_PRIV;
5810 #else
5811 CHK_SV;
5812 /* Restore CPU state */
5813 gen_helper_40x_rfci(cpu_env);
5814 gen_sync_exception(ctx);
5815 #endif /* defined(CONFIG_USER_ONLY) */
5816 }
5817
5818 static void gen_rfci(DisasContext *ctx)
5819 {
5820 #if defined(CONFIG_USER_ONLY)
5821 GEN_PRIV;
5822 #else
5823 CHK_SV;
5824 /* Restore CPU state */
5825 gen_helper_rfci(cpu_env);
5826 gen_sync_exception(ctx);
5827 #endif /* defined(CONFIG_USER_ONLY) */
5828 }
5829
5830 /* BookE specific */
5831
5832 /* XXX: not implemented on 440 ? */
5833 static void gen_rfdi(DisasContext *ctx)
5834 {
5835 #if defined(CONFIG_USER_ONLY)
5836 GEN_PRIV;
5837 #else
5838 CHK_SV;
5839 /* Restore CPU state */
5840 gen_helper_rfdi(cpu_env);
5841 gen_sync_exception(ctx);
5842 #endif /* defined(CONFIG_USER_ONLY) */
5843 }
5844
5845 /* XXX: not implemented on 440 ? */
5846 static void gen_rfmci(DisasContext *ctx)
5847 {
5848 #if defined(CONFIG_USER_ONLY)
5849 GEN_PRIV;
5850 #else
5851 CHK_SV;
5852 /* Restore CPU state */
5853 gen_helper_rfmci(cpu_env);
5854 gen_sync_exception(ctx);
5855 #endif /* defined(CONFIG_USER_ONLY) */
5856 }
5857
5858 /* TLB management - PowerPC 405 implementation */
5859
5860 /* tlbre */
5861 static void gen_tlbre_40x(DisasContext *ctx)
5862 {
5863 #if defined(CONFIG_USER_ONLY)
5864 GEN_PRIV;
5865 #else
5866 CHK_SV;
5867 switch (rB(ctx->opcode)) {
5868 case 0:
5869 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5870 cpu_gpr[rA(ctx->opcode)]);
5871 break;
5872 case 1:
5873 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5874 cpu_gpr[rA(ctx->opcode)]);
5875 break;
5876 default:
5877 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5878 break;
5879 }
5880 #endif /* defined(CONFIG_USER_ONLY) */
5881 }
5882
5883 /* tlbsx - tlbsx. */
5884 static void gen_tlbsx_40x(DisasContext *ctx)
5885 {
5886 #if defined(CONFIG_USER_ONLY)
5887 GEN_PRIV;
5888 #else
5889 TCGv t0;
5890
5891 CHK_SV;
5892 t0 = tcg_temp_new();
5893 gen_addr_reg_index(ctx, t0);
5894 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5895 tcg_temp_free(t0);
5896 if (Rc(ctx->opcode)) {
5897 TCGLabel *l1 = gen_new_label();
5898 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5899 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5900 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5901 gen_set_label(l1);
5902 }
5903 #endif /* defined(CONFIG_USER_ONLY) */
5904 }
5905
5906 /* tlbwe */
5907 static void gen_tlbwe_40x(DisasContext *ctx)
5908 {
5909 #if defined(CONFIG_USER_ONLY)
5910 GEN_PRIV;
5911 #else
5912 CHK_SV;
5913
5914 switch (rB(ctx->opcode)) {
5915 case 0:
5916 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5917 cpu_gpr[rS(ctx->opcode)]);
5918 break;
5919 case 1:
5920 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5921 cpu_gpr[rS(ctx->opcode)]);
5922 break;
5923 default:
5924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5925 break;
5926 }
5927 #endif /* defined(CONFIG_USER_ONLY) */
5928 }
5929
5930 /* TLB management - PowerPC 440 implementation */
5931
5932 /* tlbre */
5933 static void gen_tlbre_440(DisasContext *ctx)
5934 {
5935 #if defined(CONFIG_USER_ONLY)
5936 GEN_PRIV;
5937 #else
5938 CHK_SV;
5939
5940 switch (rB(ctx->opcode)) {
5941 case 0:
5942 case 1:
5943 case 2:
5944 {
5945 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5946 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5947 t0, cpu_gpr[rA(ctx->opcode)]);
5948 tcg_temp_free_i32(t0);
5949 }
5950 break;
5951 default:
5952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5953 break;
5954 }
5955 #endif /* defined(CONFIG_USER_ONLY) */
5956 }
5957
5958 /* tlbsx - tlbsx. */
5959 static void gen_tlbsx_440(DisasContext *ctx)
5960 {
5961 #if defined(CONFIG_USER_ONLY)
5962 GEN_PRIV;
5963 #else
5964 TCGv t0;
5965
5966 CHK_SV;
5967 t0 = tcg_temp_new();
5968 gen_addr_reg_index(ctx, t0);
5969 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5970 tcg_temp_free(t0);
5971 if (Rc(ctx->opcode)) {
5972 TCGLabel *l1 = gen_new_label();
5973 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5974 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5975 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5976 gen_set_label(l1);
5977 }
5978 #endif /* defined(CONFIG_USER_ONLY) */
5979 }
5980
5981 /* tlbwe */
5982 static void gen_tlbwe_440(DisasContext *ctx)
5983 {
5984 #if defined(CONFIG_USER_ONLY)
5985 GEN_PRIV;
5986 #else
5987 CHK_SV;
5988 switch (rB(ctx->opcode)) {
5989 case 0:
5990 case 1:
5991 case 2:
5992 {
5993 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5994 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5995 cpu_gpr[rS(ctx->opcode)]);
5996 tcg_temp_free_i32(t0);
5997 }
5998 break;
5999 default:
6000 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6001 break;
6002 }
6003 #endif /* defined(CONFIG_USER_ONLY) */
6004 }
6005
6006 /* TLB management - PowerPC BookE 2.06 implementation */
6007
6008 /* tlbre */
6009 static void gen_tlbre_booke206(DisasContext *ctx)
6010 {
6011 #if defined(CONFIG_USER_ONLY)
6012 GEN_PRIV;
6013 #else
6014 CHK_SV;
6015 gen_helper_booke206_tlbre(cpu_env);
6016 #endif /* defined(CONFIG_USER_ONLY) */
6017 }
6018
6019 /* tlbsx - tlbsx. */
6020 static void gen_tlbsx_booke206(DisasContext *ctx)
6021 {
6022 #if defined(CONFIG_USER_ONLY)
6023 GEN_PRIV;
6024 #else
6025 TCGv t0;
6026
6027 CHK_SV;
6028 if (rA(ctx->opcode)) {
6029 t0 = tcg_temp_new();
6030 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6031 } else {
6032 t0 = tcg_const_tl(0);
6033 }
6034
6035 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6036 gen_helper_booke206_tlbsx(cpu_env, t0);
6037 tcg_temp_free(t0);
6038 #endif /* defined(CONFIG_USER_ONLY) */
6039 }
6040
6041 /* tlbwe */
6042 static void gen_tlbwe_booke206(DisasContext *ctx)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 GEN_PRIV;
6046 #else
6047 CHK_SV;
6048 gen_helper_booke206_tlbwe(cpu_env);
6049 #endif /* defined(CONFIG_USER_ONLY) */
6050 }
6051
6052 static void gen_tlbivax_booke206(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 GEN_PRIV;
6056 #else
6057 TCGv t0;
6058
6059 CHK_SV;
6060 t0 = tcg_temp_new();
6061 gen_addr_reg_index(ctx, t0);
6062 gen_helper_booke206_tlbivax(cpu_env, t0);
6063 tcg_temp_free(t0);
6064 #endif /* defined(CONFIG_USER_ONLY) */
6065 }
6066
6067 static void gen_tlbilx_booke206(DisasContext *ctx)
6068 {
6069 #if defined(CONFIG_USER_ONLY)
6070 GEN_PRIV;
6071 #else
6072 TCGv t0;
6073
6074 CHK_SV;
6075 t0 = tcg_temp_new();
6076 gen_addr_reg_index(ctx, t0);
6077
6078 switch((ctx->opcode >> 21) & 0x3) {
6079 case 0:
6080 gen_helper_booke206_tlbilx0(cpu_env, t0);
6081 break;
6082 case 1:
6083 gen_helper_booke206_tlbilx1(cpu_env, t0);
6084 break;
6085 case 3:
6086 gen_helper_booke206_tlbilx3(cpu_env, t0);
6087 break;
6088 default:
6089 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6090 break;
6091 }
6092
6093 tcg_temp_free(t0);
6094 #endif /* defined(CONFIG_USER_ONLY) */
6095 }
6096
6097
6098 /* wrtee */
6099 static void gen_wrtee(DisasContext *ctx)
6100 {
6101 #if defined(CONFIG_USER_ONLY)
6102 GEN_PRIV;
6103 #else
6104 TCGv t0;
6105
6106 CHK_SV;
6107 t0 = tcg_temp_new();
6108 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6109 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6110 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6111 tcg_temp_free(t0);
6112 /* Stop translation to have a chance to raise an exception
6113 * if we just set msr_ee to 1
6114 */
6115 gen_stop_exception(ctx);
6116 #endif /* defined(CONFIG_USER_ONLY) */
6117 }
6118
6119 /* wrteei */
6120 static void gen_wrteei(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 GEN_PRIV;
6124 #else
6125 CHK_SV;
6126 if (ctx->opcode & 0x00008000) {
6127 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6128 /* Stop translation to have a chance to raise an exception */
6129 gen_stop_exception(ctx);
6130 } else {
6131 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6132 }
6133 #endif /* defined(CONFIG_USER_ONLY) */
6134 }
6135
6136 /* PowerPC 440 specific instructions */
6137
6138 /* dlmzb */
6139 static void gen_dlmzb(DisasContext *ctx)
6140 {
6141 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6142 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6143 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6144 tcg_temp_free_i32(t0);
6145 }
6146
6147 /* mbar replaces eieio on 440 */
6148 static void gen_mbar(DisasContext *ctx)
6149 {
6150 /* interpreted as no-op */
6151 }
6152
6153 /* msync replaces sync on 440 */
6154 static void gen_msync_4xx(DisasContext *ctx)
6155 {
6156 /* interpreted as no-op */
6157 }
6158
6159 /* icbt */
6160 static void gen_icbt_440(DisasContext *ctx)
6161 {
6162 /* interpreted as no-op */
6163 /* XXX: specification say this is treated as a load by the MMU
6164 * but does not generate any exception
6165 */
6166 }
6167
6168 /* Embedded.Processor Control */
6169
6170 static void gen_msgclr(DisasContext *ctx)
6171 {
6172 #if defined(CONFIG_USER_ONLY)
6173 GEN_PRIV;
6174 #else
6175 CHK_SV;
6176 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6177 #endif /* defined(CONFIG_USER_ONLY) */
6178 }
6179
6180 static void gen_msgsnd(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 GEN_PRIV;
6184 #else
6185 CHK_SV;
6186 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6187 #endif /* defined(CONFIG_USER_ONLY) */
6188 }
6189
6190
6191 #if defined(TARGET_PPC64)
6192 static void gen_maddld(DisasContext *ctx)
6193 {
6194 TCGv_i64 t1 = tcg_temp_new_i64();
6195
6196 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6197 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6198 tcg_temp_free_i64(t1);
6199 }
6200
6201 /* maddhd maddhdu */
6202 static void gen_maddhd_maddhdu(DisasContext *ctx)
6203 {
6204 TCGv_i64 lo = tcg_temp_new_i64();
6205 TCGv_i64 hi = tcg_temp_new_i64();
6206 TCGv_i64 t1 = tcg_temp_new_i64();
6207
6208 if (Rc(ctx->opcode)) {
6209 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6210 cpu_gpr[rB(ctx->opcode)]);
6211 tcg_gen_movi_i64(t1, 0);
6212 } else {
6213 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6214 cpu_gpr[rB(ctx->opcode)]);
6215 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6216 }
6217 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6218 cpu_gpr[rC(ctx->opcode)], t1);
6219 tcg_temp_free_i64(lo);
6220 tcg_temp_free_i64(hi);
6221 tcg_temp_free_i64(t1);
6222 }
6223 #endif /* defined(TARGET_PPC64) */
6224
6225 static void gen_tbegin(DisasContext *ctx)
6226 {
6227 if (unlikely(!ctx->tm_enabled)) {
6228 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6229 return;
6230 }
6231 gen_helper_tbegin(cpu_env);
6232 }
6233
6234 #define GEN_TM_NOOP(name) \
6235 static inline void gen_##name(DisasContext *ctx) \
6236 { \
6237 if (unlikely(!ctx->tm_enabled)) { \
6238 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6239 return; \
6240 } \
6241 /* Because tbegin always fails in QEMU, these user \
6242 * space instructions all have a simple implementation: \
6243 * \
6244 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6245 * = 0b0 || 0b00 || 0b0 \
6246 */ \
6247 tcg_gen_movi_i32(cpu_crf[0], 0); \
6248 }
6249
6250 GEN_TM_NOOP(tend);
6251 GEN_TM_NOOP(tabort);
6252 GEN_TM_NOOP(tabortwc);
6253 GEN_TM_NOOP(tabortwci);
6254 GEN_TM_NOOP(tabortdc);
6255 GEN_TM_NOOP(tabortdci);
6256 GEN_TM_NOOP(tsr);
6257 static inline void gen_cp_abort(DisasContext *ctx)
6258 {
6259 // Do Nothing
6260 }
6261
6262 #define GEN_CP_PASTE_NOOP(name) \
6263 static inline void gen_##name(DisasContext *ctx) \
6264 { \
6265 /* Generate invalid exception until \
6266 * we have an implementation of the copy \
6267 * paste facility \
6268 */ \
6269 gen_invalid(ctx); \
6270 }
6271
6272 GEN_CP_PASTE_NOOP(copy)
6273 GEN_CP_PASTE_NOOP(paste)
6274
6275 static void gen_tcheck(DisasContext *ctx)
6276 {
6277 if (unlikely(!ctx->tm_enabled)) {
6278 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6279 return;
6280 }
6281 /* Because tbegin always fails, the tcheck implementation
6282 * is simple:
6283 *
6284 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6285 * = 0b1 || 0b00 || 0b0
6286 */
6287 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6288 }
6289
6290 #if defined(CONFIG_USER_ONLY)
6291 #define GEN_TM_PRIV_NOOP(name) \
6292 static inline void gen_##name(DisasContext *ctx) \
6293 { \
6294 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6295 }
6296
6297 #else
6298
6299 #define GEN_TM_PRIV_NOOP(name) \
6300 static inline void gen_##name(DisasContext *ctx) \
6301 { \
6302 CHK_SV; \
6303 if (unlikely(!ctx->tm_enabled)) { \
6304 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6305 return; \
6306 } \
6307 /* Because tbegin always fails, the implementation is \
6308 * simple: \
6309 * \
6310 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6311 * = 0b0 || 0b00 | 0b0 \
6312 */ \
6313 tcg_gen_movi_i32(cpu_crf[0], 0); \
6314 }
6315
6316 #endif
6317
6318 GEN_TM_PRIV_NOOP(treclaim);
6319 GEN_TM_PRIV_NOOP(trechkpt);
6320
6321 #include "translate/fp-impl.inc.c"
6322
6323 #include "translate/vmx-impl.inc.c"
6324
6325 #include "translate/vsx-impl.inc.c"
6326
6327 #include "translate/dfp-impl.inc.c"
6328
6329 #include "translate/spe-impl.inc.c"
6330
6331 /* Handles lfdp, lxsd, lxssp */
6332 static void gen_dform39(DisasContext *ctx)
6333 {
6334 switch (ctx->opcode & 0x3) {
6335 case 0: /* lfdp */
6336 if (ctx->insns_flags2 & PPC2_ISA205) {
6337 return gen_lfdp(ctx);
6338 }
6339 break;
6340 case 2: /* lxsd */
6341 if (ctx->insns_flags2 & PPC2_ISA300) {
6342 return gen_lxsd(ctx);
6343 }
6344 break;
6345 case 3: /* lxssp */
6346 if (ctx->insns_flags2 & PPC2_ISA300) {
6347 return gen_lxssp(ctx);
6348 }
6349 break;
6350 }
6351 return gen_invalid(ctx);
6352 }
6353
6354 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6355 static void gen_dform3D(DisasContext *ctx)
6356 {
6357 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6358 switch (ctx->opcode & 0x7) {
6359 case 1: /* lxv */
6360 if (ctx->insns_flags2 & PPC2_ISA300) {
6361 return gen_lxv(ctx);
6362 }
6363 break;
6364 case 5: /* stxv */
6365 if (ctx->insns_flags2 & PPC2_ISA300) {
6366 return gen_stxv(ctx);
6367 }
6368 break;
6369 }
6370 } else { /* DS-FORM */
6371 switch (ctx->opcode & 0x3) {
6372 case 0: /* stfdp */
6373 if (ctx->insns_flags2 & PPC2_ISA205) {
6374 return gen_stfdp(ctx);
6375 }
6376 break;
6377 case 2: /* stxsd */
6378 if (ctx->insns_flags2 & PPC2_ISA300) {
6379 return gen_stxsd(ctx);
6380 }
6381 break;
6382 case 3: /* stxssp */
6383 if (ctx->insns_flags2 & PPC2_ISA300) {
6384 return gen_stxssp(ctx);
6385 }
6386 break;
6387 }
6388 }
6389 return gen_invalid(ctx);
6390 }
6391
6392 static opcode_t opcodes[] = {
6393 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6394 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6395 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6396 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6397 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6398 #if defined(TARGET_PPC64)
6399 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6400 #endif
6401 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6402 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6403 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6404 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6405 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6406 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6407 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6408 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6409 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6410 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6411 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6412 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6413 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6414 #if defined(TARGET_PPC64)
6415 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6416 #endif
6417 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6418 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6419 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6420 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6421 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6422 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6423 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6424 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6425 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6426 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6427 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6428 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6429 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6430 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6431 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6432 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6433 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6434 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6435 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6436 #if defined(TARGET_PPC64)
6437 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6438 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6439 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6440 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6441 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6442 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6443 #endif
6444 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6445 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6446 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6447 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6448 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6449 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6450 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6451 #if defined(TARGET_PPC64)
6452 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6453 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6454 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6455 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6456 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6457 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6458 PPC_NONE, PPC2_ISA300),
6459 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6460 PPC_NONE, PPC2_ISA300),
6461 #endif
6462 #if defined(TARGET_PPC64)
6463 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6464 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6465 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6466 #endif
6467 /* handles lfdp, lxsd, lxssp */
6468 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6469 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6470 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6471 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6472 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6473 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6474 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6475 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6476 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6477 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6478 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6479 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6480 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6481 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6482 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6483 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6484 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6485 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6486 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6487 #if defined(TARGET_PPC64)
6488 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6489 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6490 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6491 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6492 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6493 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6494 #endif
6495 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6496 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6497 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6498 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6499 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6500 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6501 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6502 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6503 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6504 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6505 #if defined(TARGET_PPC64)
6506 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6507 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6508 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6509 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6510 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6511 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6512 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6513 #endif
6514 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6515 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6516 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6517 #if defined(TARGET_PPC64)
6518 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6519 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6520 #endif
6521 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6522 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6523 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6524 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6525 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6526 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6527 #if defined(TARGET_PPC64)
6528 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6529 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6530 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6531 #endif
6532 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6533 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6534 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6535 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6536 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6537 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6538 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6539 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6540 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6541 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6542 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6543 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6544 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6545 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6546 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6547 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6548 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6549 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6550 #if defined(TARGET_PPC64)
6551 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6552 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6553 PPC_SEGMENT_64B),
6554 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6555 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6556 PPC_SEGMENT_64B),
6557 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6558 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6559 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6560 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6561 #endif
6562 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6563 /* XXX Those instructions will need to be handled differently for
6564 * different ISA versions */
6565 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6566 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6567 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6568 #if defined(TARGET_PPC64)
6569 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6570 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6571 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6572 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6573 #endif
6574 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6575 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6576 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6577 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6578 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6579 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6580 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6581 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6582 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6583 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6584 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6585 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6586 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6587 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6588 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6589 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6590 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6591 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6592 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6593 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6594 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6595 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6596 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6597 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6598 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6599 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6600 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6601 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6602 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6603 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6604 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6605 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6606 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6607 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6608 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6609 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6610 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6611 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6612 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6613 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6614 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6615 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6616 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6617 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6618 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6619 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6620 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6621 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6622 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6623 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6624 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6625 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6626 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6627 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6628 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6629 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6630 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6631 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6632 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6633 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6634 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6635 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6636 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6637 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6638 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6639 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6640 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6641 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6642 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6643 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6644 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6645 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6646 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6647 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6648 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6649 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6650 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6651 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6652 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6653 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6654 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6655 PPC_NONE, PPC2_BOOKE206),
6656 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6657 PPC_NONE, PPC2_BOOKE206),
6658 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6659 PPC_NONE, PPC2_BOOKE206),
6660 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6661 PPC_NONE, PPC2_BOOKE206),
6662 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6663 PPC_NONE, PPC2_BOOKE206),
6664 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6665 PPC_NONE, PPC2_PRCNTL),
6666 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6667 PPC_NONE, PPC2_PRCNTL),
6668 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6669 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6670 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6671 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6672 PPC_BOOKE, PPC2_BOOKE206),
6673 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6674 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6675 PPC_BOOKE, PPC2_BOOKE206),
6676 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6677 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6678 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6679 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6680 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6681 #if defined(TARGET_PPC64)
6682 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6683 PPC2_ISA300),
6684 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6685 #endif
6686
6687 #undef GEN_INT_ARITH_ADD
6688 #undef GEN_INT_ARITH_ADD_CONST
6689 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6690 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6691 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6692 add_ca, compute_ca, compute_ov) \
6693 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6694 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6695 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6696 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6697 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6698 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6699 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6700 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6701 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6702 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6703 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6704
6705 #undef GEN_INT_ARITH_DIVW
6706 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6707 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6708 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6709 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6710 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6711 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6712 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6713 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6714 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6715 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6716 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6717 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6718
6719 #if defined(TARGET_PPC64)
6720 #undef GEN_INT_ARITH_DIVD
6721 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6722 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6723 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6724 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6725 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6726 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6727
6728 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6729 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6730 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6731 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6732 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6733 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6734
6735 #undef GEN_INT_ARITH_MUL_HELPER
6736 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6737 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6738 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6739 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6740 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6741 #endif
6742
6743 #undef GEN_INT_ARITH_SUBF
6744 #undef GEN_INT_ARITH_SUBF_CONST
6745 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6746 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6747 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6748 add_ca, compute_ca, compute_ov) \
6749 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6750 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6751 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6752 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6753 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6754 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6755 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6756 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6757 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6758 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6759 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6760
6761 #undef GEN_LOGICAL1
6762 #undef GEN_LOGICAL2
6763 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6764 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6765 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6766 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6767 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6768 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6769 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6770 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6771 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6772 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6773 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6774 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6775 #if defined(TARGET_PPC64)
6776 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6777 #endif
6778
6779 #if defined(TARGET_PPC64)
6780 #undef GEN_PPC64_R2
6781 #undef GEN_PPC64_R4
6782 #define GEN_PPC64_R2(name, opc1, opc2) \
6783 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6784 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6785 PPC_64B)
6786 #define GEN_PPC64_R4(name, opc1, opc2) \
6787 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6788 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6789 PPC_64B), \
6790 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6791 PPC_64B), \
6792 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6793 PPC_64B)
6794 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6795 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6796 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6797 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6798 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6799 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6800 #endif
6801
6802 #undef GEN_LD
6803 #undef GEN_LDU
6804 #undef GEN_LDUX
6805 #undef GEN_LDX_E
6806 #undef GEN_LDS
6807 #define GEN_LD(name, ldop, opc, type) \
6808 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6809 #define GEN_LDU(name, ldop, opc, type) \
6810 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6811 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6812 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6813 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6814 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6815 #define GEN_LDS(name, ldop, op, type) \
6816 GEN_LD(name, ldop, op | 0x20, type) \
6817 GEN_LDU(name, ldop, op | 0x21, type) \
6818 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6819 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6820
6821 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6822 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6823 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6824 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6825 #if defined(TARGET_PPC64)
6826 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6827 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6828 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6829 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6830 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6831
6832 /* HV/P7 and later only */
6833 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6834 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6835 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6836 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6837 #endif
6838 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6839 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6840
6841 #undef GEN_ST
6842 #undef GEN_STU
6843 #undef GEN_STUX
6844 #undef GEN_STX_E
6845 #undef GEN_STS
6846 #define GEN_ST(name, stop, opc, type) \
6847 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6848 #define GEN_STU(name, stop, opc, type) \
6849 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6850 #define GEN_STUX(name, stop, opc2, opc3, type) \
6851 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6852 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6853 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6854 #define GEN_STS(name, stop, op, type) \
6855 GEN_ST(name, stop, op | 0x20, type) \
6856 GEN_STU(name, stop, op | 0x21, type) \
6857 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6858 GEN_STX(name, stop, 0x17, op | 0x00, type)
6859
6860 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6861 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6862 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6863 #if defined(TARGET_PPC64)
6864 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6865 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6866 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6867 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6868 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6869 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6870 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6871 #endif
6872 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6873 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6874
6875 #undef GEN_CRLOGIC
6876 #define GEN_CRLOGIC(name, tcg_op, opc) \
6877 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6878 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6879 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6880 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6881 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6882 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6883 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6884 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6885 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6886
6887 #undef GEN_MAC_HANDLER
6888 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6889 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6890 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6891 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6892 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6893 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6894 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6895 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6896 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6897 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6898 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6899 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6900 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6901 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6902 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6903 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6904 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6905 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6906 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6907 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6908 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6909 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6910 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6911 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6912 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6913 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6914 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6915 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6916 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6917 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6918 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6919 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6920 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6921 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6922 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6923 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6924 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6925 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6926 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6927 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6928 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6929 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6930 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6931 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6932
6933 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6934 PPC_NONE, PPC2_TM),
6935 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6936 PPC_NONE, PPC2_TM),
6937 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6938 PPC_NONE, PPC2_TM),
6939 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6940 PPC_NONE, PPC2_TM),
6941 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6942 PPC_NONE, PPC2_TM),
6943 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6944 PPC_NONE, PPC2_TM),
6945 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6946 PPC_NONE, PPC2_TM),
6947 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6948 PPC_NONE, PPC2_TM),
6949 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6950 PPC_NONE, PPC2_TM),
6951 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6952 PPC_NONE, PPC2_TM),
6953 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6954 PPC_NONE, PPC2_TM),
6955
6956 #include "translate/fp-ops.inc.c"
6957
6958 #include "translate/vmx-ops.inc.c"
6959
6960 #include "translate/vsx-ops.inc.c"
6961
6962 #include "translate/dfp-ops.inc.c"
6963
6964 #include "translate/spe-ops.inc.c"
6965 };
6966
6967 #include "helper_regs.h"
6968 #include "translate_init.c"
6969
6970 /*****************************************************************************/
6971 /* Misc PowerPC helpers */
6972 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6973 int flags)
6974 {
6975 #define RGPL 4
6976 #define RFPL 4
6977
6978 PowerPCCPU *cpu = POWERPC_CPU(cs);
6979 CPUPPCState *env = &cpu->env;
6980 int i;
6981
6982 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6983 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6984 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6985 cs->cpu_index);
6986 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6987 TARGET_FMT_lx " iidx %d didx %d\n",
6988 env->msr, env->spr[SPR_HID0],
6989 env->hflags, env->immu_idx, env->dmmu_idx);
6990 #if !defined(NO_TIMER_DUMP)
6991 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6992 #if !defined(CONFIG_USER_ONLY)
6993 " DECR %08" PRIu32
6994 #endif
6995 "\n",
6996 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6997 #if !defined(CONFIG_USER_ONLY)
6998 , cpu_ppc_load_decr(env)
6999 #endif
7000 );
7001 #endif
7002 for (i = 0; i < 32; i++) {
7003 if ((i & (RGPL - 1)) == 0)
7004 cpu_fprintf(f, "GPR%02d", i);
7005 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7006 if ((i & (RGPL - 1)) == (RGPL - 1))
7007 cpu_fprintf(f, "\n");
7008 }
7009 cpu_fprintf(f, "CR ");
7010 for (i = 0; i < 8; i++)
7011 cpu_fprintf(f, "%01x", env->crf[i]);
7012 cpu_fprintf(f, " [");
7013 for (i = 0; i < 8; i++) {
7014 char a = '-';
7015 if (env->crf[i] & 0x08)
7016 a = 'L';
7017 else if (env->crf[i] & 0x04)
7018 a = 'G';
7019 else if (env->crf[i] & 0x02)
7020 a = 'E';
7021 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7022 }
7023 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7024 env->reserve_addr);
7025 for (i = 0; i < 32; i++) {
7026 if ((i & (RFPL - 1)) == 0)
7027 cpu_fprintf(f, "FPR%02d", i);
7028 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7029 if ((i & (RFPL - 1)) == (RFPL - 1))
7030 cpu_fprintf(f, "\n");
7031 }
7032 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7033 #if !defined(CONFIG_USER_ONLY)
7034 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7035 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7036 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7037 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7038
7039 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7040 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7041 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7042 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7043
7044 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7045 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7046 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7047 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7048
7049 #if defined(TARGET_PPC64)
7050 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7051 env->excp_model == POWERPC_EXCP_POWER8) {
7052 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7053 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7054 }
7055 #endif
7056 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7057 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7058 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7059 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7060 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7061
7062 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7063 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7064 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7065 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7066
7067 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7068 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7069 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7070 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7071
7072 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7073 " EPR " TARGET_FMT_lx "\n",
7074 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7075 env->spr[SPR_BOOKE_EPR]);
7076
7077 /* FSL-specific */
7078 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7079 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7080 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7081 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7082
7083 /*
7084 * IVORs are left out as they are large and do not change often --
7085 * they can be read with "p $ivor0", "p $ivor1", etc.
7086 */
7087 }
7088
7089 #if defined(TARGET_PPC64)
7090 if (env->flags & POWERPC_FLAG_CFAR) {
7091 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7092 }
7093 #endif
7094
7095 if (env->spr_cb[SPR_LPCR].name)
7096 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7097
7098 switch (POWERPC_MMU_VER(env->mmu_model)) {
7099 case POWERPC_MMU_32B:
7100 case POWERPC_MMU_601:
7101 case POWERPC_MMU_SOFT_6xx:
7102 case POWERPC_MMU_SOFT_74xx:
7103 #if defined(TARGET_PPC64)
7104 case POWERPC_MMU_VER_64B:
7105 case POWERPC_MMU_VER_2_03:
7106 case POWERPC_MMU_VER_2_06:
7107 case POWERPC_MMU_VER_2_07:
7108 case POWERPC_MMU_VER_3_00:
7109 #endif
7110 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7111 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7112 }
7113 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7114 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7115 break;
7116 case POWERPC_MMU_BOOKE206:
7117 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7118 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7119 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7120 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7121
7122 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7123 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7124 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7125 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7126
7127 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7128 " TLB1CFG " TARGET_FMT_lx "\n",
7129 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7130 env->spr[SPR_BOOKE_TLB1CFG]);
7131 break;
7132 default:
7133 break;
7134 }
7135 #endif
7136
7137 #undef RGPL
7138 #undef RFPL
7139 }
7140
7141 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7142 fprintf_function cpu_fprintf, int flags)
7143 {
7144 #if defined(DO_PPC_STATISTICS)
7145 PowerPCCPU *cpu = POWERPC_CPU(cs);
7146 opc_handler_t **t1, **t2, **t3, *handler;
7147 int op1, op2, op3;
7148
7149 t1 = cpu->env.opcodes;
7150 for (op1 = 0; op1 < 64; op1++) {
7151 handler = t1[op1];
7152 if (is_indirect_opcode(handler)) {
7153 t2 = ind_table(handler);
7154 for (op2 = 0; op2 < 32; op2++) {
7155 handler = t2[op2];
7156 if (is_indirect_opcode(handler)) {
7157 t3 = ind_table(handler);
7158 for (op3 = 0; op3 < 32; op3++) {
7159 handler = t3[op3];
7160 if (handler->count == 0)
7161 continue;
7162 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7163 "%016" PRIx64 " %" PRId64 "\n",
7164 op1, op2, op3, op1, (op3 << 5) | op2,
7165 handler->oname,
7166 handler->count, handler->count);
7167 }
7168 } else {
7169 if (handler->count == 0)
7170 continue;
7171 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7172 "%016" PRIx64 " %" PRId64 "\n",
7173 op1, op2, op1, op2, handler->oname,
7174 handler->count, handler->count);
7175 }
7176 }
7177 } else {
7178 if (handler->count == 0)
7179 continue;
7180 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7181 " %" PRId64 "\n",
7182 op1, op1, handler->oname,
7183 handler->count, handler->count);
7184 }
7185 }
7186 #endif
7187 }
7188
7189 /*****************************************************************************/
7190 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7191 {
7192 PowerPCCPU *cpu = ppc_env_get_cpu(env);
7193 CPUState *cs = CPU(cpu);
7194 DisasContext ctx, *ctxp = &ctx;
7195 opc_handler_t **table, *handler;
7196 target_ulong pc_start;
7197 int num_insns;
7198 int max_insns;
7199
7200 pc_start = tb->pc;
7201 ctx.nip = pc_start;
7202 ctx.tb = tb;
7203 ctx.exception = POWERPC_EXCP_NONE;
7204 ctx.spr_cb = env->spr_cb;
7205 ctx.pr = msr_pr;
7206 ctx.mem_idx = env->dmmu_idx;
7207 ctx.dr = msr_dr;
7208 #if !defined(CONFIG_USER_ONLY)
7209 ctx.hv = msr_hv || !env->has_hv_mode;
7210 #endif
7211 ctx.insns_flags = env->insns_flags;
7212 ctx.insns_flags2 = env->insns_flags2;
7213 ctx.access_type = -1;
7214 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7215 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7216 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7217 #if defined(TARGET_PPC64)
7218 ctx.sf_mode = msr_is_64bit(env, env->msr);
7219 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7220 #endif
7221 if (env->mmu_model == POWERPC_MMU_32B ||
7222 env->mmu_model == POWERPC_MMU_601 ||
7223 (env->mmu_model & POWERPC_MMU_64B))
7224 ctx.lazy_tlb_flush = true;
7225
7226 ctx.fpu_enabled = !!msr_fp;
7227 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7228 ctx.spe_enabled = !!msr_spe;
7229 else
7230 ctx.spe_enabled = false;
7231 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7232 ctx.altivec_enabled = !!msr_vr;
7233 else
7234 ctx.altivec_enabled = false;
7235 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7236 ctx.vsx_enabled = !!msr_vsx;
7237 } else {
7238 ctx.vsx_enabled = false;
7239 }
7240 #if defined(TARGET_PPC64)
7241 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7242 ctx.tm_enabled = !!msr_tm;
7243 } else {
7244 ctx.tm_enabled = false;
7245 }
7246 #endif
7247 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7248 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7249 else
7250 ctx.singlestep_enabled = 0;
7251 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7252 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7253 if (unlikely(cs->singlestep_enabled)) {
7254 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7255 }
7256 #if defined (DO_SINGLE_STEP) && 0
7257 /* Single step trace mode */
7258 msr_se = 1;
7259 #endif
7260 num_insns = 0;
7261 max_insns = tb->cflags & CF_COUNT_MASK;
7262 if (max_insns == 0) {
7263 max_insns = CF_COUNT_MASK;
7264 }
7265 if (max_insns > TCG_MAX_INSNS) {
7266 max_insns = TCG_MAX_INSNS;
7267 }
7268
7269 gen_tb_start(tb);
7270 tcg_clear_temp_count();
7271 /* Set env in case of segfault during code fetch */
7272 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7273 tcg_gen_insn_start(ctx.nip);
7274 num_insns++;
7275
7276 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7277 gen_debug_exception(ctxp);
7278 /* The address covered by the breakpoint must be included in
7279 [tb->pc, tb->pc + tb->size) in order to for it to be
7280 properly cleared -- thus we increment the PC here so that
7281 the logic setting tb->size below does the right thing. */
7282 ctx.nip += 4;
7283 break;
7284 }
7285
7286 LOG_DISAS("----------------\n");
7287 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7288 ctx.nip, ctx.mem_idx, (int)msr_ir);
7289 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7290 gen_io_start();
7291 if (unlikely(need_byteswap(&ctx))) {
7292 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7293 } else {
7294 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7295 }
7296 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7297 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7298 opc3(ctx.opcode), opc4(ctx.opcode),
7299 ctx.le_mode ? "little" : "big");
7300 ctx.nip += 4;
7301 table = env->opcodes;
7302 handler = table[opc1(ctx.opcode)];
7303 if (is_indirect_opcode(handler)) {
7304 table = ind_table(handler);
7305 handler = table[opc2(ctx.opcode)];
7306 if (is_indirect_opcode(handler)) {
7307 table = ind_table(handler);
7308 handler = table[opc3(ctx.opcode)];
7309 if (is_indirect_opcode(handler)) {
7310 table = ind_table(handler);
7311 handler = table[opc4(ctx.opcode)];
7312 }
7313 }
7314 }
7315 /* Is opcode *REALLY* valid ? */
7316 if (unlikely(handler->handler == &gen_invalid)) {
7317 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7318 "%02x - %02x - %02x - %02x (%08x) "
7319 TARGET_FMT_lx " %d\n",
7320 opc1(ctx.opcode), opc2(ctx.opcode),
7321 opc3(ctx.opcode), opc4(ctx.opcode),
7322 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7323 } else {
7324 uint32_t inval;
7325
7326 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7327 inval = handler->inval2;
7328 } else {
7329 inval = handler->inval1;
7330 }
7331
7332 if (unlikely((ctx.opcode & inval) != 0)) {
7333 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7334 "%02x - %02x - %02x - %02x (%08x) "
7335 TARGET_FMT_lx "\n", ctx.opcode & inval,
7336 opc1(ctx.opcode), opc2(ctx.opcode),
7337 opc3(ctx.opcode), opc4(ctx.opcode),
7338 ctx.opcode, ctx.nip - 4);
7339 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7340 break;
7341 }
7342 }
7343 (*(handler->handler))(&ctx);
7344 #if defined(DO_PPC_STATISTICS)
7345 handler->count++;
7346 #endif
7347 /* Check trace mode exceptions */
7348 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7349 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7350 ctx.exception != POWERPC_SYSCALL &&
7351 ctx.exception != POWERPC_EXCP_TRAP &&
7352 ctx.exception != POWERPC_EXCP_BRANCH)) {
7353 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7354 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7355 (cs->singlestep_enabled) ||
7356 singlestep ||
7357 num_insns >= max_insns)) {
7358 /* if we reach a page boundary or are single stepping, stop
7359 * generation
7360 */
7361 break;
7362 }
7363 if (tcg_check_temp_count()) {
7364 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7365 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7366 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7367 exit(1);
7368 }
7369 }
7370 if (tb->cflags & CF_LAST_IO)
7371 gen_io_end();
7372 if (ctx.exception == POWERPC_EXCP_NONE) {
7373 gen_goto_tb(&ctx, 0, ctx.nip);
7374 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7375 if (unlikely(cs->singlestep_enabled)) {
7376 gen_debug_exception(ctxp);
7377 }
7378 /* Generate the return instruction */
7379 tcg_gen_exit_tb(0);
7380 }
7381 gen_tb_end(tb, num_insns);
7382
7383 tb->size = ctx.nip - pc_start;
7384 tb->icount = num_insns;
7385
7386 #if defined(DEBUG_DISAS)
7387 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7388 && qemu_log_in_addr_range(pc_start)) {
7389 int flags;
7390 flags = env->bfd_mach;
7391 flags |= ctx.le_mode << 16;
7392 qemu_log_lock();
7393 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7394 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7395 qemu_log("\n");
7396 qemu_log_unlock();
7397 }
7398 #endif
7399 }
7400
7401 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7402 target_ulong *data)
7403 {
7404 env->nip = data[0];
7405 }
AR7 emulation for QEMU