1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
5 typedef struct DisasContext
{
9 /* Nonzero if this instruction has been conditionally skipped. */
11 /* The label that will be jumped to when the instruction is skipped. */
13 /* Thumb-2 conditional execution bits. */
16 struct TranslationBlock
*tb
;
17 int singlestep_enabled
;
20 #if !defined(CONFIG_USER_ONLY)
23 ARMMMUIdx mmu_idx
; /* MMU index to use for normal loads/stores */
24 bool ns
; /* Use non-secure CPREG bank on access */
25 int fp_excp_el
; /* FP exception EL or 0 if enabled */
26 /* Flag indicating that exceptions from secure mode are routed to EL3. */
27 bool secure_routed_to_el3
;
28 bool vfp_enabled
; /* FP enabled via FPSCR.EN */
31 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
32 * so that top level loop can generate correct syndrome information.
38 uint64_t features
; /* CPU features bits */
39 /* Because unallocated encodings generate different exception syndrome
40 * information from traps due to FP being disabled, we can't do a single
41 * "is fp access disabled" check at a high level in the decode tree.
42 * To help in catching bugs where the access check was forgotten in some
43 * code path, we set this flag when the access check is done, and assert
44 * that it is set at the point where we actually touch the FP regs.
46 bool fp_access_checked
;
47 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
48 * single-step support).
52 /* True if the insn just emitted was a load-exclusive instruction
53 * (necessary for syndrome information for single step exceptions),
54 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
57 /* True if a single-step exception will be taken to the current EL */
59 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
61 #define TMP_A64_MAX 16
63 TCGv_i64 tmp_a64
[TMP_A64_MAX
];
66 extern TCGv_ptr cpu_env
;
68 static inline int arm_dc_feature(DisasContext
*dc
, int feature
)
70 return (dc
->features
& (1ULL << feature
)) != 0;
73 static inline int get_mem_index(DisasContext
*s
)
78 /* Function used to determine the target exception EL when otherwise not known
81 static inline int default_exception_el(DisasContext
*s
)
83 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
84 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
85 * exceptions can only be routed to ELs above 1, so we target the higher of
86 * 1 or the current EL.
88 return (s
->mmu_idx
== ARMMMUIdx_S1SE0
&& s
->secure_routed_to_el3
)
89 ? 3 : MAX(1, s
->current_el
);
92 /* target-specific extra values for is_jmp */
93 /* These instructions trap after executing, so the A32/T32 decoder must
94 * defer them until after the conditional execution state has been updated.
95 * WFI also needs special handling when single-stepping.
99 /* For instructions which unconditionally cause an exception we can skip
100 * emitting unreachable code at the end of the TB in the A64 decoder
107 #define DISAS_YIELD 10
109 #ifdef TARGET_AARCH64
110 void a64_translate_init(void);
111 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
112 TranslationBlock
*tb
,
114 void gen_a64_set_pc_im(uint64_t val
);
115 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
116 fprintf_function cpu_fprintf
, int flags
);
118 static inline void a64_translate_init(void)
122 static inline void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
123 TranslationBlock
*tb
,
128 static inline void gen_a64_set_pc_im(uint64_t val
)
132 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
133 fprintf_function cpu_fprintf
,
139 void arm_gen_test_cc(int cc
, TCGLabel
*label
);
141 #endif /* TARGET_ARM_TRANSLATE_H */