2 * s390 PCI instructions
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
17 #include "s390-pci-inst.h"
18 #include "s390-pci-bus.h"
19 #include "exec/memory-internal.h"
20 #include "qemu/error-report.h"
21 #include "sysemu/hw_accel.h"
22 #include "hw/s390x/tod.h"
24 #ifndef DEBUG_S390PCI_INST
25 #define DEBUG_S390PCI_INST 0
28 #define DPRINTF(fmt, ...) \
30 if (DEBUG_S390PCI_INST) { \
31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
35 static void s390_set_status_code(CPUS390XState
*env
,
36 uint8_t r
, uint64_t status_code
)
38 env
->regs
[r
] &= ~0xff000000ULL
;
39 env
->regs
[r
] |= (status_code
& 0xff) << 24;
42 static int list_pci(ClpReqRspListPci
*rrb
, uint8_t *cc
)
44 S390PCIBusDevice
*pbdev
= NULL
;
45 S390pciState
*s
= s390_get_phb();
46 uint32_t res_code
, initial_l2
, g_l2
;
48 uint64_t resume_token
;
51 if (lduw_p(&rrb
->request
.hdr
.len
) != 32) {
52 res_code
= CLP_RC_LEN
;
57 if ((ldl_p(&rrb
->request
.fmt
) & CLP_MASK_FMT
) != 0) {
58 res_code
= CLP_RC_FMT
;
63 if ((ldl_p(&rrb
->request
.fmt
) & ~CLP_MASK_FMT
) != 0 ||
64 ldq_p(&rrb
->request
.reserved1
) != 0) {
65 res_code
= CLP_RC_RESNOT0
;
70 resume_token
= ldq_p(&rrb
->request
.resume_token
);
73 pbdev
= s390_pci_find_dev_by_idx(s
, resume_token
);
75 res_code
= CLP_RC_LISTPCI_BADRT
;
80 pbdev
= s390_pci_find_next_avail_dev(s
, NULL
);
83 if (lduw_p(&rrb
->response
.hdr
.len
) < 48) {
89 initial_l2
= lduw_p(&rrb
->response
.hdr
.len
);
90 if ((initial_l2
- LIST_PCI_HDR_LEN
) % sizeof(ClpFhListEntry
)
92 res_code
= CLP_RC_LEN
;
98 stl_p(&rrb
->response
.fmt
, 0);
99 stq_p(&rrb
->response
.reserved1
, 0);
100 stl_p(&rrb
->response
.mdd
, FH_MASK_SHM
);
101 stw_p(&rrb
->response
.max_fn
, PCI_MAX_FUNCTIONS
);
102 rrb
->response
.flags
= UID_CHECKING_ENABLED
;
103 rrb
->response
.entry_size
= sizeof(ClpFhListEntry
);
106 g_l2
= LIST_PCI_HDR_LEN
;
107 while (g_l2
< initial_l2
&& pbdev
) {
108 stw_p(&rrb
->response
.fh_list
[i
].device_id
,
109 pci_get_word(pbdev
->pdev
->config
+ PCI_DEVICE_ID
));
110 stw_p(&rrb
->response
.fh_list
[i
].vendor_id
,
111 pci_get_word(pbdev
->pdev
->config
+ PCI_VENDOR_ID
));
112 /* Ignore RESERVED devices. */
113 stl_p(&rrb
->response
.fh_list
[i
].config
,
114 pbdev
->state
== ZPCI_FS_STANDBY
? 0 : 1 << 31);
115 stl_p(&rrb
->response
.fh_list
[i
].fid
, pbdev
->fid
);
116 stl_p(&rrb
->response
.fh_list
[i
].fh
, pbdev
->fh
);
118 g_l2
+= sizeof(ClpFhListEntry
);
119 /* Add endian check for DPRINTF? */
120 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
122 lduw_p(&rrb
->response
.fh_list
[i
].vendor_id
),
123 lduw_p(&rrb
->response
.fh_list
[i
].device_id
),
124 ldl_p(&rrb
->response
.fh_list
[i
].fid
),
125 ldl_p(&rrb
->response
.fh_list
[i
].fh
));
126 pbdev
= s390_pci_find_next_avail_dev(s
, pbdev
);
133 resume_token
= pbdev
->fh
& FH_MASK_INDEX
;
135 stq_p(&rrb
->response
.resume_token
, resume_token
);
136 stw_p(&rrb
->response
.hdr
.len
, g_l2
);
137 stw_p(&rrb
->response
.hdr
.rsp
, CLP_RC_OK
);
140 DPRINTF("list pci failed rc 0x%x\n", rc
);
141 stw_p(&rrb
->response
.hdr
.rsp
, res_code
);
146 int clp_service_call(S390CPU
*cpu
, uint8_t r2
, uintptr_t ra
)
150 S390PCIBusDevice
*pbdev
;
153 uint8_t buffer
[4096 * 2];
155 CPUS390XState
*env
= &cpu
->env
;
156 S390pciState
*s
= s390_get_phb();
159 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
160 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
164 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
, sizeof(*reqh
))) {
165 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
168 reqh
= (ClpReqHdr
*)buffer
;
169 req_len
= lduw_p(&reqh
->len
);
170 if (req_len
< 16 || req_len
> 8184 || (req_len
% 8 != 0)) {
171 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
175 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
176 req_len
+ sizeof(*resh
))) {
177 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
180 resh
= (ClpRspHdr
*)(buffer
+ req_len
);
181 res_len
= lduw_p(&resh
->len
);
182 if (res_len
< 8 || res_len
> 8176 || (res_len
% 8 != 0)) {
183 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
186 if ((req_len
+ res_len
) > 8192) {
187 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
191 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
192 req_len
+ res_len
)) {
193 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
198 stw_p(&resh
->rsp
, CLP_RC_LEN
);
202 switch (lduw_p(&reqh
->cmd
)) {
204 ClpReqRspListPci
*rrb
= (ClpReqRspListPci
*)buffer
;
208 case CLP_SET_PCI_FN
: {
209 ClpReqSetPci
*reqsetpci
= (ClpReqSetPci
*)reqh
;
210 ClpRspSetPci
*ressetpci
= (ClpRspSetPci
*)resh
;
212 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqsetpci
->fh
));
214 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
218 switch (reqsetpci
->oc
) {
219 case CLP_SET_ENABLE_PCI_FN
:
220 switch (reqsetpci
->ndas
) {
222 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_DMAAS
);
227 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_RES
);
231 if (pbdev
->fh
& FH_MASK_ENABLE
) {
232 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
236 pbdev
->fh
|= FH_MASK_ENABLE
;
237 pbdev
->state
= ZPCI_FS_ENABLED
;
238 stl_p(&ressetpci
->fh
, pbdev
->fh
);
239 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
241 case CLP_SET_DISABLE_PCI_FN
:
242 if (!(pbdev
->fh
& FH_MASK_ENABLE
)) {
243 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
246 device_reset(DEVICE(pbdev
));
247 pbdev
->fh
&= ~FH_MASK_ENABLE
;
248 pbdev
->state
= ZPCI_FS_DISABLED
;
249 stl_p(&ressetpci
->fh
, pbdev
->fh
);
250 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
253 DPRINTF("unknown set pci command\n");
254 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
259 case CLP_QUERY_PCI_FN
: {
260 ClpReqQueryPci
*reqquery
= (ClpReqQueryPci
*)reqh
;
261 ClpRspQueryPci
*resquery
= (ClpRspQueryPci
*)resh
;
263 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqquery
->fh
));
265 DPRINTF("query pci no pci dev\n");
266 stw_p(&resquery
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
270 for (i
= 0; i
< PCI_BAR_COUNT
; i
++) {
271 uint32_t data
= pci_get_long(pbdev
->pdev
->config
+
272 PCI_BASE_ADDRESS_0
+ (i
* 4));
274 stl_p(&resquery
->bar
[i
], data
);
275 resquery
->bar_size
[i
] = pbdev
->pdev
->io_regions
[i
].size
?
276 ctz64(pbdev
->pdev
->io_regions
[i
].size
) : 0;
277 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64
"barsize 0x%x\n", i
,
278 ldl_p(&resquery
->bar
[i
]),
279 pbdev
->pdev
->io_regions
[i
].size
,
280 resquery
->bar_size
[i
]);
283 stq_p(&resquery
->sdma
, ZPCI_SDMA_ADDR
);
284 stq_p(&resquery
->edma
, ZPCI_EDMA_ADDR
);
285 stl_p(&resquery
->fid
, pbdev
->fid
);
286 stw_p(&resquery
->pchid
, 0);
287 stw_p(&resquery
->ug
, 1);
288 stl_p(&resquery
->uid
, pbdev
->uid
);
289 stw_p(&resquery
->hdr
.rsp
, CLP_RC_OK
);
292 case CLP_QUERY_PCI_FNGRP
: {
293 ClpRspQueryPciGrp
*resgrp
= (ClpRspQueryPciGrp
*)resh
;
295 stq_p(&resgrp
->dasm
, 0);
296 stq_p(&resgrp
->msia
, ZPCI_MSI_ADDR
);
297 stw_p(&resgrp
->mui
, DEFAULT_MUI
);
298 stw_p(&resgrp
->i
, 128);
299 stw_p(&resgrp
->maxstbl
, 128);
302 stw_p(&resgrp
->hdr
.rsp
, CLP_RC_OK
);
306 DPRINTF("unknown clp command\n");
307 stw_p(&resh
->rsp
, CLP_RC_CMD
);
312 if (s390_cpu_virt_mem_write(cpu
, env
->regs
[r2
], r2
, buffer
,
313 req_len
+ res_len
)) {
314 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
322 * Swap data contained in s390x big endian registers to little endian
325 * @ptr: a pointer to a uint64_t data field
326 * @len: the length of the valid data, must be 1,2,4 or 8
328 static int zpci_endian_swap(uint64_t *ptr
, uint8_t len
)
330 uint64_t data
= *ptr
;
336 data
= bswap16(data
);
339 data
= bswap32(data
);
342 data
= bswap64(data
);
351 static MemoryRegion
*s390_get_subregion(MemoryRegion
*mr
, uint64_t offset
,
354 MemoryRegion
*subregion
;
355 uint64_t subregion_size
;
357 QTAILQ_FOREACH(subregion
, &mr
->subregions
, subregions_link
) {
358 subregion_size
= int128_get64(subregion
->size
);
359 if ((offset
>= subregion
->addr
) &&
360 (offset
+ len
) <= (subregion
->addr
+ subregion_size
)) {
368 static MemTxResult
zpci_read_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
369 uint64_t offset
, uint64_t *data
, uint8_t len
)
373 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
374 mr
= s390_get_subregion(mr
, offset
, len
);
376 return memory_region_dispatch_read(mr
, offset
, data
, len
,
377 MEMTXATTRS_UNSPECIFIED
);
380 int pcilg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
382 CPUS390XState
*env
= &cpu
->env
;
383 S390PCIBusDevice
*pbdev
;
391 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
392 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
397 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
401 fh
= env
->regs
[r2
] >> 32;
402 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
403 len
= env
->regs
[r2
] & 0xf;
404 offset
= env
->regs
[r2
+ 1];
406 if (!(fh
& FH_MASK_ENABLE
)) {
407 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
411 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
413 DPRINTF("pcilg no pci dev\n");
414 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
418 switch (pbdev
->state
) {
419 case ZPCI_FS_PERMANENT_ERROR
:
421 setcc(cpu
, ZPCI_PCI_LS_ERR
);
422 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
429 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
430 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
431 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
434 result
= zpci_read_bar(pbdev
, pcias
, offset
, &data
, len
);
435 if (result
!= MEMTX_OK
) {
436 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
440 case ZPCI_CONFIG_BAR
:
441 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
442 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
445 data
= pci_host_config_read_common(
446 pbdev
->pdev
, offset
, pci_config_size(pbdev
->pdev
), len
);
448 if (zpci_endian_swap(&data
, len
)) {
449 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
454 DPRINTF("pcilg invalid space\n");
455 setcc(cpu
, ZPCI_PCI_LS_ERR
);
456 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
460 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_LD
]++;
462 env
->regs
[r1
] = data
;
463 setcc(cpu
, ZPCI_PCI_LS_OK
);
467 static MemTxResult
zpci_write_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
468 uint64_t offset
, uint64_t data
, uint8_t len
)
472 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
473 mr
= s390_get_subregion(mr
, offset
, len
);
475 return memory_region_dispatch_write(mr
, offset
, data
, len
,
476 MEMTXATTRS_UNSPECIFIED
);
479 int pcistg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
481 CPUS390XState
*env
= &cpu
->env
;
482 uint64_t offset
, data
;
483 S390PCIBusDevice
*pbdev
;
489 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
490 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
495 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
499 fh
= env
->regs
[r2
] >> 32;
500 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
501 len
= env
->regs
[r2
] & 0xf;
502 offset
= env
->regs
[r2
+ 1];
503 data
= env
->regs
[r1
];
505 if (!(fh
& FH_MASK_ENABLE
)) {
506 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
510 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
512 DPRINTF("pcistg no pci dev\n");
513 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
517 switch (pbdev
->state
) {
518 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
519 * are already covered by the FH_MASK_ENABLE check above
521 case ZPCI_FS_PERMANENT_ERROR
:
523 setcc(cpu
, ZPCI_PCI_LS_ERR
);
524 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
531 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
532 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
534 * A length of 0 is invalid and length should not cross a double word
536 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
537 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
541 result
= zpci_write_bar(pbdev
, pcias
, offset
, data
, len
);
542 if (result
!= MEMTX_OK
) {
543 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
547 case ZPCI_CONFIG_BAR
:
548 /* ZPCI uses the pseudo BAR number 15 as configuration space */
549 /* possible access lengths are 1,2,4 and must not cross a word */
550 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
551 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
554 /* len = 1,2,4 so we do not need to test */
555 zpci_endian_swap(&data
, len
);
556 pci_host_config_write_common(pbdev
->pdev
, offset
,
557 pci_config_size(pbdev
->pdev
),
561 DPRINTF("pcistg invalid space\n");
562 setcc(cpu
, ZPCI_PCI_LS_ERR
);
563 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
567 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_ST
]++;
569 setcc(cpu
, ZPCI_PCI_LS_OK
);
573 static void s390_pci_update_iotlb(S390PCIIOMMU
*iommu
, S390IOTLBEntry
*entry
)
575 S390IOTLBEntry
*cache
= g_hash_table_lookup(iommu
->iotlb
, &entry
->iova
);
576 IOMMUTLBEntry notify
= {
577 .target_as
= &address_space_memory
,
579 .translated_addr
= entry
->translated_addr
,
581 .addr_mask
= ~PAGE_MASK
,
584 if (entry
->perm
== IOMMU_NONE
) {
588 g_hash_table_remove(iommu
->iotlb
, &entry
->iova
);
591 if (cache
->perm
== entry
->perm
&&
592 cache
->translated_addr
== entry
->translated_addr
) {
596 notify
.perm
= IOMMU_NONE
;
597 memory_region_notify_iommu(&iommu
->iommu_mr
, 0, notify
);
598 notify
.perm
= entry
->perm
;
601 cache
= g_new(S390IOTLBEntry
, 1);
602 cache
->iova
= entry
->iova
;
603 cache
->translated_addr
= entry
->translated_addr
;
604 cache
->len
= PAGE_SIZE
;
605 cache
->perm
= entry
->perm
;
606 g_hash_table_replace(iommu
->iotlb
, &cache
->iova
, cache
);
609 memory_region_notify_iommu(&iommu
->iommu_mr
, 0, notify
);
612 int rpcit_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
614 CPUS390XState
*env
= &cpu
->env
;
617 S390PCIBusDevice
*pbdev
;
619 S390IOTLBEntry entry
;
622 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
623 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
628 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
632 fh
= env
->regs
[r1
] >> 32;
633 start
= env
->regs
[r2
];
634 end
= start
+ env
->regs
[r2
+ 1];
636 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
638 DPRINTF("rpcit no pci dev\n");
639 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
643 switch (pbdev
->state
) {
644 case ZPCI_FS_RESERVED
:
645 case ZPCI_FS_STANDBY
:
646 case ZPCI_FS_DISABLED
:
647 case ZPCI_FS_PERMANENT_ERROR
:
648 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
651 setcc(cpu
, ZPCI_PCI_LS_ERR
);
652 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_ERROR_RECOVER
);
658 iommu
= pbdev
->iommu
;
659 if (!iommu
->g_iota
) {
660 error
= ERR_EVENT_INVALAS
;
664 if (end
< iommu
->pba
|| start
> iommu
->pal
) {
665 error
= ERR_EVENT_OORANGE
;
669 while (start
< end
) {
670 error
= s390_guest_io_table_walk(iommu
->g_iota
, start
, &entry
);
676 while (entry
.iova
< start
&& entry
.iova
< end
) {
677 s390_pci_update_iotlb(iommu
, &entry
);
678 entry
.iova
+= PAGE_SIZE
;
679 entry
.translated_addr
+= PAGE_SIZE
;
684 pbdev
->state
= ZPCI_FS_ERROR
;
685 setcc(cpu
, ZPCI_PCI_LS_ERR
);
686 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_FUNC_IN_ERR
);
687 s390_pci_generate_error_event(error
, pbdev
->fh
, pbdev
->fid
, start
, 0);
689 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_RPCIT
]++;
690 setcc(cpu
, ZPCI_PCI_LS_OK
);
695 int pcistb_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r3
, uint64_t gaddr
,
696 uint8_t ar
, uintptr_t ra
)
698 CPUS390XState
*env
= &cpu
->env
;
699 S390PCIBusDevice
*pbdev
;
709 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
710 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
714 fh
= env
->regs
[r1
] >> 32;
715 pcias
= (env
->regs
[r1
] >> 16) & 0xf;
716 len
= env
->regs
[r1
] & 0xff;
717 offset
= env
->regs
[r3
];
719 if (!(fh
& FH_MASK_ENABLE
)) {
720 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
724 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
726 DPRINTF("pcistb no pci dev fh 0x%x\n", fh
);
727 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
731 switch (pbdev
->state
) {
732 case ZPCI_FS_PERMANENT_ERROR
:
734 setcc(cpu
, ZPCI_PCI_LS_ERR
);
735 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_BLOCKED
);
741 if (pcias
> ZPCI_IO_BAR_MAX
) {
742 DPRINTF("pcistb invalid space\n");
743 setcc(cpu
, ZPCI_PCI_LS_ERR
);
744 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INVAL_AS
);
748 /* Verify the address, offset and length */
749 /* offset must be a multiple of 8 */
751 goto specification_error
;
753 /* Length must be greater than 8, a multiple of 8 */
754 /* and not greater than maxstbl */
755 if ((len
<= 8) || (len
% 8) || (len
> pbdev
->maxstbl
)) {
756 goto specification_error
;
758 /* Do not cross a 4K-byte boundary */
759 if (((offset
& 0xfff) + len
) > 0x1000) {
760 goto specification_error
;
762 /* Guest address must be double word aligned */
763 if (gaddr
& 0x07UL
) {
764 goto specification_error
;
767 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
768 mr
= s390_get_subregion(mr
, offset
, len
);
771 if (!memory_region_access_valid(mr
, offset
, len
, true,
772 MEMTXATTRS_UNSPECIFIED
)) {
773 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
777 if (s390_cpu_virt_mem_read(cpu
, gaddr
, ar
, buffer
, len
)) {
778 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
782 for (i
= 0; i
< len
/ 8; i
++) {
783 result
= memory_region_dispatch_write(mr
, offset
+ i
* 8,
784 ldq_p(buffer
+ i
* 8), 8,
785 MEMTXATTRS_UNSPECIFIED
);
786 if (result
!= MEMTX_OK
) {
787 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
792 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_STB
]++;
794 setcc(cpu
, ZPCI_PCI_LS_OK
);
798 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
802 static int reg_irqs(CPUS390XState
*env
, S390PCIBusDevice
*pbdev
, ZpciFib fib
)
805 uint8_t isc
= FIB_DATA_ISC(ldl_p(&fib
.data
));
807 pbdev
->routes
.adapter
.adapter_id
= css_get_adapter_id(
808 CSS_IO_ADAPTER_PCI
, isc
);
809 pbdev
->summary_ind
= get_indicator(ldq_p(&fib
.aisb
), sizeof(uint64_t));
810 len
= BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib
.data
))) * sizeof(unsigned long);
811 pbdev
->indicator
= get_indicator(ldq_p(&fib
.aibv
), len
);
813 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
818 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
823 pbdev
->routes
.adapter
.summary_addr
= ldq_p(&fib
.aisb
);
824 pbdev
->routes
.adapter
.summary_offset
= FIB_DATA_AISBO(ldl_p(&fib
.data
));
825 pbdev
->routes
.adapter
.ind_addr
= ldq_p(&fib
.aibv
);
826 pbdev
->routes
.adapter
.ind_offset
= FIB_DATA_AIBVO(ldl_p(&fib
.data
));
828 pbdev
->noi
= FIB_DATA_NOI(ldl_p(&fib
.data
));
829 pbdev
->sum
= FIB_DATA_SUM(ldl_p(&fib
.data
));
831 DPRINTF("reg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
834 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
835 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
836 pbdev
->summary_ind
= NULL
;
837 pbdev
->indicator
= NULL
;
841 int pci_dereg_irqs(S390PCIBusDevice
*pbdev
)
843 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
844 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
846 pbdev
->summary_ind
= NULL
;
847 pbdev
->indicator
= NULL
;
848 pbdev
->routes
.adapter
.summary_addr
= 0;
849 pbdev
->routes
.adapter
.summary_offset
= 0;
850 pbdev
->routes
.adapter
.ind_addr
= 0;
851 pbdev
->routes
.adapter
.ind_offset
= 0;
856 DPRINTF("dereg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
860 static int reg_ioat(CPUS390XState
*env
, S390PCIIOMMU
*iommu
, ZpciFib fib
,
863 uint64_t pba
= ldq_p(&fib
.pba
);
864 uint64_t pal
= ldq_p(&fib
.pal
);
865 uint64_t g_iota
= ldq_p(&fib
.iota
);
866 uint8_t dt
= (g_iota
>> 2) & 0x7;
867 uint8_t t
= (g_iota
>> 11) & 0x1;
871 if (pba
> pal
|| pba
< ZPCI_SDMA_ADDR
|| pal
> ZPCI_EDMA_ADDR
) {
872 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
876 /* currently we only support designation type 1 with translation */
877 if (!(dt
== ZPCI_IOTA_RTTO
&& t
)) {
878 error_report("unsupported ioat dt %d t %d", dt
, t
);
879 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
885 iommu
->g_iota
= g_iota
;
887 s390_pci_iommu_enable(iommu
);
892 void pci_dereg_ioat(S390PCIIOMMU
*iommu
)
894 s390_pci_iommu_disable(iommu
);
900 void fmb_timer_free(S390PCIBusDevice
*pbdev
)
902 if (pbdev
->fmb_timer
) {
903 timer_del(pbdev
->fmb_timer
);
904 timer_free(pbdev
->fmb_timer
);
905 pbdev
->fmb_timer
= NULL
;
908 memset(&pbdev
->fmb
, 0, sizeof(ZpciFmb
));
911 static int fmb_do_update(S390PCIBusDevice
*pbdev
, int offset
, uint64_t val
,
915 uint64_t dst
= pbdev
->fmb_addr
+ offset
;
919 address_space_stq_be(&address_space_memory
, dst
, val
,
920 MEMTXATTRS_UNSPECIFIED
,
924 address_space_stl_be(&address_space_memory
, dst
, val
,
925 MEMTXATTRS_UNSPECIFIED
,
929 address_space_stw_be(&address_space_memory
, dst
, val
,
930 MEMTXATTRS_UNSPECIFIED
,
934 address_space_stb(&address_space_memory
, dst
, val
,
935 MEMTXATTRS_UNSPECIFIED
,
942 if (ret
!= MEMTX_OK
) {
943 s390_pci_generate_error_event(ERR_EVENT_FMBA
, pbdev
->fh
, pbdev
->fid
,
945 fmb_timer_free(pbdev
);
951 static void fmb_update(void *opaque
)
953 S390PCIBusDevice
*pbdev
= opaque
;
954 int64_t t
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
958 pbdev
->fmb
.last_update
*= 2;
959 pbdev
->fmb
.last_update
|= UPDATE_U_BIT
;
960 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, last_update
),
961 pbdev
->fmb
.last_update
,
962 sizeof(pbdev
->fmb
.last_update
))) {
966 /* Update FMB sample count */
967 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, sample
),
969 sizeof(pbdev
->fmb
.sample
))) {
973 /* Update FMB counters */
974 for (i
= 0; i
< ZPCI_FMB_CNT_MAX
; i
++) {
975 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, counter
[i
]),
976 pbdev
->fmb
.counter
[i
],
977 sizeof(pbdev
->fmb
.counter
[0]))) {
982 /* Clear U bit and update the time */
983 pbdev
->fmb
.last_update
= time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
984 pbdev
->fmb
.last_update
*= 2;
985 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, last_update
),
986 pbdev
->fmb
.last_update
,
987 sizeof(pbdev
->fmb
.last_update
))) {
990 timer_mod(pbdev
->fmb_timer
, t
+ DEFAULT_MUI
);
993 int mpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
996 CPUS390XState
*env
= &cpu
->env
;
1000 S390PCIBusDevice
*pbdev
;
1001 uint64_t cc
= ZPCI_PCI_LS_OK
;
1003 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
1004 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
1008 oc
= env
->regs
[r1
] & 0xff;
1009 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1010 fh
= env
->regs
[r1
] >> 32;
1013 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
1017 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
1019 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh
);
1020 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1024 switch (pbdev
->state
) {
1025 case ZPCI_FS_RESERVED
:
1026 case ZPCI_FS_STANDBY
:
1027 case ZPCI_FS_DISABLED
:
1028 case ZPCI_FS_PERMANENT_ERROR
:
1029 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1035 if (s390_cpu_virt_mem_read(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1036 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
1041 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
1046 case ZPCI_MOD_FC_REG_INT
:
1047 if (pbdev
->summary_ind
) {
1048 cc
= ZPCI_PCI_LS_ERR
;
1049 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1050 } else if (reg_irqs(env
, pbdev
, fib
)) {
1051 cc
= ZPCI_PCI_LS_ERR
;
1052 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_RES_NOT_AVAIL
);
1055 case ZPCI_MOD_FC_DEREG_INT
:
1056 if (!pbdev
->summary_ind
) {
1057 cc
= ZPCI_PCI_LS_ERR
;
1058 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1060 pci_dereg_irqs(pbdev
);
1063 case ZPCI_MOD_FC_REG_IOAT
:
1065 cc
= ZPCI_PCI_LS_ERR
;
1066 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1067 } else if (pbdev
->iommu
->enabled
) {
1068 cc
= ZPCI_PCI_LS_ERR
;
1069 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1070 } else if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
1071 cc
= ZPCI_PCI_LS_ERR
;
1072 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
1075 case ZPCI_MOD_FC_DEREG_IOAT
:
1077 cc
= ZPCI_PCI_LS_ERR
;
1078 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1079 } else if (!pbdev
->iommu
->enabled
) {
1080 cc
= ZPCI_PCI_LS_ERR
;
1081 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1083 pci_dereg_ioat(pbdev
->iommu
);
1086 case ZPCI_MOD_FC_REREG_IOAT
:
1088 cc
= ZPCI_PCI_LS_ERR
;
1089 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1090 } else if (!pbdev
->iommu
->enabled
) {
1091 cc
= ZPCI_PCI_LS_ERR
;
1092 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1094 pci_dereg_ioat(pbdev
->iommu
);
1095 if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
1096 cc
= ZPCI_PCI_LS_ERR
;
1097 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
1101 case ZPCI_MOD_FC_RESET_ERROR
:
1102 switch (pbdev
->state
) {
1103 case ZPCI_FS_BLOCKED
:
1105 pbdev
->state
= ZPCI_FS_ENABLED
;
1108 cc
= ZPCI_PCI_LS_ERR
;
1109 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1112 case ZPCI_MOD_FC_RESET_BLOCK
:
1113 switch (pbdev
->state
) {
1115 pbdev
->state
= ZPCI_FS_BLOCKED
;
1118 cc
= ZPCI_PCI_LS_ERR
;
1119 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1122 case ZPCI_MOD_FC_SET_MEASURE
: {
1123 uint64_t fmb_addr
= ldq_p(&fib
.fmb_addr
);
1125 if (fmb_addr
& FMBK_MASK
) {
1126 cc
= ZPCI_PCI_LS_ERR
;
1127 s390_pci_generate_error_event(ERR_EVENT_FMBPRO
, pbdev
->fh
,
1128 pbdev
->fid
, fmb_addr
, 0);
1129 fmb_timer_free(pbdev
);
1134 /* Stop updating FMB. */
1135 fmb_timer_free(pbdev
);
1139 if (!pbdev
->fmb_timer
) {
1140 pbdev
->fmb_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
1142 } else if (timer_pending(pbdev
->fmb_timer
)) {
1143 /* Remove pending timer to update FMB address. */
1144 timer_del(pbdev
->fmb_timer
);
1146 pbdev
->fmb_addr
= fmb_addr
;
1147 timer_mod(pbdev
->fmb_timer
,
1148 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + DEFAULT_MUI
);
1152 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 6, ra
);
1153 cc
= ZPCI_PCI_LS_ERR
;
1160 int stpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
1163 CPUS390XState
*env
= &cpu
->env
;
1167 S390PCIBusDevice
*pbdev
;
1169 uint64_t cc
= ZPCI_PCI_LS_OK
;
1171 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
1172 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
1176 fh
= env
->regs
[r1
] >> 32;
1177 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1180 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1181 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_INVAL_DMAAS
);
1186 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
1190 pbdev
= s390_pci_find_dev_by_idx(s390_get_phb(), fh
& FH_MASK_INDEX
);
1192 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1196 memset(&fib
, 0, sizeof(fib
));
1198 switch (pbdev
->state
) {
1199 case ZPCI_FS_RESERVED
:
1200 case ZPCI_FS_STANDBY
:
1201 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1203 case ZPCI_FS_DISABLED
:
1204 if (fh
& FH_MASK_ENABLE
) {
1205 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1209 /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1210 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1213 case ZPCI_FS_BLOCKED
:
1215 case ZPCI_FS_ENABLED
:
1217 if (pbdev
->iommu
->enabled
) {
1220 if (!(fh
& FH_MASK_ENABLE
)) {
1221 env
->regs
[r1
] |= 1ULL << 63;
1224 case ZPCI_FS_PERMANENT_ERROR
:
1225 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1226 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_PERM_ERROR
);
1230 stq_p(&fib
.pba
, pbdev
->iommu
->pba
);
1231 stq_p(&fib
.pal
, pbdev
->iommu
->pal
);
1232 stq_p(&fib
.iota
, pbdev
->iommu
->g_iota
);
1233 stq_p(&fib
.aibv
, pbdev
->routes
.adapter
.ind_addr
);
1234 stq_p(&fib
.aisb
, pbdev
->routes
.adapter
.summary_addr
);
1235 stq_p(&fib
.fmb_addr
, pbdev
->fmb_addr
);
1237 data
= ((uint32_t)pbdev
->isc
<< 28) | ((uint32_t)pbdev
->noi
<< 16) |
1238 ((uint32_t)pbdev
->routes
.adapter
.ind_offset
<< 8) |
1239 ((uint32_t)pbdev
->sum
<< 7) | pbdev
->routes
.adapter
.summary_offset
;
1240 stl_p(&fib
.data
, data
);
1243 if (s390_cpu_virt_mem_write(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1244 s390_cpu_virt_mem_handle_exc(cpu
, ra
);