2 * ARM translation: AArch32 VFP instructions
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 * Copyright (c) 2019 Linaro, Ltd.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 * This file is intended to be included from translate.c; it uses
25 * some macros and definitions provided by that file.
26 * It might be possible to convert it to a standalone .c file eventually.
29 /* Include the generated VFP decoder */
30 #include "decode-vfp.inc.c"
31 #include "decode-vfp-uncond.inc.c"
34 * The imm8 encodes the sign bit, enough bits to represent an exponent in
35 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
36 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
38 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
44 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
45 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
46 extract32(imm8
, 0, 6);
50 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
51 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
52 (extract32(imm8
, 0, 6) << 3);
56 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
57 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
58 (extract32(imm8
, 0, 6) << 6);
61 g_assert_not_reached();
67 * Return the offset of a 16-bit half of the specified VFP single-precision
68 * register. If top is true, returns the top 16 bits; otherwise the bottom
71 static inline long vfp_f16_offset(unsigned reg
, bool top
)
73 long offs
= vfp_reg_offset(false, reg
);
74 #ifdef HOST_WORDS_BIGENDIAN
87 * Check that VFP access is enabled. If it is, do the necessary
88 * M-profile lazy-FP handling and then return true.
89 * If not, emit code to generate an appropriate exception and
91 * The ignore_vfp_enabled argument specifies that we should ignore
92 * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
93 * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
95 static bool full_vfp_access_check(DisasContext
*s
, bool ignore_vfp_enabled
)
98 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
99 gen_exception_insn(s
, s
->pc_curr
, EXCP_NOCP
, syn_uncategorized(),
102 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
103 syn_fp_access_trap(1, 0xe, false),
109 if (!s
->vfp_enabled
&& !ignore_vfp_enabled
) {
110 assert(!arm_dc_feature(s
, ARM_FEATURE_M
));
111 unallocated_encoding(s
);
115 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
116 /* Handle M-profile lazy FP state mechanics */
118 /* Trigger lazy-state preservation if necessary */
121 * Lazy state saving affects external memory and also the NVIC,
122 * so we must mark it as an IO operation for icount.
124 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
127 gen_helper_v7m_preserve_fp_state(cpu_env
);
128 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
132 * If the preserve_fp_state helper doesn't throw an exception
133 * then it will clear LSPACT; we don't need to repeat this for
134 * any further FP insns in this TB.
136 s
->v7m_lspact
= false;
139 /* Update ownership of FP context: set FPCCR.S to match current state */
140 if (s
->v8m_fpccr_s_wrong
) {
143 tmp
= load_cpu_field(v7m
.fpccr
[M_REG_S
]);
145 tcg_gen_ori_i32(tmp
, tmp
, R_V7M_FPCCR_S_MASK
);
147 tcg_gen_andi_i32(tmp
, tmp
, ~R_V7M_FPCCR_S_MASK
);
149 store_cpu_field(tmp
, v7m
.fpccr
[M_REG_S
]);
150 /* Don't need to do this for any further FP insns in this TB */
151 s
->v8m_fpccr_s_wrong
= false;
154 if (s
->v7m_new_fp_ctxt_needed
) {
156 * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
159 TCGv_i32 control
, fpscr
;
160 uint32_t bits
= R_V7M_CONTROL_FPCA_MASK
;
162 fpscr
= load_cpu_field(v7m
.fpdscr
[s
->v8m_secure
]);
163 gen_helper_vfp_set_fpscr(cpu_env
, fpscr
);
164 tcg_temp_free_i32(fpscr
);
166 * We don't need to arrange to end the TB, because the only
167 * parts of FPSCR which we cache in the TB flags are the VECLEN
168 * and VECSTRIDE, and those don't exist for M-profile.
172 bits
|= R_V7M_CONTROL_SFPA_MASK
;
174 control
= load_cpu_field(v7m
.control
[M_REG_S
]);
175 tcg_gen_ori_i32(control
, control
, bits
);
176 store_cpu_field(control
, v7m
.control
[M_REG_S
]);
177 /* Don't need to do this for any further FP insns in this TB */
178 s
->v7m_new_fp_ctxt_needed
= false;
186 * The most usual kind of VFP access check, for everything except
187 * FMXR/FMRX to the always-available special registers.
189 static bool vfp_access_check(DisasContext
*s
)
191 return full_vfp_access_check(s
, false);
194 static bool trans_VSEL(DisasContext
*s
, arg_VSEL
*a
)
199 if (!dc_isar_feature(aa32_vsel
, s
)) {
203 if (dp
&& !dc_isar_feature(aa32_fpdp_v2
, s
)) {
207 /* UNDEF accesses to D16-D31 if they don't exist */
208 if (dp
&& !dc_isar_feature(aa32_simd_r32
, s
) &&
209 ((a
->vm
| a
->vn
| a
->vd
) & 0x10)) {
217 if (!vfp_access_check(s
)) {
222 TCGv_i64 frn
, frm
, dest
;
223 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
225 zero
= tcg_const_i64(0);
227 frn
= tcg_temp_new_i64();
228 frm
= tcg_temp_new_i64();
229 dest
= tcg_temp_new_i64();
231 zf
= tcg_temp_new_i64();
232 nf
= tcg_temp_new_i64();
233 vf
= tcg_temp_new_i64();
235 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
236 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
237 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
239 neon_load_reg64(frn
, rn
);
240 neon_load_reg64(frm
, rm
);
243 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
247 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
250 case 2: /* ge: N == V -> N ^ V == 0 */
251 tmp
= tcg_temp_new_i64();
252 tcg_gen_xor_i64(tmp
, vf
, nf
);
253 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
255 tcg_temp_free_i64(tmp
);
257 case 3: /* gt: !Z && N == V */
258 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
260 tmp
= tcg_temp_new_i64();
261 tcg_gen_xor_i64(tmp
, vf
, nf
);
262 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
264 tcg_temp_free_i64(tmp
);
267 neon_store_reg64(dest
, rd
);
268 tcg_temp_free_i64(frn
);
269 tcg_temp_free_i64(frm
);
270 tcg_temp_free_i64(dest
);
272 tcg_temp_free_i64(zf
);
273 tcg_temp_free_i64(nf
);
274 tcg_temp_free_i64(vf
);
276 tcg_temp_free_i64(zero
);
278 TCGv_i32 frn
, frm
, dest
;
281 zero
= tcg_const_i32(0);
283 frn
= tcg_temp_new_i32();
284 frm
= tcg_temp_new_i32();
285 dest
= tcg_temp_new_i32();
286 neon_load_reg32(frn
, rn
);
287 neon_load_reg32(frm
, rm
);
290 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
294 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
297 case 2: /* ge: N == V -> N ^ V == 0 */
298 tmp
= tcg_temp_new_i32();
299 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
300 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
302 tcg_temp_free_i32(tmp
);
304 case 3: /* gt: !Z && N == V */
305 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
307 tmp
= tcg_temp_new_i32();
308 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
309 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
311 tcg_temp_free_i32(tmp
);
314 neon_store_reg32(dest
, rd
);
315 tcg_temp_free_i32(frn
);
316 tcg_temp_free_i32(frm
);
317 tcg_temp_free_i32(dest
);
319 tcg_temp_free_i32(zero
);
326 * Table for converting the most common AArch32 encoding of
327 * rounding mode to arm_fprounding order (which matches the
328 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
330 static const uint8_t fp_decode_rm
[] = {
337 static bool trans_VRINT(DisasContext
*s
, arg_VRINT
*a
)
343 int rounding
= fp_decode_rm
[a
->rm
];
345 if (!dc_isar_feature(aa32_vrint
, s
)) {
349 if (dp
&& !dc_isar_feature(aa32_fpdp_v2
, s
)) {
353 /* UNDEF accesses to D16-D31 if they don't exist */
354 if (dp
&& !dc_isar_feature(aa32_simd_r32
, s
) &&
355 ((a
->vm
| a
->vd
) & 0x10)) {
362 if (!vfp_access_check(s
)) {
366 fpst
= get_fpstatus_ptr(0);
368 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
369 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
374 tcg_op
= tcg_temp_new_i64();
375 tcg_res
= tcg_temp_new_i64();
376 neon_load_reg64(tcg_op
, rm
);
377 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
378 neon_store_reg64(tcg_res
, rd
);
379 tcg_temp_free_i64(tcg_op
);
380 tcg_temp_free_i64(tcg_res
);
384 tcg_op
= tcg_temp_new_i32();
385 tcg_res
= tcg_temp_new_i32();
386 neon_load_reg32(tcg_op
, rm
);
387 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
388 neon_store_reg32(tcg_res
, rd
);
389 tcg_temp_free_i32(tcg_op
);
390 tcg_temp_free_i32(tcg_res
);
393 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
394 tcg_temp_free_i32(tcg_rmode
);
396 tcg_temp_free_ptr(fpst
);
400 static bool trans_VCVT(DisasContext
*s
, arg_VCVT
*a
)
405 TCGv_i32 tcg_rmode
, tcg_shift
;
406 int rounding
= fp_decode_rm
[a
->rm
];
407 bool is_signed
= a
->op
;
409 if (!dc_isar_feature(aa32_vcvt_dr
, s
)) {
413 if (dp
&& !dc_isar_feature(aa32_fpdp_v2
, s
)) {
417 /* UNDEF accesses to D16-D31 if they don't exist */
418 if (dp
&& !dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
425 if (!vfp_access_check(s
)) {
429 fpst
= get_fpstatus_ptr(0);
431 tcg_shift
= tcg_const_i32(0);
433 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
434 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
437 TCGv_i64 tcg_double
, tcg_res
;
439 tcg_double
= tcg_temp_new_i64();
440 tcg_res
= tcg_temp_new_i64();
441 tcg_tmp
= tcg_temp_new_i32();
442 neon_load_reg64(tcg_double
, rm
);
444 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
446 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
448 tcg_gen_extrl_i64_i32(tcg_tmp
, tcg_res
);
449 neon_store_reg32(tcg_tmp
, rd
);
450 tcg_temp_free_i32(tcg_tmp
);
451 tcg_temp_free_i64(tcg_res
);
452 tcg_temp_free_i64(tcg_double
);
454 TCGv_i32 tcg_single
, tcg_res
;
455 tcg_single
= tcg_temp_new_i32();
456 tcg_res
= tcg_temp_new_i32();
457 neon_load_reg32(tcg_single
, rm
);
459 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
461 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
463 neon_store_reg32(tcg_res
, rd
);
464 tcg_temp_free_i32(tcg_res
);
465 tcg_temp_free_i32(tcg_single
);
468 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
469 tcg_temp_free_i32(tcg_rmode
);
471 tcg_temp_free_i32(tcg_shift
);
473 tcg_temp_free_ptr(fpst
);
478 static bool trans_VMOV_to_gp(DisasContext
*s
, arg_VMOV_to_gp
*a
)
480 /* VMOV scalar to general purpose register */
485 /* SIZE == 2 is a VFP instruction; otherwise NEON. */
487 ? !dc_isar_feature(aa32_fpsp_v2
, s
)
488 : !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
492 /* UNDEF accesses to D16-D31 if they don't exist */
493 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
497 offset
= a
->index
<< a
->size
;
498 pass
= extract32(offset
, 2, 1);
499 offset
= extract32(offset
, 0, 2) * 8;
501 if (!vfp_access_check(s
)) {
505 tmp
= neon_load_reg(a
->vn
, pass
);
509 tcg_gen_shri_i32(tmp
, tmp
, offset
);
520 tcg_gen_shri_i32(tmp
, tmp
, 16);
526 tcg_gen_sari_i32(tmp
, tmp
, 16);
535 store_reg(s
, a
->rt
, tmp
);
540 static bool trans_VMOV_from_gp(DisasContext
*s
, arg_VMOV_from_gp
*a
)
542 /* VMOV general purpose register to scalar */
547 /* SIZE == 2 is a VFP instruction; otherwise NEON. */
549 ? !dc_isar_feature(aa32_fpsp_v2
, s
)
550 : !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
554 /* UNDEF accesses to D16-D31 if they don't exist */
555 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
559 offset
= a
->index
<< a
->size
;
560 pass
= extract32(offset
, 2, 1);
561 offset
= extract32(offset
, 0, 2) * 8;
563 if (!vfp_access_check(s
)) {
567 tmp
= load_reg(s
, a
->rt
);
570 tmp2
= neon_load_reg(a
->vn
, pass
);
571 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 8);
572 tcg_temp_free_i32(tmp2
);
575 tmp2
= neon_load_reg(a
->vn
, pass
);
576 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 16);
577 tcg_temp_free_i32(tmp2
);
582 neon_store_reg(a
->vn
, pass
, tmp
);
587 static bool trans_VDUP(DisasContext
*s
, arg_VDUP
*a
)
589 /* VDUP (general purpose register) */
593 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
597 /* UNDEF accesses to D16-D31 if they don't exist */
598 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
606 if (a
->q
&& (a
->vn
& 1)) {
610 vec_size
= a
->q
? 16 : 8;
619 if (!vfp_access_check(s
)) {
623 tmp
= load_reg(s
, a
->rt
);
624 tcg_gen_gvec_dup_i32(size
, neon_reg_offset(a
->vn
, 0),
625 vec_size
, vec_size
, tmp
);
626 tcg_temp_free_i32(tmp
);
631 static bool trans_VMSR_VMRS(DisasContext
*s
, arg_VMSR_VMRS
*a
)
634 bool ignore_vfp_enabled
= false;
636 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
640 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
642 * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
643 * Accesses to R15 are UNPREDICTABLE; we choose to undef.
644 * (FPSCR -> r15 is a special case which writes to the PSR flags.)
646 if (a
->rt
== 15 && (!a
->l
|| a
->reg
!= ARM_VFP_FPSCR
)) {
654 * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
655 * all ID registers to privileged access only.
657 if (IS_USER(s
) && dc_isar_feature(aa32_fpsp_v3
, s
)) {
660 ignore_vfp_enabled
= true;
664 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_MVFR
)) {
667 ignore_vfp_enabled
= true;
670 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
673 ignore_vfp_enabled
= true;
681 ignore_vfp_enabled
= true;
684 case ARM_VFP_FPINST2
:
685 /* Not present in VFPv3 */
686 if (IS_USER(s
) || dc_isar_feature(aa32_fpsp_v3
, s
)) {
694 if (!full_vfp_access_check(s
, ignore_vfp_enabled
)) {
699 /* VMRS, move VFP special register to gp register */
705 if (s
->current_el
== 1) {
706 TCGv_i32 tcg_reg
, tcg_rt
;
709 gen_set_pc_im(s
, s
->pc_curr
);
710 tcg_reg
= tcg_const_i32(a
->reg
);
711 tcg_rt
= tcg_const_i32(a
->rt
);
712 gen_helper_check_hcr_el2_trap(cpu_env
, tcg_rt
, tcg_reg
);
713 tcg_temp_free_i32(tcg_reg
);
714 tcg_temp_free_i32(tcg_rt
);
719 case ARM_VFP_FPINST2
:
720 tmp
= load_cpu_field(vfp
.xregs
[a
->reg
]);
724 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
725 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
727 tmp
= tcg_temp_new_i32();
728 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
732 g_assert_not_reached();
736 /* Set the 4 flag bits in the CPSR. */
738 tcg_temp_free_i32(tmp
);
740 store_reg(s
, a
->rt
, tmp
);
743 /* VMSR, move gp register to VFP special register */
749 /* Writes are ignored. */
752 tmp
= load_reg(s
, a
->rt
);
753 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
754 tcg_temp_free_i32(tmp
);
759 * TODO: VFP subarchitecture support.
760 * For now, keep the EN bit only
762 tmp
= load_reg(s
, a
->rt
);
763 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
764 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
768 case ARM_VFP_FPINST2
:
769 tmp
= load_reg(s
, a
->rt
);
770 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
773 g_assert_not_reached();
780 static bool trans_VMOV_single(DisasContext
*s
, arg_VMOV_single
*a
)
784 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
788 if (!vfp_access_check(s
)) {
793 /* VFP to general purpose register */
794 tmp
= tcg_temp_new_i32();
795 neon_load_reg32(tmp
, a
->vn
);
797 /* Set the 4 flag bits in the CPSR. */
799 tcg_temp_free_i32(tmp
);
801 store_reg(s
, a
->rt
, tmp
);
804 /* general purpose register to VFP */
805 tmp
= load_reg(s
, a
->rt
);
806 neon_store_reg32(tmp
, a
->vn
);
807 tcg_temp_free_i32(tmp
);
813 static bool trans_VMOV_64_sp(DisasContext
*s
, arg_VMOV_64_sp
*a
)
817 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
822 * VMOV between two general-purpose registers and two single precision
823 * floating point registers
825 if (!vfp_access_check(s
)) {
831 tmp
= tcg_temp_new_i32();
832 neon_load_reg32(tmp
, a
->vm
);
833 store_reg(s
, a
->rt
, tmp
);
834 tmp
= tcg_temp_new_i32();
835 neon_load_reg32(tmp
, a
->vm
+ 1);
836 store_reg(s
, a
->rt2
, tmp
);
839 tmp
= load_reg(s
, a
->rt
);
840 neon_store_reg32(tmp
, a
->vm
);
841 tcg_temp_free_i32(tmp
);
842 tmp
= load_reg(s
, a
->rt2
);
843 neon_store_reg32(tmp
, a
->vm
+ 1);
844 tcg_temp_free_i32(tmp
);
850 static bool trans_VMOV_64_dp(DisasContext
*s
, arg_VMOV_64_dp
*a
)
855 * VMOV between two general-purpose registers and one double precision
856 * floating point register. Note that this does not require support
857 * for double precision arithmetic.
859 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
863 /* UNDEF accesses to D16-D31 if they don't exist */
864 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
868 if (!vfp_access_check(s
)) {
874 tmp
= tcg_temp_new_i32();
875 neon_load_reg32(tmp
, a
->vm
* 2);
876 store_reg(s
, a
->rt
, tmp
);
877 tmp
= tcg_temp_new_i32();
878 neon_load_reg32(tmp
, a
->vm
* 2 + 1);
879 store_reg(s
, a
->rt2
, tmp
);
882 tmp
= load_reg(s
, a
->rt
);
883 neon_store_reg32(tmp
, a
->vm
* 2);
884 tcg_temp_free_i32(tmp
);
885 tmp
= load_reg(s
, a
->rt2
);
886 neon_store_reg32(tmp
, a
->vm
* 2 + 1);
887 tcg_temp_free_i32(tmp
);
893 static bool trans_VLDR_VSTR_sp(DisasContext
*s
, arg_VLDR_VSTR_sp
*a
)
898 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
902 if (!vfp_access_check(s
)) {
906 offset
= a
->imm
<< 2;
911 /* For thumb, use of PC is UNPREDICTABLE. */
912 addr
= add_reg_for_lit(s
, a
->rn
, offset
);
913 tmp
= tcg_temp_new_i32();
915 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
916 neon_store_reg32(tmp
, a
->vd
);
918 neon_load_reg32(tmp
, a
->vd
);
919 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
921 tcg_temp_free_i32(tmp
);
922 tcg_temp_free_i32(addr
);
927 static bool trans_VLDR_VSTR_dp(DisasContext
*s
, arg_VLDR_VSTR_dp
*a
)
933 /* Note that this does not require support for double arithmetic. */
934 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
938 /* UNDEF accesses to D16-D31 if they don't exist */
939 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
943 if (!vfp_access_check(s
)) {
947 offset
= a
->imm
<< 2;
952 /* For thumb, use of PC is UNPREDICTABLE. */
953 addr
= add_reg_for_lit(s
, a
->rn
, offset
);
954 tmp
= tcg_temp_new_i64();
956 gen_aa32_ld64(s
, tmp
, addr
, get_mem_index(s
));
957 neon_store_reg64(tmp
, a
->vd
);
959 neon_load_reg64(tmp
, a
->vd
);
960 gen_aa32_st64(s
, tmp
, addr
, get_mem_index(s
));
962 tcg_temp_free_i64(tmp
);
963 tcg_temp_free_i32(addr
);
968 static bool trans_VLDM_VSTM_sp(DisasContext
*s
, arg_VLDM_VSTM_sp
*a
)
974 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
980 if (n
== 0 || (a
->vd
+ n
) > 32) {
982 * UNPREDICTABLE cases for bad immediates: we choose to
983 * UNDEF to avoid generating huge numbers of TCG ops
987 if (a
->rn
== 15 && a
->w
) {
988 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
992 if (!vfp_access_check(s
)) {
996 /* For thumb, use of PC is UNPREDICTABLE. */
997 addr
= add_reg_for_lit(s
, a
->rn
, 0);
1000 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
1003 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
1005 * Here 'addr' is the lowest address we will store to,
1006 * and is either the old SP (if post-increment) or
1007 * the new SP (if pre-decrement). For post-increment
1008 * where the old value is below the limit and the new
1009 * value is above, it is UNKNOWN whether the limit check
1010 * triggers; we choose to trigger.
1012 gen_helper_v8m_stackcheck(cpu_env
, addr
);
1016 tmp
= tcg_temp_new_i32();
1017 for (i
= 0; i
< n
; i
++) {
1020 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1021 neon_store_reg32(tmp
, a
->vd
+ i
);
1024 neon_load_reg32(tmp
, a
->vd
+ i
);
1025 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1027 tcg_gen_addi_i32(addr
, addr
, offset
);
1029 tcg_temp_free_i32(tmp
);
1033 offset
= -offset
* n
;
1034 tcg_gen_addi_i32(addr
, addr
, offset
);
1036 store_reg(s
, a
->rn
, addr
);
1038 tcg_temp_free_i32(addr
);
1044 static bool trans_VLDM_VSTM_dp(DisasContext
*s
, arg_VLDM_VSTM_dp
*a
)
1051 /* Note that this does not require support for double arithmetic. */
1052 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
1058 if (n
== 0 || (a
->vd
+ n
) > 32 || n
> 16) {
1060 * UNPREDICTABLE cases for bad immediates: we choose to
1061 * UNDEF to avoid generating huge numbers of TCG ops
1065 if (a
->rn
== 15 && a
->w
) {
1066 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1070 /* UNDEF accesses to D16-D31 if they don't exist */
1071 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
+ n
) > 16) {
1075 if (!vfp_access_check(s
)) {
1079 /* For thumb, use of PC is UNPREDICTABLE. */
1080 addr
= add_reg_for_lit(s
, a
->rn
, 0);
1083 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
1086 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
1088 * Here 'addr' is the lowest address we will store to,
1089 * and is either the old SP (if post-increment) or
1090 * the new SP (if pre-decrement). For post-increment
1091 * where the old value is below the limit and the new
1092 * value is above, it is UNKNOWN whether the limit check
1093 * triggers; we choose to trigger.
1095 gen_helper_v8m_stackcheck(cpu_env
, addr
);
1099 tmp
= tcg_temp_new_i64();
1100 for (i
= 0; i
< n
; i
++) {
1103 gen_aa32_ld64(s
, tmp
, addr
, get_mem_index(s
));
1104 neon_store_reg64(tmp
, a
->vd
+ i
);
1107 neon_load_reg64(tmp
, a
->vd
+ i
);
1108 gen_aa32_st64(s
, tmp
, addr
, get_mem_index(s
));
1110 tcg_gen_addi_i32(addr
, addr
, offset
);
1112 tcg_temp_free_i64(tmp
);
1116 offset
= -offset
* n
;
1117 } else if (a
->imm
& 1) {
1124 tcg_gen_addi_i32(addr
, addr
, offset
);
1126 store_reg(s
, a
->rn
, addr
);
1128 tcg_temp_free_i32(addr
);
1135 * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
1136 * The callback should emit code to write a value to vd. If
1137 * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
1138 * will contain the old value of the relevant VFP register;
1139 * otherwise it must be written to only.
1141 typedef void VFPGen3OpSPFn(TCGv_i32 vd
,
1142 TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
);
1143 typedef void VFPGen3OpDPFn(TCGv_i64 vd
,
1144 TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
);
1147 * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
1148 * The callback should emit code to write a value to vd (which
1149 * should be written to only).
1151 typedef void VFPGen2OpSPFn(TCGv_i32 vd
, TCGv_i32 vm
);
1152 typedef void VFPGen2OpDPFn(TCGv_i64 vd
, TCGv_i64 vm
);
1155 * Return true if the specified S reg is in a scalar bank
1156 * (ie if it is s0..s7)
1158 static inline bool vfp_sreg_is_scalar(int reg
)
1160 return (reg
& 0x18) == 0;
1164 * Return true if the specified D reg is in a scalar bank
1165 * (ie if it is d0..d3 or d16..d19)
1167 static inline bool vfp_dreg_is_scalar(int reg
)
1169 return (reg
& 0xc) == 0;
1173 * Advance the S reg number forwards by delta within its bank
1174 * (ie increment the low 3 bits but leave the rest the same)
1176 static inline int vfp_advance_sreg(int reg
, int delta
)
1178 return ((reg
+ delta
) & 0x7) | (reg
& ~0x7);
1182 * Advance the D reg number forwards by delta within its bank
1183 * (ie increment the low 2 bits but leave the rest the same)
1185 static inline int vfp_advance_dreg(int reg
, int delta
)
1187 return ((reg
+ delta
) & 0x3) | (reg
& ~0x3);
1191 * Perform a 3-operand VFP data processing instruction. fn is the
1192 * callback to do the actual operation; this function deals with the
1193 * code to handle looping around for VFP vector processing.
1195 static bool do_vfp_3op_sp(DisasContext
*s
, VFPGen3OpSPFn
*fn
,
1196 int vd
, int vn
, int vm
, bool reads_vd
)
1198 uint32_t delta_m
= 0;
1199 uint32_t delta_d
= 0;
1200 int veclen
= s
->vec_len
;
1201 TCGv_i32 f0
, f1
, fd
;
1204 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
1208 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1209 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1213 if (!vfp_access_check(s
)) {
1218 /* Figure out what type of vector operation this is. */
1219 if (vfp_sreg_is_scalar(vd
)) {
1223 delta_d
= s
->vec_stride
+ 1;
1225 if (vfp_sreg_is_scalar(vm
)) {
1226 /* mixed scalar/vector */
1235 f0
= tcg_temp_new_i32();
1236 f1
= tcg_temp_new_i32();
1237 fd
= tcg_temp_new_i32();
1238 fpst
= get_fpstatus_ptr(0);
1240 neon_load_reg32(f0
, vn
);
1241 neon_load_reg32(f1
, vm
);
1245 neon_load_reg32(fd
, vd
);
1247 fn(fd
, f0
, f1
, fpst
);
1248 neon_store_reg32(fd
, vd
);
1254 /* Set up the operands for the next iteration */
1256 vd
= vfp_advance_sreg(vd
, delta_d
);
1257 vn
= vfp_advance_sreg(vn
, delta_d
);
1258 neon_load_reg32(f0
, vn
);
1260 vm
= vfp_advance_sreg(vm
, delta_m
);
1261 neon_load_reg32(f1
, vm
);
1265 tcg_temp_free_i32(f0
);
1266 tcg_temp_free_i32(f1
);
1267 tcg_temp_free_i32(fd
);
1268 tcg_temp_free_ptr(fpst
);
1273 static bool do_vfp_3op_dp(DisasContext
*s
, VFPGen3OpDPFn
*fn
,
1274 int vd
, int vn
, int vm
, bool reads_vd
)
1276 uint32_t delta_m
= 0;
1277 uint32_t delta_d
= 0;
1278 int veclen
= s
->vec_len
;
1279 TCGv_i64 f0
, f1
, fd
;
1282 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
1286 /* UNDEF accesses to D16-D31 if they don't exist */
1287 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((vd
| vn
| vm
) & 0x10)) {
1291 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1292 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1296 if (!vfp_access_check(s
)) {
1301 /* Figure out what type of vector operation this is. */
1302 if (vfp_dreg_is_scalar(vd
)) {
1306 delta_d
= (s
->vec_stride
>> 1) + 1;
1308 if (vfp_dreg_is_scalar(vm
)) {
1309 /* mixed scalar/vector */
1318 f0
= tcg_temp_new_i64();
1319 f1
= tcg_temp_new_i64();
1320 fd
= tcg_temp_new_i64();
1321 fpst
= get_fpstatus_ptr(0);
1323 neon_load_reg64(f0
, vn
);
1324 neon_load_reg64(f1
, vm
);
1328 neon_load_reg64(fd
, vd
);
1330 fn(fd
, f0
, f1
, fpst
);
1331 neon_store_reg64(fd
, vd
);
1336 /* Set up the operands for the next iteration */
1338 vd
= vfp_advance_dreg(vd
, delta_d
);
1339 vn
= vfp_advance_dreg(vn
, delta_d
);
1340 neon_load_reg64(f0
, vn
);
1342 vm
= vfp_advance_dreg(vm
, delta_m
);
1343 neon_load_reg64(f1
, vm
);
1347 tcg_temp_free_i64(f0
);
1348 tcg_temp_free_i64(f1
);
1349 tcg_temp_free_i64(fd
);
1350 tcg_temp_free_ptr(fpst
);
1355 static bool do_vfp_2op_sp(DisasContext
*s
, VFPGen2OpSPFn
*fn
, int vd
, int vm
)
1357 uint32_t delta_m
= 0;
1358 uint32_t delta_d
= 0;
1359 int veclen
= s
->vec_len
;
1362 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
1366 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1367 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1371 if (!vfp_access_check(s
)) {
1376 /* Figure out what type of vector operation this is. */
1377 if (vfp_sreg_is_scalar(vd
)) {
1381 delta_d
= s
->vec_stride
+ 1;
1383 if (vfp_sreg_is_scalar(vm
)) {
1384 /* mixed scalar/vector */
1393 f0
= tcg_temp_new_i32();
1394 fd
= tcg_temp_new_i32();
1396 neon_load_reg32(f0
, vm
);
1400 neon_store_reg32(fd
, vd
);
1407 /* single source one-many */
1409 vd
= vfp_advance_sreg(vd
, delta_d
);
1410 neon_store_reg32(fd
, vd
);
1415 /* Set up the operands for the next iteration */
1417 vd
= vfp_advance_sreg(vd
, delta_d
);
1418 vm
= vfp_advance_sreg(vm
, delta_m
);
1419 neon_load_reg32(f0
, vm
);
1422 tcg_temp_free_i32(f0
);
1423 tcg_temp_free_i32(fd
);
1428 static bool do_vfp_2op_dp(DisasContext
*s
, VFPGen2OpDPFn
*fn
, int vd
, int vm
)
1430 uint32_t delta_m
= 0;
1431 uint32_t delta_d
= 0;
1432 int veclen
= s
->vec_len
;
1435 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
1439 /* UNDEF accesses to D16-D31 if they don't exist */
1440 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((vd
| vm
) & 0x10)) {
1444 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1445 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1449 if (!vfp_access_check(s
)) {
1454 /* Figure out what type of vector operation this is. */
1455 if (vfp_dreg_is_scalar(vd
)) {
1459 delta_d
= (s
->vec_stride
>> 1) + 1;
1461 if (vfp_dreg_is_scalar(vm
)) {
1462 /* mixed scalar/vector */
1471 f0
= tcg_temp_new_i64();
1472 fd
= tcg_temp_new_i64();
1474 neon_load_reg64(f0
, vm
);
1478 neon_store_reg64(fd
, vd
);
1485 /* single source one-many */
1487 vd
= vfp_advance_dreg(vd
, delta_d
);
1488 neon_store_reg64(fd
, vd
);
1493 /* Set up the operands for the next iteration */
1495 vd
= vfp_advance_dreg(vd
, delta_d
);
1496 vd
= vfp_advance_dreg(vm
, delta_m
);
1497 neon_load_reg64(f0
, vm
);
1500 tcg_temp_free_i64(f0
);
1501 tcg_temp_free_i64(fd
);
1506 static void gen_VMLA_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1508 /* Note that order of inputs to the add matters for NaNs */
1509 TCGv_i32 tmp
= tcg_temp_new_i32();
1511 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1512 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1513 tcg_temp_free_i32(tmp
);
1516 static bool trans_VMLA_sp(DisasContext
*s
, arg_VMLA_sp
*a
)
1518 return do_vfp_3op_sp(s
, gen_VMLA_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1521 static void gen_VMLA_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1523 /* Note that order of inputs to the add matters for NaNs */
1524 TCGv_i64 tmp
= tcg_temp_new_i64();
1526 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1527 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1528 tcg_temp_free_i64(tmp
);
1531 static bool trans_VMLA_dp(DisasContext
*s
, arg_VMLA_dp
*a
)
1533 return do_vfp_3op_dp(s
, gen_VMLA_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1536 static void gen_VMLS_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1539 * VMLS: vd = vd + -(vn * vm)
1540 * Note that order of inputs to the add matters for NaNs.
1542 TCGv_i32 tmp
= tcg_temp_new_i32();
1544 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1545 gen_helper_vfp_negs(tmp
, tmp
);
1546 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1547 tcg_temp_free_i32(tmp
);
1550 static bool trans_VMLS_sp(DisasContext
*s
, arg_VMLS_sp
*a
)
1552 return do_vfp_3op_sp(s
, gen_VMLS_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1555 static void gen_VMLS_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1558 * VMLS: vd = vd + -(vn * vm)
1559 * Note that order of inputs to the add matters for NaNs.
1561 TCGv_i64 tmp
= tcg_temp_new_i64();
1563 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1564 gen_helper_vfp_negd(tmp
, tmp
);
1565 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1566 tcg_temp_free_i64(tmp
);
1569 static bool trans_VMLS_dp(DisasContext
*s
, arg_VMLS_dp
*a
)
1571 return do_vfp_3op_dp(s
, gen_VMLS_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1574 static void gen_VNMLS_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1577 * VNMLS: -fd + (fn * fm)
1578 * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1579 * plausible looking simplifications because this will give wrong results
1582 TCGv_i32 tmp
= tcg_temp_new_i32();
1584 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1585 gen_helper_vfp_negs(vd
, vd
);
1586 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1587 tcg_temp_free_i32(tmp
);
1590 static bool trans_VNMLS_sp(DisasContext
*s
, arg_VNMLS_sp
*a
)
1592 return do_vfp_3op_sp(s
, gen_VNMLS_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1595 static void gen_VNMLS_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1598 * VNMLS: -fd + (fn * fm)
1599 * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1600 * plausible looking simplifications because this will give wrong results
1603 TCGv_i64 tmp
= tcg_temp_new_i64();
1605 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1606 gen_helper_vfp_negd(vd
, vd
);
1607 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1608 tcg_temp_free_i64(tmp
);
1611 static bool trans_VNMLS_dp(DisasContext
*s
, arg_VNMLS_dp
*a
)
1613 return do_vfp_3op_dp(s
, gen_VNMLS_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1616 static void gen_VNMLA_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1618 /* VNMLA: -fd + -(fn * fm) */
1619 TCGv_i32 tmp
= tcg_temp_new_i32();
1621 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1622 gen_helper_vfp_negs(tmp
, tmp
);
1623 gen_helper_vfp_negs(vd
, vd
);
1624 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1625 tcg_temp_free_i32(tmp
);
1628 static bool trans_VNMLA_sp(DisasContext
*s
, arg_VNMLA_sp
*a
)
1630 return do_vfp_3op_sp(s
, gen_VNMLA_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1633 static void gen_VNMLA_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1635 /* VNMLA: -fd + (fn * fm) */
1636 TCGv_i64 tmp
= tcg_temp_new_i64();
1638 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1639 gen_helper_vfp_negd(tmp
, tmp
);
1640 gen_helper_vfp_negd(vd
, vd
);
1641 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1642 tcg_temp_free_i64(tmp
);
1645 static bool trans_VNMLA_dp(DisasContext
*s
, arg_VNMLA_dp
*a
)
1647 return do_vfp_3op_dp(s
, gen_VNMLA_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1650 static bool trans_VMUL_sp(DisasContext
*s
, arg_VMUL_sp
*a
)
1652 return do_vfp_3op_sp(s
, gen_helper_vfp_muls
, a
->vd
, a
->vn
, a
->vm
, false);
1655 static bool trans_VMUL_dp(DisasContext
*s
, arg_VMUL_dp
*a
)
1657 return do_vfp_3op_dp(s
, gen_helper_vfp_muld
, a
->vd
, a
->vn
, a
->vm
, false);
1660 static void gen_VNMUL_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1662 /* VNMUL: -(fn * fm) */
1663 gen_helper_vfp_muls(vd
, vn
, vm
, fpst
);
1664 gen_helper_vfp_negs(vd
, vd
);
1667 static bool trans_VNMUL_sp(DisasContext
*s
, arg_VNMUL_sp
*a
)
1669 return do_vfp_3op_sp(s
, gen_VNMUL_sp
, a
->vd
, a
->vn
, a
->vm
, false);
1672 static void gen_VNMUL_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1674 /* VNMUL: -(fn * fm) */
1675 gen_helper_vfp_muld(vd
, vn
, vm
, fpst
);
1676 gen_helper_vfp_negd(vd
, vd
);
1679 static bool trans_VNMUL_dp(DisasContext
*s
, arg_VNMUL_dp
*a
)
1681 return do_vfp_3op_dp(s
, gen_VNMUL_dp
, a
->vd
, a
->vn
, a
->vm
, false);
1684 static bool trans_VADD_sp(DisasContext
*s
, arg_VADD_sp
*a
)
1686 return do_vfp_3op_sp(s
, gen_helper_vfp_adds
, a
->vd
, a
->vn
, a
->vm
, false);
1689 static bool trans_VADD_dp(DisasContext
*s
, arg_VADD_dp
*a
)
1691 return do_vfp_3op_dp(s
, gen_helper_vfp_addd
, a
->vd
, a
->vn
, a
->vm
, false);
1694 static bool trans_VSUB_sp(DisasContext
*s
, arg_VSUB_sp
*a
)
1696 return do_vfp_3op_sp(s
, gen_helper_vfp_subs
, a
->vd
, a
->vn
, a
->vm
, false);
1699 static bool trans_VSUB_dp(DisasContext
*s
, arg_VSUB_dp
*a
)
1701 return do_vfp_3op_dp(s
, gen_helper_vfp_subd
, a
->vd
, a
->vn
, a
->vm
, false);
1704 static bool trans_VDIV_sp(DisasContext
*s
, arg_VDIV_sp
*a
)
1706 return do_vfp_3op_sp(s
, gen_helper_vfp_divs
, a
->vd
, a
->vn
, a
->vm
, false);
1709 static bool trans_VDIV_dp(DisasContext
*s
, arg_VDIV_dp
*a
)
1711 return do_vfp_3op_dp(s
, gen_helper_vfp_divd
, a
->vd
, a
->vn
, a
->vm
, false);
1714 static bool trans_VMINNM_sp(DisasContext
*s
, arg_VMINNM_sp
*a
)
1716 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
1719 return do_vfp_3op_sp(s
, gen_helper_vfp_minnums
,
1720 a
->vd
, a
->vn
, a
->vm
, false);
1723 static bool trans_VMAXNM_sp(DisasContext
*s
, arg_VMAXNM_sp
*a
)
1725 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
1728 return do_vfp_3op_sp(s
, gen_helper_vfp_maxnums
,
1729 a
->vd
, a
->vn
, a
->vm
, false);
1732 static bool trans_VMINNM_dp(DisasContext
*s
, arg_VMINNM_dp
*a
)
1734 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
1737 return do_vfp_3op_dp(s
, gen_helper_vfp_minnumd
,
1738 a
->vd
, a
->vn
, a
->vm
, false);
1741 static bool trans_VMAXNM_dp(DisasContext
*s
, arg_VMAXNM_dp
*a
)
1743 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
1746 return do_vfp_3op_dp(s
, gen_helper_vfp_maxnumd
,
1747 a
->vd
, a
->vn
, a
->vm
, false);
1750 static bool do_vfm_sp(DisasContext
*s
, arg_VFMA_sp
*a
, bool neg_n
, bool neg_d
)
1753 * VFNMA : fd = muladd(-fd, fn, fm)
1754 * VFNMS : fd = muladd(-fd, -fn, fm)
1755 * VFMA : fd = muladd( fd, fn, fm)
1756 * VFMS : fd = muladd( fd, -fn, fm)
1758 * These are fused multiply-add, and must be done as one floating
1759 * point operation with no rounding between the multiplication and
1760 * addition steps. NB that doing the negations here as separate
1761 * steps is correct : an input NaN should come out with its sign
1762 * bit flipped if it is a negated-input.
1765 TCGv_i32 vn
, vm
, vd
;
1768 * Present in VFPv4 only.
1769 * Note that we can't rely on the SIMDFMAC check alone, because
1770 * in a Neon-no-VFP core that ID register field will be non-zero.
1772 if (!dc_isar_feature(aa32_simdfmac
, s
) ||
1773 !dc_isar_feature(aa32_fpsp_v2
, s
)) {
1777 * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
1778 * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
1780 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
1784 if (!vfp_access_check(s
)) {
1788 vn
= tcg_temp_new_i32();
1789 vm
= tcg_temp_new_i32();
1790 vd
= tcg_temp_new_i32();
1792 neon_load_reg32(vn
, a
->vn
);
1793 neon_load_reg32(vm
, a
->vm
);
1796 gen_helper_vfp_negs(vn
, vn
);
1798 neon_load_reg32(vd
, a
->vd
);
1801 gen_helper_vfp_negs(vd
, vd
);
1803 fpst
= get_fpstatus_ptr(0);
1804 gen_helper_vfp_muladds(vd
, vn
, vm
, vd
, fpst
);
1805 neon_store_reg32(vd
, a
->vd
);
1807 tcg_temp_free_ptr(fpst
);
1808 tcg_temp_free_i32(vn
);
1809 tcg_temp_free_i32(vm
);
1810 tcg_temp_free_i32(vd
);
1815 static bool trans_VFMA_sp(DisasContext
*s
, arg_VFMA_sp
*a
)
1817 return do_vfm_sp(s
, a
, false, false);
1820 static bool trans_VFMS_sp(DisasContext
*s
, arg_VFMS_sp
*a
)
1822 return do_vfm_sp(s
, a
, true, false);
1825 static bool trans_VFNMA_sp(DisasContext
*s
, arg_VFNMA_sp
*a
)
1827 return do_vfm_sp(s
, a
, false, true);
1830 static bool trans_VFNMS_sp(DisasContext
*s
, arg_VFNMS_sp
*a
)
1832 return do_vfm_sp(s
, a
, true, true);
1835 static bool do_vfm_dp(DisasContext
*s
, arg_VFMA_dp
*a
, bool neg_n
, bool neg_d
)
1838 * VFNMA : fd = muladd(-fd, fn, fm)
1839 * VFNMS : fd = muladd(-fd, -fn, fm)
1840 * VFMA : fd = muladd( fd, fn, fm)
1841 * VFMS : fd = muladd( fd, -fn, fm)
1843 * These are fused multiply-add, and must be done as one floating
1844 * point operation with no rounding between the multiplication and
1845 * addition steps. NB that doing the negations here as separate
1846 * steps is correct : an input NaN should come out with its sign
1847 * bit flipped if it is a negated-input.
1850 TCGv_i64 vn
, vm
, vd
;
1853 * Present in VFPv4 only.
1854 * Note that we can't rely on the SIMDFMAC check alone, because
1855 * in a Neon-no-VFP core that ID register field will be non-zero.
1857 if (!dc_isar_feature(aa32_simdfmac
, s
) ||
1858 !dc_isar_feature(aa32_fpdp_v2
, s
)) {
1862 * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
1863 * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
1865 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
1869 /* UNDEF accesses to D16-D31 if they don't exist. */
1870 if (!dc_isar_feature(aa32_simd_r32
, s
) &&
1871 ((a
->vd
| a
->vn
| a
->vm
) & 0x10)) {
1875 /* UNDEF accesses to D16-D31 if they don't exist. */
1876 if (!dc_isar_feature(aa32_simd_r32
, s
) &&
1877 ((a
->vd
| a
->vn
| a
->vm
) & 0x10)) {
1881 if (!vfp_access_check(s
)) {
1885 vn
= tcg_temp_new_i64();
1886 vm
= tcg_temp_new_i64();
1887 vd
= tcg_temp_new_i64();
1889 neon_load_reg64(vn
, a
->vn
);
1890 neon_load_reg64(vm
, a
->vm
);
1893 gen_helper_vfp_negd(vn
, vn
);
1895 neon_load_reg64(vd
, a
->vd
);
1898 gen_helper_vfp_negd(vd
, vd
);
1900 fpst
= get_fpstatus_ptr(0);
1901 gen_helper_vfp_muladdd(vd
, vn
, vm
, vd
, fpst
);
1902 neon_store_reg64(vd
, a
->vd
);
1904 tcg_temp_free_ptr(fpst
);
1905 tcg_temp_free_i64(vn
);
1906 tcg_temp_free_i64(vm
);
1907 tcg_temp_free_i64(vd
);
1912 static bool trans_VFMA_dp(DisasContext
*s
, arg_VFMA_dp
*a
)
1914 return do_vfm_dp(s
, a
, false, false);
1917 static bool trans_VFMS_dp(DisasContext
*s
, arg_VFMS_dp
*a
)
1919 return do_vfm_dp(s
, a
, true, false);
1922 static bool trans_VFNMA_dp(DisasContext
*s
, arg_VFNMA_dp
*a
)
1924 return do_vfm_dp(s
, a
, false, true);
1927 static bool trans_VFNMS_dp(DisasContext
*s
, arg_VFNMS_dp
*a
)
1929 return do_vfm_dp(s
, a
, true, true);
1932 static bool trans_VMOV_imm_sp(DisasContext
*s
, arg_VMOV_imm_sp
*a
)
1934 uint32_t delta_d
= 0;
1935 int veclen
= s
->vec_len
;
1941 if (!dc_isar_feature(aa32_fpsp_v3
, s
)) {
1945 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1946 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1950 if (!vfp_access_check(s
)) {
1955 /* Figure out what type of vector operation this is. */
1956 if (vfp_sreg_is_scalar(vd
)) {
1960 delta_d
= s
->vec_stride
+ 1;
1964 fd
= tcg_const_i32(vfp_expand_imm(MO_32
, a
->imm
));
1967 neon_store_reg32(fd
, vd
);
1973 /* Set up the operands for the next iteration */
1975 vd
= vfp_advance_sreg(vd
, delta_d
);
1978 tcg_temp_free_i32(fd
);
1982 static bool trans_VMOV_imm_dp(DisasContext
*s
, arg_VMOV_imm_dp
*a
)
1984 uint32_t delta_d
= 0;
1985 int veclen
= s
->vec_len
;
1991 if (!dc_isar_feature(aa32_fpdp_v3
, s
)) {
1995 /* UNDEF accesses to D16-D31 if they don't exist. */
1996 if (!dc_isar_feature(aa32_simd_r32
, s
) && (vd
& 0x10)) {
2000 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
2001 (veclen
!= 0 || s
->vec_stride
!= 0)) {
2005 if (!vfp_access_check(s
)) {
2010 /* Figure out what type of vector operation this is. */
2011 if (vfp_dreg_is_scalar(vd
)) {
2015 delta_d
= (s
->vec_stride
>> 1) + 1;
2019 fd
= tcg_const_i64(vfp_expand_imm(MO_64
, a
->imm
));
2022 neon_store_reg64(fd
, vd
);
2028 /* Set up the operands for the next iteration */
2030 vd
= vfp_advance_dreg(vd
, delta_d
);
2033 tcg_temp_free_i64(fd
);
2037 static bool trans_VMOV_reg_sp(DisasContext
*s
, arg_VMOV_reg_sp
*a
)
2039 return do_vfp_2op_sp(s
, tcg_gen_mov_i32
, a
->vd
, a
->vm
);
2042 static bool trans_VMOV_reg_dp(DisasContext
*s
, arg_VMOV_reg_dp
*a
)
2044 return do_vfp_2op_dp(s
, tcg_gen_mov_i64
, a
->vd
, a
->vm
);
2047 static bool trans_VABS_sp(DisasContext
*s
, arg_VABS_sp
*a
)
2049 return do_vfp_2op_sp(s
, gen_helper_vfp_abss
, a
->vd
, a
->vm
);
2052 static bool trans_VABS_dp(DisasContext
*s
, arg_VABS_dp
*a
)
2054 return do_vfp_2op_dp(s
, gen_helper_vfp_absd
, a
->vd
, a
->vm
);
2057 static bool trans_VNEG_sp(DisasContext
*s
, arg_VNEG_sp
*a
)
2059 return do_vfp_2op_sp(s
, gen_helper_vfp_negs
, a
->vd
, a
->vm
);
2062 static bool trans_VNEG_dp(DisasContext
*s
, arg_VNEG_dp
*a
)
2064 return do_vfp_2op_dp(s
, gen_helper_vfp_negd
, a
->vd
, a
->vm
);
2067 static void gen_VSQRT_sp(TCGv_i32 vd
, TCGv_i32 vm
)
2069 gen_helper_vfp_sqrts(vd
, vm
, cpu_env
);
2072 static bool trans_VSQRT_sp(DisasContext
*s
, arg_VSQRT_sp
*a
)
2074 return do_vfp_2op_sp(s
, gen_VSQRT_sp
, a
->vd
, a
->vm
);
2077 static void gen_VSQRT_dp(TCGv_i64 vd
, TCGv_i64 vm
)
2079 gen_helper_vfp_sqrtd(vd
, vm
, cpu_env
);
2082 static bool trans_VSQRT_dp(DisasContext
*s
, arg_VSQRT_dp
*a
)
2084 return do_vfp_2op_dp(s
, gen_VSQRT_dp
, a
->vd
, a
->vm
);
2087 static bool trans_VCMP_sp(DisasContext
*s
, arg_VCMP_sp
*a
)
2091 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
2095 /* Vm/M bits must be zero for the Z variant */
2096 if (a
->z
&& a
->vm
!= 0) {
2100 if (!vfp_access_check(s
)) {
2104 vd
= tcg_temp_new_i32();
2105 vm
= tcg_temp_new_i32();
2107 neon_load_reg32(vd
, a
->vd
);
2109 tcg_gen_movi_i32(vm
, 0);
2111 neon_load_reg32(vm
, a
->vm
);
2115 gen_helper_vfp_cmpes(vd
, vm
, cpu_env
);
2117 gen_helper_vfp_cmps(vd
, vm
, cpu_env
);
2120 tcg_temp_free_i32(vd
);
2121 tcg_temp_free_i32(vm
);
2126 static bool trans_VCMP_dp(DisasContext
*s
, arg_VCMP_dp
*a
)
2130 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2134 /* Vm/M bits must be zero for the Z variant */
2135 if (a
->z
&& a
->vm
!= 0) {
2139 /* UNDEF accesses to D16-D31 if they don't exist. */
2140 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2144 if (!vfp_access_check(s
)) {
2148 vd
= tcg_temp_new_i64();
2149 vm
= tcg_temp_new_i64();
2151 neon_load_reg64(vd
, a
->vd
);
2153 tcg_gen_movi_i64(vm
, 0);
2155 neon_load_reg64(vm
, a
->vm
);
2159 gen_helper_vfp_cmped(vd
, vm
, cpu_env
);
2161 gen_helper_vfp_cmpd(vd
, vm
, cpu_env
);
2164 tcg_temp_free_i64(vd
);
2165 tcg_temp_free_i64(vm
);
2170 static bool trans_VCVT_f32_f16(DisasContext
*s
, arg_VCVT_f32_f16
*a
)
2176 if (!dc_isar_feature(aa32_fp16_spconv
, s
)) {
2180 if (!vfp_access_check(s
)) {
2184 fpst
= get_fpstatus_ptr(false);
2185 ahp_mode
= get_ahp_flag();
2186 tmp
= tcg_temp_new_i32();
2187 /* The T bit tells us if we want the low or high 16 bits of Vm */
2188 tcg_gen_ld16u_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vm
, a
->t
));
2189 gen_helper_vfp_fcvt_f16_to_f32(tmp
, tmp
, fpst
, ahp_mode
);
2190 neon_store_reg32(tmp
, a
->vd
);
2191 tcg_temp_free_i32(ahp_mode
);
2192 tcg_temp_free_ptr(fpst
);
2193 tcg_temp_free_i32(tmp
);
2197 static bool trans_VCVT_f64_f16(DisasContext
*s
, arg_VCVT_f64_f16
*a
)
2204 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2208 if (!dc_isar_feature(aa32_fp16_dpconv
, s
)) {
2212 /* UNDEF accesses to D16-D31 if they don't exist. */
2213 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
2217 if (!vfp_access_check(s
)) {
2221 fpst
= get_fpstatus_ptr(false);
2222 ahp_mode
= get_ahp_flag();
2223 tmp
= tcg_temp_new_i32();
2224 /* The T bit tells us if we want the low or high 16 bits of Vm */
2225 tcg_gen_ld16u_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vm
, a
->t
));
2226 vd
= tcg_temp_new_i64();
2227 gen_helper_vfp_fcvt_f16_to_f64(vd
, tmp
, fpst
, ahp_mode
);
2228 neon_store_reg64(vd
, a
->vd
);
2229 tcg_temp_free_i32(ahp_mode
);
2230 tcg_temp_free_ptr(fpst
);
2231 tcg_temp_free_i32(tmp
);
2232 tcg_temp_free_i64(vd
);
2236 static bool trans_VCVT_f16_f32(DisasContext
*s
, arg_VCVT_f16_f32
*a
)
2242 if (!dc_isar_feature(aa32_fp16_spconv
, s
)) {
2246 if (!vfp_access_check(s
)) {
2250 fpst
= get_fpstatus_ptr(false);
2251 ahp_mode
= get_ahp_flag();
2252 tmp
= tcg_temp_new_i32();
2254 neon_load_reg32(tmp
, a
->vm
);
2255 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp_mode
);
2256 tcg_gen_st16_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vd
, a
->t
));
2257 tcg_temp_free_i32(ahp_mode
);
2258 tcg_temp_free_ptr(fpst
);
2259 tcg_temp_free_i32(tmp
);
2263 static bool trans_VCVT_f16_f64(DisasContext
*s
, arg_VCVT_f16_f64
*a
)
2270 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2274 if (!dc_isar_feature(aa32_fp16_dpconv
, s
)) {
2278 /* UNDEF accesses to D16-D31 if they don't exist. */
2279 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
2283 if (!vfp_access_check(s
)) {
2287 fpst
= get_fpstatus_ptr(false);
2288 ahp_mode
= get_ahp_flag();
2289 tmp
= tcg_temp_new_i32();
2290 vm
= tcg_temp_new_i64();
2292 neon_load_reg64(vm
, a
->vm
);
2293 gen_helper_vfp_fcvt_f64_to_f16(tmp
, vm
, fpst
, ahp_mode
);
2294 tcg_temp_free_i64(vm
);
2295 tcg_gen_st16_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vd
, a
->t
));
2296 tcg_temp_free_i32(ahp_mode
);
2297 tcg_temp_free_ptr(fpst
);
2298 tcg_temp_free_i32(tmp
);
2302 static bool trans_VRINTR_sp(DisasContext
*s
, arg_VRINTR_sp
*a
)
2307 if (!dc_isar_feature(aa32_vrint
, s
)) {
2311 if (!vfp_access_check(s
)) {
2315 tmp
= tcg_temp_new_i32();
2316 neon_load_reg32(tmp
, a
->vm
);
2317 fpst
= get_fpstatus_ptr(false);
2318 gen_helper_rints(tmp
, tmp
, fpst
);
2319 neon_store_reg32(tmp
, a
->vd
);
2320 tcg_temp_free_ptr(fpst
);
2321 tcg_temp_free_i32(tmp
);
2325 static bool trans_VRINTR_dp(DisasContext
*s
, arg_VRINTR_dp
*a
)
2330 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2334 if (!dc_isar_feature(aa32_vrint
, s
)) {
2338 /* UNDEF accesses to D16-D31 if they don't exist. */
2339 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2343 if (!vfp_access_check(s
)) {
2347 tmp
= tcg_temp_new_i64();
2348 neon_load_reg64(tmp
, a
->vm
);
2349 fpst
= get_fpstatus_ptr(false);
2350 gen_helper_rintd(tmp
, tmp
, fpst
);
2351 neon_store_reg64(tmp
, a
->vd
);
2352 tcg_temp_free_ptr(fpst
);
2353 tcg_temp_free_i64(tmp
);
2357 static bool trans_VRINTZ_sp(DisasContext
*s
, arg_VRINTZ_sp
*a
)
2363 if (!dc_isar_feature(aa32_vrint
, s
)) {
2367 if (!vfp_access_check(s
)) {
2371 tmp
= tcg_temp_new_i32();
2372 neon_load_reg32(tmp
, a
->vm
);
2373 fpst
= get_fpstatus_ptr(false);
2374 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
2375 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2376 gen_helper_rints(tmp
, tmp
, fpst
);
2377 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2378 neon_store_reg32(tmp
, a
->vd
);
2379 tcg_temp_free_ptr(fpst
);
2380 tcg_temp_free_i32(tcg_rmode
);
2381 tcg_temp_free_i32(tmp
);
2385 static bool trans_VRINTZ_dp(DisasContext
*s
, arg_VRINTZ_dp
*a
)
2391 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2395 if (!dc_isar_feature(aa32_vrint
, s
)) {
2399 /* UNDEF accesses to D16-D31 if they don't exist. */
2400 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2404 if (!vfp_access_check(s
)) {
2408 tmp
= tcg_temp_new_i64();
2409 neon_load_reg64(tmp
, a
->vm
);
2410 fpst
= get_fpstatus_ptr(false);
2411 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
2412 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2413 gen_helper_rintd(tmp
, tmp
, fpst
);
2414 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2415 neon_store_reg64(tmp
, a
->vd
);
2416 tcg_temp_free_ptr(fpst
);
2417 tcg_temp_free_i64(tmp
);
2418 tcg_temp_free_i32(tcg_rmode
);
2422 static bool trans_VRINTX_sp(DisasContext
*s
, arg_VRINTX_sp
*a
)
2427 if (!dc_isar_feature(aa32_vrint
, s
)) {
2431 if (!vfp_access_check(s
)) {
2435 tmp
= tcg_temp_new_i32();
2436 neon_load_reg32(tmp
, a
->vm
);
2437 fpst
= get_fpstatus_ptr(false);
2438 gen_helper_rints_exact(tmp
, tmp
, fpst
);
2439 neon_store_reg32(tmp
, a
->vd
);
2440 tcg_temp_free_ptr(fpst
);
2441 tcg_temp_free_i32(tmp
);
2445 static bool trans_VRINTX_dp(DisasContext
*s
, arg_VRINTX_dp
*a
)
2450 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2454 if (!dc_isar_feature(aa32_vrint
, s
)) {
2458 /* UNDEF accesses to D16-D31 if they don't exist. */
2459 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2463 if (!vfp_access_check(s
)) {
2467 tmp
= tcg_temp_new_i64();
2468 neon_load_reg64(tmp
, a
->vm
);
2469 fpst
= get_fpstatus_ptr(false);
2470 gen_helper_rintd_exact(tmp
, tmp
, fpst
);
2471 neon_store_reg64(tmp
, a
->vd
);
2472 tcg_temp_free_ptr(fpst
);
2473 tcg_temp_free_i64(tmp
);
2477 static bool trans_VCVT_sp(DisasContext
*s
, arg_VCVT_sp
*a
)
2482 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2486 /* UNDEF accesses to D16-D31 if they don't exist. */
2487 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
2491 if (!vfp_access_check(s
)) {
2495 vm
= tcg_temp_new_i32();
2496 vd
= tcg_temp_new_i64();
2497 neon_load_reg32(vm
, a
->vm
);
2498 gen_helper_vfp_fcvtds(vd
, vm
, cpu_env
);
2499 neon_store_reg64(vd
, a
->vd
);
2500 tcg_temp_free_i32(vm
);
2501 tcg_temp_free_i64(vd
);
2505 static bool trans_VCVT_dp(DisasContext
*s
, arg_VCVT_dp
*a
)
2510 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2514 /* UNDEF accesses to D16-D31 if they don't exist. */
2515 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
2519 if (!vfp_access_check(s
)) {
2523 vd
= tcg_temp_new_i32();
2524 vm
= tcg_temp_new_i64();
2525 neon_load_reg64(vm
, a
->vm
);
2526 gen_helper_vfp_fcvtsd(vd
, vm
, cpu_env
);
2527 neon_store_reg32(vd
, a
->vd
);
2528 tcg_temp_free_i32(vd
);
2529 tcg_temp_free_i64(vm
);
2533 static bool trans_VCVT_int_sp(DisasContext
*s
, arg_VCVT_int_sp
*a
)
2538 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
2542 if (!vfp_access_check(s
)) {
2546 vm
= tcg_temp_new_i32();
2547 neon_load_reg32(vm
, a
->vm
);
2548 fpst
= get_fpstatus_ptr(false);
2551 gen_helper_vfp_sitos(vm
, vm
, fpst
);
2554 gen_helper_vfp_uitos(vm
, vm
, fpst
);
2556 neon_store_reg32(vm
, a
->vd
);
2557 tcg_temp_free_i32(vm
);
2558 tcg_temp_free_ptr(fpst
);
2562 static bool trans_VCVT_int_dp(DisasContext
*s
, arg_VCVT_int_dp
*a
)
2568 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2572 /* UNDEF accesses to D16-D31 if they don't exist. */
2573 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
2577 if (!vfp_access_check(s
)) {
2581 vm
= tcg_temp_new_i32();
2582 vd
= tcg_temp_new_i64();
2583 neon_load_reg32(vm
, a
->vm
);
2584 fpst
= get_fpstatus_ptr(false);
2587 gen_helper_vfp_sitod(vd
, vm
, fpst
);
2590 gen_helper_vfp_uitod(vd
, vm
, fpst
);
2592 neon_store_reg64(vd
, a
->vd
);
2593 tcg_temp_free_i32(vm
);
2594 tcg_temp_free_i64(vd
);
2595 tcg_temp_free_ptr(fpst
);
2599 static bool trans_VJCVT(DisasContext
*s
, arg_VJCVT
*a
)
2604 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2608 if (!dc_isar_feature(aa32_jscvt
, s
)) {
2612 /* UNDEF accesses to D16-D31 if they don't exist. */
2613 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
2617 if (!vfp_access_check(s
)) {
2621 vm
= tcg_temp_new_i64();
2622 vd
= tcg_temp_new_i32();
2623 neon_load_reg64(vm
, a
->vm
);
2624 gen_helper_vjcvt(vd
, vm
, cpu_env
);
2625 neon_store_reg32(vd
, a
->vd
);
2626 tcg_temp_free_i64(vm
);
2627 tcg_temp_free_i32(vd
);
2631 static bool trans_VCVT_fix_sp(DisasContext
*s
, arg_VCVT_fix_sp
*a
)
2637 if (!dc_isar_feature(aa32_fpsp_v3
, s
)) {
2641 if (!vfp_access_check(s
)) {
2645 frac_bits
= (a
->opc
& 1) ? (32 - a
->imm
) : (16 - a
->imm
);
2647 vd
= tcg_temp_new_i32();
2648 neon_load_reg32(vd
, a
->vd
);
2650 fpst
= get_fpstatus_ptr(false);
2651 shift
= tcg_const_i32(frac_bits
);
2653 /* Switch on op:U:sx bits */
2656 gen_helper_vfp_shtos(vd
, vd
, shift
, fpst
);
2659 gen_helper_vfp_sltos(vd
, vd
, shift
, fpst
);
2662 gen_helper_vfp_uhtos(vd
, vd
, shift
, fpst
);
2665 gen_helper_vfp_ultos(vd
, vd
, shift
, fpst
);
2668 gen_helper_vfp_toshs_round_to_zero(vd
, vd
, shift
, fpst
);
2671 gen_helper_vfp_tosls_round_to_zero(vd
, vd
, shift
, fpst
);
2674 gen_helper_vfp_touhs_round_to_zero(vd
, vd
, shift
, fpst
);
2677 gen_helper_vfp_touls_round_to_zero(vd
, vd
, shift
, fpst
);
2680 g_assert_not_reached();
2683 neon_store_reg32(vd
, a
->vd
);
2684 tcg_temp_free_i32(vd
);
2685 tcg_temp_free_i32(shift
);
2686 tcg_temp_free_ptr(fpst
);
2690 static bool trans_VCVT_fix_dp(DisasContext
*s
, arg_VCVT_fix_dp
*a
)
2697 if (!dc_isar_feature(aa32_fpdp_v3
, s
)) {
2701 /* UNDEF accesses to D16-D31 if they don't exist. */
2702 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
2706 if (!vfp_access_check(s
)) {
2710 frac_bits
= (a
->opc
& 1) ? (32 - a
->imm
) : (16 - a
->imm
);
2712 vd
= tcg_temp_new_i64();
2713 neon_load_reg64(vd
, a
->vd
);
2715 fpst
= get_fpstatus_ptr(false);
2716 shift
= tcg_const_i32(frac_bits
);
2718 /* Switch on op:U:sx bits */
2721 gen_helper_vfp_shtod(vd
, vd
, shift
, fpst
);
2724 gen_helper_vfp_sltod(vd
, vd
, shift
, fpst
);
2727 gen_helper_vfp_uhtod(vd
, vd
, shift
, fpst
);
2730 gen_helper_vfp_ultod(vd
, vd
, shift
, fpst
);
2733 gen_helper_vfp_toshd_round_to_zero(vd
, vd
, shift
, fpst
);
2736 gen_helper_vfp_tosld_round_to_zero(vd
, vd
, shift
, fpst
);
2739 gen_helper_vfp_touhd_round_to_zero(vd
, vd
, shift
, fpst
);
2742 gen_helper_vfp_tould_round_to_zero(vd
, vd
, shift
, fpst
);
2745 g_assert_not_reached();
2748 neon_store_reg64(vd
, a
->vd
);
2749 tcg_temp_free_i64(vd
);
2750 tcg_temp_free_i32(shift
);
2751 tcg_temp_free_ptr(fpst
);
2755 static bool trans_VCVT_sp_int(DisasContext
*s
, arg_VCVT_sp_int
*a
)
2760 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
2764 if (!vfp_access_check(s
)) {
2768 fpst
= get_fpstatus_ptr(false);
2769 vm
= tcg_temp_new_i32();
2770 neon_load_reg32(vm
, a
->vm
);
2774 gen_helper_vfp_tosizs(vm
, vm
, fpst
);
2776 gen_helper_vfp_tosis(vm
, vm
, fpst
);
2780 gen_helper_vfp_touizs(vm
, vm
, fpst
);
2782 gen_helper_vfp_touis(vm
, vm
, fpst
);
2785 neon_store_reg32(vm
, a
->vd
);
2786 tcg_temp_free_i32(vm
);
2787 tcg_temp_free_ptr(fpst
);
2791 static bool trans_VCVT_dp_int(DisasContext
*s
, arg_VCVT_dp_int
*a
)
2797 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2801 /* UNDEF accesses to D16-D31 if they don't exist. */
2802 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
2806 if (!vfp_access_check(s
)) {
2810 fpst
= get_fpstatus_ptr(false);
2811 vm
= tcg_temp_new_i64();
2812 vd
= tcg_temp_new_i32();
2813 neon_load_reg64(vm
, a
->vm
);
2817 gen_helper_vfp_tosizd(vd
, vm
, fpst
);
2819 gen_helper_vfp_tosid(vd
, vm
, fpst
);
2823 gen_helper_vfp_touizd(vd
, vm
, fpst
);
2825 gen_helper_vfp_touid(vd
, vm
, fpst
);
2828 neon_store_reg32(vd
, a
->vd
);
2829 tcg_temp_free_i32(vd
);
2830 tcg_temp_free_i64(vm
);
2831 tcg_temp_free_ptr(fpst
);
2836 * Decode VLLDM and VLSTM are nonstandard because:
2837 * * if there is no FPU then these insns must NOP in
2838 * Secure state and UNDEF in Nonsecure state
2839 * * if there is an FPU then these insns do not have
2840 * the usual behaviour that vfp_access_check() provides of
2841 * being controlled by CPACR/NSACR enable bits or the
2842 * lazy-stacking logic.
2844 static bool trans_VLLDM_VLSTM(DisasContext
*s
, arg_VLLDM_VLSTM
*a
)
2848 if (!arm_dc_feature(s
, ARM_FEATURE_M
) ||
2849 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
2852 /* If not secure, UNDEF. */
2853 if (!s
->v8m_secure
) {
2856 /* If no fpu, NOP. */
2857 if (!dc_isar_feature(aa32_vfp
, s
)) {
2861 fptr
= load_reg(s
, a
->rn
);
2863 gen_helper_v7m_vlldm(cpu_env
, fptr
);
2865 gen_helper_v7m_vlstm(cpu_env
, fptr
);
2867 tcg_temp_free_i32(fptr
);
2869 /* End the TB, because we have updated FP control bits */
2870 s
->base
.is_jmp
= DISAS_UPDATE
;