hw/riscv/opentitan.c

   1 /*
   2  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Provides a board compatible with the OpenTitan FPGA platform:
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/riscv/opentitan.h"
  23 #include "qapi/error.h"
  24 #include "hw/boards.h"
  25 #include "hw/misc/unimp.h"
  26 #include "hw/riscv/boot.h"
  27 #include "exec/address-spaces.h"
  28 #include "qemu/units.h"
  29 #include "sysemu/sysemu.h"
  30
  31 static const struct MemmapEntry {
  32     hwaddr base;
  33     hwaddr size;
  34 } ibex_memmap[] = {
  35     [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
  36     [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
  37     [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
  38     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
  39     [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
  40     [IBEX_DEV_SPI] =            {  0x40050000,  0x1000  },
  41     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
  42     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
  43     [IBEX_DEV_RV_TIMER] =       {  0x40100000,  0x1000  },
  44     [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
  45     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
  46     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
  47     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
  48     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
  49     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
  50     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
  51     [IBEX_DEV_USBDEV] =         {  0x40500000,  0x1000  },
  52     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
  53     [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
  54     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
  55     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
  56     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
  57     [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
  58     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
  59     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
  60     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
  61     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
  62     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
  63     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
  64     [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
  65 };
  66
  67 static void opentitan_board_init(MachineState *machine)
  68 {
  69     const struct MemmapEntry *memmap = ibex_memmap;
  70     OpenTitanState *s = g_new0(OpenTitanState, 1);
  71     MemoryRegion *sys_mem = get_system_memory();
  72     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  73
  74     /* Initialize SoC */
  75     object_initialize_child(OBJECT(machine), "soc", &s->soc,
  76                             TYPE_RISCV_IBEX_SOC);
  77     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  78
  79     memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
  80         memmap[IBEX_DEV_RAM].size, &error_fatal);
  81     memory_region_add_subregion(sys_mem,
  82         memmap[IBEX_DEV_RAM].base, main_mem);
  83
  84     if (machine->firmware) {
  85         riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
  86     }
  87
  88     if (machine->kernel_filename) {
  89         riscv_load_kernel(machine->kernel_filename,
  90                           memmap[IBEX_DEV_RAM].base, NULL);
  91     }
  92 }
  93
  94 static void opentitan_machine_init(MachineClass *mc)
  95 {
  96     mc->desc = "RISC-V Board compatible with OpenTitan";
  97     mc->init = opentitan_board_init;
  98     mc->max_cpus = 1;
  99     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 100 }
 101
 102 DEFINE_MACHINE("opentitan", opentitan_machine_init)
 103
 104 static void lowrisc_ibex_soc_init(Object *obj)
 105 {
 106     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
 107
 108     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 109
 110     object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
 111
 112     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 113 }
 114
 115 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 116 {
 117     const struct MemmapEntry *memmap = ibex_memmap;
 118     MachineState *ms = MACHINE(qdev_get_machine());
 119     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
 120     MemoryRegion *sys_mem = get_system_memory();
 121
 122     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 123                             &error_abort);
 124     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 125                             &error_abort);
 126     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
 127     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 128
 129     /* Boot ROM */
 130     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
 131                            memmap[IBEX_DEV_ROM].size, &error_fatal);
 132     memory_region_add_subregion(sys_mem,
 133         memmap[IBEX_DEV_ROM].base, &s->rom);
 134
 135     /* Flash memory */
 136     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
 137                            memmap[IBEX_DEV_FLASH].size, &error_fatal);
 138     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
 139                                 &s->flash_mem);
 140
 141     /* PLIC */
 142     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
 143         return;
 144     }
 145     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 146
 147     /* UART */
 148     qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
 149     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
 150         return;
 151     }
 152     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
 153     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 154                        0, qdev_get_gpio_in(DEVICE(&s->plic),
 155                        IBEX_UART_TX_WATERMARK_IRQ));
 156     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 157                        1, qdev_get_gpio_in(DEVICE(&s->plic),
 158                        IBEX_UART_RX_WATERMARK_IRQ));
 159     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 160                        2, qdev_get_gpio_in(DEVICE(&s->plic),
 161                        IBEX_UART_TX_EMPTY_IRQ));
 162     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 163                        3, qdev_get_gpio_in(DEVICE(&s->plic),
 164                        IBEX_UART_RX_OVERFLOW_IRQ));
 165
 166     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
 167         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
 168     create_unimplemented_device("riscv.lowrisc.ibex.spi",
 169         memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
 170     create_unimplemented_device("riscv.lowrisc.ibex.i2c",
 171         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
 172     create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
 173         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
 174     create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
 175         memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
 176     create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
 177         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
 178     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
 179         memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
 180     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
 181         memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
 182     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
 183         memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
 184     create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
 185         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
 186     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
 187         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
 188     create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
 189         memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
 190     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
 191         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
 192     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
 193         memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
 194     create_unimplemented_device("riscv.lowrisc.ibex.aes",
 195         memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
 196     create_unimplemented_device("riscv.lowrisc.ibex.hmac",
 197         memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
 198     create_unimplemented_device("riscv.lowrisc.ibex.kmac",
 199         memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
 200     create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
 201         memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
 202     create_unimplemented_device("riscv.lowrisc.ibex.csrng",
 203         memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
 204     create_unimplemented_device("riscv.lowrisc.ibex.entropy",
 205         memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
 206     create_unimplemented_device("riscv.lowrisc.ibex.edn0",
 207         memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
 208     create_unimplemented_device("riscv.lowrisc.ibex.edn1",
 209         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
 210     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
 211         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
 212     create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
 213         memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
 214     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
 215         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
 216 }
 217
 218 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 219 {
 220     DeviceClass *dc = DEVICE_CLASS(oc);
 221
 222     dc->realize = lowrisc_ibex_soc_realize;
 223     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 224     dc->user_creatable = false;
 225 }
 226
 227 static const TypeInfo lowrisc_ibex_soc_type_info = {
 228     .name = TYPE_RISCV_IBEX_SOC,
 229     .parent = TYPE_DEVICE,
 230     .instance_size = sizeof(LowRISCIbexSoCState),
 231     .instance_init = lowrisc_ibex_soc_init,
 232     .class_init = lowrisc_ibex_soc_class_init,
 233 };
 234
 235 static void lowrisc_ibex_soc_register_types(void)
 236 {
 237     type_register_static(&lowrisc_ibex_soc_type_info);
 238 }
 239
 240 type_init(lowrisc_ibex_soc_register_types)