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hw/sd: sd: Skip write protect groups check in sd_erase() for high capacity cards
[qemu/ar7.git] / hw / riscv / microchip_pfsoc.c
blobe952b49e8c513f4aaafc4e97a45d9d9582114a4e
1 /*
2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
10 *
11 * 0) CLINT (Core Level Interruptor)
12 * 1) PLIC (Platform Level Interrupt Controller)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it
16 * 5) SiFive Platform DMA (Direct Memory Access Controller)
17 * 6) GEM (Gigabit Ethernet MAC Controller)
18 * 7) DMC (DDR Memory Controller)
19 * 8) IOSCB modules
20 *
21 * This board currently generates devicetree dynamically that indicates at least
22 * two harts and up to five harts.
23 *
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms and conditions of the GNU General Public License,
26 * version 2 or later, as published by the Free Software Foundation.
27 *
28 * This program is distributed in the hope it will be useful, but WITHOUT
29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
31 * more details.
32 *
33 * You should have received a copy of the GNU General Public License along with
34 * this program. If not, see <http://www.gnu.org/licenses/>.
35 */
36
37 #include "qemu/osdep.h"
38 #include "qemu/error-report.h"
39 #include "qemu/log.h"
40 #include "qemu/units.h"
41 #include "qemu/cutils.h"
42 #include "qapi/error.h"
43 #include "hw/boards.h"
44 #include "hw/irq.h"
45 #include "hw/loader.h"
46 #include "hw/sysbus.h"
47 #include "chardev/char.h"
48 #include "hw/cpu/cluster.h"
49 #include "target/riscv/cpu.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/riscv/boot.h"
52 #include "hw/riscv/riscv_hart.h"
53 #include "hw/riscv/microchip_pfsoc.h"
54 #include "hw/intc/sifive_clint.h"
55 #include "hw/intc/sifive_plic.h"
56 #include "sysemu/sysemu.h"
57
58 /*
59 * The BIOS image used by this machine is called Hart Software Services (HSS).
60 * See https://github.com/polarfire-soc/hart-software-services
61 */
62 #define BIOS_FILENAME "hss.bin"
63 #define RESET_VECTOR 0x20220000
64
65 /* CLINT timebase frequency */
66 #define CLINT_TIMEBASE_FREQ 1000000
67
68 /* GEM version */
69 #define GEM_REVISION 0x0107010c
70
71 /*
72 * The complete description of the whole PolarFire SoC memory map is scattered
73 * in different documents. There are several places to look at for memory maps:
74 *
75 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
76 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
77 * https://www.microsemi.com/document-portal/doc_download/
78 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
79 * describes the whole picture of the PolarFire SoC memory map.
80 *
81 * 2 A zip file for PolarFire soC memory map, which can be downloaded from
82 * https://www.microsemi.com/document-portal/doc_download/
83 * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
84 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
85 * describes the complete integrated peripherals memory map
86 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
87 * describes the complete IOSCB modules memory maps
88 */
89 static const struct MemmapEntry {
90 hwaddr base;
91 hwaddr size;
92 } microchip_pfsoc_memmap[] = {
93 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
94 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
95 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
96 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
97 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
98 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
99 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
100 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
101 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
102 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
103 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
104 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
105 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
106 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
107 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
108 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
109 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
110 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
111 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
112 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
113 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
114 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
115 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
116 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
117 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
118 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
119 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
120 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
121 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
122 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
123 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
124 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
125 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
126 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
127 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
128 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
129 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
130 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
131 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
132 };
133
134 static void microchip_pfsoc_soc_instance_init(Object *obj)
135 {
136 MachineState *ms = MACHINE(qdev_get_machine());
137 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
138
139 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
140 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
141
142 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
143 TYPE_RISCV_HART_ARRAY);
144 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
145 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
146 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
147 TYPE_RISCV_CPU_SIFIVE_E51);
148 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
149
150 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
151 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
152
153 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
154 TYPE_RISCV_HART_ARRAY);
155 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
156 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
157 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
158 TYPE_RISCV_CPU_SIFIVE_U54);
159 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
160
161 object_initialize_child(obj, "dma-controller", &s->dma,
162 TYPE_SIFIVE_PDMA);
163
164 object_initialize_child(obj, "sysreg", &s->sysreg,
165 TYPE_MCHP_PFSOC_SYSREG);
166
167 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
168 TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
169 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
170 TYPE_MCHP_PFSOC_DDR_CFG);
171
172 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
173 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
174
175 object_initialize_child(obj, "sd-controller", &s->sdhci,
176 TYPE_CADENCE_SDHCI);
177
178 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
179 }
180
181 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
182 {
183 MachineState *ms = MACHINE(qdev_get_machine());
184 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
185 const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
186 MemoryRegion *system_memory = get_system_memory();
187 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
188 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
189 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
190 MemoryRegion *envm_data = g_new(MemoryRegion, 1);
191 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
192 char *plic_hart_config;
193 size_t plic_hart_config_len;
194 NICInfo *nd;
195 int i;
196
197 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
198 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
199 /*
200 * The cluster must be realized after the RISC-V hart array container,
201 * as the container's CPU object is only created on realize, and the
202 * CPU must exist and have been parented into the cluster before the
203 * cluster is realized.
204 */
205 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
206 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
207
208 /* Reserved Memory at address 0 */
209 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
210 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
211 memory_region_add_subregion(system_memory,
212 memmap[MICROCHIP_PFSOC_RSVD0].base,
213 rsvd0_mem);
214
215 /* E51 DTIM */
216 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
217 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
218 memory_region_add_subregion(system_memory,
219 memmap[MICROCHIP_PFSOC_E51_DTIM].base,
220 e51_dtim_mem);
221
222 /* Bus Error Units */
223 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
224 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
225 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
226 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
227 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
228 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
229 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
230 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
231 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
232 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
235 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
236 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
237 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
238
239 /* CLINT */
240 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
241 memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
242 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
243 CLINT_TIMEBASE_FREQ, false);
244
245 /* L2 cache controller */
246 create_unimplemented_device("microchip.pfsoc.l2cc",
247 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
248
249 /*
250 * Add L2-LIM at reset size.
251 * This should be reduced in size as the L2 Cache Controller WayEnable
252 * register is incremented. Unfortunately I don't see a nice (or any) way
253 * to handle reducing or blocking out the L2 LIM while still allowing it
254 * be re returned to all enabled after a reset. For the time being, just
255 * leave it enabled all the time. This won't break anything, but will be
256 * too generous to misbehaving guests.
257 */
258 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
259 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
260 memory_region_add_subregion(system_memory,
261 memmap[MICROCHIP_PFSOC_L2LIM].base,
262 l2lim_mem);
263
264 /* create PLIC hart topology configuration string */
265 plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
266 ms->smp.cpus;
267 plic_hart_config = g_malloc0(plic_hart_config_len);
268 for (i = 0; i < ms->smp.cpus; i++) {
269 if (i != 0) {
270 strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
271 plic_hart_config_len);
272 } else {
273 strncat(plic_hart_config, "M", plic_hart_config_len);
274 }
275 plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
276 }
277
278 /* PLIC */
279 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
280 plic_hart_config, 0,
281 MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
282 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
283 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
284 MICROCHIP_PFSOC_PLIC_PENDING_BASE,
285 MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
286 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
287 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
288 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
289 memmap[MICROCHIP_PFSOC_PLIC].size);
290 g_free(plic_hart_config);
291
292 /* DMA */
293 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
294 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
295 memmap[MICROCHIP_PFSOC_DMA].base);
296 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
298 qdev_get_gpio_in(DEVICE(s->plic),
299 MICROCHIP_PFSOC_DMA_IRQ0 + i));
300 }
301
302 /* SYSREG */
303 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
304 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
305 memmap[MICROCHIP_PFSOC_SYSREG].base);
306
307 /* MPUCFG */
308 create_unimplemented_device("microchip.pfsoc.mpucfg",
309 memmap[MICROCHIP_PFSOC_MPUCFG].base,
310 memmap[MICROCHIP_PFSOC_MPUCFG].size);
311
312 /* DDR SGMII PHY */
313 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
315 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
316
317 /* DDR CFG */
318 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
320 memmap[MICROCHIP_PFSOC_DDR_CFG].base);
321
322 /* SDHCI */
323 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
325 memmap[MICROCHIP_PFSOC_EMMC_SD].base);
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
327 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
328
329 /* MMUARTs */
330 s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
331 memmap[MICROCHIP_PFSOC_MMUART0].base,
332 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
333 serial_hd(0));
334 s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
335 memmap[MICROCHIP_PFSOC_MMUART1].base,
336 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
337 serial_hd(1));
338 s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
339 memmap[MICROCHIP_PFSOC_MMUART2].base,
340 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
341 serial_hd(2));
342 s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
343 memmap[MICROCHIP_PFSOC_MMUART3].base,
344 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
345 serial_hd(3));
346 s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
347 memmap[MICROCHIP_PFSOC_MMUART4].base,
348 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
349 serial_hd(4));
350
351 /* SPI */
352 create_unimplemented_device("microchip.pfsoc.spi0",
353 memmap[MICROCHIP_PFSOC_SPI0].base,
354 memmap[MICROCHIP_PFSOC_SPI0].size);
355 create_unimplemented_device("microchip.pfsoc.spi1",
356 memmap[MICROCHIP_PFSOC_SPI1].base,
357 memmap[MICROCHIP_PFSOC_SPI1].size);
358
359 /* I2C1 */
360 create_unimplemented_device("microchip.pfsoc.i2c1",
361 memmap[MICROCHIP_PFSOC_I2C1].base,
362 memmap[MICROCHIP_PFSOC_I2C1].size);
363
364 /* GEMs */
365
366 nd = &nd_table[0];
367 if (nd->used) {
368 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
369 qdev_set_nic_properties(DEVICE(&s->gem0), nd);
370 }
371 nd = &nd_table[1];
372 if (nd->used) {
373 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
374 qdev_set_nic_properties(DEVICE(&s->gem1), nd);
375 }
376
377 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
378 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
379 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
380 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
381 memmap[MICROCHIP_PFSOC_GEM0].base);
382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
383 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
384
385 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
386 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
387 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
389 memmap[MICROCHIP_PFSOC_GEM1].base);
390 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
391 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
392
393 /* GPIOs */
394 create_unimplemented_device("microchip.pfsoc.gpio0",
395 memmap[MICROCHIP_PFSOC_GPIO0].base,
396 memmap[MICROCHIP_PFSOC_GPIO0].size);
397 create_unimplemented_device("microchip.pfsoc.gpio1",
398 memmap[MICROCHIP_PFSOC_GPIO1].base,
399 memmap[MICROCHIP_PFSOC_GPIO1].size);
400 create_unimplemented_device("microchip.pfsoc.gpio2",
401 memmap[MICROCHIP_PFSOC_GPIO2].base,
402 memmap[MICROCHIP_PFSOC_GPIO2].size);
403
404 /* eNVM */
405 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
406 memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
407 &error_fatal);
408 memory_region_add_subregion(system_memory,
409 memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
410 envm_data);
411
412 /* IOSCB */
413 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
414 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
415 memmap[MICROCHIP_PFSOC_IOSCB].base);
416
417 /* QSPI Flash */
418 memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
419 "microchip.pfsoc.qspi_xip",
420 memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
421 &error_fatal);
422 memory_region_add_subregion(system_memory,
423 memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
424 qspi_xip_mem);
425 }
426
427 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
428 {
429 DeviceClass *dc = DEVICE_CLASS(oc);
430
431 dc->realize = microchip_pfsoc_soc_realize;
432 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
433 dc->user_creatable = false;
434 }
435
436 static const TypeInfo microchip_pfsoc_soc_type_info = {
437 .name = TYPE_MICROCHIP_PFSOC,
438 .parent = TYPE_DEVICE,
439 .instance_size = sizeof(MicrochipPFSoCState),
440 .instance_init = microchip_pfsoc_soc_instance_init,
441 .class_init = microchip_pfsoc_soc_class_init,
442 };
443
444 static void microchip_pfsoc_soc_register_types(void)
445 {
446 type_register_static(&microchip_pfsoc_soc_type_info);
447 }
448
449 type_init(microchip_pfsoc_soc_register_types)
450
451 static void microchip_icicle_kit_machine_init(MachineState *machine)
452 {
453 MachineClass *mc = MACHINE_GET_CLASS(machine);
454 const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
455 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
456 MemoryRegion *system_memory = get_system_memory();
457 MemoryRegion *mem_low = g_new(MemoryRegion, 1);
458 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
459 MemoryRegion *mem_high = g_new(MemoryRegion, 1);
460 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
461 uint64_t mem_high_size;
462 DriveInfo *dinfo = drive_get_next(IF_SD);
463
464 /* Sanity check on RAM size */
465 if (machine->ram_size < mc->default_ram_size) {
466 char *sz = size_to_str(mc->default_ram_size);
467 error_report("Invalid RAM size, should be bigger than %s", sz);
468 g_free(sz);
469 exit(EXIT_FAILURE);
470 }
471
472 /* Initialize SoC */
473 object_initialize_child(OBJECT(machine), "soc", &s->soc,
474 TYPE_MICROCHIP_PFSOC);
475 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
476
477 /* Register RAM */
478 memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
479 memmap[MICROCHIP_PFSOC_DRAM_LO].size,
480 &error_fatal);
481 memory_region_init_alias(mem_low_alias, NULL,
482 "microchip.icicle.kit.ram_low.alias",
483 mem_low, 0,
484 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
485 memory_region_add_subregion(system_memory,
486 memmap[MICROCHIP_PFSOC_DRAM_LO].base,
487 mem_low);
488 memory_region_add_subregion(system_memory,
489 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
490 mem_low_alias);
491
492 mem_high_size = machine->ram_size - 1 * GiB;
493
494 memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
495 mem_high_size, &error_fatal);
496 memory_region_init_alias(mem_high_alias, NULL,
497 "microchip.icicle.kit.ram_high.alias",
498 mem_high, 0, mem_high_size);
499 memory_region_add_subregion(system_memory,
500 memmap[MICROCHIP_PFSOC_DRAM_HI].base,
501 mem_high);
502 memory_region_add_subregion(system_memory,
503 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
504 mem_high_alias);
505
506 /* Load the firmware */
507 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
508
509 /* Attach an SD card */
510 if (dinfo) {
511 CadenceSDHCIState *sdhci = &(s->soc.sdhci);
512 DeviceState *card = qdev_new(TYPE_SD_CARD);
513
514 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
515 &error_fatal);
516 qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
517 }
518 }
519
520 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
521 {
522 MachineClass *mc = MACHINE_CLASS(oc);
523
524 mc->desc = "Microchip PolarFire SoC Icicle Kit";
525 mc->init = microchip_icicle_kit_machine_init;
526 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
527 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
528 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
529 mc->default_cpus = mc->min_cpus;
530
531 /*
532 * Map 513 MiB high memory, the mimimum required high memory size, because
533 * HSS will do memory test against the high memory address range regardless
534 * of physical memory installed.
535 *
536 * See memory_tests() in mss_ddr.c in the HSS source code.
537 */
538 mc->default_ram_size = 1537 * MiB;
539 }
540
541 static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
542 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
543 .parent = TYPE_MACHINE,
544 .class_init = microchip_icicle_kit_machine_class_init,
545 .instance_size = sizeof(MicrochipIcicleKitState),
546 };
547
548 static void microchip_icicle_kit_machine_init_register_types(void)
549 {
550 type_register_static(&microchip_icicle_kit_machine_typeinfo);
551 }
552
553 type_init(microchip_icicle_kit_machine_init_register_types)
AR7 emulation for QEMU