4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
26 #include "exec/exec-all.h"
29 static void alpha_cpu_set_pc(CPUState
*cs
, vaddr value
)
31 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
36 static bool alpha_cpu_has_work(CPUState
*cs
)
38 /* Here we are checking to see if the CPU should wake up from HALT.
39 We will have gotten into this state only for WTINT from PALmode. */
40 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
41 asleep even if (some) interrupts have been asserted. For now,
42 assume that if a CPU really wants to stay asleep, it will mask
43 interrupts at the chipset level, which will prevent these bits
44 from being set in the first place. */
45 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_MCHK
);
51 static void alpha_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
53 info
->mach
= bfd_mach_alpha_ev6
;
54 info
->print_insn
= print_insn_alpha
;
57 static void alpha_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
59 CPUState
*cs
= CPU(dev
);
60 AlphaCPUClass
*acc
= ALPHA_CPU_GET_CLASS(dev
);
61 Error
*local_err
= NULL
;
63 cpu_exec_realizefn(cs
, &local_err
);
64 if (local_err
!= NULL
) {
65 error_propagate(errp
, local_err
);
71 acc
->parent_realize(dev
, errp
);
74 static void alpha_cpu_list_entry(gpointer data
, gpointer user_data
)
76 ObjectClass
*oc
= data
;
78 qemu_printf(" %s\n", object_class_get_name(oc
));
81 void alpha_cpu_list(void)
85 list
= object_class_get_list_sorted(TYPE_ALPHA_CPU
, false);
86 qemu_printf("Available CPUs:\n");
87 g_slist_foreach(list
, alpha_cpu_list_entry
, NULL
);
92 typedef struct AlphaCPUAlias
{
97 static const AlphaCPUAlias alpha_cpu_aliases
[] = {
98 { "21064", ALPHA_CPU_TYPE_NAME("ev4") },
99 { "21164", ALPHA_CPU_TYPE_NAME("ev5") },
100 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") },
101 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
102 { "21264", ALPHA_CPU_TYPE_NAME("ev6") },
103 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") },
106 static ObjectClass
*alpha_cpu_class_by_name(const char *cpu_model
)
112 oc
= object_class_by_name(cpu_model
);
113 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_ALPHA_CPU
) != NULL
&&
114 !object_class_is_abstract(oc
)) {
118 for (i
= 0; i
< ARRAY_SIZE(alpha_cpu_aliases
); i
++) {
119 if (strcmp(cpu_model
, alpha_cpu_aliases
[i
].alias
) == 0) {
120 oc
= object_class_by_name(alpha_cpu_aliases
[i
].typename
);
121 assert(oc
!= NULL
&& !object_class_is_abstract(oc
));
126 typename
= g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model
);
127 oc
= object_class_by_name(typename
);
129 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
133 /* TODO: remove match everything nonsense */
134 /* Default to ev67; no reason not to emulate insns by default. */
136 oc
= object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
142 static void ev4_cpu_initfn(Object
*obj
)
144 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
145 CPUAlphaState
*env
= &cpu
->env
;
147 env
->implver
= IMPLVER_2106x
;
150 static void ev5_cpu_initfn(Object
*obj
)
152 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
153 CPUAlphaState
*env
= &cpu
->env
;
155 env
->implver
= IMPLVER_21164
;
158 static void ev56_cpu_initfn(Object
*obj
)
160 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
161 CPUAlphaState
*env
= &cpu
->env
;
163 env
->amask
|= AMASK_BWX
;
166 static void pca56_cpu_initfn(Object
*obj
)
168 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
169 CPUAlphaState
*env
= &cpu
->env
;
171 env
->amask
|= AMASK_MVI
;
174 static void ev6_cpu_initfn(Object
*obj
)
176 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
177 CPUAlphaState
*env
= &cpu
->env
;
179 env
->implver
= IMPLVER_21264
;
180 env
->amask
= AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
;
183 static void ev67_cpu_initfn(Object
*obj
)
185 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
186 CPUAlphaState
*env
= &cpu
->env
;
188 env
->amask
|= AMASK_CIX
| AMASK_PREFETCH
;
191 static void alpha_cpu_initfn(Object
*obj
)
193 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
194 CPUAlphaState
*env
= &cpu
->env
;
196 cpu_set_cpustate_pointers(cpu
);
199 #if defined(CONFIG_USER_ONLY)
200 env
->flags
= ENV_FLAG_PS_USER
| ENV_FLAG_FEN
;
201 cpu_alpha_store_fpcr(env
, (uint64_t)(FPCR_INVD
| FPCR_DZED
| FPCR_OVFD
202 | FPCR_UNFD
| FPCR_INED
| FPCR_DNOD
203 | FPCR_DYN_NORMAL
) << 32);
205 env
->flags
= ENV_FLAG_PAL_MODE
| ENV_FLAG_FEN
;
209 static void alpha_cpu_class_init(ObjectClass
*oc
, void *data
)
211 DeviceClass
*dc
= DEVICE_CLASS(oc
);
212 CPUClass
*cc
= CPU_CLASS(oc
);
213 AlphaCPUClass
*acc
= ALPHA_CPU_CLASS(oc
);
215 device_class_set_parent_realize(dc
, alpha_cpu_realizefn
,
216 &acc
->parent_realize
);
218 cc
->class_by_name
= alpha_cpu_class_by_name
;
219 cc
->has_work
= alpha_cpu_has_work
;
220 cc
->do_interrupt
= alpha_cpu_do_interrupt
;
221 cc
->cpu_exec_interrupt
= alpha_cpu_exec_interrupt
;
222 cc
->dump_state
= alpha_cpu_dump_state
;
223 cc
->set_pc
= alpha_cpu_set_pc
;
224 cc
->gdb_read_register
= alpha_cpu_gdb_read_register
;
225 cc
->gdb_write_register
= alpha_cpu_gdb_write_register
;
226 cc
->tlb_fill
= alpha_cpu_tlb_fill
;
227 #ifndef CONFIG_USER_ONLY
228 cc
->do_transaction_failed
= alpha_cpu_do_transaction_failed
;
229 cc
->do_unaligned_access
= alpha_cpu_do_unaligned_access
;
230 cc
->get_phys_page_debug
= alpha_cpu_get_phys_page_debug
;
231 dc
->vmsd
= &vmstate_alpha_cpu
;
233 cc
->disas_set_info
= alpha_cpu_disas_set_info
;
234 cc
->tcg_initialize
= alpha_translate_init
;
236 cc
->gdb_num_core_regs
= 67;
239 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
241 .parent = base_type, \
242 .instance_init = initfn, \
243 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \
246 static const TypeInfo alpha_cpu_type_infos
[] = {
248 .name
= TYPE_ALPHA_CPU
,
250 .instance_size
= sizeof(AlphaCPU
),
251 .instance_init
= alpha_cpu_initfn
,
253 .class_size
= sizeof(AlphaCPUClass
),
254 .class_init
= alpha_cpu_class_init
,
256 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev4", ev4_cpu_initfn
),
257 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev5", ev5_cpu_initfn
),
258 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn
),
259 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
261 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev6", ev6_cpu_initfn
),
262 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn
),
263 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL
),
266 DEFINE_TYPES(alpha_cpu_type_infos
)