2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/sifive_plic.h"
33 #include "hw/riscv/sifive_clint.h"
34 #include "hw/riscv/sifive_test.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "chardev/char.h"
38 #include "sysemu/arch_init.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/sysemu.h"
41 #include "exec/address-spaces.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci-host/gpex.h"
47 #if defined(TARGET_RISCV32)
48 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
50 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
53 static const struct MemmapEntry
{
57 [VIRT_DEBUG
] = { 0x0, 0x100 },
58 [VIRT_MROM
] = { 0x1000, 0x11000 },
59 [VIRT_TEST
] = { 0x100000, 0x1000 },
60 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
61 [VIRT_PLIC
] = { 0xc000000, 0x4000000 },
62 [VIRT_UART0
] = { 0x10000000, 0x100 },
63 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
64 [VIRT_DRAM
] = { 0x80000000, 0x0 },
65 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
66 [VIRT_PCIE_PIO
] = { 0x03000000, 0x00010000 },
67 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
70 static void create_pcie_irq_map(void *fdt
, char *nodename
,
71 uint32_t plic_phandle
)
75 full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
* FDT_INT_MAP_WIDTH
] = {};
76 uint32_t *irq_map
= full_irq_map
;
78 /* This code creates a standard swizzle of interrupts such that
79 * each device's first interrupt is based on it's PCI_SLOT number.
80 * (See pci_swizzle_map_irq_fn())
82 * We only need one entry per interrupt in the table (not one per
83 * possible slot) seeing the interrupt-map-mask will allow the table
84 * to wrap to any number of devices.
86 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
87 int devfn
= dev
* 0x8;
89 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
90 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
93 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
95 i
+= FDT_PCI_ADDR_CELLS
;
96 irq_map
[i
] = cpu_to_be32(pin
+ 1);
98 i
+= FDT_PCI_INT_CELLS
;
99 irq_map
[i
++] = cpu_to_be32(plic_phandle
);
101 i
+= FDT_PLIC_ADDR_CELLS
;
102 irq_map
[i
] = cpu_to_be32(irq_nr
);
104 irq_map
+= FDT_INT_MAP_WIDTH
;
108 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map",
109 full_irq_map
, sizeof(full_irq_map
));
111 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
115 static void *create_fdt(RISCVVirtState
*s
, const struct MemmapEntry
*memmap
,
116 uint64_t mem_size
, const char *cmdline
)
122 uint32_t plic_phandle
, phandle
= 1;
125 fdt
= s
->fdt
= create_device_tree(&s
->fdt_size
);
127 error_report("create_device_tree() failed");
131 qemu_fdt_setprop_string(fdt
, "/", "model", "riscv-virtio,qemu");
132 qemu_fdt_setprop_string(fdt
, "/", "compatible", "riscv-virtio");
133 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
134 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
136 qemu_fdt_add_subnode(fdt
, "/soc");
137 qemu_fdt_setprop(fdt
, "/soc", "ranges", NULL
, 0);
138 qemu_fdt_setprop_string(fdt
, "/soc", "compatible", "simple-bus");
139 qemu_fdt_setprop_cell(fdt
, "/soc", "#size-cells", 0x2);
140 qemu_fdt_setprop_cell(fdt
, "/soc", "#address-cells", 0x2);
142 nodename
= g_strdup_printf("/memory@%lx",
143 (long)memmap
[VIRT_DRAM
].base
);
144 qemu_fdt_add_subnode(fdt
, nodename
);
145 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
146 memmap
[VIRT_DRAM
].base
>> 32, memmap
[VIRT_DRAM
].base
,
147 mem_size
>> 32, mem_size
);
148 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
151 qemu_fdt_add_subnode(fdt
, "/cpus");
152 qemu_fdt_setprop_cell(fdt
, "/cpus", "timebase-frequency",
153 SIFIVE_CLINT_TIMEBASE_FREQ
);
154 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0x0);
155 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 0x1);
157 for (cpu
= s
->soc
.num_harts
- 1; cpu
>= 0; cpu
--) {
158 int cpu_phandle
= phandle
++;
160 nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
161 char *intc
= g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
162 char *isa
= riscv_isa_string(&s
->soc
.harts
[cpu
]);
163 qemu_fdt_add_subnode(fdt
, nodename
);
164 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency",
166 qemu_fdt_setprop_string(fdt
, nodename
, "mmu-type", "riscv,sv48");
167 qemu_fdt_setprop_string(fdt
, nodename
, "riscv,isa", isa
);
168 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv");
169 qemu_fdt_setprop_string(fdt
, nodename
, "status", "okay");
170 qemu_fdt_setprop_cell(fdt
, nodename
, "reg", cpu
);
171 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "cpu");
172 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", cpu_phandle
);
173 qemu_fdt_setprop_cell(fdt
, nodename
, "linux,phandle", cpu_phandle
);
174 intc_phandle
= phandle
++;
175 qemu_fdt_add_subnode(fdt
, intc
);
176 qemu_fdt_setprop_cell(fdt
, intc
, "phandle", intc_phandle
);
177 qemu_fdt_setprop_cell(fdt
, intc
, "linux,phandle", intc_phandle
);
178 qemu_fdt_setprop_string(fdt
, intc
, "compatible", "riscv,cpu-intc");
179 qemu_fdt_setprop(fdt
, intc
, "interrupt-controller", NULL
, 0);
180 qemu_fdt_setprop_cell(fdt
, intc
, "#interrupt-cells", 1);
186 /* Add cpu-topology node */
187 qemu_fdt_add_subnode(fdt
, "/cpus/cpu-map");
188 qemu_fdt_add_subnode(fdt
, "/cpus/cpu-map/cluster0");
189 for (cpu
= s
->soc
.num_harts
- 1; cpu
>= 0; cpu
--) {
190 char *core_nodename
= g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
192 char *cpu_nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
193 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, cpu_nodename
);
194 qemu_fdt_add_subnode(fdt
, core_nodename
);
195 qemu_fdt_setprop_cell(fdt
, core_nodename
, "cpu", intc_phandle
);
196 g_free(core_nodename
);
197 g_free(cpu_nodename
);
200 cells
= g_new0(uint32_t, s
->soc
.num_harts
* 4);
201 for (cpu
= 0; cpu
< s
->soc
.num_harts
; cpu
++) {
203 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
204 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
205 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
206 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
207 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
208 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
211 nodename
= g_strdup_printf("/soc/clint@%lx",
212 (long)memmap
[VIRT_CLINT
].base
);
213 qemu_fdt_add_subnode(fdt
, nodename
);
214 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,clint0");
215 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
216 0x0, memmap
[VIRT_CLINT
].base
,
217 0x0, memmap
[VIRT_CLINT
].size
);
218 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
219 cells
, s
->soc
.num_harts
* sizeof(uint32_t) * 4);
223 plic_phandle
= phandle
++;
224 cells
= g_new0(uint32_t, s
->soc
.num_harts
* 4);
225 for (cpu
= 0; cpu
< s
->soc
.num_harts
; cpu
++) {
227 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
228 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
229 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
230 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
231 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
232 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
235 nodename
= g_strdup_printf("/soc/interrupt-controller@%lx",
236 (long)memmap
[VIRT_PLIC
].base
);
237 qemu_fdt_add_subnode(fdt
, nodename
);
238 qemu_fdt_setprop_cells(fdt
, nodename
, "#address-cells",
239 FDT_PLIC_ADDR_CELLS
);
240 qemu_fdt_setprop_cell(fdt
, nodename
, "#interrupt-cells",
242 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,plic0");
243 qemu_fdt_setprop(fdt
, nodename
, "interrupt-controller", NULL
, 0);
244 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
245 cells
, s
->soc
.num_harts
* sizeof(uint32_t) * 4);
246 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
247 0x0, memmap
[VIRT_PLIC
].base
,
248 0x0, memmap
[VIRT_PLIC
].size
);
249 qemu_fdt_setprop_string(fdt
, nodename
, "reg-names", "control");
250 qemu_fdt_setprop_cell(fdt
, nodename
, "riscv,max-priority", 7);
251 qemu_fdt_setprop_cell(fdt
, nodename
, "riscv,ndev", VIRTIO_NDEV
);
252 qemu_fdt_setprop_cells(fdt
, nodename
, "phandle", plic_phandle
);
253 qemu_fdt_setprop_cells(fdt
, nodename
, "linux,phandle", plic_phandle
);
254 plic_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
258 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
259 nodename
= g_strdup_printf("/virtio_mmio@%lx",
260 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
261 qemu_fdt_add_subnode(fdt
, nodename
);
262 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "virtio,mmio");
263 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
264 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
265 0x0, memmap
[VIRT_VIRTIO
].size
);
266 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-parent", plic_phandle
);
267 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupts", VIRTIO_IRQ
+ i
);
271 nodename
= g_strdup_printf("/soc/pci@%lx",
272 (long) memmap
[VIRT_PCIE_ECAM
].base
);
273 qemu_fdt_add_subnode(fdt
, nodename
);
274 qemu_fdt_setprop_cells(fdt
, nodename
, "#address-cells",
276 qemu_fdt_setprop_cells(fdt
, nodename
, "#interrupt-cells",
278 qemu_fdt_setprop_cells(fdt
, nodename
, "#size-cells", 0x2);
279 qemu_fdt_setprop_string(fdt
, nodename
, "compatible",
280 "pci-host-ecam-generic");
281 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "pci");
282 qemu_fdt_setprop_cell(fdt
, nodename
, "linux,pci-domain", 0);
283 qemu_fdt_setprop_cells(fdt
, nodename
, "bus-range", 0,
284 memmap
[VIRT_PCIE_ECAM
].size
/
285 PCIE_MMCFG_SIZE_MIN
- 1);
286 qemu_fdt_setprop(fdt
, nodename
, "dma-coherent", NULL
, 0);
287 qemu_fdt_setprop_cells(fdt
, nodename
, "reg", 0, memmap
[VIRT_PCIE_ECAM
].base
,
288 0, memmap
[VIRT_PCIE_ECAM
].size
);
289 qemu_fdt_setprop_sized_cells(fdt
, nodename
, "ranges",
290 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
291 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
292 1, FDT_PCI_RANGE_MMIO
,
293 2, memmap
[VIRT_PCIE_MMIO
].base
,
294 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
);
295 create_pcie_irq_map(fdt
, nodename
, plic_phandle
);
298 nodename
= g_strdup_printf("/test@%lx",
299 (long)memmap
[VIRT_TEST
].base
);
300 qemu_fdt_add_subnode(fdt
, nodename
);
301 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "sifive,test0");
302 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
303 0x0, memmap
[VIRT_TEST
].base
,
304 0x0, memmap
[VIRT_TEST
].size
);
307 nodename
= g_strdup_printf("/uart@%lx",
308 (long)memmap
[VIRT_UART0
].base
);
309 qemu_fdt_add_subnode(fdt
, nodename
);
310 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "ns16550a");
311 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
312 0x0, memmap
[VIRT_UART0
].base
,
313 0x0, memmap
[VIRT_UART0
].size
);
314 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency", 3686400);
315 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-parent", plic_phandle
);
316 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupts", UART0_IRQ
);
318 qemu_fdt_add_subnode(fdt
, "/chosen");
319 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", nodename
);
321 qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
329 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
330 hwaddr ecam_base
, hwaddr ecam_size
,
331 hwaddr mmio_base
, hwaddr mmio_size
,
333 DeviceState
*plic
, bool link_up
)
336 MemoryRegion
*ecam_alias
, *ecam_reg
;
337 MemoryRegion
*mmio_alias
, *mmio_reg
;
341 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
343 qdev_init_nofail(dev
);
345 ecam_alias
= g_new0(MemoryRegion
, 1);
346 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
347 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
348 ecam_reg
, 0, ecam_size
);
349 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
351 mmio_alias
= g_new0(MemoryRegion
, 1);
352 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
353 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
354 mmio_reg
, mmio_base
, mmio_size
);
355 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
357 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
359 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
360 irq
= qdev_get_gpio_in(plic
, PCIE_IRQ
+ i
);
362 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
363 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
369 static void riscv_virt_board_init(MachineState
*machine
)
371 const struct MemmapEntry
*memmap
= virt_memmap
;
373 RISCVVirtState
*s
= g_new0(RISCVVirtState
, 1);
374 MemoryRegion
*system_memory
= get_system_memory();
375 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
376 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
377 char *plic_hart_config
;
378 size_t plic_hart_config_len
;
380 unsigned int smp_cpus
= machine
->smp
.cpus
;
384 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
, sizeof(s
->soc
),
385 TYPE_RISCV_HART_ARRAY
, &error_abort
, NULL
);
386 object_property_set_str(OBJECT(&s
->soc
), machine
->cpu_type
, "cpu-type",
388 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
390 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
393 /* register system main memory (actual RAM) */
394 memory_region_init_ram(main_mem
, NULL
, "riscv_virt_board.ram",
395 machine
->ram_size
, &error_fatal
);
396 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
399 /* create device tree */
400 fdt
= create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
403 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
404 memmap
[VIRT_MROM
].size
, &error_fatal
);
405 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
408 riscv_find_and_load_firmware(machine
, BIOS_FILENAME
,
409 memmap
[VIRT_DRAM
].base
);
411 if (machine
->kernel_filename
) {
412 uint64_t kernel_entry
= riscv_load_kernel(machine
->kernel_filename
);
414 if (machine
->initrd_filename
) {
416 hwaddr end
= riscv_load_initrd(machine
->initrd_filename
,
417 machine
->ram_size
, kernel_entry
,
419 qemu_fdt_setprop_cell(fdt
, "/chosen",
420 "linux,initrd-start", start
);
421 qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
427 uint32_t reset_vec
[8] = {
428 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
429 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
430 0xf1402573, /* csrr a0, mhartid */
431 #if defined(TARGET_RISCV32)
432 0x0182a283, /* lw t0, 24(t0) */
433 #elif defined(TARGET_RISCV64)
434 0x0182b283, /* ld t0, 24(t0) */
436 0x00028067, /* jr t0 */
438 memmap
[VIRT_DRAM
].base
, /* start: .dword memmap[VIRT_DRAM].base */
443 /* copy in the reset vector in little_endian byte order */
444 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
445 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
447 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
448 memmap
[VIRT_MROM
].base
, &address_space_memory
);
450 /* copy in the device tree */
451 if (fdt_pack(s
->fdt
) || fdt_totalsize(s
->fdt
) >
452 memmap
[VIRT_MROM
].size
- sizeof(reset_vec
)) {
453 error_report("not enough space to store device-tree");
456 qemu_fdt_dumpdtb(s
->fdt
, fdt_totalsize(s
->fdt
));
457 rom_add_blob_fixed_as("mrom.fdt", s
->fdt
, fdt_totalsize(s
->fdt
),
458 memmap
[VIRT_MROM
].base
+ sizeof(reset_vec
),
459 &address_space_memory
);
461 /* create PLIC hart topology configuration string */
462 plic_hart_config_len
= (strlen(VIRT_PLIC_HART_CONFIG
) + 1) * smp_cpus
;
463 plic_hart_config
= g_malloc0(plic_hart_config_len
);
464 for (i
= 0; i
< smp_cpus
; i
++) {
466 strncat(plic_hart_config
, ",", plic_hart_config_len
);
468 strncat(plic_hart_config
, VIRT_PLIC_HART_CONFIG
, plic_hart_config_len
);
469 plic_hart_config_len
-= (strlen(VIRT_PLIC_HART_CONFIG
) + 1);
473 s
->plic
= sifive_plic_create(memmap
[VIRT_PLIC
].base
,
475 VIRT_PLIC_NUM_SOURCES
,
476 VIRT_PLIC_NUM_PRIORITIES
,
477 VIRT_PLIC_PRIORITY_BASE
,
478 VIRT_PLIC_PENDING_BASE
,
479 VIRT_PLIC_ENABLE_BASE
,
480 VIRT_PLIC_ENABLE_STRIDE
,
481 VIRT_PLIC_CONTEXT_BASE
,
482 VIRT_PLIC_CONTEXT_STRIDE
,
483 memmap
[VIRT_PLIC
].size
);
484 sifive_clint_create(memmap
[VIRT_CLINT
].base
,
485 memmap
[VIRT_CLINT
].size
, smp_cpus
,
486 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
);
487 sifive_test_create(memmap
[VIRT_TEST
].base
);
489 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
490 sysbus_create_simple("virtio-mmio",
491 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
492 qdev_get_gpio_in(DEVICE(s
->plic
), VIRTIO_IRQ
+ i
));
495 gpex_pcie_init(system_memory
,
496 memmap
[VIRT_PCIE_ECAM
].base
,
497 memmap
[VIRT_PCIE_ECAM
].size
,
498 memmap
[VIRT_PCIE_MMIO
].base
,
499 memmap
[VIRT_PCIE_MMIO
].size
,
500 memmap
[VIRT_PCIE_PIO
].base
,
501 DEVICE(s
->plic
), true);
503 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
504 0, qdev_get_gpio_in(DEVICE(s
->plic
), UART0_IRQ
), 399193,
505 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
507 g_free(plic_hart_config
);
510 static void riscv_virt_board_machine_init(MachineClass
*mc
)
512 mc
->desc
= "RISC-V VirtIO Board (Privileged ISA v1.10)";
513 mc
->init
= riscv_virt_board_init
;
514 mc
->max_cpus
= 8; /* hardcoded limit in BBL */
515 mc
->default_cpu_type
= VIRT_CPU
;
518 DEFINE_MACHINE("virt", riscv_virt_board_machine_init
)