?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
docker.py: add --run-as-current-user
[qemu/ar7.git] / hw / i386 / pc.c
blobc14ed86439fa38ece5e3c08278c93d1238fafc13
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/apic.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
35 #include "hw/ide.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "migration/vmstate.h"
44 #include "multiboot.h"
45 #include "hw/timer/mc146818rtc.h"
46 #include "hw/dma/i8257.h"
47 #include "hw/timer/i8254.h"
48 #include "hw/input/i8042.h"
49 #include "hw/irq.h"
50 #include "hw/audio/pcspk.h"
51 #include "hw/pci/msi.h"
52 #include "hw/sysbus.h"
53 #include "sysemu/sysemu.h"
54 #include "sysemu/tcg.h"
55 #include "sysemu/numa.h"
56 #include "sysemu/kvm.h"
57 #include "sysemu/qtest.h"
58 #include "sysemu/reset.h"
59 #include "sysemu/runstate.h"
60 #include "kvm_i386.h"
61 #include "hw/xen/xen.h"
62 #include "hw/xen/start_info.h"
63 #include "ui/qemu-spice.h"
64 #include "exec/memory.h"
65 #include "exec/address-spaces.h"
66 #include "sysemu/arch_init.h"
67 #include "qemu/bitmap.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "qemu/option.h"
71 #include "hw/acpi/acpi.h"
72 #include "hw/acpi/cpu_hotplug.h"
73 #include "hw/boards.h"
74 #include "acpi-build.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "qapi/error.h"
77 #include "qapi/qapi-visit-common.h"
78 #include "qapi/visitor.h"
79 #include "hw/core/cpu.h"
80 #include "hw/nmi.h"
81 #include "hw/usb.h"
82 #include "hw/i386/intel_iommu.h"
83 #include "hw/net/ne2000-isa.h"
84 #include "standard-headers/asm-x86/bootparam.h"
85 #include "hw/virtio/virtio-pmem-pci.h"
86 #include "hw/mem/memory-device.h"
87 #include "sysemu/replay.h"
88 #include "qapi/qmp/qerror.h"
89 #include "config-devices.h"
90
91 /* debug PC/ISA interrupts */
92 //#define DEBUG_IRQ
93
94 #ifdef DEBUG_IRQ
95 #define DPRINTF(fmt, ...) \
96 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
97 #else
98 #define DPRINTF(fmt, ...)
99 #endif
100
101 #define E820_NR_ENTRIES 16
102
103 struct e820_entry {
104 uint64_t address;
105 uint64_t length;
106 uint32_t type;
107 } QEMU_PACKED __attribute((__aligned__(4)));
108
109 struct e820_table {
110 uint32_t count;
111 struct e820_entry entry[E820_NR_ENTRIES];
112 } QEMU_PACKED __attribute((__aligned__(4)));
113
114 static struct e820_table e820_reserve;
115 static struct e820_entry *e820_table;
116 static unsigned e820_entries;
117 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
118
119 /* Physical Address of PVH entry point read from kernel ELF NOTE */
120 static size_t pvh_start_addr;
121
122 GlobalProperty pc_compat_4_1[] = {};
123 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
124
125 GlobalProperty pc_compat_4_0[] = {};
126 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
127
128 GlobalProperty pc_compat_3_1[] = {
129 { "intel-iommu", "dma-drain", "off" },
130 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
131 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
132 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
133 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
134 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
135 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
136 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
137 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
138 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
139 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
140 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
141 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
142 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
143 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
144 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
146 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
147 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
148 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
149 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
150 };
151 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
152
153 GlobalProperty pc_compat_3_0[] = {
154 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
155 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
156 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
157 };
158 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
159
160 GlobalProperty pc_compat_2_12[] = {
161 { TYPE_X86_CPU, "legacy-cache", "on" },
162 { TYPE_X86_CPU, "topoext", "off" },
163 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
164 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
165 };
166 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
167
168 GlobalProperty pc_compat_2_11[] = {
169 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
170 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
171 };
172 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
173
174 GlobalProperty pc_compat_2_10[] = {
175 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
176 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
177 { "q35-pcihost", "x-pci-hole64-fix", "off" },
178 };
179 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
180
181 GlobalProperty pc_compat_2_9[] = {
182 { "mch", "extended-tseg-mbytes", "0" },
183 };
184 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
185
186 GlobalProperty pc_compat_2_8[] = {
187 { TYPE_X86_CPU, "tcg-cpuid", "off" },
188 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
189 { "ICH9-LPC", "x-smi-broadcast", "off" },
190 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
191 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
192 };
193 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
194
195 GlobalProperty pc_compat_2_7[] = {
196 { TYPE_X86_CPU, "l3-cache", "off" },
197 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
198 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
199 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
200 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
201 { "isa-pcspk", "migrate", "off" },
202 };
203 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
204
205 GlobalProperty pc_compat_2_6[] = {
206 { TYPE_X86_CPU, "cpuid-0xb", "off" },
207 { "vmxnet3", "romfile", "" },
208 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
209 { "apic-common", "legacy-instance-id", "on", }
210 };
211 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
212
213 GlobalProperty pc_compat_2_5[] = {};
214 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
215
216 GlobalProperty pc_compat_2_4[] = {
217 PC_CPU_MODEL_IDS("2.4.0")
218 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
219 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
220 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
221 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
222 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
223 { TYPE_X86_CPU, "check", "off" },
224 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
225 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
226 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
227 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
228 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
229 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
230 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
231 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
232 };
233 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
234
235 GlobalProperty pc_compat_2_3[] = {
236 PC_CPU_MODEL_IDS("2.3.0")
237 { TYPE_X86_CPU, "arat", "off" },
238 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
239 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
240 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
241 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
242 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
243 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
244 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
245 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
247 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
249 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
250 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
251 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
252 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
253 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
254 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
255 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
256 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
257 };
258 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
259
260 GlobalProperty pc_compat_2_2[] = {
261 PC_CPU_MODEL_IDS("2.2.0")
262 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
263 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
265 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
268 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
269 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
270 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
271 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
272 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
273 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
274 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
275 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
276 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
277 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
278 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
279 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
280 };
281 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
282
283 GlobalProperty pc_compat_2_1[] = {
284 PC_CPU_MODEL_IDS("2.1.0")
285 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
286 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
287 };
288 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
289
290 GlobalProperty pc_compat_2_0[] = {
291 PC_CPU_MODEL_IDS("2.0.0")
292 { "virtio-scsi-pci", "any_layout", "off" },
293 { "PIIX4_PM", "memory-hotplug-support", "off" },
294 { "apic", "version", "0x11" },
295 { "nec-usb-xhci", "superspeed-ports-first", "off" },
296 { "nec-usb-xhci", "force-pcie-endcap", "on" },
297 { "pci-serial", "prog_if", "0" },
298 { "pci-serial-2x", "prog_if", "0" },
299 { "pci-serial-4x", "prog_if", "0" },
300 { "virtio-net-pci", "guest_announce", "off" },
301 { "ICH9-LPC", "memory-hotplug-support", "off" },
302 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
303 { "ioh3420", COMPAT_PROP_PCP, "off" },
304 };
305 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
306
307 GlobalProperty pc_compat_1_7[] = {
308 PC_CPU_MODEL_IDS("1.7.0")
309 { TYPE_USB_DEVICE, "msos-desc", "no" },
310 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
311 { "hpet", HPET_INTCAP, "4" },
312 };
313 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
314
315 GlobalProperty pc_compat_1_6[] = {
316 PC_CPU_MODEL_IDS("1.6.0")
317 { "e1000", "mitigation", "off" },
318 { "qemu64-" TYPE_X86_CPU, "model", "2" },
319 { "qemu32-" TYPE_X86_CPU, "model", "3" },
320 { "i440FX-pcihost", "short_root_bus", "1" },
321 { "q35-pcihost", "short_root_bus", "1" },
322 };
323 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
324
325 GlobalProperty pc_compat_1_5[] = {
326 PC_CPU_MODEL_IDS("1.5.0")
327 { "Conroe-" TYPE_X86_CPU, "model", "2" },
328 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
329 { "Penryn-" TYPE_X86_CPU, "model", "2" },
330 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
331 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
332 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
333 { "virtio-net-pci", "any_layout", "off" },
334 { TYPE_X86_CPU, "pmu", "on" },
335 { "i440FX-pcihost", "short_root_bus", "0" },
336 { "q35-pcihost", "short_root_bus", "0" },
337 };
338 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
339
340 GlobalProperty pc_compat_1_4[] = {
341 PC_CPU_MODEL_IDS("1.4.0")
342 { "scsi-hd", "discard_granularity", "0" },
343 { "scsi-cd", "discard_granularity", "0" },
344 { "scsi-disk", "discard_granularity", "0" },
345 { "ide-hd", "discard_granularity", "0" },
346 { "ide-cd", "discard_granularity", "0" },
347 { "ide-drive", "discard_granularity", "0" },
348 { "virtio-blk-pci", "discard_granularity", "0" },
349 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
350 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
351 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
352 { "e1000", "romfile", "pxe-e1000.rom" },
353 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
354 { "pcnet", "romfile", "pxe-pcnet.rom" },
355 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
356 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
357 { "486-" TYPE_X86_CPU, "model", "0" },
358 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
359 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
360 };
361 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
362
363 void gsi_handler(void *opaque, int n, int level)
364 {
365 GSIState *s = opaque;
366
367 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
368 if (n < ISA_NUM_IRQS) {
369 qemu_set_irq(s->i8259_irq[n], level);
370 }
371 qemu_set_irq(s->ioapic_irq[n], level);
372 }
373
374 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
375 unsigned size)
376 {
377 }
378
379 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
380 {
381 return 0xffffffffffffffffULL;
382 }
383
384 /* MSDOS compatibility mode FPU exception support */
385 static qemu_irq ferr_irq;
386
387 void pc_register_ferr_irq(qemu_irq irq)
388 {
389 ferr_irq = irq;
390 }
391
392 /* XXX: add IGNNE support */
393 void cpu_set_ferr(CPUX86State *s)
394 {
395 qemu_irq_raise(ferr_irq);
396 }
397
398 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
399 unsigned size)
400 {
401 qemu_irq_lower(ferr_irq);
402 }
403
404 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
405 {
406 return 0xffffffffffffffffULL;
407 }
408
409 /* TSC handling */
410 uint64_t cpu_get_tsc(CPUX86State *env)
411 {
412 return cpu_get_ticks();
413 }
414
415 /* IRQ handling */
416 int cpu_get_pic_interrupt(CPUX86State *env)
417 {
418 X86CPU *cpu = env_archcpu(env);
419 int intno;
420
421 if (!kvm_irqchip_in_kernel()) {
422 intno = apic_get_interrupt(cpu->apic_state);
423 if (intno >= 0) {
424 return intno;
425 }
426 /* read the irq from the PIC */
427 if (!apic_accept_pic_intr(cpu->apic_state)) {
428 return -1;
429 }
430 }
431
432 intno = pic_read_irq(isa_pic);
433 return intno;
434 }
435
436 static void pic_irq_request(void *opaque, int irq, int level)
437 {
438 CPUState *cs = first_cpu;
439 X86CPU *cpu = X86_CPU(cs);
440
441 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
442 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
443 CPU_FOREACH(cs) {
444 cpu = X86_CPU(cs);
445 if (apic_accept_pic_intr(cpu->apic_state)) {
446 apic_deliver_pic_intr(cpu->apic_state, level);
447 }
448 }
449 } else {
450 if (level) {
451 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
452 } else {
453 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
454 }
455 }
456 }
457
458 /* PC cmos mappings */
459
460 #define REG_EQUIPMENT_BYTE 0x14
461
462 int cmos_get_fd_drive_type(FloppyDriveType fd0)
463 {
464 int val;
465
466 switch (fd0) {
467 case FLOPPY_DRIVE_TYPE_144:
468 /* 1.44 Mb 3"5 drive */
469 val = 4;
470 break;
471 case FLOPPY_DRIVE_TYPE_288:
472 /* 2.88 Mb 3"5 drive */
473 val = 5;
474 break;
475 case FLOPPY_DRIVE_TYPE_120:
476 /* 1.2 Mb 5"5 drive */
477 val = 2;
478 break;
479 case FLOPPY_DRIVE_TYPE_NONE:
480 default:
481 val = 0;
482 break;
483 }
484 return val;
485 }
486
487 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
488 int16_t cylinders, int8_t heads, int8_t sectors)
489 {
490 rtc_set_memory(s, type_ofs, 47);
491 rtc_set_memory(s, info_ofs, cylinders);
492 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
493 rtc_set_memory(s, info_ofs + 2, heads);
494 rtc_set_memory(s, info_ofs + 3, 0xff);
495 rtc_set_memory(s, info_ofs + 4, 0xff);
496 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
497 rtc_set_memory(s, info_ofs + 6, cylinders);
498 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
499 rtc_set_memory(s, info_ofs + 8, sectors);
500 }
501
502 /* convert boot_device letter to something recognizable by the bios */
503 static int boot_device2nibble(char boot_device)
504 {
505 switch(boot_device) {
506 case 'a':
507 case 'b':
508 return 0x01; /* floppy boot */
509 case 'c':
510 return 0x02; /* hard drive boot */
511 case 'd':
512 return 0x03; /* CD-ROM boot */
513 case 'n':
514 return 0x04; /* Network boot */
515 }
516 return 0;
517 }
518
519 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
520 {
521 #define PC_MAX_BOOT_DEVICES 3
522 int nbds, bds[3] = { 0, };
523 int i;
524
525 nbds = strlen(boot_device);
526 if (nbds > PC_MAX_BOOT_DEVICES) {
527 error_setg(errp, "Too many boot devices for PC");
528 return;
529 }
530 for (i = 0; i < nbds; i++) {
531 bds[i] = boot_device2nibble(boot_device[i]);
532 if (bds[i] == 0) {
533 error_setg(errp, "Invalid boot device for PC: '%c'",
534 boot_device[i]);
535 return;
536 }
537 }
538 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
539 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
540 }
541
542 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
543 {
544 set_boot_dev(opaque, boot_device, errp);
545 }
546
547 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
548 {
549 int val, nb, i;
550 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
551 FLOPPY_DRIVE_TYPE_NONE };
552
553 /* floppy type */
554 if (floppy) {
555 for (i = 0; i < 2; i++) {
556 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
557 }
558 }
559 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
560 cmos_get_fd_drive_type(fd_type[1]);
561 rtc_set_memory(rtc_state, 0x10, val);
562
563 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
564 nb = 0;
565 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
566 nb++;
567 }
568 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
569 nb++;
570 }
571 switch (nb) {
572 case 0:
573 break;
574 case 1:
575 val |= 0x01; /* 1 drive, ready for boot */
576 break;
577 case 2:
578 val |= 0x41; /* 2 drives, ready for boot */
579 break;
580 }
581 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
582 }
583
584 typedef struct pc_cmos_init_late_arg {
585 ISADevice *rtc_state;
586 BusState *idebus[2];
587 } pc_cmos_init_late_arg;
588
589 typedef struct check_fdc_state {
590 ISADevice *floppy;
591 bool multiple;
592 } CheckFdcState;
593
594 static int check_fdc(Object *obj, void *opaque)
595 {
596 CheckFdcState *state = opaque;
597 Object *fdc;
598 uint32_t iobase;
599 Error *local_err = NULL;
600
601 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
602 if (!fdc) {
603 return 0;
604 }
605
606 iobase = object_property_get_uint(obj, "iobase", &local_err);
607 if (local_err || iobase != 0x3f0) {
608 error_free(local_err);
609 return 0;
610 }
611
612 if (state->floppy) {
613 state->multiple = true;
614 } else {
615 state->floppy = ISA_DEVICE(obj);
616 }
617 return 0;
618 }
619
620 static const char * const fdc_container_path[] = {
621 "/unattached", "/peripheral", "/peripheral-anon"
622 };
623
624 /*
625 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
626 * and ACPI objects.
627 */
628 ISADevice *pc_find_fdc0(void)
629 {
630 int i;
631 Object *container;
632 CheckFdcState state = { 0 };
633
634 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
635 container = container_get(qdev_get_machine(), fdc_container_path[i]);
636 object_child_foreach(container, check_fdc, &state);
637 }
638
639 if (state.multiple) {
640 warn_report("multiple floppy disk controllers with "
641 "iobase=0x3f0 have been found");
642 error_printf("the one being picked for CMOS setup might not reflect "
643 "your intent");
644 }
645
646 return state.floppy;
647 }
648
649 static void pc_cmos_init_late(void *opaque)
650 {
651 pc_cmos_init_late_arg *arg = opaque;
652 ISADevice *s = arg->rtc_state;
653 int16_t cylinders;
654 int8_t heads, sectors;
655 int val;
656 int i, trans;
657
658 val = 0;
659 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
660 &cylinders, &heads, &sectors) >= 0) {
661 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
662 val |= 0xf0;
663 }
664 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
665 &cylinders, &heads, &sectors) >= 0) {
666 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
667 val |= 0x0f;
668 }
669 rtc_set_memory(s, 0x12, val);
670
671 val = 0;
672 for (i = 0; i < 4; i++) {
673 /* NOTE: ide_get_geometry() returns the physical
674 geometry. It is always such that: 1 <= sects <= 63, 1
675 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
676 geometry can be different if a translation is done. */
677 if (arg->idebus[i / 2] &&
678 ide_get_geometry(arg->idebus[i / 2], i % 2,
679 &cylinders, &heads, &sectors) >= 0) {
680 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
681 assert((trans & ~3) == 0);
682 val |= trans << (i * 2);
683 }
684 }
685 rtc_set_memory(s, 0x39, val);
686
687 pc_cmos_init_floppy(s, pc_find_fdc0());
688
689 qemu_unregister_reset(pc_cmos_init_late, opaque);
690 }
691
692 void pc_cmos_init(PCMachineState *pcms,
693 BusState *idebus0, BusState *idebus1,
694 ISADevice *s)
695 {
696 int val;
697 static pc_cmos_init_late_arg arg;
698
699 /* various important CMOS locations needed by PC/Bochs bios */
700
701 /* memory size */
702 /* base memory (first MiB) */
703 val = MIN(pcms->below_4g_mem_size / KiB, 640);
704 rtc_set_memory(s, 0x15, val);
705 rtc_set_memory(s, 0x16, val >> 8);
706 /* extended memory (next 64MiB) */
707 if (pcms->below_4g_mem_size > 1 * MiB) {
708 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
709 } else {
710 val = 0;
711 }
712 if (val > 65535)
713 val = 65535;
714 rtc_set_memory(s, 0x17, val);
715 rtc_set_memory(s, 0x18, val >> 8);
716 rtc_set_memory(s, 0x30, val);
717 rtc_set_memory(s, 0x31, val >> 8);
718 /* memory between 16MiB and 4GiB */
719 if (pcms->below_4g_mem_size > 16 * MiB) {
720 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
721 } else {
722 val = 0;
723 }
724 if (val > 65535)
725 val = 65535;
726 rtc_set_memory(s, 0x34, val);
727 rtc_set_memory(s, 0x35, val >> 8);
728 /* memory above 4GiB */
729 val = pcms->above_4g_mem_size / 65536;
730 rtc_set_memory(s, 0x5b, val);
731 rtc_set_memory(s, 0x5c, val >> 8);
732 rtc_set_memory(s, 0x5d, val >> 16);
733
734 object_property_add_link(OBJECT(pcms), "rtc_state",
735 TYPE_ISA_DEVICE,
736 (Object **)&pcms->rtc,
737 object_property_allow_set_link,
738 OBJ_PROP_LINK_STRONG, &error_abort);
739 object_property_set_link(OBJECT(pcms), OBJECT(s),
740 "rtc_state", &error_abort);
741
742 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
743
744 val = 0;
745 val |= 0x02; /* FPU is there */
746 val |= 0x04; /* PS/2 mouse installed */
747 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
748
749 /* hard drives and FDC */
750 arg.rtc_state = s;
751 arg.idebus[0] = idebus0;
752 arg.idebus[1] = idebus1;
753 qemu_register_reset(pc_cmos_init_late, &arg);
754 }
755
756 #define TYPE_PORT92 "port92"
757 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
758
759 /* port 92 stuff: could be split off */
760 typedef struct Port92State {
761 ISADevice parent_obj;
762
763 MemoryRegion io;
764 uint8_t outport;
765 qemu_irq a20_out;
766 } Port92State;
767
768 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
769 unsigned size)
770 {
771 Port92State *s = opaque;
772 int oldval = s->outport;
773
774 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
775 s->outport = val;
776 qemu_set_irq(s->a20_out, (val >> 1) & 1);
777 if ((val & 1) && !(oldval & 1)) {
778 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
779 }
780 }
781
782 static uint64_t port92_read(void *opaque, hwaddr addr,
783 unsigned size)
784 {
785 Port92State *s = opaque;
786 uint32_t ret;
787
788 ret = s->outport;
789 DPRINTF("port92: read 0x%02x\n", ret);
790 return ret;
791 }
792
793 static void port92_init(ISADevice *dev, qemu_irq a20_out)
794 {
795 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
796 }
797
798 static const VMStateDescription vmstate_port92_isa = {
799 .name = "port92",
800 .version_id = 1,
801 .minimum_version_id = 1,
802 .fields = (VMStateField[]) {
803 VMSTATE_UINT8(outport, Port92State),
804 VMSTATE_END_OF_LIST()
805 }
806 };
807
808 static void port92_reset(DeviceState *d)
809 {
810 Port92State *s = PORT92(d);
811
812 s->outport &= ~1;
813 }
814
815 static const MemoryRegionOps port92_ops = {
816 .read = port92_read,
817 .write = port92_write,
818 .impl = {
819 .min_access_size = 1,
820 .max_access_size = 1,
821 },
822 .endianness = DEVICE_LITTLE_ENDIAN,
823 };
824
825 static void port92_initfn(Object *obj)
826 {
827 Port92State *s = PORT92(obj);
828
829 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
830
831 s->outport = 0;
832
833 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
834 }
835
836 static void port92_realizefn(DeviceState *dev, Error **errp)
837 {
838 ISADevice *isadev = ISA_DEVICE(dev);
839 Port92State *s = PORT92(dev);
840
841 isa_register_ioport(isadev, &s->io, 0x92);
842 }
843
844 static void port92_class_initfn(ObjectClass *klass, void *data)
845 {
846 DeviceClass *dc = DEVICE_CLASS(klass);
847
848 dc->realize = port92_realizefn;
849 dc->reset = port92_reset;
850 dc->vmsd = &vmstate_port92_isa;
851 /*
852 * Reason: unlike ordinary ISA devices, this one needs additional
853 * wiring: its A20 output line needs to be wired up by
854 * port92_init().
855 */
856 dc->user_creatable = false;
857 }
858
859 static const TypeInfo port92_info = {
860 .name = TYPE_PORT92,
861 .parent = TYPE_ISA_DEVICE,
862 .instance_size = sizeof(Port92State),
863 .instance_init = port92_initfn,
864 .class_init = port92_class_initfn,
865 };
866
867 static void port92_register_types(void)
868 {
869 type_register_static(&port92_info);
870 }
871
872 type_init(port92_register_types)
873
874 static void handle_a20_line_change(void *opaque, int irq, int level)
875 {
876 X86CPU *cpu = opaque;
877
878 /* XXX: send to all CPUs ? */
879 /* XXX: add logic to handle multiple A20 line sources */
880 x86_cpu_set_a20(cpu, level);
881 }
882
883 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
884 {
885 int index = le32_to_cpu(e820_reserve.count);
886 struct e820_entry *entry;
887
888 if (type != E820_RAM) {
889 /* old FW_CFG_E820_TABLE entry -- reservations only */
890 if (index >= E820_NR_ENTRIES) {
891 return -EBUSY;
892 }
893 entry = &e820_reserve.entry[index++];
894
895 entry->address = cpu_to_le64(address);
896 entry->length = cpu_to_le64(length);
897 entry->type = cpu_to_le32(type);
898
899 e820_reserve.count = cpu_to_le32(index);
900 }
901
902 /* new "etc/e820" file -- include ram too */
903 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
904 e820_table[e820_entries].address = cpu_to_le64(address);
905 e820_table[e820_entries].length = cpu_to_le64(length);
906 e820_table[e820_entries].type = cpu_to_le32(type);
907 e820_entries++;
908
909 return e820_entries;
910 }
911
912 int e820_get_num_entries(void)
913 {
914 return e820_entries;
915 }
916
917 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
918 {
919 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
920 *address = le64_to_cpu(e820_table[idx].address);
921 *length = le64_to_cpu(e820_table[idx].length);
922 return true;
923 }
924 return false;
925 }
926
927 /* Calculates initial APIC ID for a specific CPU index
928 *
929 * Currently we need to be able to calculate the APIC ID from the CPU index
930 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
931 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
932 * all CPUs up to max_cpus.
933 */
934 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
935 unsigned int cpu_index)
936 {
937 MachineState *ms = MACHINE(pcms);
938 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
939 uint32_t correct_id;
940 static bool warned;
941
942 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
943 ms->smp.threads, cpu_index);
944 if (pcmc->compat_apic_id_mode) {
945 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
946 error_report("APIC IDs set in compatibility mode, "
947 "CPU topology won't match the configuration");
948 warned = true;
949 }
950 return cpu_index;
951 } else {
952 return correct_id;
953 }
954 }
955
956 static void pc_build_smbios(PCMachineState *pcms)
957 {
958 uint8_t *smbios_tables, *smbios_anchor;
959 size_t smbios_tables_len, smbios_anchor_len;
960 struct smbios_phys_mem_area *mem_array;
961 unsigned i, array_count;
962 MachineState *ms = MACHINE(pcms);
963 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
964
965 /* tell smbios about cpuid version and features */
966 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
967
968 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
969 if (smbios_tables) {
970 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
971 smbios_tables, smbios_tables_len);
972 }
973
974 /* build the array of physical mem area from e820 table */
975 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
976 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
977 uint64_t addr, len;
978
979 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
980 mem_array[array_count].address = addr;
981 mem_array[array_count].length = len;
982 array_count++;
983 }
984 }
985 smbios_get_tables(ms, mem_array, array_count,
986 &smbios_tables, &smbios_tables_len,
987 &smbios_anchor, &smbios_anchor_len);
988 g_free(mem_array);
989
990 if (smbios_anchor) {
991 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
992 smbios_tables, smbios_tables_len);
993 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
994 smbios_anchor, smbios_anchor_len);
995 }
996 }
997
998 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
999 {
1000 FWCfgState *fw_cfg;
1001 uint64_t *numa_fw_cfg;
1002 int i;
1003 const CPUArchIdList *cpus;
1004 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1005
1006 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
1007 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1008
1009 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1010 *
1011 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1012 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1013 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1014 * for CPU hotplug also uses APIC ID and not "CPU index".
1015 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1016 * but the "limit to the APIC ID values SeaBIOS may see".
1017 *
1018 * So for compatibility reasons with old BIOSes we are stuck with
1019 * "etc/max-cpus" actually being apic_id_limit
1020 */
1021 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
1022 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1023 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1024 acpi_tables, acpi_tables_len);
1025 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
1026
1027 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
1028 &e820_reserve, sizeof(e820_reserve));
1029 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1030 sizeof(struct e820_entry) * e820_entries);
1031
1032 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
1033 /* allocate memory for the NUMA channel: one (64bit) word for the number
1034 * of nodes, one word for each VCPU->node and one word for each node to
1035 * hold the amount of memory.
1036 */
1037 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
1038 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
1039 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1040 for (i = 0; i < cpus->len; i++) {
1041 unsigned int apic_id = cpus->cpus[i].arch_id;
1042 assert(apic_id < pcms->apic_id_limit);
1043 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
1044 }
1045 for (i = 0; i < nb_numa_nodes; i++) {
1046 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1047 cpu_to_le64(numa_info[i].node_mem);
1048 }
1049 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
1050 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1051 sizeof(*numa_fw_cfg));
1052
1053 return fw_cfg;
1054 }
1055
1056 static long get_file_size(FILE *f)
1057 {
1058 long where, size;
1059
1060 /* XXX: on Unix systems, using fstat() probably makes more sense */
1061
1062 where = ftell(f);
1063 fseek(f, 0, SEEK_END);
1064 size = ftell(f);
1065 fseek(f, where, SEEK_SET);
1066
1067 return size;
1068 }
1069
1070 struct setup_data {
1071 uint64_t next;
1072 uint32_t type;
1073 uint32_t len;
1074 uint8_t data[0];
1075 } __attribute__((packed));
1076
1077
1078 /*
1079 * The entry point into the kernel for PVH boot is different from
1080 * the native entry point. The PVH entry is defined by the x86/HVM
1081 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1082 *
1083 * This function is passed to load_elf() when it is called from
1084 * load_elfboot() which then additionally checks for an ELF Note of
1085 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1086 * parse the PVH entry address from the ELF Note.
1087 *
1088 * Due to trickery in elf_opts.h, load_elf() is actually available as
1089 * load_elf32() or load_elf64() and this routine needs to be able
1090 * to deal with being called as 32 or 64 bit.
1091 *
1092 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1093 * global variable. (although the entry point is 32-bit, the kernel
1094 * binary can be either 32-bit or 64-bit).
1095 */
1096 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1097 {
1098 size_t *elf_note_data_addr;
1099
1100 /* Check if ELF Note header passed in is valid */
1101 if (arg1 == NULL) {
1102 return 0;
1103 }
1104
1105 if (is64) {
1106 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1107 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1108 uint64_t phdr_align = *(uint64_t *)arg2;
1109 uint64_t nhdr_namesz = nhdr64->n_namesz;
1110
1111 elf_note_data_addr =
1112 ((void *)nhdr64) + nhdr_size64 +
1113 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1114 } else {
1115 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1116 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1117 uint32_t phdr_align = *(uint32_t *)arg2;
1118 uint32_t nhdr_namesz = nhdr32->n_namesz;
1119
1120 elf_note_data_addr =
1121 ((void *)nhdr32) + nhdr_size32 +
1122 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1123 }
1124
1125 pvh_start_addr = *elf_note_data_addr;
1126
1127 return pvh_start_addr;
1128 }
1129
1130 static bool load_elfboot(const char *kernel_filename,
1131 int kernel_file_size,
1132 uint8_t *header,
1133 size_t pvh_xen_start_addr,
1134 FWCfgState *fw_cfg)
1135 {
1136 uint32_t flags = 0;
1137 uint32_t mh_load_addr = 0;
1138 uint32_t elf_kernel_size = 0;
1139 uint64_t elf_entry;
1140 uint64_t elf_low, elf_high;
1141 int kernel_size;
1142
1143 if (ldl_p(header) != 0x464c457f) {
1144 return false; /* no elfboot */
1145 }
1146
1147 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1148 flags = elf_is64 ?
1149 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1150
1151 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1152 error_report("elfboot unsupported flags = %x", flags);
1153 exit(1);
1154 }
1155
1156 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1157 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1158 NULL, &elf_note_type, &elf_entry,
1159 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1160 0, 0);
1161
1162 if (kernel_size < 0) {
1163 error_report("Error while loading elf kernel");
1164 exit(1);
1165 }
1166 mh_load_addr = elf_low;
1167 elf_kernel_size = elf_high - elf_low;
1168
1169 if (pvh_start_addr == 0) {
1170 error_report("Error loading uncompressed kernel without PVH ELF Note");
1171 exit(1);
1172 }
1173 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1174 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1175 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1176
1177 return true;
1178 }
1179
1180 static void load_linux(PCMachineState *pcms,
1181 FWCfgState *fw_cfg)
1182 {
1183 uint16_t protocol;
1184 int setup_size, kernel_size, cmdline_size;
1185 int dtb_size, setup_data_offset;
1186 uint32_t initrd_max;
1187 uint8_t header[8192], *setup, *kernel;
1188 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1189 FILE *f;
1190 char *vmode;
1191 MachineState *machine = MACHINE(pcms);
1192 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1193 struct setup_data *setup_data;
1194 const char *kernel_filename = machine->kernel_filename;
1195 const char *initrd_filename = machine->initrd_filename;
1196 const char *dtb_filename = machine->dtb;
1197 const char *kernel_cmdline = machine->kernel_cmdline;
1198
1199 /* Align to 16 bytes as a paranoia measure */
1200 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1201
1202 /* load the kernel header */
1203 f = fopen(kernel_filename, "rb");
1204 if (!f || !(kernel_size = get_file_size(f)) ||
1205 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1206 MIN(ARRAY_SIZE(header), kernel_size)) {
1207 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1208 kernel_filename, strerror(errno));
1209 exit(1);
1210 }
1211
1212 /* kernel protocol version */
1213 #if 0
1214 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
1215 #endif
1216 if (ldl_p(header+0x202) == 0x53726448) {
1217 protocol = lduw_p(header+0x206);
1218 } else {
1219 /*
1220 * This could be a multiboot kernel. If it is, let's stop treating it
1221 * like a Linux kernel.
1222 * Note: some multiboot images could be in the ELF format (the same of
1223 * PVH), so we try multiboot first since we check the multiboot magic
1224 * header before to load it.
1225 */
1226 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1227 kernel_cmdline, kernel_size, header)) {
1228 return;
1229 }
1230 /*
1231 * Check if the file is an uncompressed kernel file (ELF) and load it,
1232 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1233 * If load_elfboot() is successful, populate the fw_cfg info.
1234 */
1235 if (pcmc->pvh_enabled &&
1236 load_elfboot(kernel_filename, kernel_size,
1237 header, pvh_start_addr, fw_cfg)) {
1238 fclose(f);
1239
1240 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1241 strlen(kernel_cmdline) + 1);
1242 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1243
1244 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1245 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1246 header, sizeof(header));
1247
1248 /* load initrd */
1249 if (initrd_filename) {
1250 GMappedFile *mapped_file;
1251 gsize initrd_size;
1252 gchar *initrd_data;
1253 GError *gerr = NULL;
1254
1255 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1256 if (!mapped_file) {
1257 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1258 initrd_filename, gerr->message);
1259 exit(1);
1260 }
1261 pcms->initrd_mapped_file = mapped_file;
1262
1263 initrd_data = g_mapped_file_get_contents(mapped_file);
1264 initrd_size = g_mapped_file_get_length(mapped_file);
1265 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1266 if (initrd_size >= initrd_max) {
1267 fprintf(stderr, "qemu: initrd is too large, cannot support."
1268 "(max: %"PRIu32", need %"PRId64")\n",
1269 initrd_max, (uint64_t)initrd_size);
1270 exit(1);
1271 }
1272
1273 initrd_addr = (initrd_max - initrd_size) & ~4095;
1274
1275 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1276 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1277 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1278 initrd_size);
1279 }
1280
1281 option_rom[nb_option_roms].bootindex = 0;
1282 option_rom[nb_option_roms].name = "pvh.bin";
1283 nb_option_roms++;
1284
1285 return;
1286 }
1287 protocol = 0;
1288 }
1289
1290 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
1291 /* Low kernel */
1292 real_addr = 0x90000;
1293 cmdline_addr = 0x9a000 - cmdline_size;
1294 prot_addr = 0x10000;
1295 } else if (protocol < 0x202) {
1296 /* High but ancient kernel */
1297 real_addr = 0x90000;
1298 cmdline_addr = 0x9a000 - cmdline_size;
1299 prot_addr = 0x100000;
1300 } else {
1301 /* High and recent kernel */
1302 real_addr = 0x10000;
1303 cmdline_addr = 0x20000;
1304 prot_addr = 0x100000;
1305 }
1306
1307 #if 0
1308 fprintf(stderr,
1309 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1310 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1311 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1312 real_addr,
1313 cmdline_addr,
1314 prot_addr);
1315 #endif
1316
1317 /* highest address for loading the initrd */
1318 if (protocol >= 0x20c &&
1319 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1320 /*
1321 * Linux has supported initrd up to 4 GB for a very long time (2007,
1322 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1323 * though it only sets initrd_max to 2 GB to "work around bootloader
1324 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1325 * has supported this.
1326 *
1327 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1328 * be loaded into any address.
1329 *
1330 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1331 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1332 * field).
1333 *
1334 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1335 */
1336 initrd_max = UINT32_MAX;
1337 } else if (protocol >= 0x203) {
1338 initrd_max = ldl_p(header+0x22c);
1339 } else {
1340 initrd_max = 0x37ffffff;
1341 }
1342
1343 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1344 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1345 }
1346
1347 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1348 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
1349 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1350
1351 if (protocol >= 0x202) {
1352 stl_p(header+0x228, cmdline_addr);
1353 } else {
1354 stw_p(header+0x20, 0xA33F);
1355 stw_p(header+0x22, cmdline_addr-real_addr);
1356 }
1357
1358 /* handle vga= parameter */
1359 vmode = strstr(kernel_cmdline, "vga=");
1360 if (vmode) {
1361 unsigned int video_mode;
1362 /* skip "vga=" */
1363 vmode += 4;
1364 if (!strncmp(vmode, "normal", 6)) {
1365 video_mode = 0xffff;
1366 } else if (!strncmp(vmode, "ext", 3)) {
1367 video_mode = 0xfffe;
1368 } else if (!strncmp(vmode, "ask", 3)) {
1369 video_mode = 0xfffd;
1370 } else {
1371 video_mode = strtol(vmode, NULL, 0);
1372 }
1373 stw_p(header+0x1fa, video_mode);
1374 }
1375
1376 /* loader type */
1377 /* High nybble = B reserved for QEMU; low nybble is revision number.
1378 If this code is substantially changed, you may want to consider
1379 incrementing the revision. */
1380 if (protocol >= 0x200) {
1381 header[0x210] = 0xB0;
1382 }
1383 /* heap */
1384 if (protocol >= 0x201) {
1385 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1386 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1387 }
1388
1389 /* load initrd */
1390 if (initrd_filename) {
1391 GMappedFile *mapped_file;
1392 gsize initrd_size;
1393 gchar *initrd_data;
1394 GError *gerr = NULL;
1395
1396 if (protocol < 0x200) {
1397 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1398 exit(1);
1399 }
1400
1401 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1402 if (!mapped_file) {
1403 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1404 initrd_filename, gerr->message);
1405 exit(1);
1406 }
1407 pcms->initrd_mapped_file = mapped_file;
1408
1409 initrd_data = g_mapped_file_get_contents(mapped_file);
1410 initrd_size = g_mapped_file_get_length(mapped_file);
1411 if (initrd_size >= initrd_max) {
1412 fprintf(stderr, "qemu: initrd is too large, cannot support."
1413 "(max: %"PRIu32", need %"PRId64")\n",
1414 initrd_max, (uint64_t)initrd_size);
1415 exit(1);
1416 }
1417
1418 initrd_addr = (initrd_max-initrd_size) & ~4095;
1419
1420 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1421 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1422 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1423
1424 stl_p(header+0x218, initrd_addr);
1425 stl_p(header+0x21c, initrd_size);
1426 }
1427
1428 /* load kernel and setup */
1429 setup_size = header[0x1f1];
1430 if (setup_size == 0) {
1431 setup_size = 4;
1432 }
1433 setup_size = (setup_size+1)*512;
1434 if (setup_size > kernel_size) {
1435 fprintf(stderr, "qemu: invalid kernel header\n");
1436 exit(1);
1437 }
1438 kernel_size -= setup_size;
1439
1440 setup = g_malloc(setup_size);
1441 kernel = g_malloc(kernel_size);
1442 fseek(f, 0, SEEK_SET);
1443 if (fread(setup, 1, setup_size, f) != setup_size) {
1444 fprintf(stderr, "fread() failed\n");
1445 exit(1);
1446 }
1447 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1448 fprintf(stderr, "fread() failed\n");
1449 exit(1);
1450 }
1451 fclose(f);
1452
1453 /* append dtb to kernel */
1454 if (dtb_filename) {
1455 if (protocol < 0x209) {
1456 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1457 exit(1);
1458 }
1459
1460 dtb_size = get_image_size(dtb_filename);
1461 if (dtb_size <= 0) {
1462 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1463 dtb_filename, strerror(errno));
1464 exit(1);
1465 }
1466
1467 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1468 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1469 kernel = g_realloc(kernel, kernel_size);
1470
1471 stq_p(header+0x250, prot_addr + setup_data_offset);
1472
1473 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1474 setup_data->next = 0;
1475 setup_data->type = cpu_to_le32(SETUP_DTB);
1476 setup_data->len = cpu_to_le32(dtb_size);
1477
1478 load_image_size(dtb_filename, setup_data->data, dtb_size);
1479 }
1480
1481 memcpy(setup, header, MIN(sizeof(header), setup_size));
1482
1483 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1484 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1485 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1486
1487 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1488 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1489 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1490
1491 option_rom[nb_option_roms].bootindex = 0;
1492 option_rom[nb_option_roms].name = "linuxboot.bin";
1493 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1494 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1495 }
1496 nb_option_roms++;
1497 }
1498
1499 #define NE2000_NB_MAX 6
1500
1501 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1502 0x280, 0x380 };
1503 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1504
1505 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1506 {
1507 static int nb_ne2k = 0;
1508
1509 if (nb_ne2k == NE2000_NB_MAX)
1510 return;
1511 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1512 ne2000_irq[nb_ne2k], nd);
1513 nb_ne2k++;
1514 }
1515
1516 DeviceState *cpu_get_current_apic(void)
1517 {
1518 if (current_cpu) {
1519 X86CPU *cpu = X86_CPU(current_cpu);
1520 return cpu->apic_state;
1521 } else {
1522 return NULL;
1523 }
1524 }
1525
1526 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1527 {
1528 X86CPU *cpu = opaque;
1529
1530 if (level) {
1531 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1532 }
1533 }
1534
1535 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
1536 {
1537 Object *cpu = NULL;
1538 Error *local_err = NULL;
1539 CPUX86State *env = NULL;
1540
1541 cpu = object_new(MACHINE(pcms)->cpu_type);
1542
1543 env = &X86_CPU(cpu)->env;
1544 env->nr_dies = pcms->smp_dies;
1545
1546 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1547 object_property_set_bool(cpu, true, "realized", &local_err);
1548
1549 object_unref(cpu);
1550 error_propagate(errp, local_err);
1551 }
1552
1553 /*
1554 * This function is very similar to smp_parse()
1555 * in hw/core/machine.c but includes CPU die support.
1556 */
1557 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
1558 {
1559 PCMachineState *pcms = PC_MACHINE(ms);
1560
1561 if (opts) {
1562 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
1563 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
1564 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
1565 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
1566 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
1567
1568 /* compute missing values, prefer sockets over cores over threads */
1569 if (cpus == 0 || sockets == 0) {
1570 cores = cores > 0 ? cores : 1;
1571 threads = threads > 0 ? threads : 1;
1572 if (cpus == 0) {
1573 sockets = sockets > 0 ? sockets : 1;
1574 cpus = cores * threads * dies * sockets;
1575 } else {
1576 ms->smp.max_cpus =
1577 qemu_opt_get_number(opts, "maxcpus", cpus);
1578 sockets = ms->smp.max_cpus / (cores * threads * dies);
1579 }
1580 } else if (cores == 0) {
1581 threads = threads > 0 ? threads : 1;
1582 cores = cpus / (sockets * dies * threads);
1583 cores = cores > 0 ? cores : 1;
1584 } else if (threads == 0) {
1585 threads = cpus / (cores * dies * sockets);
1586 threads = threads > 0 ? threads : 1;
1587 } else if (sockets * dies * cores * threads < cpus) {
1588 error_report("cpu topology: "
1589 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
1590 "smp_cpus (%u)",
1591 sockets, dies, cores, threads, cpus);
1592 exit(1);
1593 }
1594
1595 ms->smp.max_cpus =
1596 qemu_opt_get_number(opts, "maxcpus", cpus);
1597
1598 if (ms->smp.max_cpus < cpus) {
1599 error_report("maxcpus must be equal to or greater than smp");
1600 exit(1);
1601 }
1602
1603 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
1604 error_report("cpu topology: "
1605 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
1606 "maxcpus (%u)",
1607 sockets, dies, cores, threads,
1608 ms->smp.max_cpus);
1609 exit(1);
1610 }
1611
1612 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
1613 warn_report("Invalid CPU topology deprecated: "
1614 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
1615 "!= maxcpus (%u)",
1616 sockets, dies, cores, threads,
1617 ms->smp.max_cpus);
1618 }
1619
1620 ms->smp.cpus = cpus;
1621 ms->smp.cores = cores;
1622 ms->smp.threads = threads;
1623 pcms->smp_dies = dies;
1624 }
1625
1626 if (ms->smp.cpus > 1) {
1627 Error *blocker = NULL;
1628 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
1629 replay_add_blocker(blocker);
1630 }
1631 }
1632
1633 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
1634 {
1635 PCMachineState *pcms = PC_MACHINE(ms);
1636 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
1637 Error *local_err = NULL;
1638
1639 if (id < 0) {
1640 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1641 return;
1642 }
1643
1644 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1645 error_setg(errp, "Unable to add CPU: %" PRIi64
1646 ", resulting APIC ID (%" PRIi64 ") is too large",
1647 id, apic_id);
1648 return;
1649 }
1650
1651 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
1652 if (local_err) {
1653 error_propagate(errp, local_err);
1654 return;
1655 }
1656 }
1657
1658 void pc_cpus_init(PCMachineState *pcms)
1659 {
1660 int i;
1661 const CPUArchIdList *possible_cpus;
1662 MachineState *ms = MACHINE(pcms);
1663 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1664 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
1665
1666 x86_cpu_set_default_version(pcmc->default_cpu_version);
1667
1668 /* Calculates the limit to CPU APIC ID values
1669 *
1670 * Limit for the APIC ID value, so that all
1671 * CPU APIC IDs are < pcms->apic_id_limit.
1672 *
1673 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1674 */
1675 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
1676 ms->smp.max_cpus - 1) + 1;
1677 possible_cpus = mc->possible_cpu_arch_ids(ms);
1678 for (i = 0; i < ms->smp.cpus; i++) {
1679 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
1680 }
1681 }
1682
1683 static void pc_build_feature_control_file(PCMachineState *pcms)
1684 {
1685 MachineState *ms = MACHINE(pcms);
1686 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1687 CPUX86State *env = &cpu->env;
1688 uint32_t unused, ecx, edx;
1689 uint64_t feature_control_bits = 0;
1690 uint64_t *val;
1691
1692 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1693 if (ecx & CPUID_EXT_VMX) {
1694 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1695 }
1696
1697 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1698 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1699 (env->mcg_cap & MCG_LMCE_P)) {
1700 feature_control_bits |= FEATURE_CONTROL_LMCE;
1701 }
1702
1703 if (!feature_control_bits) {
1704 return;
1705 }
1706
1707 val = g_malloc(sizeof(*val));
1708 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1709 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1710 }
1711
1712 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1713 {
1714 if (cpus_count > 0xff) {
1715 /* If the number of CPUs can't be represented in 8 bits, the
1716 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1717 * to make old BIOSes fail more predictably.
1718 */
1719 rtc_set_memory(rtc, 0x5f, 0);
1720 } else {
1721 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1722 }
1723 }
1724
1725 static
1726 void pc_machine_done(Notifier *notifier, void *data)
1727 {
1728 PCMachineState *pcms = container_of(notifier,
1729 PCMachineState, machine_done);
1730 PCIBus *bus = pcms->bus;
1731
1732 /* set the number of CPUs */
1733 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1734
1735 if (bus) {
1736 int extra_hosts = 0;
1737
1738 QLIST_FOREACH(bus, &bus->child, sibling) {
1739 /* look for expander root buses */
1740 if (pci_bus_is_root(bus)) {
1741 extra_hosts++;
1742 }
1743 }
1744 if (extra_hosts && pcms->fw_cfg) {
1745 uint64_t *val = g_malloc(sizeof(*val));
1746 *val = cpu_to_le64(extra_hosts);
1747 fw_cfg_add_file(pcms->fw_cfg,
1748 "etc/extra-pci-roots", val, sizeof(*val));
1749 }
1750 }
1751
1752 acpi_setup();
1753 if (pcms->fw_cfg) {
1754 pc_build_smbios(pcms);
1755 pc_build_feature_control_file(pcms);
1756 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1757 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1758 }
1759
1760 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1761 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1762
1763 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1764 iommu->intr_eim != ON_OFF_AUTO_ON) {
1765 error_report("current -smp configuration requires "
1766 "Extended Interrupt Mode enabled. "
1767 "You can add an IOMMU using: "
1768 "-device intel-iommu,intremap=on,eim=on");
1769 exit(EXIT_FAILURE);
1770 }
1771 }
1772 }
1773
1774 void pc_guest_info_init(PCMachineState *pcms)
1775 {
1776 int i;
1777
1778 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1779 pcms->numa_nodes = nb_numa_nodes;
1780 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1781 sizeof *pcms->node_mem);
1782 for (i = 0; i < nb_numa_nodes; i++) {
1783 pcms->node_mem[i] = numa_info[i].node_mem;
1784 }
1785
1786 pcms->machine_done.notify = pc_machine_done;
1787 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1788 }
1789
1790 /* setup pci memory address space mapping into system address space */
1791 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1792 MemoryRegion *pci_address_space)
1793 {
1794 /* Set to lower priority than RAM */
1795 memory_region_add_subregion_overlap(system_memory, 0x0,
1796 pci_address_space, -1);
1797 }
1798
1799 void xen_load_linux(PCMachineState *pcms)
1800 {
1801 int i;
1802 FWCfgState *fw_cfg;
1803
1804 assert(MACHINE(pcms)->kernel_filename != NULL);
1805
1806 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1807 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1808 rom_set_fw(fw_cfg);
1809
1810 load_linux(pcms, fw_cfg);
1811 for (i = 0; i < nb_option_roms; i++) {
1812 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1813 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1814 !strcmp(option_rom[i].name, "pvh.bin") ||
1815 !strcmp(option_rom[i].name, "multiboot.bin"));
1816 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1817 }
1818 pcms->fw_cfg = fw_cfg;
1819 }
1820
1821 void pc_memory_init(PCMachineState *pcms,
1822 MemoryRegion *system_memory,
1823 MemoryRegion *rom_memory,
1824 MemoryRegion **ram_memory)
1825 {
1826 int linux_boot, i;
1827 MemoryRegion *ram, *option_rom_mr;
1828 MemoryRegion *ram_below_4g, *ram_above_4g;
1829 FWCfgState *fw_cfg;
1830 MachineState *machine = MACHINE(pcms);
1831 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1832
1833 assert(machine->ram_size == pcms->below_4g_mem_size +
1834 pcms->above_4g_mem_size);
1835
1836 linux_boot = (machine->kernel_filename != NULL);
1837
1838 /* Allocate RAM. We allocate it as a single memory region and use
1839 * aliases to address portions of it, mostly for backwards compatibility
1840 * with older qemus that used qemu_ram_alloc().
1841 */
1842 ram = g_malloc(sizeof(*ram));
1843 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1844 machine->ram_size);
1845 *ram_memory = ram;
1846 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1847 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1848 0, pcms->below_4g_mem_size);
1849 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1850 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1851 if (pcms->above_4g_mem_size > 0) {
1852 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1853 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1854 pcms->below_4g_mem_size,
1855 pcms->above_4g_mem_size);
1856 memory_region_add_subregion(system_memory, 0x100000000ULL,
1857 ram_above_4g);
1858 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1859 }
1860
1861 if (!pcmc->has_reserved_memory &&
1862 (machine->ram_slots ||
1863 (machine->maxram_size > machine->ram_size))) {
1864 MachineClass *mc = MACHINE_GET_CLASS(machine);
1865
1866 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1867 mc->name);
1868 exit(EXIT_FAILURE);
1869 }
1870
1871 /* always allocate the device memory information */
1872 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1873
1874 /* initialize device memory address space */
1875 if (pcmc->has_reserved_memory &&
1876 (machine->ram_size < machine->maxram_size)) {
1877 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1878
1879 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1880 error_report("unsupported amount of memory slots: %"PRIu64,
1881 machine->ram_slots);
1882 exit(EXIT_FAILURE);
1883 }
1884
1885 if (QEMU_ALIGN_UP(machine->maxram_size,
1886 TARGET_PAGE_SIZE) != machine->maxram_size) {
1887 error_report("maximum memory size must by aligned to multiple of "
1888 "%d bytes", TARGET_PAGE_SIZE);
1889 exit(EXIT_FAILURE);
1890 }
1891
1892 machine->device_memory->base =
1893 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1894
1895 if (pcmc->enforce_aligned_dimm) {
1896 /* size device region assuming 1G page max alignment per slot */
1897 device_mem_size += (1 * GiB) * machine->ram_slots;
1898 }
1899
1900 if ((machine->device_memory->base + device_mem_size) <
1901 device_mem_size) {
1902 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1903 machine->maxram_size);
1904 exit(EXIT_FAILURE);
1905 }
1906
1907 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1908 "device-memory", device_mem_size);
1909 memory_region_add_subregion(system_memory, machine->device_memory->base,
1910 &machine->device_memory->mr);
1911 }
1912
1913 /* Initialize PC system firmware */
1914 pc_system_firmware_init(pcms, rom_memory);
1915
1916 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1917 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1918 &error_fatal);
1919 if (pcmc->pci_enabled) {
1920 memory_region_set_readonly(option_rom_mr, true);
1921 }
1922 memory_region_add_subregion_overlap(rom_memory,
1923 PC_ROM_MIN_VGA,
1924 option_rom_mr,
1925 1);
1926
1927 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1928
1929 rom_set_fw(fw_cfg);
1930
1931 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1932 uint64_t *val = g_malloc(sizeof(*val));
1933 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1934 uint64_t res_mem_end = machine->device_memory->base;
1935
1936 if (!pcmc->broken_reserved_end) {
1937 res_mem_end += memory_region_size(&machine->device_memory->mr);
1938 }
1939 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1940 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1941 }
1942
1943 if (linux_boot) {
1944 load_linux(pcms, fw_cfg);
1945 }
1946
1947 for (i = 0; i < nb_option_roms; i++) {
1948 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1949 }
1950 pcms->fw_cfg = fw_cfg;
1951
1952 /* Init default IOAPIC address space */
1953 pcms->ioapic_as = &address_space_memory;
1954 }
1955
1956 /*
1957 * The 64bit pci hole starts after "above 4G RAM" and
1958 * potentially the space reserved for memory hotplug.
1959 */
1960 uint64_t pc_pci_hole64_start(void)
1961 {
1962 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1963 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1964 MachineState *ms = MACHINE(pcms);
1965 uint64_t hole64_start = 0;
1966
1967 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1968 hole64_start = ms->device_memory->base;
1969 if (!pcmc->broken_reserved_end) {
1970 hole64_start += memory_region_size(&ms->device_memory->mr);
1971 }
1972 } else {
1973 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1974 }
1975
1976 return ROUND_UP(hole64_start, 1 * GiB);
1977 }
1978
1979 qemu_irq pc_allocate_cpu_irq(void)
1980 {
1981 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1982 }
1983
1984 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1985 {
1986 DeviceState *dev = NULL;
1987
1988 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1989 if (pci_bus) {
1990 PCIDevice *pcidev = pci_vga_init(pci_bus);
1991 dev = pcidev ? &pcidev->qdev : NULL;
1992 } else if (isa_bus) {
1993 ISADevice *isadev = isa_vga_init(isa_bus);
1994 dev = isadev ? DEVICE(isadev) : NULL;
1995 }
1996 rom_reset_order_override();
1997 return dev;
1998 }
1999
2000 static const MemoryRegionOps ioport80_io_ops = {
2001 .write = ioport80_write,
2002 .read = ioport80_read,
2003 .endianness = DEVICE_NATIVE_ENDIAN,
2004 .impl = {
2005 .min_access_size = 1,
2006 .max_access_size = 1,
2007 },
2008 };
2009
2010 static const MemoryRegionOps ioportF0_io_ops = {
2011 .write = ioportF0_write,
2012 .read = ioportF0_read,
2013 .endianness = DEVICE_NATIVE_ENDIAN,
2014 .impl = {
2015 .min_access_size = 1,
2016 .max_access_size = 1,
2017 },
2018 };
2019
2020 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
2021 {
2022 int i;
2023 DriveInfo *fd[MAX_FD];
2024 qemu_irq *a20_line;
2025 ISADevice *i8042, *port92, *vmmouse;
2026
2027 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
2028 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
2029
2030 for (i = 0; i < MAX_FD; i++) {
2031 fd[i] = drive_get(IF_FLOPPY, 0, i);
2032 create_fdctrl |= !!fd[i];
2033 }
2034 if (create_fdctrl) {
2035 fdctrl_init_isa(isa_bus, fd);
2036 }
2037
2038 i8042 = isa_create_simple(isa_bus, "i8042");
2039 if (!no_vmport) {
2040 vmport_init(isa_bus);
2041 vmmouse = isa_try_create(isa_bus, "vmmouse");
2042 } else {
2043 vmmouse = NULL;
2044 }
2045 if (vmmouse) {
2046 DeviceState *dev = DEVICE(vmmouse);
2047 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
2048 qdev_init_nofail(dev);
2049 }
2050 port92 = isa_create_simple(isa_bus, "port92");
2051
2052 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
2053 i8042_setup_a20_line(i8042, a20_line[0]);
2054 port92_init(port92, a20_line[1]);
2055 g_free(a20_line);
2056 }
2057
2058 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
2059 ISADevice **rtc_state,
2060 bool create_fdctrl,
2061 bool no_vmport,
2062 bool has_pit,
2063 uint32_t hpet_irqs)
2064 {
2065 int i;
2066 DeviceState *hpet = NULL;
2067 int pit_isa_irq = 0;
2068 qemu_irq pit_alt_irq = NULL;
2069 qemu_irq rtc_irq = NULL;
2070 ISADevice *pit = NULL;
2071 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2072 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
2073
2074 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
2075 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
2076
2077 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
2078 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
2079
2080 /*
2081 * Check if an HPET shall be created.
2082 *
2083 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2084 * when the HPET wants to take over. Thus we have to disable the latter.
2085 */
2086 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
2087 /* In order to set property, here not using sysbus_try_create_simple */
2088 hpet = qdev_try_create(NULL, TYPE_HPET);
2089 if (hpet) {
2090 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2091 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2092 * IRQ8 and IRQ2.
2093 */
2094 uint8_t compat = object_property_get_uint(OBJECT(hpet),
2095 HPET_INTCAP, NULL);
2096 if (!compat) {
2097 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2098 }
2099 qdev_init_nofail(hpet);
2100 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2101
2102 for (i = 0; i < GSI_NUM_PINS; i++) {
2103 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
2104 }
2105 pit_isa_irq = -1;
2106 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2107 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
2108 }
2109 }
2110 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
2111
2112 qemu_register_boot_set(pc_boot_set, *rtc_state);
2113
2114 if (!xen_enabled() && has_pit) {
2115 if (kvm_pit_in_kernel()) {
2116 pit = kvm_pit_init(isa_bus, 0x40);
2117 } else {
2118 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
2119 }
2120 if (hpet) {
2121 /* connect PIT to output control line of the HPET */
2122 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
2123 }
2124 pcspk_init(isa_bus, pit);
2125 }
2126
2127 i8257_dma_init(isa_bus, 0);
2128
2129 /* Super I/O */
2130 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
2131 }
2132
2133 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
2134 {
2135 int i;
2136
2137 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
2138 for (i = 0; i < nb_nics; i++) {
2139 NICInfo *nd = &nd_table[i];
2140 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
2141
2142 if (g_str_equal(model, "ne2k_isa")) {
2143 pc_init_ne2k_isa(isa_bus, nd);
2144 } else {
2145 pci_nic_init_nofail(nd, pci_bus, model, NULL);
2146 }
2147 }
2148 rom_reset_order_override();
2149 }
2150
2151 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2152 {
2153 DeviceState *dev;
2154 SysBusDevice *d;
2155 unsigned int i;
2156
2157 if (kvm_ioapic_in_kernel()) {
2158 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
2159 } else {
2160 dev = qdev_create(NULL, TYPE_IOAPIC);
2161 }
2162 if (parent_name) {
2163 object_property_add_child(object_resolve_path(parent_name, NULL),
2164 "ioapic", OBJECT(dev), NULL);
2165 }
2166 qdev_init_nofail(dev);
2167 d = SYS_BUS_DEVICE(dev);
2168 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
2169
2170 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2171 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2172 }
2173 }
2174
2175 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2176 Error **errp)
2177 {
2178 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2179 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2180 const MachineState *ms = MACHINE(hotplug_dev);
2181 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2182 const uint64_t legacy_align = TARGET_PAGE_SIZE;
2183 Error *local_err = NULL;
2184
2185 /*
2186 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2187 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2188 * addition to cover this case.
2189 */
2190 if (!pcms->acpi_dev || !acpi_enabled) {
2191 error_setg(errp,
2192 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2193 return;
2194 }
2195
2196 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2197 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2198 return;
2199 }
2200
2201 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
2202 if (local_err) {
2203 error_propagate(errp, local_err);
2204 return;
2205 }
2206
2207 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
2208 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
2209 }
2210
2211 static void pc_memory_plug(HotplugHandler *hotplug_dev,
2212 DeviceState *dev, Error **errp)
2213 {
2214 Error *local_err = NULL;
2215 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2216 MachineState *ms = MACHINE(hotplug_dev);
2217 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2218
2219 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
2220 if (local_err) {
2221 goto out;
2222 }
2223
2224 if (is_nvdimm) {
2225 nvdimm_plug(ms->nvdimms_state);
2226 }
2227
2228 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
2229 out:
2230 error_propagate(errp, local_err);
2231 }
2232
2233 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2234 DeviceState *dev, Error **errp)
2235 {
2236 Error *local_err = NULL;
2237 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2238
2239 /*
2240 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2241 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2242 * addition to cover this case.
2243 */
2244 if (!pcms->acpi_dev || !acpi_enabled) {
2245 error_setg(&local_err,
2246 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2247 goto out;
2248 }
2249
2250 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2251 error_setg(&local_err,
2252 "nvdimm device hot unplug is not supported yet.");
2253 goto out;
2254 }
2255
2256 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2257 &local_err);
2258 out:
2259 error_propagate(errp, local_err);
2260 }
2261
2262 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2263 DeviceState *dev, Error **errp)
2264 {
2265 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2266 Error *local_err = NULL;
2267
2268 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2269 if (local_err) {
2270 goto out;
2271 }
2272
2273 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
2274 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2275 out:
2276 error_propagate(errp, local_err);
2277 }
2278
2279 static int pc_apic_cmp(const void *a, const void *b)
2280 {
2281 CPUArchId *apic_a = (CPUArchId *)a;
2282 CPUArchId *apic_b = (CPUArchId *)b;
2283
2284 return apic_a->arch_id - apic_b->arch_id;
2285 }
2286
2287 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2288 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2289 * entry corresponding to CPU's apic_id returns NULL.
2290 */
2291 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2292 {
2293 CPUArchId apic_id, *found_cpu;
2294
2295 apic_id.arch_id = id;
2296 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2297 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
2298 pc_apic_cmp);
2299 if (found_cpu && idx) {
2300 *idx = found_cpu - ms->possible_cpus->cpus;
2301 }
2302 return found_cpu;
2303 }
2304
2305 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2306 DeviceState *dev, Error **errp)
2307 {
2308 CPUArchId *found_cpu;
2309 Error *local_err = NULL;
2310 X86CPU *cpu = X86_CPU(dev);
2311 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2312
2313 if (pcms->acpi_dev) {
2314 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2315 if (local_err) {
2316 goto out;
2317 }
2318 }
2319
2320 /* increment the number of CPUs */
2321 pcms->boot_cpus++;
2322 if (pcms->rtc) {
2323 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2324 }
2325 if (pcms->fw_cfg) {
2326 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2327 }
2328
2329 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2330 found_cpu->cpu = OBJECT(dev);
2331 out:
2332 error_propagate(errp, local_err);
2333 }
2334 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2335 DeviceState *dev, Error **errp)
2336 {
2337 int idx = -1;
2338 Error *local_err = NULL;
2339 X86CPU *cpu = X86_CPU(dev);
2340 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2341
2342 if (!pcms->acpi_dev) {
2343 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2344 goto out;
2345 }
2346
2347 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2348 assert(idx != -1);
2349 if (idx == 0) {
2350 error_setg(&local_err, "Boot CPU is unpluggable");
2351 goto out;
2352 }
2353
2354 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2355 &local_err);
2356 if (local_err) {
2357 goto out;
2358 }
2359
2360 out:
2361 error_propagate(errp, local_err);
2362
2363 }
2364
2365 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2366 DeviceState *dev, Error **errp)
2367 {
2368 CPUArchId *found_cpu;
2369 Error *local_err = NULL;
2370 X86CPU *cpu = X86_CPU(dev);
2371 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2372
2373 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2374 if (local_err) {
2375 goto out;
2376 }
2377
2378 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2379 found_cpu->cpu = NULL;
2380 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2381
2382 /* decrement the number of CPUs */
2383 pcms->boot_cpus--;
2384 /* Update the number of CPUs in CMOS */
2385 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2386 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2387 out:
2388 error_propagate(errp, local_err);
2389 }
2390
2391 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2392 DeviceState *dev, Error **errp)
2393 {
2394 int idx;
2395 CPUState *cs;
2396 CPUArchId *cpu_slot;
2397 X86CPUTopoInfo topo;
2398 X86CPU *cpu = X86_CPU(dev);
2399 CPUX86State *env = &cpu->env;
2400 MachineState *ms = MACHINE(hotplug_dev);
2401 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2402 unsigned int smp_cores = ms->smp.cores;
2403 unsigned int smp_threads = ms->smp.threads;
2404
2405 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2406 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2407 ms->cpu_type);
2408 return;
2409 }
2410
2411 env->nr_dies = pcms->smp_dies;
2412
2413 /*
2414 * If APIC ID is not set,
2415 * set it based on socket/die/core/thread properties.
2416 */
2417 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2418 int max_socket = (ms->smp.max_cpus - 1) /
2419 smp_threads / smp_cores / pcms->smp_dies;
2420
2421 if (cpu->socket_id < 0) {
2422 error_setg(errp, "CPU socket-id is not set");
2423 return;
2424 } else if (cpu->socket_id > max_socket) {
2425 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2426 cpu->socket_id, max_socket);
2427 return;
2428 } else if (cpu->die_id > pcms->smp_dies - 1) {
2429 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
2430 cpu->die_id, max_socket);
2431 return;
2432 }
2433 if (cpu->core_id < 0) {
2434 error_setg(errp, "CPU core-id is not set");
2435 return;
2436 } else if (cpu->core_id > (smp_cores - 1)) {
2437 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2438 cpu->core_id, smp_cores - 1);
2439 return;
2440 }
2441 if (cpu->thread_id < 0) {
2442 error_setg(errp, "CPU thread-id is not set");
2443 return;
2444 } else if (cpu->thread_id > (smp_threads - 1)) {
2445 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2446 cpu->thread_id, smp_threads - 1);
2447 return;
2448 }
2449
2450 topo.pkg_id = cpu->socket_id;
2451 topo.die_id = cpu->die_id;
2452 topo.core_id = cpu->core_id;
2453 topo.smt_id = cpu->thread_id;
2454 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
2455 smp_threads, &topo);
2456 }
2457
2458 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2459 if (!cpu_slot) {
2460 MachineState *ms = MACHINE(pcms);
2461
2462 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2463 smp_cores, smp_threads, &topo);
2464 error_setg(errp,
2465 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
2466 " APIC ID %" PRIu32 ", valid index range 0:%d",
2467 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
2468 cpu->apic_id, ms->possible_cpus->len - 1);
2469 return;
2470 }
2471
2472 if (cpu_slot->cpu) {
2473 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2474 idx, cpu->apic_id);
2475 return;
2476 }
2477
2478 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2479 * so that machine_query_hotpluggable_cpus would show correct values
2480 */
2481 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2482 * once -smp refactoring is complete and there will be CPU private
2483 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2484 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2485 smp_cores, smp_threads, &topo);
2486 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2487 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2488 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2489 return;
2490 }
2491 cpu->socket_id = topo.pkg_id;
2492
2493 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
2494 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
2495 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
2496 return;
2497 }
2498 cpu->die_id = topo.die_id;
2499
2500 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2501 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2502 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2503 return;
2504 }
2505 cpu->core_id = topo.core_id;
2506
2507 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2508 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2509 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2510 return;
2511 }
2512 cpu->thread_id = topo.smt_id;
2513
2514 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
2515 !kvm_hv_vpindex_settable()) {
2516 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2517 return;
2518 }
2519
2520 cs = CPU(cpu);
2521 cs->cpu_index = idx;
2522
2523 numa_cpu_pre_plug(cpu_slot, dev, errp);
2524 }
2525
2526 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
2527 DeviceState *dev, Error **errp)
2528 {
2529 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2530 Error *local_err = NULL;
2531
2532 if (!hotplug_dev2) {
2533 /*
2534 * Without a bus hotplug handler, we cannot control the plug/unplug
2535 * order. This should never be the case on x86, however better add
2536 * a safety net.
2537 */
2538 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
2539 return;
2540 }
2541 /*
2542 * First, see if we can plug this memory device at all. If that
2543 * succeeds, branch of to the actual hotplug handler.
2544 */
2545 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
2546 &local_err);
2547 if (!local_err) {
2548 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
2549 }
2550 error_propagate(errp, local_err);
2551 }
2552
2553 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
2554 DeviceState *dev, Error **errp)
2555 {
2556 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2557 Error *local_err = NULL;
2558
2559 /*
2560 * Plug the memory device first and then branch off to the actual
2561 * hotplug handler. If that one fails, we can easily undo the memory
2562 * device bits.
2563 */
2564 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2565 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
2566 if (local_err) {
2567 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2568 }
2569 error_propagate(errp, local_err);
2570 }
2571
2572 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
2573 DeviceState *dev, Error **errp)
2574 {
2575 /* We don't support virtio pmem hot unplug */
2576 error_setg(errp, "virtio pmem device unplug not supported.");
2577 }
2578
2579 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
2580 DeviceState *dev, Error **errp)
2581 {
2582 /* We don't support virtio pmem hot unplug */
2583 }
2584
2585 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2586 DeviceState *dev, Error **errp)
2587 {
2588 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2589 pc_memory_pre_plug(hotplug_dev, dev, errp);
2590 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2591 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2592 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2593 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
2594 }
2595 }
2596
2597 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2598 DeviceState *dev, Error **errp)
2599 {
2600 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2601 pc_memory_plug(hotplug_dev, dev, errp);
2602 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2603 pc_cpu_plug(hotplug_dev, dev, errp);
2604 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2605 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
2606 }
2607 }
2608
2609 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2610 DeviceState *dev, Error **errp)
2611 {
2612 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2613 pc_memory_unplug_request(hotplug_dev, dev, errp);
2614 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2615 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2616 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2617 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
2618 } else {
2619 error_setg(errp, "acpi: device unplug request for not supported device"
2620 " type: %s", object_get_typename(OBJECT(dev)));
2621 }
2622 }
2623
2624 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2625 DeviceState *dev, Error **errp)
2626 {
2627 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2628 pc_memory_unplug(hotplug_dev, dev, errp);
2629 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2630 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2631 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2632 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
2633 } else {
2634 error_setg(errp, "acpi: device unplug for not supported device"
2635 " type: %s", object_get_typename(OBJECT(dev)));
2636 }
2637 }
2638
2639 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
2640 DeviceState *dev)
2641 {
2642 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2643 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
2644 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2645 return HOTPLUG_HANDLER(machine);
2646 }
2647
2648 return NULL;
2649 }
2650
2651 static void
2652 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2653 const char *name, void *opaque,
2654 Error **errp)
2655 {
2656 MachineState *ms = MACHINE(obj);
2657 int64_t value = 0;
2658
2659 if (ms->device_memory) {
2660 value = memory_region_size(&ms->device_memory->mr);
2661 }
2662
2663 visit_type_int(v, name, &value, errp);
2664 }
2665
2666 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2667 const char *name, void *opaque,
2668 Error **errp)
2669 {
2670 PCMachineState *pcms = PC_MACHINE(obj);
2671 uint64_t value = pcms->max_ram_below_4g;
2672
2673 visit_type_size(v, name, &value, errp);
2674 }
2675
2676 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2677 const char *name, void *opaque,
2678 Error **errp)
2679 {
2680 PCMachineState *pcms = PC_MACHINE(obj);
2681 Error *error = NULL;
2682 uint64_t value;
2683
2684 visit_type_size(v, name, &value, &error);
2685 if (error) {
2686 error_propagate(errp, error);
2687 return;
2688 }
2689 if (value > 4 * GiB) {
2690 error_setg(&error,
2691 "Machine option 'max-ram-below-4g=%"PRIu64
2692 "' expects size less than or equal to 4G", value);
2693 error_propagate(errp, error);
2694 return;
2695 }
2696
2697 if (value < 1 * MiB) {
2698 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2699 "BIOS may not work with less than 1MiB", value);
2700 }
2701
2702 pcms->max_ram_below_4g = value;
2703 }
2704
2705 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2706 void *opaque, Error **errp)
2707 {
2708 PCMachineState *pcms = PC_MACHINE(obj);
2709 OnOffAuto vmport = pcms->vmport;
2710
2711 visit_type_OnOffAuto(v, name, &vmport, errp);
2712 }
2713
2714 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2715 void *opaque, Error **errp)
2716 {
2717 PCMachineState *pcms = PC_MACHINE(obj);
2718
2719 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2720 }
2721
2722 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2723 {
2724 bool smm_available = false;
2725
2726 if (pcms->smm == ON_OFF_AUTO_OFF) {
2727 return false;
2728 }
2729
2730 if (tcg_enabled() || qtest_enabled()) {
2731 smm_available = true;
2732 } else if (kvm_enabled()) {
2733 smm_available = kvm_has_smm();
2734 }
2735
2736 if (smm_available) {
2737 return true;
2738 }
2739
2740 if (pcms->smm == ON_OFF_AUTO_ON) {
2741 error_report("System Management Mode not supported by this hypervisor.");
2742 exit(1);
2743 }
2744 return false;
2745 }
2746
2747 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2748 void *opaque, Error **errp)
2749 {
2750 PCMachineState *pcms = PC_MACHINE(obj);
2751 OnOffAuto smm = pcms->smm;
2752
2753 visit_type_OnOffAuto(v, name, &smm, errp);
2754 }
2755
2756 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2757 void *opaque, Error **errp)
2758 {
2759 PCMachineState *pcms = PC_MACHINE(obj);
2760
2761 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2762 }
2763
2764 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2765 {
2766 PCMachineState *pcms = PC_MACHINE(obj);
2767
2768 return pcms->smbus_enabled;
2769 }
2770
2771 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2772 {
2773 PCMachineState *pcms = PC_MACHINE(obj);
2774
2775 pcms->smbus_enabled = value;
2776 }
2777
2778 static bool pc_machine_get_sata(Object *obj, Error **errp)
2779 {
2780 PCMachineState *pcms = PC_MACHINE(obj);
2781
2782 return pcms->sata_enabled;
2783 }
2784
2785 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2786 {
2787 PCMachineState *pcms = PC_MACHINE(obj);
2788
2789 pcms->sata_enabled = value;
2790 }
2791
2792 static bool pc_machine_get_pit(Object *obj, Error **errp)
2793 {
2794 PCMachineState *pcms = PC_MACHINE(obj);
2795
2796 return pcms->pit_enabled;
2797 }
2798
2799 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2800 {
2801 PCMachineState *pcms = PC_MACHINE(obj);
2802
2803 pcms->pit_enabled = value;
2804 }
2805
2806 static void pc_machine_initfn(Object *obj)
2807 {
2808 PCMachineState *pcms = PC_MACHINE(obj);
2809
2810 pcms->max_ram_below_4g = 0; /* use default */
2811 pcms->smm = ON_OFF_AUTO_AUTO;
2812 #ifdef CONFIG_VMPORT
2813 pcms->vmport = ON_OFF_AUTO_AUTO;
2814 #else
2815 pcms->vmport = ON_OFF_AUTO_OFF;
2816 #endif /* CONFIG_VMPORT */
2817 /* acpi build is enabled by default if machine supports it */
2818 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2819 pcms->smbus_enabled = true;
2820 pcms->sata_enabled = true;
2821 pcms->pit_enabled = true;
2822 pcms->smp_dies = 1;
2823
2824 pc_system_flash_create(pcms);
2825 }
2826
2827 static void pc_machine_reset(MachineState *machine)
2828 {
2829 CPUState *cs;
2830 X86CPU *cpu;
2831
2832 qemu_devices_reset();
2833
2834 /* Reset APIC after devices have been reset to cancel
2835 * any changes that qemu_devices_reset() might have done.
2836 */
2837 CPU_FOREACH(cs) {
2838 cpu = X86_CPU(cs);
2839
2840 if (cpu->apic_state) {
2841 device_reset(cpu->apic_state);
2842 }
2843 }
2844 }
2845
2846 static void pc_machine_wakeup(MachineState *machine)
2847 {
2848 cpu_synchronize_all_states();
2849 pc_machine_reset(machine);
2850 cpu_synchronize_all_post_reset();
2851 }
2852
2853 static CpuInstanceProperties
2854 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2855 {
2856 MachineClass *mc = MACHINE_GET_CLASS(ms);
2857 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2858
2859 assert(cpu_index < possible_cpus->len);
2860 return possible_cpus->cpus[cpu_index].props;
2861 }
2862
2863 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2864 {
2865 X86CPUTopoInfo topo;
2866 PCMachineState *pcms = PC_MACHINE(ms);
2867
2868 assert(idx < ms->possible_cpus->len);
2869 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2870 pcms->smp_dies, ms->smp.cores,
2871 ms->smp.threads, &topo);
2872 return topo.pkg_id % nb_numa_nodes;
2873 }
2874
2875 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2876 {
2877 PCMachineState *pcms = PC_MACHINE(ms);
2878 int i;
2879 unsigned int max_cpus = ms->smp.max_cpus;
2880
2881 if (ms->possible_cpus) {
2882 /*
2883 * make sure that max_cpus hasn't changed since the first use, i.e.
2884 * -smp hasn't been parsed after it
2885 */
2886 assert(ms->possible_cpus->len == max_cpus);
2887 return ms->possible_cpus;
2888 }
2889
2890 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2891 sizeof(CPUArchId) * max_cpus);
2892 ms->possible_cpus->len = max_cpus;
2893 for (i = 0; i < ms->possible_cpus->len; i++) {
2894 X86CPUTopoInfo topo;
2895
2896 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2897 ms->possible_cpus->cpus[i].vcpus_count = 1;
2898 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
2899 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2900 pcms->smp_dies, ms->smp.cores,
2901 ms->smp.threads, &topo);
2902 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2903 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2904 ms->possible_cpus->cpus[i].props.has_die_id = true;
2905 ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
2906 ms->possible_cpus->cpus[i].props.has_core_id = true;
2907 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2908 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2909 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2910 }
2911 return ms->possible_cpus;
2912 }
2913
2914 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2915 {
2916 /* cpu index isn't used */
2917 CPUState *cs;
2918
2919 CPU_FOREACH(cs) {
2920 X86CPU *cpu = X86_CPU(cs);
2921
2922 if (!cpu->apic_state) {
2923 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2924 } else {
2925 apic_deliver_nmi(cpu->apic_state);
2926 }
2927 }
2928 }
2929
2930 static void pc_machine_class_init(ObjectClass *oc, void *data)
2931 {
2932 MachineClass *mc = MACHINE_CLASS(oc);
2933 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2934 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2935 NMIClass *nc = NMI_CLASS(oc);
2936
2937 pcmc->pci_enabled = true;
2938 pcmc->has_acpi_build = true;
2939 pcmc->rsdp_in_ram = true;
2940 pcmc->smbios_defaults = true;
2941 pcmc->smbios_uuid_encoded = true;
2942 pcmc->gigabyte_align = true;
2943 pcmc->has_reserved_memory = true;
2944 pcmc->kvmclock_enabled = true;
2945 pcmc->enforce_aligned_dimm = true;
2946 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2947 * to be used at the moment, 32K should be enough for a while. */
2948 pcmc->acpi_data_size = 0x20000 + 0x8000;
2949 pcmc->save_tsc_khz = true;
2950 pcmc->linuxboot_dma_enabled = true;
2951 pcmc->pvh_enabled = true;
2952 assert(!mc->get_hotplug_handler);
2953 mc->get_hotplug_handler = pc_get_hotplug_handler;
2954 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2955 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2956 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2957 mc->auto_enable_numa_with_memhp = true;
2958 mc->has_hotpluggable_cpus = true;
2959 mc->default_boot_order = "cad";
2960 mc->hot_add_cpu = pc_hot_add_cpu;
2961 mc->smp_parse = pc_smp_parse;
2962 mc->block_default_type = IF_IDE;
2963 mc->max_cpus = 255;
2964 mc->reset = pc_machine_reset;
2965 mc->wakeup = pc_machine_wakeup;
2966 hc->pre_plug = pc_machine_device_pre_plug_cb;
2967 hc->plug = pc_machine_device_plug_cb;
2968 hc->unplug_request = pc_machine_device_unplug_request_cb;
2969 hc->unplug = pc_machine_device_unplug_cb;
2970 nc->nmi_monitor_handler = x86_nmi;
2971 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2972 mc->nvdimm_supported = true;
2973 mc->numa_mem_supported = true;
2974
2975 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2976 pc_machine_get_device_memory_region_size, NULL,
2977 NULL, NULL, &error_abort);
2978
2979 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2980 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2981 NULL, NULL, &error_abort);
2982
2983 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2984 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2985
2986 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2987 pc_machine_get_smm, pc_machine_set_smm,
2988 NULL, NULL, &error_abort);
2989 object_class_property_set_description(oc, PC_MACHINE_SMM,
2990 "Enable SMM (pc & q35)", &error_abort);
2991
2992 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2993 pc_machine_get_vmport, pc_machine_set_vmport,
2994 NULL, NULL, &error_abort);
2995 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2996 "Enable vmport (pc & q35)", &error_abort);
2997
2998 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2999 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
3000
3001 object_class_property_add_bool(oc, PC_MACHINE_SATA,
3002 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
3003
3004 object_class_property_add_bool(oc, PC_MACHINE_PIT,
3005 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
3006 }
3007
3008 static const TypeInfo pc_machine_info = {
3009 .name = TYPE_PC_MACHINE,
3010 .parent = TYPE_MACHINE,
3011 .abstract = true,
3012 .instance_size = sizeof(PCMachineState),
3013 .instance_init = pc_machine_initfn,
3014 .class_size = sizeof(PCMachineClass),
3015 .class_init = pc_machine_class_init,
3016 .interfaces = (InterfaceInfo[]) {
3017 { TYPE_HOTPLUG_HANDLER },
3018 { TYPE_NMI },
3019 { }
3020 },
3021 };
3022
3023 static void pc_machine_register_types(void)
3024 {
3025 type_register_static(&pc_machine_info);
3026 }
3027
3028 type_init(pc_machine_register_types)
AR7 emulation for QEMU