trace: switch position of headers to what Meson requires
[qemu/ar7.git] / target / xtensa / core-dc232b / xtensa-modules.inc.c
blob164df3b1a472f7cda2dabc365c79096fb4286252
1 /* Xtensa configuration-specific ISA information.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 2 of the
9 License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
21 #include "qemu/osdep.h"
22 #include "xtensa-isa.h"
23 #include "xtensa-isa-internal.h"
26 /* Sysregs. */
28 static xtensa_sysreg_internal sysregs[] = {
29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
39 { "MMID", 89, 0 },
40 { "DDR", 104, 0 },
41 { "176", 176, 0 },
42 { "208", 208, 0 },
43 { "INTERRUPT", 226, 0 },
44 { "INTCLEAR", 227, 0 },
45 { "CCOUNT", 234, 0 },
46 { "PRID", 235, 0 },
47 { "ICOUNT", 236, 0 },
48 { "CCOMPARE0", 240, 0 },
49 { "CCOMPARE1", 241, 0 },
50 { "CCOMPARE2", 242, 0 },
51 { "VECBASE", 231, 0 },
52 { "EPC1", 177, 0 },
53 { "EPC2", 178, 0 },
54 { "EPC3", 179, 0 },
55 { "EPC4", 180, 0 },
56 { "EPC5", 181, 0 },
57 { "EPC6", 182, 0 },
58 { "EPC7", 183, 0 },
59 { "EXCSAVE1", 209, 0 },
60 { "EXCSAVE2", 210, 0 },
61 { "EXCSAVE3", 211, 0 },
62 { "EXCSAVE4", 212, 0 },
63 { "EXCSAVE5", 213, 0 },
64 { "EXCSAVE6", 214, 0 },
65 { "EXCSAVE7", 215, 0 },
66 { "EPS2", 194, 0 },
67 { "EPS3", 195, 0 },
68 { "EPS4", 196, 0 },
69 { "EPS5", 197, 0 },
70 { "EPS6", 198, 0 },
71 { "EPS7", 199, 0 },
72 { "EXCCAUSE", 232, 0 },
73 { "DEPC", 192, 0 },
74 { "EXCVADDR", 238, 0 },
75 { "WINDOWBASE", 72, 0 },
76 { "WINDOWSTART", 73, 0 },
77 { "SAR", 3, 0 },
78 { "LITBASE", 5, 0 },
79 { "PS", 230, 0 },
80 { "MISC0", 244, 0 },
81 { "MISC1", 245, 0 },
82 { "INTENABLE", 228, 0 },
83 { "DBREAKA0", 144, 0 },
84 { "DBREAKC0", 160, 0 },
85 { "DBREAKA1", 145, 0 },
86 { "DBREAKC1", 161, 0 },
87 { "IBREAKA0", 128, 0 },
88 { "IBREAKA1", 129, 0 },
89 { "IBREAKENABLE", 96, 0 },
90 { "ICOUNTLEVEL", 237, 0 },
91 { "DEBUGCAUSE", 233, 0 },
92 { "RASID", 90, 0 },
93 { "ITLBCFG", 91, 0 },
94 { "DTLBCFG", 92, 0 },
95 { "CPENABLE", 224, 0 },
96 { "SCOMPARE1", 12, 0 },
97 { "THREADPTR", 231, 1 },
98 { "EXPSTATE", 230, 1 }
101 #define NUM_SYSREGS 70
102 #define MAX_SPECIAL_REG 245
103 #define MAX_USER_REG 231
106 /* Processor states. */
108 static xtensa_state_internal states[] = {
109 { "LCOUNT", 32, 0 },
110 { "PC", 32, 0 },
111 { "ICOUNT", 32, 0 },
112 { "DDR", 32, 0 },
113 { "INTERRUPT", 22, 0 },
114 { "CCOUNT", 32, 0 },
115 { "XTSYNC", 1, 0 },
116 { "VECBASE", 22, 0 },
117 { "EPC1", 32, 0 },
118 { "EPC2", 32, 0 },
119 { "EPC3", 32, 0 },
120 { "EPC4", 32, 0 },
121 { "EPC5", 32, 0 },
122 { "EPC6", 32, 0 },
123 { "EPC7", 32, 0 },
124 { "EXCSAVE1", 32, 0 },
125 { "EXCSAVE2", 32, 0 },
126 { "EXCSAVE3", 32, 0 },
127 { "EXCSAVE4", 32, 0 },
128 { "EXCSAVE5", 32, 0 },
129 { "EXCSAVE6", 32, 0 },
130 { "EXCSAVE7", 32, 0 },
131 { "EPS2", 15, 0 },
132 { "EPS3", 15, 0 },
133 { "EPS4", 15, 0 },
134 { "EPS5", 15, 0 },
135 { "EPS6", 15, 0 },
136 { "EPS7", 15, 0 },
137 { "EXCCAUSE", 6, 0 },
138 { "PSINTLEVEL", 4, 0 },
139 { "PSUM", 1, 0 },
140 { "PSWOE", 1, 0 },
141 { "PSRING", 2, 0 },
142 { "PSEXCM", 1, 0 },
143 { "DEPC", 32, 0 },
144 { "EXCVADDR", 32, 0 },
145 { "WindowBase", 3, 0 },
146 { "WindowStart", 8, 0 },
147 { "PSCALLINC", 2, 0 },
148 { "PSOWB", 4, 0 },
149 { "LBEG", 32, 0 },
150 { "LEND", 32, 0 },
151 { "SAR", 6, 0 },
152 { "THREADPTR", 32, 0 },
153 { "LITBADDR", 20, 0 },
154 { "LITBEN", 1, 0 },
155 { "MISC0", 32, 0 },
156 { "MISC1", 32, 0 },
157 { "ACC", 40, 0 },
158 { "InOCDMode", 1, 0 },
159 { "INTENABLE", 22, 0 },
160 { "DBREAKA0", 32, 0 },
161 { "DBREAKC0", 8, 0 },
162 { "DBREAKA1", 32, 0 },
163 { "DBREAKC1", 8, 0 },
164 { "IBREAKA0", 32, 0 },
165 { "IBREAKA1", 32, 0 },
166 { "IBREAKENABLE", 2, 0 },
167 { "ICOUNTLEVEL", 4, 0 },
168 { "DEBUGCAUSE", 6, 0 },
169 { "DBNUM", 4, 0 },
170 { "CCOMPARE0", 32, 0 },
171 { "CCOMPARE1", 32, 0 },
172 { "CCOMPARE2", 32, 0 },
173 { "ASID3", 8, 0 },
174 { "ASID2", 8, 0 },
175 { "ASID1", 8, 0 },
176 { "INSTPGSZID4", 2, 0 },
177 { "DATAPGSZID4", 2, 0 },
178 { "PTBASE", 10, 0 },
179 { "CPENABLE", 8, 0 },
180 { "SCOMPARE1", 32, 0 },
181 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
184 #define NUM_STATES 73
186 /* Macros for xtensa_state numbers (for use in iclasses because the
187 state numbers are not available when the iclass table is generated). */
189 #define STATE_LCOUNT 0
190 #define STATE_PC 1
191 #define STATE_ICOUNT 2
192 #define STATE_DDR 3
193 #define STATE_INTERRUPT 4
194 #define STATE_CCOUNT 5
195 #define STATE_XTSYNC 6
196 #define STATE_VECBASE 7
197 #define STATE_EPC1 8
198 #define STATE_EPC2 9
199 #define STATE_EPC3 10
200 #define STATE_EPC4 11
201 #define STATE_EPC5 12
202 #define STATE_EPC6 13
203 #define STATE_EPC7 14
204 #define STATE_EXCSAVE1 15
205 #define STATE_EXCSAVE2 16
206 #define STATE_EXCSAVE3 17
207 #define STATE_EXCSAVE4 18
208 #define STATE_EXCSAVE5 19
209 #define STATE_EXCSAVE6 20
210 #define STATE_EXCSAVE7 21
211 #define STATE_EPS2 22
212 #define STATE_EPS3 23
213 #define STATE_EPS4 24
214 #define STATE_EPS5 25
215 #define STATE_EPS6 26
216 #define STATE_EPS7 27
217 #define STATE_EXCCAUSE 28
218 #define STATE_PSINTLEVEL 29
219 #define STATE_PSUM 30
220 #define STATE_PSWOE 31
221 #define STATE_PSRING 32
222 #define STATE_PSEXCM 33
223 #define STATE_DEPC 34
224 #define STATE_EXCVADDR 35
225 #define STATE_WindowBase 36
226 #define STATE_WindowStart 37
227 #define STATE_PSCALLINC 38
228 #define STATE_PSOWB 39
229 #define STATE_LBEG 40
230 #define STATE_LEND 41
231 #define STATE_SAR 42
232 #define STATE_THREADPTR 43
233 #define STATE_LITBADDR 44
234 #define STATE_LITBEN 45
235 #define STATE_MISC0 46
236 #define STATE_MISC1 47
237 #define STATE_ACC 48
238 #define STATE_InOCDMode 49
239 #define STATE_INTENABLE 50
240 #define STATE_DBREAKA0 51
241 #define STATE_DBREAKC0 52
242 #define STATE_DBREAKA1 53
243 #define STATE_DBREAKC1 54
244 #define STATE_IBREAKA0 55
245 #define STATE_IBREAKA1 56
246 #define STATE_IBREAKENABLE 57
247 #define STATE_ICOUNTLEVEL 58
248 #define STATE_DEBUGCAUSE 59
249 #define STATE_DBNUM 60
250 #define STATE_CCOMPARE0 61
251 #define STATE_CCOMPARE1 62
252 #define STATE_CCOMPARE2 63
253 #define STATE_ASID3 64
254 #define STATE_ASID2 65
255 #define STATE_ASID1 66
256 #define STATE_INSTPGSZID4 67
257 #define STATE_DATAPGSZID4 68
258 #define STATE_PTBASE 69
259 #define STATE_CPENABLE 70
260 #define STATE_SCOMPARE1 71
261 #define STATE_EXPSTATE 72
264 /* Field definitions. */
266 static unsigned
267 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
269 unsigned tie_t = 0;
270 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
271 return tie_t;
274 static void
275 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
277 uint32 tie_t;
278 tie_t = (val << 28) >> 28;
279 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
282 static unsigned
283 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
285 unsigned tie_t = 0;
286 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
287 return tie_t;
290 static void
291 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
293 uint32 tie_t;
294 tie_t = (val << 28) >> 28;
295 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
298 static unsigned
299 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
301 unsigned tie_t = 0;
302 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
303 return tie_t;
306 static void
307 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
309 uint32 tie_t;
310 tie_t = (val << 28) >> 28;
311 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
314 static unsigned
315 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
317 unsigned tie_t = 0;
318 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
319 return tie_t;
322 static void
323 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
325 uint32 tie_t;
326 tie_t = (val << 31) >> 31;
327 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
330 static unsigned
331 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
333 unsigned tie_t = 0;
334 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
335 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
336 return tie_t;
339 static void
340 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
342 uint32 tie_t;
343 tie_t = (val << 28) >> 28;
344 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
345 tie_t = (val << 27) >> 31;
346 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
349 static unsigned
350 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
352 unsigned tie_t = 0;
353 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
354 return tie_t;
357 static void
358 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
360 uint32 tie_t;
361 tie_t = (val << 20) >> 20;
362 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
365 static unsigned
366 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
368 unsigned tie_t = 0;
369 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
370 return tie_t;
373 static void
374 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
376 uint32 tie_t;
377 tie_t = (val << 24) >> 24;
378 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
381 static unsigned
382 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
384 unsigned tie_t = 0;
385 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
386 return tie_t;
389 static void
390 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
392 uint32 tie_t;
393 tie_t = (val << 28) >> 28;
394 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
397 static unsigned
398 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
400 unsigned tie_t = 0;
401 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
402 return tie_t;
405 static void
406 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
408 uint32 tie_t;
409 tie_t = (val << 28) >> 28;
410 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
413 static unsigned
414 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
416 unsigned tie_t = 0;
417 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
418 return tie_t;
421 static void
422 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
424 uint32 tie_t;
425 tie_t = (val << 28) >> 28;
426 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
429 static unsigned
430 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
432 unsigned tie_t = 0;
433 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
434 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
435 return tie_t;
438 static void
439 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
441 uint32 tie_t;
442 tie_t = (val << 24) >> 24;
443 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
444 tie_t = (val << 20) >> 28;
445 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
448 static unsigned
449 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
451 unsigned tie_t = 0;
452 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
453 return tie_t;
456 static void
457 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
459 uint32 tie_t;
460 tie_t = (val << 16) >> 16;
461 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
464 static unsigned
465 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
467 unsigned tie_t = 0;
468 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
469 return tie_t;
472 static void
473 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
475 uint32 tie_t;
476 tie_t = (val << 30) >> 30;
477 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
480 static unsigned
481 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
483 unsigned tie_t = 0;
484 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
485 return tie_t;
488 static void
489 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
491 uint32 tie_t;
492 tie_t = (val << 30) >> 30;
493 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
496 static unsigned
497 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
499 unsigned tie_t = 0;
500 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
501 return tie_t;
504 static void
505 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
507 uint32 tie_t;
508 tie_t = (val << 14) >> 14;
509 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
512 static unsigned
513 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
515 unsigned tie_t = 0;
516 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
517 return tie_t;
520 static void
521 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
523 uint32 tie_t;
524 tie_t = (val << 28) >> 28;
525 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
528 static unsigned
529 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
531 unsigned tie_t = 0;
532 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
533 return tie_t;
536 static void
537 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
539 uint32 tie_t;
540 tie_t = (val << 28) >> 28;
541 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
544 static unsigned
545 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
547 unsigned tie_t = 0;
548 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
549 return tie_t;
552 static void
553 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
555 uint32 tie_t;
556 tie_t = (val << 28) >> 28;
557 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
560 static unsigned
561 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
563 unsigned tie_t = 0;
564 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
565 return tie_t;
568 static void
569 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
571 uint32 tie_t;
572 tie_t = (val << 28) >> 28;
573 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
576 static unsigned
577 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
579 unsigned tie_t = 0;
580 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
581 return tie_t;
584 static void
585 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
587 uint32 tie_t;
588 tie_t = (val << 28) >> 28;
589 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
592 static unsigned
593 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
595 unsigned tie_t = 0;
596 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
597 return tie_t;
600 static void
601 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
603 uint32 tie_t;
604 tie_t = (val << 28) >> 28;
605 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
608 static unsigned
609 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
611 unsigned tie_t = 0;
612 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
613 return tie_t;
616 static void
617 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
619 uint32 tie_t;
620 tie_t = (val << 28) >> 28;
621 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
624 static unsigned
625 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
627 unsigned tie_t = 0;
628 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
629 return tie_t;
632 static void
633 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
635 uint32 tie_t;
636 tie_t = (val << 28) >> 28;
637 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
640 static unsigned
641 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
643 unsigned tie_t = 0;
644 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
645 return tie_t;
648 static void
649 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
651 uint32 tie_t;
652 tie_t = (val << 31) >> 31;
653 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
656 static unsigned
657 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
659 unsigned tie_t = 0;
660 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
661 return tie_t;
664 static void
665 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
667 uint32 tie_t;
668 tie_t = (val << 31) >> 31;
669 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
672 static unsigned
673 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
675 unsigned tie_t = 0;
676 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
677 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
678 return tie_t;
681 static void
682 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
684 uint32 tie_t;
685 tie_t = (val << 28) >> 28;
686 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
687 tie_t = (val << 27) >> 31;
688 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
691 static unsigned
692 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
694 unsigned tie_t = 0;
695 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
696 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
697 return tie_t;
700 static void
701 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
703 uint32 tie_t;
704 tie_t = (val << 28) >> 28;
705 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
706 tie_t = (val << 27) >> 31;
707 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
710 static unsigned
711 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
713 unsigned tie_t = 0;
714 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
715 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
716 return tie_t;
719 static void
720 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
722 uint32 tie_t;
723 tie_t = (val << 28) >> 28;
724 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
725 tie_t = (val << 27) >> 31;
726 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
729 static unsigned
730 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
732 unsigned tie_t = 0;
733 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
734 return tie_t;
737 static void
738 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
740 uint32 tie_t;
741 tie_t = (val << 31) >> 31;
742 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
745 static unsigned
746 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
748 unsigned tie_t = 0;
749 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
750 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
751 return tie_t;
754 static void
755 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
757 uint32 tie_t;
758 tie_t = (val << 28) >> 28;
759 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
760 tie_t = (val << 27) >> 31;
761 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
764 static unsigned
765 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
767 unsigned tie_t = 0;
768 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
769 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
770 return tie_t;
773 static void
774 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
776 uint32 tie_t;
777 tie_t = (val << 28) >> 28;
778 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
779 tie_t = (val << 24) >> 28;
780 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
783 static unsigned
784 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
786 unsigned tie_t = 0;
787 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
788 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
789 return tie_t;
792 static void
793 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
795 uint32 tie_t;
796 tie_t = (val << 28) >> 28;
797 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
798 tie_t = (val << 24) >> 28;
799 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
802 static unsigned
803 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
805 unsigned tie_t = 0;
806 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
807 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
808 return tie_t;
811 static void
812 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
814 uint32 tie_t;
815 tie_t = (val << 28) >> 28;
816 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
817 tie_t = (val << 24) >> 28;
818 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
821 static unsigned
822 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
824 unsigned tie_t = 0;
825 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
826 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
827 return tie_t;
830 static void
831 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
833 uint32 tie_t;
834 tie_t = (val << 28) >> 28;
835 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
836 tie_t = (val << 24) >> 28;
837 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
840 static unsigned
841 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
843 unsigned tie_t = 0;
844 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
845 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
846 return tie_t;
849 static void
850 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
852 uint32 tie_t;
853 tie_t = (val << 28) >> 28;
854 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
855 tie_t = (val << 24) >> 28;
856 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
859 static unsigned
860 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
862 unsigned tie_t = 0;
863 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
864 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
865 return tie_t;
868 static void
869 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
871 uint32 tie_t;
872 tie_t = (val << 28) >> 28;
873 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
874 tie_t = (val << 24) >> 28;
875 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
878 static unsigned
879 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
881 unsigned tie_t = 0;
882 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
883 return tie_t;
886 static void
887 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
889 uint32 tie_t;
890 tie_t = (val << 29) >> 29;
891 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
894 static unsigned
895 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
897 unsigned tie_t = 0;
898 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
899 return tie_t;
902 static void
903 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
905 uint32 tie_t;
906 tie_t = (val << 28) >> 28;
907 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
910 static unsigned
911 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
913 unsigned tie_t = 0;
914 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
915 return tie_t;
918 static void
919 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
921 uint32 tie_t;
922 tie_t = (val << 28) >> 28;
923 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
926 static unsigned
927 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
929 unsigned tie_t = 0;
930 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
931 return tie_t;
934 static void
935 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
937 uint32 tie_t;
938 tie_t = (val << 28) >> 28;
939 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
942 static unsigned
943 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
945 unsigned tie_t = 0;
946 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
947 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
948 return tie_t;
951 static void
952 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
954 uint32 tie_t;
955 tie_t = (val << 30) >> 30;
956 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
957 tie_t = (val << 28) >> 30;
958 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
961 static unsigned
962 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
964 unsigned tie_t = 0;
965 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
966 return tie_t;
969 static void
970 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
972 uint32 tie_t;
973 tie_t = (val << 31) >> 31;
974 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
977 static unsigned
978 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
980 unsigned tie_t = 0;
981 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
982 return tie_t;
985 static void
986 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
988 uint32 tie_t;
989 tie_t = (val << 31) >> 31;
990 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
993 static unsigned
994 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
996 unsigned tie_t = 0;
997 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
998 return tie_t;
1001 static void
1002 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1004 uint32 tie_t;
1005 tie_t = (val << 28) >> 28;
1006 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1009 static unsigned
1010 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1012 unsigned tie_t = 0;
1013 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1014 return tie_t;
1017 static void
1018 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1020 uint32 tie_t;
1021 tie_t = (val << 28) >> 28;
1022 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1025 static unsigned
1026 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1028 unsigned tie_t = 0;
1029 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1030 return tie_t;
1033 static void
1034 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1036 uint32 tie_t;
1037 tie_t = (val << 30) >> 30;
1038 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1041 static unsigned
1042 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1044 unsigned tie_t = 0;
1045 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1046 return tie_t;
1049 static void
1050 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1052 uint32 tie_t;
1053 tie_t = (val << 30) >> 30;
1054 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1057 static unsigned
1058 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1060 unsigned tie_t = 0;
1061 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1062 return tie_t;
1065 static void
1066 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1068 uint32 tie_t;
1069 tie_t = (val << 28) >> 28;
1070 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1073 static unsigned
1074 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1076 unsigned tie_t = 0;
1077 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1078 return tie_t;
1081 static void
1082 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1084 uint32 tie_t;
1085 tie_t = (val << 28) >> 28;
1086 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1089 static unsigned
1090 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1092 unsigned tie_t = 0;
1093 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1094 return tie_t;
1097 static void
1098 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1100 uint32 tie_t;
1101 tie_t = (val << 29) >> 29;
1102 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1105 static unsigned
1106 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1108 unsigned tie_t = 0;
1109 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1110 return tie_t;
1113 static void
1114 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1116 uint32 tie_t;
1117 tie_t = (val << 29) >> 29;
1118 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1121 static unsigned
1122 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1124 unsigned tie_t = 0;
1125 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1126 return tie_t;
1129 static void
1130 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1132 uint32 tie_t;
1133 tie_t = (val << 31) >> 31;
1134 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1137 static unsigned
1138 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1140 unsigned tie_t = 0;
1141 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1142 return tie_t;
1145 static void
1146 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1148 uint32 tie_t;
1149 tie_t = (val << 31) >> 31;
1150 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1153 static unsigned
1154 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1156 unsigned tie_t = 0;
1157 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1158 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1159 return tie_t;
1162 static void
1163 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1165 uint32 tie_t;
1166 tie_t = (val << 28) >> 28;
1167 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1168 tie_t = (val << 26) >> 30;
1169 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1172 static unsigned
1173 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1175 unsigned tie_t = 0;
1176 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1177 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1178 return tie_t;
1181 static void
1182 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1184 uint32 tie_t;
1185 tie_t = (val << 28) >> 28;
1186 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1187 tie_t = (val << 26) >> 30;
1188 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1191 static unsigned
1192 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1194 unsigned tie_t = 0;
1195 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1196 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1197 return tie_t;
1200 static void
1201 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1203 uint32 tie_t;
1204 tie_t = (val << 28) >> 28;
1205 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1206 tie_t = (val << 25) >> 29;
1207 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1210 static unsigned
1211 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1213 unsigned tie_t = 0;
1214 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1215 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1216 return tie_t;
1219 static void
1220 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1222 uint32 tie_t;
1223 tie_t = (val << 28) >> 28;
1224 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1225 tie_t = (val << 25) >> 29;
1226 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1229 static unsigned
1230 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
1232 unsigned tie_t = 0;
1233 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1234 return tie_t;
1237 static void
1238 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1240 uint32 tie_t;
1241 tie_t = (val << 31) >> 31;
1242 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1245 static unsigned
1246 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1248 unsigned tie_t = 0;
1249 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1250 return tie_t;
1253 static void
1254 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1256 uint32 tie_t;
1257 tie_t = (val << 31) >> 31;
1258 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1261 static unsigned
1262 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
1264 unsigned tie_t = 0;
1265 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1266 return tie_t;
1269 static void
1270 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1272 uint32 tie_t;
1273 tie_t = (val << 30) >> 30;
1274 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1277 static unsigned
1278 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
1280 unsigned tie_t = 0;
1281 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1282 return tie_t;
1285 static void
1286 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1288 uint32 tie_t;
1289 tie_t = (val << 31) >> 31;
1290 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1293 static unsigned
1294 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1296 unsigned tie_t = 0;
1297 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1298 return tie_t;
1301 static void
1302 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1304 uint32 tie_t;
1305 tie_t = (val << 31) >> 31;
1306 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1309 static unsigned
1310 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
1312 unsigned tie_t = 0;
1313 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1314 return tie_t;
1317 static void
1318 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1320 uint32 tie_t;
1321 tie_t = (val << 30) >> 30;
1322 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1325 static unsigned
1326 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
1328 unsigned tie_t = 0;
1329 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1330 return tie_t;
1333 static void
1334 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1336 uint32 tie_t;
1337 tie_t = (val << 30) >> 30;
1338 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1341 static unsigned
1342 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1344 unsigned tie_t = 0;
1345 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1346 return tie_t;
1349 static void
1350 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1352 uint32 tie_t;
1353 tie_t = (val << 31) >> 31;
1354 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1357 static unsigned
1358 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1360 unsigned tie_t = 0;
1361 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1362 return tie_t;
1365 static void
1366 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1368 uint32 tie_t;
1369 tie_t = (val << 31) >> 31;
1370 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1373 static unsigned
1374 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1376 unsigned tie_t = 0;
1377 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1378 return tie_t;
1381 static void
1382 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1384 uint32 tie_t;
1385 tie_t = (val << 17) >> 17;
1386 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1389 static unsigned
1390 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1392 unsigned tie_t = 0;
1393 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1394 return tie_t;
1397 static void
1398 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1400 uint32 tie_t;
1401 tie_t = (val << 14) >> 14;
1402 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1405 static unsigned
1406 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1408 unsigned tie_t = 0;
1409 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1410 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1411 return tie_t;
1414 static void
1415 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1417 uint32 tie_t;
1418 tie_t = (val << 28) >> 28;
1419 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1420 tie_t = (val << 27) >> 31;
1421 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1424 static unsigned
1425 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1427 unsigned tie_t = 0;
1428 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1429 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1430 return tie_t;
1433 static void
1434 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1436 uint32 tie_t;
1437 tie_t = (val << 28) >> 28;
1438 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1439 tie_t = (val << 27) >> 31;
1440 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1443 static unsigned
1444 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1446 unsigned tie_t = 0;
1447 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1448 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1449 return tie_t;
1452 static void
1453 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1455 uint32 tie_t;
1456 tie_t = (val << 28) >> 28;
1457 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1458 tie_t = (val << 27) >> 31;
1459 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1462 static unsigned
1463 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
1465 unsigned tie_t = 0;
1466 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1467 return tie_t;
1470 static void
1471 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1473 uint32 tie_t;
1474 tie_t = (val << 29) >> 29;
1475 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1478 static unsigned
1479 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1481 unsigned tie_t = 0;
1482 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1483 return tie_t;
1486 static void
1487 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1489 uint32 tie_t;
1490 tie_t = (val << 29) >> 29;
1491 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1494 static unsigned
1495 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1497 unsigned tie_t = 0;
1498 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1499 return tie_t;
1502 static void
1503 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1505 uint32 tie_t;
1506 tie_t = (val << 29) >> 29;
1507 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1510 static void
1511 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1512 uint32 val ATTRIBUTE_UNUSED)
1514 /* Do nothing. */
1517 static unsigned
1518 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1520 return 0;
1523 static unsigned
1524 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1526 return 4;
1529 static unsigned
1530 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1532 return 8;
1535 static unsigned
1536 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1538 return 12;
1541 static unsigned
1542 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1544 return 0;
1547 static unsigned
1548 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1550 return 1;
1553 static unsigned
1554 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1556 return 2;
1559 static unsigned
1560 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1562 return 3;
1566 /* Functional units. */
1568 static xtensa_funcUnit_internal funcUnits[] = {
1573 /* Register files. */
1575 static xtensa_regfile_internal regfiles[] = {
1576 { "AR", "a", 0, 32, 32 },
1577 { "MR", "m", 1, 32, 4 }
1581 /* Interfaces. */
1583 static xtensa_interface_internal interfaces[] = {
1584 { "IMPWIRE", 32, 0, 0, 'i' }
1588 /* Constant tables. */
1590 /* constant table ai4c */
1591 static const unsigned CONST_TBL_ai4c_0[] = {
1592 0xffffffff,
1593 0x1,
1594 0x2,
1595 0x3,
1596 0x4,
1597 0x5,
1598 0x6,
1599 0x7,
1600 0x8,
1601 0x9,
1602 0xa,
1603 0xb,
1604 0xc,
1605 0xd,
1606 0xe,
1607 0xf,
1611 /* constant table b4c */
1612 static const unsigned CONST_TBL_b4c_0[] = {
1613 0xffffffff,
1614 0x1,
1615 0x2,
1616 0x3,
1617 0x4,
1618 0x5,
1619 0x6,
1620 0x7,
1621 0x8,
1622 0xa,
1623 0xc,
1624 0x10,
1625 0x20,
1626 0x40,
1627 0x80,
1628 0x100,
1632 /* constant table b4cu */
1633 static const unsigned CONST_TBL_b4cu_0[] = {
1634 0x8000,
1635 0x10000,
1636 0x2,
1637 0x3,
1638 0x4,
1639 0x5,
1640 0x6,
1641 0x7,
1642 0x8,
1643 0xa,
1644 0xc,
1645 0x10,
1646 0x20,
1647 0x40,
1648 0x80,
1649 0x100,
1654 /* Instruction operands. */
1656 static int
1657 Operand_soffsetx4_decode (uint32 *valp)
1659 unsigned soffsetx4_0, offset_0;
1660 offset_0 = *valp & 0x3ffff;
1661 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1662 *valp = soffsetx4_0;
1663 return 0;
1666 static int
1667 Operand_soffsetx4_encode (uint32 *valp)
1669 unsigned offset_0, soffsetx4_0;
1670 soffsetx4_0 = *valp;
1671 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1672 *valp = offset_0;
1673 return 0;
1676 static int
1677 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1679 *valp -= (pc & ~0x3);
1680 return 0;
1683 static int
1684 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1686 *valp += (pc & ~0x3);
1687 return 0;
1690 static int
1691 Operand_uimm12x8_decode (uint32 *valp)
1693 unsigned uimm12x8_0, imm12_0;
1694 imm12_0 = *valp & 0xfff;
1695 uimm12x8_0 = imm12_0 << 3;
1696 *valp = uimm12x8_0;
1697 return 0;
1700 static int
1701 Operand_uimm12x8_encode (uint32 *valp)
1703 unsigned imm12_0, uimm12x8_0;
1704 uimm12x8_0 = *valp;
1705 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1706 *valp = imm12_0;
1707 return 0;
1710 static int
1711 Operand_simm4_decode (uint32 *valp)
1713 unsigned simm4_0, mn_0;
1714 mn_0 = *valp & 0xf;
1715 simm4_0 = ((int) mn_0 << 28) >> 28;
1716 *valp = simm4_0;
1717 return 0;
1720 static int
1721 Operand_simm4_encode (uint32 *valp)
1723 unsigned mn_0, simm4_0;
1724 simm4_0 = *valp;
1725 mn_0 = (simm4_0 & 0xf);
1726 *valp = mn_0;
1727 return 0;
1730 static int
1731 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1733 return 0;
1736 static int
1737 Operand_arr_encode (uint32 *valp)
1739 return (*valp & ~0xf) != 0;
1742 static int
1743 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1745 return 0;
1748 static int
1749 Operand_ars_encode (uint32 *valp)
1751 return (*valp & ~0xf) != 0;
1754 static int
1755 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1757 return 0;
1760 static int
1761 Operand_art_encode (uint32 *valp)
1763 return (*valp & ~0xf) != 0;
1766 static int
1767 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1769 return 0;
1772 static int
1773 Operand_ar0_encode (uint32 *valp)
1775 return (*valp & ~0x1f) != 0;
1778 static int
1779 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1781 return 0;
1784 static int
1785 Operand_ar4_encode (uint32 *valp)
1787 return (*valp & ~0x1f) != 0;
1790 static int
1791 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1793 return 0;
1796 static int
1797 Operand_ar8_encode (uint32 *valp)
1799 return (*valp & ~0x1f) != 0;
1802 static int
1803 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1805 return 0;
1808 static int
1809 Operand_ar12_encode (uint32 *valp)
1811 return (*valp & ~0x1f) != 0;
1814 static int
1815 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1817 return 0;
1820 static int
1821 Operand_ars_entry_encode (uint32 *valp)
1823 return (*valp & ~0x1f) != 0;
1826 static int
1827 Operand_immrx4_decode (uint32 *valp)
1829 unsigned immrx4_0, r_0;
1830 r_0 = *valp & 0xf;
1831 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1832 *valp = immrx4_0;
1833 return 0;
1836 static int
1837 Operand_immrx4_encode (uint32 *valp)
1839 unsigned r_0, immrx4_0;
1840 immrx4_0 = *valp;
1841 r_0 = ((immrx4_0 >> 2) & 0xf);
1842 *valp = r_0;
1843 return 0;
1846 static int
1847 Operand_lsi4x4_decode (uint32 *valp)
1849 unsigned lsi4x4_0, r_0;
1850 r_0 = *valp & 0xf;
1851 lsi4x4_0 = r_0 << 2;
1852 *valp = lsi4x4_0;
1853 return 0;
1856 static int
1857 Operand_lsi4x4_encode (uint32 *valp)
1859 unsigned r_0, lsi4x4_0;
1860 lsi4x4_0 = *valp;
1861 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1862 *valp = r_0;
1863 return 0;
1866 static int
1867 Operand_simm7_decode (uint32 *valp)
1869 unsigned simm7_0, imm7_0;
1870 imm7_0 = *valp & 0x7f;
1871 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1872 *valp = simm7_0;
1873 return 0;
1876 static int
1877 Operand_simm7_encode (uint32 *valp)
1879 unsigned imm7_0, simm7_0;
1880 simm7_0 = *valp;
1881 imm7_0 = (simm7_0 & 0x7f);
1882 *valp = imm7_0;
1883 return 0;
1886 static int
1887 Operand_uimm6_decode (uint32 *valp)
1889 unsigned uimm6_0, imm6_0;
1890 imm6_0 = *valp & 0x3f;
1891 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1892 *valp = uimm6_0;
1893 return 0;
1896 static int
1897 Operand_uimm6_encode (uint32 *valp)
1899 unsigned imm6_0, uimm6_0;
1900 uimm6_0 = *valp;
1901 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1902 *valp = imm6_0;
1903 return 0;
1906 static int
1907 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1909 *valp -= pc;
1910 return 0;
1913 static int
1914 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1916 *valp += pc;
1917 return 0;
1920 static int
1921 Operand_ai4const_decode (uint32 *valp)
1923 unsigned ai4const_0, t_0;
1924 t_0 = *valp & 0xf;
1925 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1926 *valp = ai4const_0;
1927 return 0;
1930 static int
1931 Operand_ai4const_encode (uint32 *valp)
1933 unsigned t_0, ai4const_0;
1934 ai4const_0 = *valp;
1935 switch (ai4const_0)
1937 case 0xffffffff: t_0 = 0; break;
1938 case 0x1: t_0 = 0x1; break;
1939 case 0x2: t_0 = 0x2; break;
1940 case 0x3: t_0 = 0x3; break;
1941 case 0x4: t_0 = 0x4; break;
1942 case 0x5: t_0 = 0x5; break;
1943 case 0x6: t_0 = 0x6; break;
1944 case 0x7: t_0 = 0x7; break;
1945 case 0x8: t_0 = 0x8; break;
1946 case 0x9: t_0 = 0x9; break;
1947 case 0xa: t_0 = 0xa; break;
1948 case 0xb: t_0 = 0xb; break;
1949 case 0xc: t_0 = 0xc; break;
1950 case 0xd: t_0 = 0xd; break;
1951 case 0xe: t_0 = 0xe; break;
1952 default: t_0 = 0xf; break;
1954 *valp = t_0;
1955 return 0;
1958 static int
1959 Operand_b4const_decode (uint32 *valp)
1961 unsigned b4const_0, r_0;
1962 r_0 = *valp & 0xf;
1963 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1964 *valp = b4const_0;
1965 return 0;
1968 static int
1969 Operand_b4const_encode (uint32 *valp)
1971 unsigned r_0, b4const_0;
1972 b4const_0 = *valp;
1973 switch (b4const_0)
1975 case 0xffffffff: r_0 = 0; break;
1976 case 0x1: r_0 = 0x1; break;
1977 case 0x2: r_0 = 0x2; break;
1978 case 0x3: r_0 = 0x3; break;
1979 case 0x4: r_0 = 0x4; break;
1980 case 0x5: r_0 = 0x5; break;
1981 case 0x6: r_0 = 0x6; break;
1982 case 0x7: r_0 = 0x7; break;
1983 case 0x8: r_0 = 0x8; break;
1984 case 0xa: r_0 = 0x9; break;
1985 case 0xc: r_0 = 0xa; break;
1986 case 0x10: r_0 = 0xb; break;
1987 case 0x20: r_0 = 0xc; break;
1988 case 0x40: r_0 = 0xd; break;
1989 case 0x80: r_0 = 0xe; break;
1990 default: r_0 = 0xf; break;
1992 *valp = r_0;
1993 return 0;
1996 static int
1997 Operand_b4constu_decode (uint32 *valp)
1999 unsigned b4constu_0, r_0;
2000 r_0 = *valp & 0xf;
2001 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2002 *valp = b4constu_0;
2003 return 0;
2006 static int
2007 Operand_b4constu_encode (uint32 *valp)
2009 unsigned r_0, b4constu_0;
2010 b4constu_0 = *valp;
2011 switch (b4constu_0)
2013 case 0x8000: r_0 = 0; break;
2014 case 0x10000: r_0 = 0x1; break;
2015 case 0x2: r_0 = 0x2; break;
2016 case 0x3: r_0 = 0x3; break;
2017 case 0x4: r_0 = 0x4; break;
2018 case 0x5: r_0 = 0x5; break;
2019 case 0x6: r_0 = 0x6; break;
2020 case 0x7: r_0 = 0x7; break;
2021 case 0x8: r_0 = 0x8; break;
2022 case 0xa: r_0 = 0x9; break;
2023 case 0xc: r_0 = 0xa; break;
2024 case 0x10: r_0 = 0xb; break;
2025 case 0x20: r_0 = 0xc; break;
2026 case 0x40: r_0 = 0xd; break;
2027 case 0x80: r_0 = 0xe; break;
2028 default: r_0 = 0xf; break;
2030 *valp = r_0;
2031 return 0;
2034 static int
2035 Operand_uimm8_decode (uint32 *valp)
2037 unsigned uimm8_0, imm8_0;
2038 imm8_0 = *valp & 0xff;
2039 uimm8_0 = imm8_0;
2040 *valp = uimm8_0;
2041 return 0;
2044 static int
2045 Operand_uimm8_encode (uint32 *valp)
2047 unsigned imm8_0, uimm8_0;
2048 uimm8_0 = *valp;
2049 imm8_0 = (uimm8_0 & 0xff);
2050 *valp = imm8_0;
2051 return 0;
2054 static int
2055 Operand_uimm8x2_decode (uint32 *valp)
2057 unsigned uimm8x2_0, imm8_0;
2058 imm8_0 = *valp & 0xff;
2059 uimm8x2_0 = imm8_0 << 1;
2060 *valp = uimm8x2_0;
2061 return 0;
2064 static int
2065 Operand_uimm8x2_encode (uint32 *valp)
2067 unsigned imm8_0, uimm8x2_0;
2068 uimm8x2_0 = *valp;
2069 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2070 *valp = imm8_0;
2071 return 0;
2074 static int
2075 Operand_uimm8x4_decode (uint32 *valp)
2077 unsigned uimm8x4_0, imm8_0;
2078 imm8_0 = *valp & 0xff;
2079 uimm8x4_0 = imm8_0 << 2;
2080 *valp = uimm8x4_0;
2081 return 0;
2084 static int
2085 Operand_uimm8x4_encode (uint32 *valp)
2087 unsigned imm8_0, uimm8x4_0;
2088 uimm8x4_0 = *valp;
2089 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2090 *valp = imm8_0;
2091 return 0;
2094 static int
2095 Operand_uimm4x16_decode (uint32 *valp)
2097 unsigned uimm4x16_0, op2_0;
2098 op2_0 = *valp & 0xf;
2099 uimm4x16_0 = op2_0 << 4;
2100 *valp = uimm4x16_0;
2101 return 0;
2104 static int
2105 Operand_uimm4x16_encode (uint32 *valp)
2107 unsigned op2_0, uimm4x16_0;
2108 uimm4x16_0 = *valp;
2109 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2110 *valp = op2_0;
2111 return 0;
2114 static int
2115 Operand_simm8_decode (uint32 *valp)
2117 unsigned simm8_0, imm8_0;
2118 imm8_0 = *valp & 0xff;
2119 simm8_0 = ((int) imm8_0 << 24) >> 24;
2120 *valp = simm8_0;
2121 return 0;
2124 static int
2125 Operand_simm8_encode (uint32 *valp)
2127 unsigned imm8_0, simm8_0;
2128 simm8_0 = *valp;
2129 imm8_0 = (simm8_0 & 0xff);
2130 *valp = imm8_0;
2131 return 0;
2134 static int
2135 Operand_simm8x256_decode (uint32 *valp)
2137 unsigned simm8x256_0, imm8_0;
2138 imm8_0 = *valp & 0xff;
2139 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2140 *valp = simm8x256_0;
2141 return 0;
2144 static int
2145 Operand_simm8x256_encode (uint32 *valp)
2147 unsigned imm8_0, simm8x256_0;
2148 simm8x256_0 = *valp;
2149 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2150 *valp = imm8_0;
2151 return 0;
2154 static int
2155 Operand_simm12b_decode (uint32 *valp)
2157 unsigned simm12b_0, imm12b_0;
2158 imm12b_0 = *valp & 0xfff;
2159 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2160 *valp = simm12b_0;
2161 return 0;
2164 static int
2165 Operand_simm12b_encode (uint32 *valp)
2167 unsigned imm12b_0, simm12b_0;
2168 simm12b_0 = *valp;
2169 imm12b_0 = (simm12b_0 & 0xfff);
2170 *valp = imm12b_0;
2171 return 0;
2174 static int
2175 Operand_msalp32_decode (uint32 *valp)
2177 unsigned msalp32_0, sal_0;
2178 sal_0 = *valp & 0x1f;
2179 msalp32_0 = 0x20 - sal_0;
2180 *valp = msalp32_0;
2181 return 0;
2184 static int
2185 Operand_msalp32_encode (uint32 *valp)
2187 unsigned sal_0, msalp32_0;
2188 msalp32_0 = *valp;
2189 sal_0 = (0x20 - msalp32_0) & 0x1f;
2190 *valp = sal_0;
2191 return 0;
2194 static int
2195 Operand_op2p1_decode (uint32 *valp)
2197 unsigned op2p1_0, op2_0;
2198 op2_0 = *valp & 0xf;
2199 op2p1_0 = op2_0 + 0x1;
2200 *valp = op2p1_0;
2201 return 0;
2204 static int
2205 Operand_op2p1_encode (uint32 *valp)
2207 unsigned op2_0, op2p1_0;
2208 op2p1_0 = *valp;
2209 op2_0 = (op2p1_0 - 0x1) & 0xf;
2210 *valp = op2_0;
2211 return 0;
2214 static int
2215 Operand_label8_decode (uint32 *valp)
2217 unsigned label8_0, imm8_0;
2218 imm8_0 = *valp & 0xff;
2219 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2220 *valp = label8_0;
2221 return 0;
2224 static int
2225 Operand_label8_encode (uint32 *valp)
2227 unsigned imm8_0, label8_0;
2228 label8_0 = *valp;
2229 imm8_0 = (label8_0 - 0x4) & 0xff;
2230 *valp = imm8_0;
2231 return 0;
2234 static int
2235 Operand_label8_ator (uint32 *valp, uint32 pc)
2237 *valp -= pc;
2238 return 0;
2241 static int
2242 Operand_label8_rtoa (uint32 *valp, uint32 pc)
2244 *valp += pc;
2245 return 0;
2248 static int
2249 Operand_ulabel8_decode (uint32 *valp)
2251 unsigned ulabel8_0, imm8_0;
2252 imm8_0 = *valp & 0xff;
2253 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2254 *valp = ulabel8_0;
2255 return 0;
2258 static int
2259 Operand_ulabel8_encode (uint32 *valp)
2261 unsigned imm8_0, ulabel8_0;
2262 ulabel8_0 = *valp;
2263 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2264 *valp = imm8_0;
2265 return 0;
2268 static int
2269 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2271 *valp -= pc;
2272 return 0;
2275 static int
2276 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2278 *valp += pc;
2279 return 0;
2282 static int
2283 Operand_label12_decode (uint32 *valp)
2285 unsigned label12_0, imm12_0;
2286 imm12_0 = *valp & 0xfff;
2287 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2288 *valp = label12_0;
2289 return 0;
2292 static int
2293 Operand_label12_encode (uint32 *valp)
2295 unsigned imm12_0, label12_0;
2296 label12_0 = *valp;
2297 imm12_0 = (label12_0 - 0x4) & 0xfff;
2298 *valp = imm12_0;
2299 return 0;
2302 static int
2303 Operand_label12_ator (uint32 *valp, uint32 pc)
2305 *valp -= pc;
2306 return 0;
2309 static int
2310 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2312 *valp += pc;
2313 return 0;
2316 static int
2317 Operand_soffset_decode (uint32 *valp)
2319 unsigned soffset_0, offset_0;
2320 offset_0 = *valp & 0x3ffff;
2321 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2322 *valp = soffset_0;
2323 return 0;
2326 static int
2327 Operand_soffset_encode (uint32 *valp)
2329 unsigned offset_0, soffset_0;
2330 soffset_0 = *valp;
2331 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2332 *valp = offset_0;
2333 return 0;
2336 static int
2337 Operand_soffset_ator (uint32 *valp, uint32 pc)
2339 *valp -= pc;
2340 return 0;
2343 static int
2344 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2346 *valp += pc;
2347 return 0;
2350 static int
2351 Operand_uimm16x4_decode (uint32 *valp)
2353 unsigned uimm16x4_0, imm16_0;
2354 imm16_0 = *valp & 0xffff;
2355 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2356 *valp = uimm16x4_0;
2357 return 0;
2360 static int
2361 Operand_uimm16x4_encode (uint32 *valp)
2363 unsigned imm16_0, uimm16x4_0;
2364 uimm16x4_0 = *valp;
2365 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2366 *valp = imm16_0;
2367 return 0;
2370 static int
2371 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2373 *valp -= ((pc + 3) & ~0x3);
2374 return 0;
2377 static int
2378 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2380 *valp += ((pc + 3) & ~0x3);
2381 return 0;
2384 static int
2385 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
2387 return 0;
2390 static int
2391 Operand_mx_encode (uint32 *valp)
2393 return (*valp & ~0x3) != 0;
2396 static int
2397 Operand_my_decode (uint32 *valp)
2399 *valp += 2;
2400 return 0;
2403 static int
2404 Operand_my_encode (uint32 *valp)
2406 int error;
2407 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2408 *valp = *valp & 1;
2409 return error;
2412 static int
2413 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
2415 return 0;
2418 static int
2419 Operand_mw_encode (uint32 *valp)
2421 return (*valp & ~0x3) != 0;
2424 static int
2425 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
2427 return 0;
2430 static int
2431 Operand_mr0_encode (uint32 *valp)
2433 return (*valp & ~0x3) != 0;
2436 static int
2437 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2439 return 0;
2442 static int
2443 Operand_mr1_encode (uint32 *valp)
2445 return (*valp & ~0x3) != 0;
2448 static int
2449 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2451 return 0;
2454 static int
2455 Operand_mr2_encode (uint32 *valp)
2457 return (*valp & ~0x3) != 0;
2460 static int
2461 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2463 return 0;
2466 static int
2467 Operand_mr3_encode (uint32 *valp)
2469 return (*valp & ~0x3) != 0;
2472 static int
2473 Operand_immt_decode (uint32 *valp)
2475 unsigned immt_0, t_0;
2476 t_0 = *valp & 0xf;
2477 immt_0 = t_0;
2478 *valp = immt_0;
2479 return 0;
2482 static int
2483 Operand_immt_encode (uint32 *valp)
2485 unsigned t_0, immt_0;
2486 immt_0 = *valp;
2487 t_0 = immt_0 & 0xf;
2488 *valp = t_0;
2489 return 0;
2492 static int
2493 Operand_imms_decode (uint32 *valp)
2495 unsigned imms_0, s_0;
2496 s_0 = *valp & 0xf;
2497 imms_0 = s_0;
2498 *valp = imms_0;
2499 return 0;
2502 static int
2503 Operand_imms_encode (uint32 *valp)
2505 unsigned s_0, imms_0;
2506 imms_0 = *valp;
2507 s_0 = imms_0 & 0xf;
2508 *valp = s_0;
2509 return 0;
2512 static int
2513 Operand_tp7_decode (uint32 *valp)
2515 unsigned tp7_0, t_0;
2516 t_0 = *valp & 0xf;
2517 tp7_0 = t_0 + 0x7;
2518 *valp = tp7_0;
2519 return 0;
2522 static int
2523 Operand_tp7_encode (uint32 *valp)
2525 unsigned t_0, tp7_0;
2526 tp7_0 = *valp;
2527 t_0 = (tp7_0 - 0x7) & 0xf;
2528 *valp = t_0;
2529 return 0;
2532 static int
2533 Operand_xt_wbr15_label_decode (uint32 *valp)
2535 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
2536 xt_wbr15_imm_0 = *valp & 0x7fff;
2537 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2538 *valp = xt_wbr15_label_0;
2539 return 0;
2542 static int
2543 Operand_xt_wbr15_label_encode (uint32 *valp)
2545 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
2546 xt_wbr15_label_0 = *valp;
2547 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2548 *valp = xt_wbr15_imm_0;
2549 return 0;
2552 static int
2553 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2555 *valp -= pc;
2556 return 0;
2559 static int
2560 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2562 *valp += pc;
2563 return 0;
2566 static int
2567 Operand_xt_wbr18_label_decode (uint32 *valp)
2569 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
2570 xt_wbr18_imm_0 = *valp & 0x3ffff;
2571 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2572 *valp = xt_wbr18_label_0;
2573 return 0;
2576 static int
2577 Operand_xt_wbr18_label_encode (uint32 *valp)
2579 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
2580 xt_wbr18_label_0 = *valp;
2581 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2582 *valp = xt_wbr18_imm_0;
2583 return 0;
2586 static int
2587 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2589 *valp -= pc;
2590 return 0;
2593 static int
2594 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2596 *valp += pc;
2597 return 0;
2600 static xtensa_operand_internal operands[] = {
2601 { "soffsetx4", 10, -1, 0,
2602 XTENSA_OPERAND_IS_PCRELATIVE,
2603 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2604 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2605 { "uimm12x8", 3, -1, 0,
2607 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2608 0, 0 },
2609 { "simm4", 26, -1, 0,
2611 Operand_simm4_encode, Operand_simm4_decode,
2612 0, 0 },
2613 { "arr", 14, 0, 1,
2614 XTENSA_OPERAND_IS_REGISTER,
2615 Operand_arr_encode, Operand_arr_decode,
2616 0, 0 },
2617 { "ars", 5, 0, 1,
2618 XTENSA_OPERAND_IS_REGISTER,
2619 Operand_ars_encode, Operand_ars_decode,
2620 0, 0 },
2621 { "*ars_invisible", 5, 0, 1,
2622 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2623 Operand_ars_encode, Operand_ars_decode,
2624 0, 0 },
2625 { "art", 0, 0, 1,
2626 XTENSA_OPERAND_IS_REGISTER,
2627 Operand_art_encode, Operand_art_decode,
2628 0, 0 },
2629 { "ar0", 48, 0, 1,
2630 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2631 Operand_ar0_encode, Operand_ar0_decode,
2632 0, 0 },
2633 { "ar4", 49, 0, 1,
2634 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2635 Operand_ar4_encode, Operand_ar4_decode,
2636 0, 0 },
2637 { "ar8", 50, 0, 1,
2638 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2639 Operand_ar8_encode, Operand_ar8_decode,
2640 0, 0 },
2641 { "ar12", 51, 0, 1,
2642 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2643 Operand_ar12_encode, Operand_ar12_decode,
2644 0, 0 },
2645 { "ars_entry", 5, 0, 1,
2646 XTENSA_OPERAND_IS_REGISTER,
2647 Operand_ars_entry_encode, Operand_ars_entry_decode,
2648 0, 0 },
2649 { "immrx4", 14, -1, 0,
2651 Operand_immrx4_encode, Operand_immrx4_decode,
2652 0, 0 },
2653 { "lsi4x4", 14, -1, 0,
2655 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2656 0, 0 },
2657 { "simm7", 34, -1, 0,
2659 Operand_simm7_encode, Operand_simm7_decode,
2660 0, 0 },
2661 { "uimm6", 33, -1, 0,
2662 XTENSA_OPERAND_IS_PCRELATIVE,
2663 Operand_uimm6_encode, Operand_uimm6_decode,
2664 Operand_uimm6_ator, Operand_uimm6_rtoa },
2665 { "ai4const", 0, -1, 0,
2667 Operand_ai4const_encode, Operand_ai4const_decode,
2668 0, 0 },
2669 { "b4const", 14, -1, 0,
2671 Operand_b4const_encode, Operand_b4const_decode,
2672 0, 0 },
2673 { "b4constu", 14, -1, 0,
2675 Operand_b4constu_encode, Operand_b4constu_decode,
2676 0, 0 },
2677 { "uimm8", 4, -1, 0,
2679 Operand_uimm8_encode, Operand_uimm8_decode,
2680 0, 0 },
2681 { "uimm8x2", 4, -1, 0,
2683 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2684 0, 0 },
2685 { "uimm8x4", 4, -1, 0,
2687 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2688 0, 0 },
2689 { "uimm4x16", 13, -1, 0,
2691 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2692 0, 0 },
2693 { "simm8", 4, -1, 0,
2695 Operand_simm8_encode, Operand_simm8_decode,
2696 0, 0 },
2697 { "simm8x256", 4, -1, 0,
2699 Operand_simm8x256_encode, Operand_simm8x256_decode,
2700 0, 0 },
2701 { "simm12b", 6, -1, 0,
2703 Operand_simm12b_encode, Operand_simm12b_decode,
2704 0, 0 },
2705 { "msalp32", 18, -1, 0,
2707 Operand_msalp32_encode, Operand_msalp32_decode,
2708 0, 0 },
2709 { "op2p1", 13, -1, 0,
2711 Operand_op2p1_encode, Operand_op2p1_decode,
2712 0, 0 },
2713 { "label8", 4, -1, 0,
2714 XTENSA_OPERAND_IS_PCRELATIVE,
2715 Operand_label8_encode, Operand_label8_decode,
2716 Operand_label8_ator, Operand_label8_rtoa },
2717 { "ulabel8", 4, -1, 0,
2718 XTENSA_OPERAND_IS_PCRELATIVE,
2719 Operand_ulabel8_encode, Operand_ulabel8_decode,
2720 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2721 { "label12", 3, -1, 0,
2722 XTENSA_OPERAND_IS_PCRELATIVE,
2723 Operand_label12_encode, Operand_label12_decode,
2724 Operand_label12_ator, Operand_label12_rtoa },
2725 { "soffset", 10, -1, 0,
2726 XTENSA_OPERAND_IS_PCRELATIVE,
2727 Operand_soffset_encode, Operand_soffset_decode,
2728 Operand_soffset_ator, Operand_soffset_rtoa },
2729 { "uimm16x4", 7, -1, 0,
2730 XTENSA_OPERAND_IS_PCRELATIVE,
2731 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2732 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2733 { "mx", 43, 1, 1,
2734 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2735 Operand_mx_encode, Operand_mx_decode,
2736 0, 0 },
2737 { "my", 42, 1, 1,
2738 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2739 Operand_my_encode, Operand_my_decode,
2740 0, 0 },
2741 { "mw", 41, 1, 1,
2742 XTENSA_OPERAND_IS_REGISTER,
2743 Operand_mw_encode, Operand_mw_decode,
2744 0, 0 },
2745 { "mr0", 52, 1, 1,
2746 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2747 Operand_mr0_encode, Operand_mr0_decode,
2748 0, 0 },
2749 { "mr1", 53, 1, 1,
2750 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2751 Operand_mr1_encode, Operand_mr1_decode,
2752 0, 0 },
2753 { "mr2", 54, 1, 1,
2754 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2755 Operand_mr2_encode, Operand_mr2_decode,
2756 0, 0 },
2757 { "mr3", 55, 1, 1,
2758 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2759 Operand_mr3_encode, Operand_mr3_decode,
2760 0, 0 },
2761 { "immt", 0, -1, 0,
2763 Operand_immt_encode, Operand_immt_decode,
2764 0, 0 },
2765 { "imms", 5, -1, 0,
2767 Operand_imms_encode, Operand_imms_decode,
2768 0, 0 },
2769 { "tp7", 0, -1, 0,
2771 Operand_tp7_encode, Operand_tp7_decode,
2772 0, 0 },
2773 { "xt_wbr15_label", 44, -1, 0,
2774 XTENSA_OPERAND_IS_PCRELATIVE,
2775 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2776 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2777 { "xt_wbr18_label", 45, -1, 0,
2778 XTENSA_OPERAND_IS_PCRELATIVE,
2779 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2780 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2781 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2782 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2783 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2784 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2785 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2786 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2787 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2788 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2789 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2790 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2791 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2792 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2793 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2794 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2795 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2796 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2797 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2798 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2799 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2800 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2801 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2802 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2803 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2804 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2805 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2806 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2807 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2808 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2809 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2810 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2811 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2812 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2813 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2814 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2815 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
2816 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
2817 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
2818 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
2819 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
2820 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
2821 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
2822 { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
2823 { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
2824 { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
2825 { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
2826 { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
2827 { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
2828 { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
2832 /* Iclass table. */
2834 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2835 { { STATE_PSRING }, 'i' },
2836 { { STATE_PSEXCM }, 'm' },
2837 { { STATE_EPC1 }, 'i' }
2840 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2841 { { STATE_PSEXCM }, 'i' },
2842 { { STATE_PSRING }, 'i' },
2843 { { STATE_DEPC }, 'i' }
2846 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2847 { { 0 /* soffsetx4 */ }, 'i' },
2848 { { 10 /* ar12 */ }, 'o' }
2851 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2852 { { STATE_PSCALLINC }, 'o' }
2855 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2856 { { 0 /* soffsetx4 */ }, 'i' },
2857 { { 9 /* ar8 */ }, 'o' }
2860 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2861 { { STATE_PSCALLINC }, 'o' }
2864 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2865 { { 0 /* soffsetx4 */ }, 'i' },
2866 { { 8 /* ar4 */ }, 'o' }
2869 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2870 { { STATE_PSCALLINC }, 'o' }
2873 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2874 { { 4 /* ars */ }, 'i' },
2875 { { 10 /* ar12 */ }, 'o' }
2878 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2879 { { STATE_PSCALLINC }, 'o' }
2882 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2883 { { 4 /* ars */ }, 'i' },
2884 { { 9 /* ar8 */ }, 'o' }
2887 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2888 { { STATE_PSCALLINC }, 'o' }
2891 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2892 { { 4 /* ars */ }, 'i' },
2893 { { 8 /* ar4 */ }, 'o' }
2896 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2897 { { STATE_PSCALLINC }, 'o' }
2900 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2901 { { 11 /* ars_entry */ }, 's' },
2902 { { 4 /* ars */ }, 'i' },
2903 { { 1 /* uimm12x8 */ }, 'i' }
2906 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2907 { { STATE_PSCALLINC }, 'i' },
2908 { { STATE_PSEXCM }, 'i' },
2909 { { STATE_PSWOE }, 'i' },
2910 { { STATE_WindowBase }, 'm' },
2911 { { STATE_WindowStart }, 'm' }
2914 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2915 { { 6 /* art */ }, 'o' },
2916 { { 4 /* ars */ }, 'i' }
2919 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2920 { { STATE_WindowBase }, 'i' },
2921 { { STATE_WindowStart }, 'i' }
2924 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2925 { { 2 /* simm4 */ }, 'i' }
2928 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2929 { { STATE_PSEXCM }, 'i' },
2930 { { STATE_PSRING }, 'i' },
2931 { { STATE_WindowBase }, 'm' }
2934 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2935 { { 5 /* *ars_invisible */ }, 'i' }
2938 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2939 { { STATE_WindowBase }, 'm' },
2940 { { STATE_WindowStart }, 'm' },
2941 { { STATE_PSEXCM }, 'i' },
2942 { { STATE_PSWOE }, 'i' }
2945 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2946 { { STATE_EPC1 }, 'i' },
2947 { { STATE_PSEXCM }, 'm' },
2948 { { STATE_PSRING }, 'i' },
2949 { { STATE_WindowBase }, 'm' },
2950 { { STATE_WindowStart }, 'm' },
2951 { { STATE_PSOWB }, 'i' }
2954 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2955 { { 6 /* art */ }, 'o' },
2956 { { 4 /* ars */ }, 'i' },
2957 { { 12 /* immrx4 */ }, 'i' }
2960 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2961 { { STATE_PSEXCM }, 'i' },
2962 { { STATE_PSRING }, 'i' }
2965 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2966 { { 6 /* art */ }, 'i' },
2967 { { 4 /* ars */ }, 'i' },
2968 { { 12 /* immrx4 */ }, 'i' }
2971 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2972 { { STATE_PSEXCM }, 'i' },
2973 { { STATE_PSRING }, 'i' }
2976 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2977 { { 6 /* art */ }, 'o' }
2980 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2981 { { STATE_PSEXCM }, 'i' },
2982 { { STATE_PSRING }, 'i' },
2983 { { STATE_WindowBase }, 'i' }
2986 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2987 { { 6 /* art */ }, 'i' }
2990 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2991 { { STATE_PSEXCM }, 'i' },
2992 { { STATE_PSRING }, 'i' },
2993 { { STATE_WindowBase }, 'o' }
2996 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2997 { { 6 /* art */ }, 'm' }
3000 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3001 { { STATE_PSEXCM }, 'i' },
3002 { { STATE_PSRING }, 'i' },
3003 { { STATE_WindowBase }, 'm' }
3006 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3007 { { 6 /* art */ }, 'o' }
3010 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3011 { { STATE_PSEXCM }, 'i' },
3012 { { STATE_PSRING }, 'i' },
3013 { { STATE_WindowStart }, 'i' }
3016 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3017 { { 6 /* art */ }, 'i' }
3020 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3021 { { STATE_PSEXCM }, 'i' },
3022 { { STATE_PSRING }, 'i' },
3023 { { STATE_WindowStart }, 'o' }
3026 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3027 { { 6 /* art */ }, 'm' }
3030 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3031 { { STATE_PSEXCM }, 'i' },
3032 { { STATE_PSRING }, 'i' },
3033 { { STATE_WindowStart }, 'm' }
3036 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3037 { { 3 /* arr */ }, 'o' },
3038 { { 4 /* ars */ }, 'i' },
3039 { { 6 /* art */ }, 'i' }
3042 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3043 { { 3 /* arr */ }, 'o' },
3044 { { 4 /* ars */ }, 'i' },
3045 { { 16 /* ai4const */ }, 'i' }
3048 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3049 { { 4 /* ars */ }, 'i' },
3050 { { 15 /* uimm6 */ }, 'i' }
3053 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3054 { { 6 /* art */ }, 'o' },
3055 { { 4 /* ars */ }, 'i' },
3056 { { 13 /* lsi4x4 */ }, 'i' }
3059 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3060 { { 6 /* art */ }, 'o' },
3061 { { 4 /* ars */ }, 'i' }
3064 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3065 { { 4 /* ars */ }, 'o' },
3066 { { 14 /* simm7 */ }, 'i' }
3069 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3070 { { 5 /* *ars_invisible */ }, 'i' }
3073 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3074 { { 6 /* art */ }, 'i' },
3075 { { 4 /* ars */ }, 'i' },
3076 { { 13 /* lsi4x4 */ }, 'i' }
3079 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3080 { { 3 /* arr */ }, 'o' }
3083 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3084 { { STATE_THREADPTR }, 'i' }
3087 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3088 { { 6 /* art */ }, 'i' }
3091 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3092 { { STATE_THREADPTR }, 'o' }
3095 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3096 { { 6 /* art */ }, 'o' },
3097 { { 4 /* ars */ }, 'i' },
3098 { { 23 /* simm8 */ }, 'i' }
3101 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3102 { { 6 /* art */ }, 'o' },
3103 { { 4 /* ars */ }, 'i' },
3104 { { 24 /* simm8x256 */ }, 'i' }
3107 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3108 { { 3 /* arr */ }, 'o' },
3109 { { 4 /* ars */ }, 'i' },
3110 { { 6 /* art */ }, 'i' }
3113 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3114 { { 3 /* arr */ }, 'o' },
3115 { { 4 /* ars */ }, 'i' },
3116 { { 6 /* art */ }, 'i' }
3119 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3120 { { 4 /* ars */ }, 'i' },
3121 { { 17 /* b4const */ }, 'i' },
3122 { { 28 /* label8 */ }, 'i' }
3125 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3126 { { 4 /* ars */ }, 'i' },
3127 { { 47 /* bbi */ }, 'i' },
3128 { { 28 /* label8 */ }, 'i' }
3131 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3132 { { 4 /* ars */ }, 'i' },
3133 { { 18 /* b4constu */ }, 'i' },
3134 { { 28 /* label8 */ }, 'i' }
3137 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3138 { { 4 /* ars */ }, 'i' },
3139 { { 6 /* art */ }, 'i' },
3140 { { 28 /* label8 */ }, 'i' }
3143 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3144 { { 4 /* ars */ }, 'i' },
3145 { { 30 /* label12 */ }, 'i' }
3148 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3149 { { 0 /* soffsetx4 */ }, 'i' },
3150 { { 7 /* ar0 */ }, 'o' }
3153 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3154 { { 4 /* ars */ }, 'i' },
3155 { { 7 /* ar0 */ }, 'o' }
3158 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3159 { { 3 /* arr */ }, 'o' },
3160 { { 6 /* art */ }, 'i' },
3161 { { 62 /* sae */ }, 'i' },
3162 { { 27 /* op2p1 */ }, 'i' }
3165 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3166 { { 31 /* soffset */ }, 'i' }
3169 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3170 { { 4 /* ars */ }, 'i' }
3173 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3174 { { 6 /* art */ }, 'o' },
3175 { { 4 /* ars */ }, 'i' },
3176 { { 20 /* uimm8x2 */ }, 'i' }
3179 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3180 { { 6 /* art */ }, 'o' },
3181 { { 4 /* ars */ }, 'i' },
3182 { { 20 /* uimm8x2 */ }, 'i' }
3185 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3186 { { 6 /* art */ }, 'o' },
3187 { { 4 /* ars */ }, 'i' },
3188 { { 21 /* uimm8x4 */ }, 'i' }
3191 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3192 { { 6 /* art */ }, 'o' },
3193 { { 32 /* uimm16x4 */ }, 'i' }
3196 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
3197 { { STATE_LITBADDR }, 'i' },
3198 { { STATE_LITBEN }, 'i' }
3201 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3202 { { 6 /* art */ }, 'o' },
3203 { { 4 /* ars */ }, 'i' },
3204 { { 19 /* uimm8 */ }, 'i' }
3207 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3208 { { 4 /* ars */ }, 'i' },
3209 { { 29 /* ulabel8 */ }, 'i' }
3212 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3213 { { STATE_LBEG }, 'o' },
3214 { { STATE_LEND }, 'o' },
3215 { { STATE_LCOUNT }, 'o' }
3218 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3219 { { 4 /* ars */ }, 'i' },
3220 { { 29 /* ulabel8 */ }, 'i' }
3223 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3224 { { STATE_LBEG }, 'o' },
3225 { { STATE_LEND }, 'o' },
3226 { { STATE_LCOUNT }, 'o' }
3229 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3230 { { 6 /* art */ }, 'o' },
3231 { { 25 /* simm12b */ }, 'i' }
3234 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3235 { { 3 /* arr */ }, 'm' },
3236 { { 4 /* ars */ }, 'i' },
3237 { { 6 /* art */ }, 'i' }
3240 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3241 { { 3 /* arr */ }, 'o' },
3242 { { 6 /* art */ }, 'i' }
3245 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3246 { { 5 /* *ars_invisible */ }, 'i' }
3249 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3250 { { 6 /* art */ }, 'i' },
3251 { { 4 /* ars */ }, 'i' },
3252 { { 20 /* uimm8x2 */ }, 'i' }
3255 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3256 { { 6 /* art */ }, 'i' },
3257 { { 4 /* ars */ }, 'i' },
3258 { { 21 /* uimm8x4 */ }, 'i' }
3261 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3262 { { 6 /* art */ }, 'i' },
3263 { { 4 /* ars */ }, 'i' },
3264 { { 19 /* uimm8 */ }, 'i' }
3267 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3268 { { 4 /* ars */ }, 'i' }
3271 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3272 { { STATE_SAR }, 'o' }
3275 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3276 { { 66 /* sas */ }, 'i' }
3279 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3280 { { STATE_SAR }, 'o' }
3283 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3284 { { 3 /* arr */ }, 'o' },
3285 { { 4 /* ars */ }, 'i' }
3288 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3289 { { STATE_SAR }, 'i' }
3292 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3293 { { 3 /* arr */ }, 'o' },
3294 { { 4 /* ars */ }, 'i' },
3295 { { 6 /* art */ }, 'i' }
3298 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3299 { { STATE_SAR }, 'i' }
3302 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3303 { { 3 /* arr */ }, 'o' },
3304 { { 6 /* art */ }, 'i' }
3307 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3308 { { STATE_SAR }, 'i' }
3311 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3312 { { 3 /* arr */ }, 'o' },
3313 { { 4 /* ars */ }, 'i' },
3314 { { 26 /* msalp32 */ }, 'i' }
3317 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3318 { { 3 /* arr */ }, 'o' },
3319 { { 6 /* art */ }, 'i' },
3320 { { 64 /* sargt */ }, 'i' }
3323 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3324 { { 3 /* arr */ }, 'o' },
3325 { { 6 /* art */ }, 'i' },
3326 { { 50 /* s */ }, 'i' }
3329 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3330 { { STATE_XTSYNC }, 'i' }
3333 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3334 { { 6 /* art */ }, 'o' },
3335 { { 50 /* s */ }, 'i' }
3338 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3339 { { STATE_PSWOE }, 'i' },
3340 { { STATE_PSCALLINC }, 'i' },
3341 { { STATE_PSOWB }, 'i' },
3342 { { STATE_PSRING }, 'i' },
3343 { { STATE_PSUM }, 'i' },
3344 { { STATE_PSEXCM }, 'i' },
3345 { { STATE_PSINTLEVEL }, 'm' }
3348 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3349 { { 6 /* art */ }, 'o' }
3352 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3353 { { STATE_LEND }, 'i' }
3356 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3357 { { 6 /* art */ }, 'i' }
3360 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3361 { { STATE_LEND }, 'o' }
3364 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3365 { { 6 /* art */ }, 'm' }
3368 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3369 { { STATE_LEND }, 'm' }
3372 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3373 { { 6 /* art */ }, 'o' }
3376 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3377 { { STATE_LCOUNT }, 'i' }
3380 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3381 { { 6 /* art */ }, 'i' }
3384 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3385 { { STATE_XTSYNC }, 'o' },
3386 { { STATE_LCOUNT }, 'o' }
3389 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3390 { { 6 /* art */ }, 'm' }
3393 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3394 { { STATE_XTSYNC }, 'o' },
3395 { { STATE_LCOUNT }, 'm' }
3398 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3399 { { 6 /* art */ }, 'o' }
3402 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3403 { { STATE_LBEG }, 'i' }
3406 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3407 { { 6 /* art */ }, 'i' }
3410 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3411 { { STATE_LBEG }, 'o' }
3414 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3415 { { 6 /* art */ }, 'm' }
3418 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3419 { { STATE_LBEG }, 'm' }
3422 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3423 { { 6 /* art */ }, 'o' }
3426 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3427 { { STATE_SAR }, 'i' }
3430 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3431 { { 6 /* art */ }, 'i' }
3434 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3435 { { STATE_SAR }, 'o' },
3436 { { STATE_XTSYNC }, 'o' }
3439 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3440 { { 6 /* art */ }, 'm' }
3443 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3444 { { STATE_SAR }, 'm' }
3447 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3448 { { 6 /* art */ }, 'o' }
3451 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
3452 { { STATE_LITBADDR }, 'i' },
3453 { { STATE_LITBEN }, 'i' }
3456 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3457 { { 6 /* art */ }, 'i' }
3460 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
3461 { { STATE_LITBADDR }, 'o' },
3462 { { STATE_LITBEN }, 'o' }
3465 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3466 { { 6 /* art */ }, 'm' }
3469 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3470 { { STATE_LITBADDR }, 'm' },
3471 { { STATE_LITBEN }, 'm' }
3474 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
3475 { { 6 /* art */ }, 'o' }
3478 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3479 { { STATE_PSEXCM }, 'i' },
3480 { { STATE_PSRING }, 'i' }
3483 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
3484 { { 6 /* art */ }, 'o' }
3487 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3488 { { STATE_PSEXCM }, 'i' },
3489 { { STATE_PSRING }, 'i' }
3492 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3493 { { 6 /* art */ }, 'o' }
3496 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3497 { { STATE_PSWOE }, 'i' },
3498 { { STATE_PSCALLINC }, 'i' },
3499 { { STATE_PSOWB }, 'i' },
3500 { { STATE_PSRING }, 'i' },
3501 { { STATE_PSUM }, 'i' },
3502 { { STATE_PSEXCM }, 'i' },
3503 { { STATE_PSINTLEVEL }, 'i' }
3506 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3507 { { 6 /* art */ }, 'i' }
3510 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3511 { { STATE_PSWOE }, 'o' },
3512 { { STATE_PSCALLINC }, 'o' },
3513 { { STATE_PSOWB }, 'o' },
3514 { { STATE_PSRING }, 'm' },
3515 { { STATE_PSUM }, 'o' },
3516 { { STATE_PSEXCM }, 'm' },
3517 { { STATE_PSINTLEVEL }, 'o' }
3520 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3521 { { 6 /* art */ }, 'm' }
3524 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3525 { { STATE_PSWOE }, 'm' },
3526 { { STATE_PSCALLINC }, 'm' },
3527 { { STATE_PSOWB }, 'm' },
3528 { { STATE_PSRING }, 'm' },
3529 { { STATE_PSUM }, 'm' },
3530 { { STATE_PSEXCM }, 'm' },
3531 { { STATE_PSINTLEVEL }, 'm' }
3534 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3535 { { 6 /* art */ }, 'o' }
3538 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3539 { { STATE_PSEXCM }, 'i' },
3540 { { STATE_PSRING }, 'i' },
3541 { { STATE_EPC1 }, 'i' }
3544 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3545 { { 6 /* art */ }, 'i' }
3548 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3549 { { STATE_PSEXCM }, 'i' },
3550 { { STATE_PSRING }, 'i' },
3551 { { STATE_EPC1 }, 'o' }
3554 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3555 { { 6 /* art */ }, 'm' }
3558 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3559 { { STATE_PSEXCM }, 'i' },
3560 { { STATE_PSRING }, 'i' },
3561 { { STATE_EPC1 }, 'm' }
3564 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3565 { { 6 /* art */ }, 'o' }
3568 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3569 { { STATE_PSEXCM }, 'i' },
3570 { { STATE_PSRING }, 'i' },
3571 { { STATE_EXCSAVE1 }, 'i' }
3574 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3575 { { 6 /* art */ }, 'i' }
3578 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3579 { { STATE_PSEXCM }, 'i' },
3580 { { STATE_PSRING }, 'i' },
3581 { { STATE_EXCSAVE1 }, 'o' }
3584 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3585 { { 6 /* art */ }, 'm' }
3588 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3589 { { STATE_PSEXCM }, 'i' },
3590 { { STATE_PSRING }, 'i' },
3591 { { STATE_EXCSAVE1 }, 'm' }
3594 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3595 { { 6 /* art */ }, 'o' }
3598 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3599 { { STATE_PSEXCM }, 'i' },
3600 { { STATE_PSRING }, 'i' },
3601 { { STATE_EPC2 }, 'i' }
3604 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3605 { { 6 /* art */ }, 'i' }
3608 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3609 { { STATE_PSEXCM }, 'i' },
3610 { { STATE_PSRING }, 'i' },
3611 { { STATE_EPC2 }, 'o' }
3614 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3615 { { 6 /* art */ }, 'm' }
3618 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3619 { { STATE_PSEXCM }, 'i' },
3620 { { STATE_PSRING }, 'i' },
3621 { { STATE_EPC2 }, 'm' }
3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3625 { { 6 /* art */ }, 'o' }
3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3629 { { STATE_PSEXCM }, 'i' },
3630 { { STATE_PSRING }, 'i' },
3631 { { STATE_EXCSAVE2 }, 'i' }
3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3635 { { 6 /* art */ }, 'i' }
3638 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3639 { { STATE_PSEXCM }, 'i' },
3640 { { STATE_PSRING }, 'i' },
3641 { { STATE_EXCSAVE2 }, 'o' }
3644 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3645 { { 6 /* art */ }, 'm' }
3648 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3649 { { STATE_PSEXCM }, 'i' },
3650 { { STATE_PSRING }, 'i' },
3651 { { STATE_EXCSAVE2 }, 'm' }
3654 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3655 { { 6 /* art */ }, 'o' }
3658 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3659 { { STATE_PSEXCM }, 'i' },
3660 { { STATE_PSRING }, 'i' },
3661 { { STATE_EPC3 }, 'i' }
3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3665 { { 6 /* art */ }, 'i' }
3668 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3669 { { STATE_PSEXCM }, 'i' },
3670 { { STATE_PSRING }, 'i' },
3671 { { STATE_EPC3 }, 'o' }
3674 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3675 { { 6 /* art */ }, 'm' }
3678 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3679 { { STATE_PSEXCM }, 'i' },
3680 { { STATE_PSRING }, 'i' },
3681 { { STATE_EPC3 }, 'm' }
3684 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3685 { { 6 /* art */ }, 'o' }
3688 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3689 { { STATE_PSEXCM }, 'i' },
3690 { { STATE_PSRING }, 'i' },
3691 { { STATE_EXCSAVE3 }, 'i' }
3694 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3695 { { 6 /* art */ }, 'i' }
3698 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3699 { { STATE_PSEXCM }, 'i' },
3700 { { STATE_PSRING }, 'i' },
3701 { { STATE_EXCSAVE3 }, 'o' }
3704 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3705 { { 6 /* art */ }, 'm' }
3708 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3709 { { STATE_PSEXCM }, 'i' },
3710 { { STATE_PSRING }, 'i' },
3711 { { STATE_EXCSAVE3 }, 'm' }
3714 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3715 { { 6 /* art */ }, 'o' }
3718 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3719 { { STATE_PSEXCM }, 'i' },
3720 { { STATE_PSRING }, 'i' },
3721 { { STATE_EPC4 }, 'i' }
3724 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3725 { { 6 /* art */ }, 'i' }
3728 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3729 { { STATE_PSEXCM }, 'i' },
3730 { { STATE_PSRING }, 'i' },
3731 { { STATE_EPC4 }, 'o' }
3734 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3735 { { 6 /* art */ }, 'm' }
3738 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3739 { { STATE_PSEXCM }, 'i' },
3740 { { STATE_PSRING }, 'i' },
3741 { { STATE_EPC4 }, 'm' }
3744 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3745 { { 6 /* art */ }, 'o' }
3748 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3749 { { STATE_PSEXCM }, 'i' },
3750 { { STATE_PSRING }, 'i' },
3751 { { STATE_EXCSAVE4 }, 'i' }
3754 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3755 { { 6 /* art */ }, 'i' }
3758 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3759 { { STATE_PSEXCM }, 'i' },
3760 { { STATE_PSRING }, 'i' },
3761 { { STATE_EXCSAVE4 }, 'o' }
3764 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3765 { { 6 /* art */ }, 'm' }
3768 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3769 { { STATE_PSEXCM }, 'i' },
3770 { { STATE_PSRING }, 'i' },
3771 { { STATE_EXCSAVE4 }, 'm' }
3774 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3775 { { 6 /* art */ }, 'o' }
3778 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3779 { { STATE_PSEXCM }, 'i' },
3780 { { STATE_PSRING }, 'i' },
3781 { { STATE_EPC5 }, 'i' }
3784 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3785 { { 6 /* art */ }, 'i' }
3788 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3789 { { STATE_PSEXCM }, 'i' },
3790 { { STATE_PSRING }, 'i' },
3791 { { STATE_EPC5 }, 'o' }
3794 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3795 { { 6 /* art */ }, 'm' }
3798 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3799 { { STATE_PSEXCM }, 'i' },
3800 { { STATE_PSRING }, 'i' },
3801 { { STATE_EPC5 }, 'm' }
3804 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3805 { { 6 /* art */ }, 'o' }
3808 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3809 { { STATE_PSEXCM }, 'i' },
3810 { { STATE_PSRING }, 'i' },
3811 { { STATE_EXCSAVE5 }, 'i' }
3814 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3815 { { 6 /* art */ }, 'i' }
3818 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3819 { { STATE_PSEXCM }, 'i' },
3820 { { STATE_PSRING }, 'i' },
3821 { { STATE_EXCSAVE5 }, 'o' }
3824 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3825 { { 6 /* art */ }, 'm' }
3828 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3829 { { STATE_PSEXCM }, 'i' },
3830 { { STATE_PSRING }, 'i' },
3831 { { STATE_EXCSAVE5 }, 'm' }
3834 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3835 { { 6 /* art */ }, 'o' }
3838 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3839 { { STATE_PSEXCM }, 'i' },
3840 { { STATE_PSRING }, 'i' },
3841 { { STATE_EPC6 }, 'i' }
3844 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
3845 { { 6 /* art */ }, 'i' }
3848 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
3849 { { STATE_PSEXCM }, 'i' },
3850 { { STATE_PSRING }, 'i' },
3851 { { STATE_EPC6 }, 'o' }
3854 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
3855 { { 6 /* art */ }, 'm' }
3858 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
3859 { { STATE_PSEXCM }, 'i' },
3860 { { STATE_PSRING }, 'i' },
3861 { { STATE_EPC6 }, 'm' }
3864 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
3865 { { 6 /* art */ }, 'o' }
3868 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
3869 { { STATE_PSEXCM }, 'i' },
3870 { { STATE_PSRING }, 'i' },
3871 { { STATE_EXCSAVE6 }, 'i' }
3874 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
3875 { { 6 /* art */ }, 'i' }
3878 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
3879 { { STATE_PSEXCM }, 'i' },
3880 { { STATE_PSRING }, 'i' },
3881 { { STATE_EXCSAVE6 }, 'o' }
3884 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
3885 { { 6 /* art */ }, 'm' }
3888 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
3889 { { STATE_PSEXCM }, 'i' },
3890 { { STATE_PSRING }, 'i' },
3891 { { STATE_EXCSAVE6 }, 'm' }
3894 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
3895 { { 6 /* art */ }, 'o' }
3898 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
3899 { { STATE_PSEXCM }, 'i' },
3900 { { STATE_PSRING }, 'i' },
3901 { { STATE_EPC7 }, 'i' }
3904 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
3905 { { 6 /* art */ }, 'i' }
3908 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
3909 { { STATE_PSEXCM }, 'i' },
3910 { { STATE_PSRING }, 'i' },
3911 { { STATE_EPC7 }, 'o' }
3914 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
3915 { { 6 /* art */ }, 'm' }
3918 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
3919 { { STATE_PSEXCM }, 'i' },
3920 { { STATE_PSRING }, 'i' },
3921 { { STATE_EPC7 }, 'm' }
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
3925 { { 6 /* art */ }, 'o' }
3928 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
3929 { { STATE_PSEXCM }, 'i' },
3930 { { STATE_PSRING }, 'i' },
3931 { { STATE_EXCSAVE7 }, 'i' }
3934 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
3935 { { 6 /* art */ }, 'i' }
3938 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
3939 { { STATE_PSEXCM }, 'i' },
3940 { { STATE_PSRING }, 'i' },
3941 { { STATE_EXCSAVE7 }, 'o' }
3944 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
3945 { { 6 /* art */ }, 'm' }
3948 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
3949 { { STATE_PSEXCM }, 'i' },
3950 { { STATE_PSRING }, 'i' },
3951 { { STATE_EXCSAVE7 }, 'm' }
3954 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3955 { { 6 /* art */ }, 'o' }
3958 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3959 { { STATE_PSEXCM }, 'i' },
3960 { { STATE_PSRING }, 'i' },
3961 { { STATE_EPS2 }, 'i' }
3964 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3965 { { 6 /* art */ }, 'i' }
3968 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3969 { { STATE_PSEXCM }, 'i' },
3970 { { STATE_PSRING }, 'i' },
3971 { { STATE_EPS2 }, 'o' }
3974 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3975 { { 6 /* art */ }, 'm' }
3978 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3979 { { STATE_PSEXCM }, 'i' },
3980 { { STATE_PSRING }, 'i' },
3981 { { STATE_EPS2 }, 'm' }
3984 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3985 { { 6 /* art */ }, 'o' }
3988 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3989 { { STATE_PSEXCM }, 'i' },
3990 { { STATE_PSRING }, 'i' },
3991 { { STATE_EPS3 }, 'i' }
3994 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3995 { { 6 /* art */ }, 'i' }
3998 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3999 { { STATE_PSEXCM }, 'i' },
4000 { { STATE_PSRING }, 'i' },
4001 { { STATE_EPS3 }, 'o' }
4004 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4005 { { 6 /* art */ }, 'm' }
4008 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4009 { { STATE_PSEXCM }, 'i' },
4010 { { STATE_PSRING }, 'i' },
4011 { { STATE_EPS3 }, 'm' }
4014 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4015 { { 6 /* art */ }, 'o' }
4018 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4019 { { STATE_PSEXCM }, 'i' },
4020 { { STATE_PSRING }, 'i' },
4021 { { STATE_EPS4 }, 'i' }
4024 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4025 { { 6 /* art */ }, 'i' }
4028 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4029 { { STATE_PSEXCM }, 'i' },
4030 { { STATE_PSRING }, 'i' },
4031 { { STATE_EPS4 }, 'o' }
4034 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4035 { { 6 /* art */ }, 'm' }
4038 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4039 { { STATE_PSEXCM }, 'i' },
4040 { { STATE_PSRING }, 'i' },
4041 { { STATE_EPS4 }, 'm' }
4044 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4045 { { 6 /* art */ }, 'o' }
4048 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4049 { { STATE_PSEXCM }, 'i' },
4050 { { STATE_PSRING }, 'i' },
4051 { { STATE_EPS5 }, 'i' }
4054 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4055 { { 6 /* art */ }, 'i' }
4058 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4059 { { STATE_PSEXCM }, 'i' },
4060 { { STATE_PSRING }, 'i' },
4061 { { STATE_EPS5 }, 'o' }
4064 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4065 { { 6 /* art */ }, 'm' }
4068 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4069 { { STATE_PSEXCM }, 'i' },
4070 { { STATE_PSRING }, 'i' },
4071 { { STATE_EPS5 }, 'm' }
4074 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4075 { { 6 /* art */ }, 'o' }
4078 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4079 { { STATE_PSEXCM }, 'i' },
4080 { { STATE_PSRING }, 'i' },
4081 { { STATE_EPS6 }, 'i' }
4084 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4085 { { 6 /* art */ }, 'i' }
4088 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4089 { { STATE_PSEXCM }, 'i' },
4090 { { STATE_PSRING }, 'i' },
4091 { { STATE_EPS6 }, 'o' }
4094 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4095 { { 6 /* art */ }, 'm' }
4098 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4099 { { STATE_PSEXCM }, 'i' },
4100 { { STATE_PSRING }, 'i' },
4101 { { STATE_EPS6 }, 'm' }
4104 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4105 { { 6 /* art */ }, 'o' }
4108 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4109 { { STATE_PSEXCM }, 'i' },
4110 { { STATE_PSRING }, 'i' },
4111 { { STATE_EPS7 }, 'i' }
4114 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4115 { { 6 /* art */ }, 'i' }
4118 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4119 { { STATE_PSEXCM }, 'i' },
4120 { { STATE_PSRING }, 'i' },
4121 { { STATE_EPS7 }, 'o' }
4124 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4125 { { 6 /* art */ }, 'm' }
4128 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4129 { { STATE_PSEXCM }, 'i' },
4130 { { STATE_PSRING }, 'i' },
4131 { { STATE_EPS7 }, 'm' }
4134 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4135 { { 6 /* art */ }, 'o' }
4138 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4139 { { STATE_PSEXCM }, 'i' },
4140 { { STATE_PSRING }, 'i' },
4141 { { STATE_EXCVADDR }, 'i' }
4144 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4145 { { 6 /* art */ }, 'i' }
4148 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4149 { { STATE_PSEXCM }, 'i' },
4150 { { STATE_PSRING }, 'i' },
4151 { { STATE_EXCVADDR }, 'o' }
4154 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4155 { { 6 /* art */ }, 'm' }
4158 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4159 { { STATE_PSEXCM }, 'i' },
4160 { { STATE_PSRING }, 'i' },
4161 { { STATE_EXCVADDR }, 'm' }
4164 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4165 { { 6 /* art */ }, 'o' }
4168 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4169 { { STATE_PSEXCM }, 'i' },
4170 { { STATE_PSRING }, 'i' },
4171 { { STATE_DEPC }, 'i' }
4174 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4175 { { 6 /* art */ }, 'i' }
4178 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4179 { { STATE_PSEXCM }, 'i' },
4180 { { STATE_PSRING }, 'i' },
4181 { { STATE_DEPC }, 'o' }
4184 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4185 { { 6 /* art */ }, 'm' }
4188 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4189 { { STATE_PSEXCM }, 'i' },
4190 { { STATE_PSRING }, 'i' },
4191 { { STATE_DEPC }, 'm' }
4194 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4195 { { 6 /* art */ }, 'o' }
4198 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4199 { { STATE_PSEXCM }, 'i' },
4200 { { STATE_PSRING }, 'i' },
4201 { { STATE_EXCCAUSE }, 'i' },
4202 { { STATE_XTSYNC }, 'i' }
4205 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4206 { { 6 /* art */ }, 'i' }
4209 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4210 { { STATE_PSEXCM }, 'i' },
4211 { { STATE_PSRING }, 'i' },
4212 { { STATE_EXCCAUSE }, 'o' }
4215 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4216 { { 6 /* art */ }, 'm' }
4219 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4220 { { STATE_PSEXCM }, 'i' },
4221 { { STATE_PSRING }, 'i' },
4222 { { STATE_EXCCAUSE }, 'm' }
4225 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4226 { { 6 /* art */ }, 'o' }
4229 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4230 { { STATE_PSEXCM }, 'i' },
4231 { { STATE_PSRING }, 'i' },
4232 { { STATE_MISC0 }, 'i' }
4235 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4236 { { 6 /* art */ }, 'i' }
4239 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4240 { { STATE_PSEXCM }, 'i' },
4241 { { STATE_PSRING }, 'i' },
4242 { { STATE_MISC0 }, 'o' }
4245 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4246 { { 6 /* art */ }, 'm' }
4249 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4250 { { STATE_PSEXCM }, 'i' },
4251 { { STATE_PSRING }, 'i' },
4252 { { STATE_MISC0 }, 'm' }
4255 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4256 { { 6 /* art */ }, 'o' }
4259 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4260 { { STATE_PSEXCM }, 'i' },
4261 { { STATE_PSRING }, 'i' },
4262 { { STATE_MISC1 }, 'i' }
4265 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4266 { { 6 /* art */ }, 'i' }
4269 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4270 { { STATE_PSEXCM }, 'i' },
4271 { { STATE_PSRING }, 'i' },
4272 { { STATE_MISC1 }, 'o' }
4275 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4276 { { 6 /* art */ }, 'm' }
4279 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4280 { { STATE_PSEXCM }, 'i' },
4281 { { STATE_PSRING }, 'i' },
4282 { { STATE_MISC1 }, 'm' }
4285 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4286 { { 6 /* art */ }, 'o' }
4289 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
4290 { { STATE_PSEXCM }, 'i' },
4291 { { STATE_PSRING }, 'i' }
4294 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4295 { { 6 /* art */ }, 'o' }
4298 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4299 { { STATE_PSEXCM }, 'i' },
4300 { { STATE_PSRING }, 'i' },
4301 { { STATE_VECBASE }, 'i' }
4304 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4305 { { 6 /* art */ }, 'i' }
4308 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4309 { { STATE_PSEXCM }, 'i' },
4310 { { STATE_PSRING }, 'i' },
4311 { { STATE_VECBASE }, 'o' }
4314 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4315 { { 6 /* art */ }, 'm' }
4318 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4319 { { STATE_PSEXCM }, 'i' },
4320 { { STATE_PSRING }, 'i' },
4321 { { STATE_VECBASE }, 'm' }
4324 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4325 { { 4 /* ars */ }, 'i' },
4326 { { 6 /* art */ }, 'i' }
4329 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4330 { { STATE_ACC }, 'o' }
4333 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4334 { { 4 /* ars */ }, 'i' },
4335 { { 34 /* my */ }, 'i' }
4338 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4339 { { STATE_ACC }, 'o' }
4342 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4343 { { 33 /* mx */ }, 'i' },
4344 { { 6 /* art */ }, 'i' }
4347 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4348 { { STATE_ACC }, 'o' }
4351 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4352 { { 33 /* mx */ }, 'i' },
4353 { { 34 /* my */ }, 'i' }
4356 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4357 { { STATE_ACC }, 'o' }
4360 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4361 { { 4 /* ars */ }, 'i' },
4362 { { 6 /* art */ }, 'i' }
4365 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4366 { { STATE_ACC }, 'm' }
4369 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4370 { { 4 /* ars */ }, 'i' },
4371 { { 34 /* my */ }, 'i' }
4374 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4375 { { STATE_ACC }, 'm' }
4378 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4379 { { 33 /* mx */ }, 'i' },
4380 { { 6 /* art */ }, 'i' }
4383 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4384 { { STATE_ACC }, 'm' }
4387 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4388 { { 33 /* mx */ }, 'i' },
4389 { { 34 /* my */ }, 'i' }
4392 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4393 { { STATE_ACC }, 'm' }
4396 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4397 { { 35 /* mw */ }, 'o' },
4398 { { 4 /* ars */ }, 'm' },
4399 { { 33 /* mx */ }, 'i' },
4400 { { 6 /* art */ }, 'i' }
4403 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4404 { { STATE_ACC }, 'm' }
4407 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4408 { { 35 /* mw */ }, 'o' },
4409 { { 4 /* ars */ }, 'm' },
4410 { { 33 /* mx */ }, 'i' },
4411 { { 34 /* my */ }, 'i' }
4414 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4415 { { STATE_ACC }, 'm' }
4418 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4419 { { 35 /* mw */ }, 'o' },
4420 { { 4 /* ars */ }, 'm' }
4423 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
4424 { { 3 /* arr */ }, 'o' },
4425 { { 4 /* ars */ }, 'i' },
4426 { { 6 /* art */ }, 'i' }
4429 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4430 { { 6 /* art */ }, 'o' },
4431 { { 36 /* mr0 */ }, 'i' }
4434 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4435 { { 6 /* art */ }, 'i' },
4436 { { 36 /* mr0 */ }, 'o' }
4439 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4440 { { 6 /* art */ }, 'm' },
4441 { { 36 /* mr0 */ }, 'm' }
4444 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4445 { { 6 /* art */ }, 'o' },
4446 { { 37 /* mr1 */ }, 'i' }
4449 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4450 { { 6 /* art */ }, 'i' },
4451 { { 37 /* mr1 */ }, 'o' }
4454 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4455 { { 6 /* art */ }, 'm' },
4456 { { 37 /* mr1 */ }, 'm' }
4459 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4460 { { 6 /* art */ }, 'o' },
4461 { { 38 /* mr2 */ }, 'i' }
4464 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4465 { { 6 /* art */ }, 'i' },
4466 { { 38 /* mr2 */ }, 'o' }
4469 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4470 { { 6 /* art */ }, 'm' },
4471 { { 38 /* mr2 */ }, 'm' }
4474 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4475 { { 6 /* art */ }, 'o' },
4476 { { 39 /* mr3 */ }, 'i' }
4479 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4480 { { 6 /* art */ }, 'i' },
4481 { { 39 /* mr3 */ }, 'o' }
4484 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4485 { { 6 /* art */ }, 'm' },
4486 { { 39 /* mr3 */ }, 'm' }
4489 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4490 { { 6 /* art */ }, 'o' }
4493 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4494 { { STATE_ACC }, 'i' }
4497 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4498 { { 6 /* art */ }, 'i' }
4501 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4502 { { STATE_ACC }, 'm' }
4505 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4506 { { 6 /* art */ }, 'm' }
4509 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4510 { { STATE_ACC }, 'm' }
4513 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4514 { { 6 /* art */ }, 'o' }
4517 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4518 { { STATE_ACC }, 'i' }
4521 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4522 { { 6 /* art */ }, 'i' }
4525 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4526 { { STATE_ACC }, 'm' }
4529 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4530 { { 6 /* art */ }, 'm' }
4533 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4534 { { STATE_ACC }, 'm' }
4537 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4538 { { 50 /* s */ }, 'i' }
4541 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4542 { { STATE_PSWOE }, 'o' },
4543 { { STATE_PSCALLINC }, 'o' },
4544 { { STATE_PSOWB }, 'o' },
4545 { { STATE_PSRING }, 'm' },
4546 { { STATE_PSUM }, 'o' },
4547 { { STATE_PSEXCM }, 'm' },
4548 { { STATE_PSINTLEVEL }, 'o' },
4549 { { STATE_EPC1 }, 'i' },
4550 { { STATE_EPC2 }, 'i' },
4551 { { STATE_EPC3 }, 'i' },
4552 { { STATE_EPC4 }, 'i' },
4553 { { STATE_EPC5 }, 'i' },
4554 { { STATE_EPC6 }, 'i' },
4555 { { STATE_EPC7 }, 'i' },
4556 { { STATE_EPS2 }, 'i' },
4557 { { STATE_EPS3 }, 'i' },
4558 { { STATE_EPS4 }, 'i' },
4559 { { STATE_EPS5 }, 'i' },
4560 { { STATE_EPS6 }, 'i' },
4561 { { STATE_EPS7 }, 'i' },
4562 { { STATE_InOCDMode }, 'm' }
4565 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4566 { { 50 /* s */ }, 'i' }
4569 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4570 { { STATE_PSEXCM }, 'i' },
4571 { { STATE_PSRING }, 'i' },
4572 { { STATE_PSINTLEVEL }, 'o' }
4575 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4576 { { 6 /* art */ }, 'o' }
4579 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4580 { { STATE_PSEXCM }, 'i' },
4581 { { STATE_PSRING }, 'i' },
4582 { { STATE_INTERRUPT }, 'i' }
4585 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4586 { { 6 /* art */ }, 'i' }
4589 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4590 { { STATE_PSEXCM }, 'i' },
4591 { { STATE_PSRING }, 'i' },
4592 { { STATE_XTSYNC }, 'o' },
4593 { { STATE_INTERRUPT }, 'm' }
4596 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4597 { { 6 /* art */ }, 'i' }
4600 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4601 { { STATE_PSEXCM }, 'i' },
4602 { { STATE_PSRING }, 'i' },
4603 { { STATE_XTSYNC }, 'o' },
4604 { { STATE_INTERRUPT }, 'm' }
4607 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4608 { { 6 /* art */ }, 'o' }
4611 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4612 { { STATE_PSEXCM }, 'i' },
4613 { { STATE_PSRING }, 'i' },
4614 { { STATE_INTENABLE }, 'i' }
4617 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4618 { { 6 /* art */ }, 'i' }
4621 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4622 { { STATE_PSEXCM }, 'i' },
4623 { { STATE_PSRING }, 'i' },
4624 { { STATE_INTENABLE }, 'o' }
4627 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4628 { { 6 /* art */ }, 'm' }
4631 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4632 { { STATE_PSEXCM }, 'i' },
4633 { { STATE_PSRING }, 'i' },
4634 { { STATE_INTENABLE }, 'm' }
4637 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4638 { { 41 /* imms */ }, 'i' },
4639 { { 40 /* immt */ }, 'i' }
4642 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4643 { { STATE_PSEXCM }, 'i' },
4644 { { STATE_PSINTLEVEL }, 'i' }
4647 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4648 { { 41 /* imms */ }, 'i' }
4651 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4652 { { STATE_PSEXCM }, 'i' },
4653 { { STATE_PSINTLEVEL }, 'i' }
4656 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4657 { { 6 /* art */ }, 'o' }
4660 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4661 { { STATE_PSEXCM }, 'i' },
4662 { { STATE_PSRING }, 'i' },
4663 { { STATE_DBREAKA0 }, 'i' }
4666 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4667 { { 6 /* art */ }, 'i' }
4670 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4671 { { STATE_PSEXCM }, 'i' },
4672 { { STATE_PSRING }, 'i' },
4673 { { STATE_DBREAKA0 }, 'o' },
4674 { { STATE_XTSYNC }, 'o' }
4677 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4678 { { 6 /* art */ }, 'm' }
4681 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4682 { { STATE_PSEXCM }, 'i' },
4683 { { STATE_PSRING }, 'i' },
4684 { { STATE_DBREAKA0 }, 'm' },
4685 { { STATE_XTSYNC }, 'o' }
4688 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4689 { { 6 /* art */ }, 'o' }
4692 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4693 { { STATE_PSEXCM }, 'i' },
4694 { { STATE_PSRING }, 'i' },
4695 { { STATE_DBREAKC0 }, 'i' }
4698 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4699 { { 6 /* art */ }, 'i' }
4702 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4703 { { STATE_PSEXCM }, 'i' },
4704 { { STATE_PSRING }, 'i' },
4705 { { STATE_DBREAKC0 }, 'o' },
4706 { { STATE_XTSYNC }, 'o' }
4709 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4710 { { 6 /* art */ }, 'm' }
4713 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4714 { { STATE_PSEXCM }, 'i' },
4715 { { STATE_PSRING }, 'i' },
4716 { { STATE_DBREAKC0 }, 'm' },
4717 { { STATE_XTSYNC }, 'o' }
4720 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4721 { { 6 /* art */ }, 'o' }
4724 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4725 { { STATE_PSEXCM }, 'i' },
4726 { { STATE_PSRING }, 'i' },
4727 { { STATE_DBREAKA1 }, 'i' }
4730 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4731 { { 6 /* art */ }, 'i' }
4734 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4735 { { STATE_PSEXCM }, 'i' },
4736 { { STATE_PSRING }, 'i' },
4737 { { STATE_DBREAKA1 }, 'o' },
4738 { { STATE_XTSYNC }, 'o' }
4741 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4742 { { 6 /* art */ }, 'm' }
4745 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4746 { { STATE_PSEXCM }, 'i' },
4747 { { STATE_PSRING }, 'i' },
4748 { { STATE_DBREAKA1 }, 'm' },
4749 { { STATE_XTSYNC }, 'o' }
4752 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4753 { { 6 /* art */ }, 'o' }
4756 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4757 { { STATE_PSEXCM }, 'i' },
4758 { { STATE_PSRING }, 'i' },
4759 { { STATE_DBREAKC1 }, 'i' }
4762 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4763 { { 6 /* art */ }, 'i' }
4766 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4767 { { STATE_PSEXCM }, 'i' },
4768 { { STATE_PSRING }, 'i' },
4769 { { STATE_DBREAKC1 }, 'o' },
4770 { { STATE_XTSYNC }, 'o' }
4773 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4774 { { 6 /* art */ }, 'm' }
4777 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4778 { { STATE_PSEXCM }, 'i' },
4779 { { STATE_PSRING }, 'i' },
4780 { { STATE_DBREAKC1 }, 'm' },
4781 { { STATE_XTSYNC }, 'o' }
4784 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4785 { { 6 /* art */ }, 'o' }
4788 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4789 { { STATE_PSEXCM }, 'i' },
4790 { { STATE_PSRING }, 'i' },
4791 { { STATE_IBREAKA0 }, 'i' }
4794 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4795 { { 6 /* art */ }, 'i' }
4798 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4799 { { STATE_PSEXCM }, 'i' },
4800 { { STATE_PSRING }, 'i' },
4801 { { STATE_IBREAKA0 }, 'o' }
4804 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4805 { { 6 /* art */ }, 'm' }
4808 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4809 { { STATE_PSEXCM }, 'i' },
4810 { { STATE_PSRING }, 'i' },
4811 { { STATE_IBREAKA0 }, 'm' }
4814 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4815 { { 6 /* art */ }, 'o' }
4818 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4819 { { STATE_PSEXCM }, 'i' },
4820 { { STATE_PSRING }, 'i' },
4821 { { STATE_IBREAKA1 }, 'i' }
4824 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4825 { { 6 /* art */ }, 'i' }
4828 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4829 { { STATE_PSEXCM }, 'i' },
4830 { { STATE_PSRING }, 'i' },
4831 { { STATE_IBREAKA1 }, 'o' }
4834 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4835 { { 6 /* art */ }, 'm' }
4838 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4839 { { STATE_PSEXCM }, 'i' },
4840 { { STATE_PSRING }, 'i' },
4841 { { STATE_IBREAKA1 }, 'm' }
4844 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4845 { { 6 /* art */ }, 'o' }
4848 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4849 { { STATE_PSEXCM }, 'i' },
4850 { { STATE_PSRING }, 'i' },
4851 { { STATE_IBREAKENABLE }, 'i' }
4854 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4855 { { 6 /* art */ }, 'i' }
4858 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4859 { { STATE_PSEXCM }, 'i' },
4860 { { STATE_PSRING }, 'i' },
4861 { { STATE_IBREAKENABLE }, 'o' }
4864 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4865 { { 6 /* art */ }, 'm' }
4868 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4869 { { STATE_PSEXCM }, 'i' },
4870 { { STATE_PSRING }, 'i' },
4871 { { STATE_IBREAKENABLE }, 'm' }
4874 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4875 { { 6 /* art */ }, 'o' }
4878 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4879 { { STATE_PSEXCM }, 'i' },
4880 { { STATE_PSRING }, 'i' },
4881 { { STATE_DEBUGCAUSE }, 'i' },
4882 { { STATE_DBNUM }, 'i' }
4885 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4886 { { 6 /* art */ }, 'i' }
4889 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4890 { { STATE_PSEXCM }, 'i' },
4891 { { STATE_PSRING }, 'i' },
4892 { { STATE_DEBUGCAUSE }, 'o' },
4893 { { STATE_DBNUM }, 'o' }
4896 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4897 { { 6 /* art */ }, 'm' }
4900 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4901 { { STATE_PSEXCM }, 'i' },
4902 { { STATE_PSRING }, 'i' },
4903 { { STATE_DEBUGCAUSE }, 'm' },
4904 { { STATE_DBNUM }, 'm' }
4907 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4908 { { 6 /* art */ }, 'o' }
4911 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4912 { { STATE_PSEXCM }, 'i' },
4913 { { STATE_PSRING }, 'i' },
4914 { { STATE_ICOUNT }, 'i' }
4917 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4918 { { 6 /* art */ }, 'i' }
4921 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4922 { { STATE_PSEXCM }, 'i' },
4923 { { STATE_PSRING }, 'i' },
4924 { { STATE_XTSYNC }, 'o' },
4925 { { STATE_ICOUNT }, 'o' }
4928 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4929 { { 6 /* art */ }, 'm' }
4932 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4933 { { STATE_PSEXCM }, 'i' },
4934 { { STATE_PSRING }, 'i' },
4935 { { STATE_XTSYNC }, 'o' },
4936 { { STATE_ICOUNT }, 'm' }
4939 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4940 { { 6 /* art */ }, 'o' }
4943 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4944 { { STATE_PSEXCM }, 'i' },
4945 { { STATE_PSRING }, 'i' },
4946 { { STATE_ICOUNTLEVEL }, 'i' }
4949 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4950 { { 6 /* art */ }, 'i' }
4953 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4954 { { STATE_PSEXCM }, 'i' },
4955 { { STATE_PSRING }, 'i' },
4956 { { STATE_ICOUNTLEVEL }, 'o' }
4959 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4960 { { 6 /* art */ }, 'm' }
4963 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4964 { { STATE_PSEXCM }, 'i' },
4965 { { STATE_PSRING }, 'i' },
4966 { { STATE_ICOUNTLEVEL }, 'm' }
4969 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4970 { { 6 /* art */ }, 'o' }
4973 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4974 { { STATE_PSEXCM }, 'i' },
4975 { { STATE_PSRING }, 'i' },
4976 { { STATE_DDR }, 'i' }
4979 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4980 { { 6 /* art */ }, 'i' }
4983 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4984 { { STATE_PSEXCM }, 'i' },
4985 { { STATE_PSRING }, 'i' },
4986 { { STATE_XTSYNC }, 'o' },
4987 { { STATE_DDR }, 'o' }
4990 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4991 { { 6 /* art */ }, 'm' }
4994 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4995 { { STATE_PSEXCM }, 'i' },
4996 { { STATE_PSRING }, 'i' },
4997 { { STATE_XTSYNC }, 'o' },
4998 { { STATE_DDR }, 'm' }
5001 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
5002 { { 41 /* imms */ }, 'i' }
5005 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
5006 { { STATE_InOCDMode }, 'm' },
5007 { { STATE_EPC6 }, 'i' },
5008 { { STATE_PSWOE }, 'o' },
5009 { { STATE_PSCALLINC }, 'o' },
5010 { { STATE_PSOWB }, 'o' },
5011 { { STATE_PSRING }, 'o' },
5012 { { STATE_PSUM }, 'o' },
5013 { { STATE_PSEXCM }, 'o' },
5014 { { STATE_PSINTLEVEL }, 'o' },
5015 { { STATE_EPS6 }, 'i' }
5018 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
5019 { { STATE_InOCDMode }, 'm' }
5022 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
5023 { { 6 /* art */ }, 'i' }
5026 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
5027 { { STATE_PSEXCM }, 'i' },
5028 { { STATE_PSRING }, 'i' },
5029 { { STATE_XTSYNC }, 'o' }
5032 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
5033 { { 6 /* art */ }, 'o' }
5036 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
5037 { { STATE_PSEXCM }, 'i' },
5038 { { STATE_PSRING }, 'i' },
5039 { { STATE_CCOUNT }, 'i' }
5042 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
5043 { { 6 /* art */ }, 'i' }
5046 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
5047 { { STATE_PSEXCM }, 'i' },
5048 { { STATE_PSRING }, 'i' },
5049 { { STATE_XTSYNC }, 'o' },
5050 { { STATE_CCOUNT }, 'o' }
5053 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
5054 { { 6 /* art */ }, 'm' }
5057 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
5058 { { STATE_PSEXCM }, 'i' },
5059 { { STATE_PSRING }, 'i' },
5060 { { STATE_XTSYNC }, 'o' },
5061 { { STATE_CCOUNT }, 'm' }
5064 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
5065 { { 6 /* art */ }, 'o' }
5068 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
5069 { { STATE_PSEXCM }, 'i' },
5070 { { STATE_PSRING }, 'i' },
5071 { { STATE_CCOMPARE0 }, 'i' }
5074 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
5075 { { 6 /* art */ }, 'i' }
5078 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
5079 { { STATE_PSEXCM }, 'i' },
5080 { { STATE_PSRING }, 'i' },
5081 { { STATE_CCOMPARE0 }, 'o' },
5082 { { STATE_INTERRUPT }, 'm' }
5085 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
5086 { { 6 /* art */ }, 'm' }
5089 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
5090 { { STATE_PSEXCM }, 'i' },
5091 { { STATE_PSRING }, 'i' },
5092 { { STATE_CCOMPARE0 }, 'm' },
5093 { { STATE_INTERRUPT }, 'm' }
5096 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
5097 { { 6 /* art */ }, 'o' }
5100 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
5101 { { STATE_PSEXCM }, 'i' },
5102 { { STATE_PSRING }, 'i' },
5103 { { STATE_CCOMPARE1 }, 'i' }
5106 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
5107 { { 6 /* art */ }, 'i' }
5110 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
5111 { { STATE_PSEXCM }, 'i' },
5112 { { STATE_PSRING }, 'i' },
5113 { { STATE_CCOMPARE1 }, 'o' },
5114 { { STATE_INTERRUPT }, 'm' }
5117 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
5118 { { 6 /* art */ }, 'm' }
5121 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
5122 { { STATE_PSEXCM }, 'i' },
5123 { { STATE_PSRING }, 'i' },
5124 { { STATE_CCOMPARE1 }, 'm' },
5125 { { STATE_INTERRUPT }, 'm' }
5128 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
5129 { { 6 /* art */ }, 'o' }
5132 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
5133 { { STATE_PSEXCM }, 'i' },
5134 { { STATE_PSRING }, 'i' },
5135 { { STATE_CCOMPARE2 }, 'i' }
5138 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
5139 { { 6 /* art */ }, 'i' }
5142 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
5143 { { STATE_PSEXCM }, 'i' },
5144 { { STATE_PSRING }, 'i' },
5145 { { STATE_CCOMPARE2 }, 'o' },
5146 { { STATE_INTERRUPT }, 'm' }
5149 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
5150 { { 6 /* art */ }, 'm' }
5153 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
5154 { { STATE_PSEXCM }, 'i' },
5155 { { STATE_PSRING }, 'i' },
5156 { { STATE_CCOMPARE2 }, 'm' },
5157 { { STATE_INTERRUPT }, 'm' }
5160 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
5161 { { 4 /* ars */ }, 'i' },
5162 { { 21 /* uimm8x4 */ }, 'i' }
5165 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
5166 { { 4 /* ars */ }, 'i' },
5167 { { 22 /* uimm4x16 */ }, 'i' }
5170 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
5171 { { STATE_PSEXCM }, 'i' },
5172 { { STATE_PSRING }, 'i' }
5175 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
5176 { { 4 /* ars */ }, 'i' },
5177 { { 21 /* uimm8x4 */ }, 'i' }
5180 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
5181 { { STATE_PSEXCM }, 'i' },
5182 { { STATE_PSRING }, 'i' }
5185 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
5186 { { 6 /* art */ }, 'o' },
5187 { { 4 /* ars */ }, 'i' }
5190 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
5191 { { STATE_PSEXCM }, 'i' },
5192 { { STATE_PSRING }, 'i' }
5195 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
5196 { { 6 /* art */ }, 'i' },
5197 { { 4 /* ars */ }, 'i' }
5200 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
5201 { { STATE_PSEXCM }, 'i' },
5202 { { STATE_PSRING }, 'i' }
5205 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
5206 { { 4 /* ars */ }, 'i' },
5207 { { 21 /* uimm8x4 */ }, 'i' }
5210 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
5211 { { 4 /* ars */ }, 'i' },
5212 { { 22 /* uimm4x16 */ }, 'i' }
5215 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
5216 { { STATE_PSEXCM }, 'i' },
5217 { { STATE_PSRING }, 'i' }
5220 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
5221 { { 4 /* ars */ }, 'i' },
5222 { { 21 /* uimm8x4 */ }, 'i' }
5225 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
5226 { { STATE_PSEXCM }, 'i' },
5227 { { STATE_PSRING }, 'i' }
5230 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
5231 { { 4 /* ars */ }, 'i' },
5232 { { 21 /* uimm8x4 */ }, 'i' }
5235 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
5236 { { 4 /* ars */ }, 'i' },
5237 { { 22 /* uimm4x16 */ }, 'i' }
5240 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
5241 { { STATE_PSEXCM }, 'i' },
5242 { { STATE_PSRING }, 'i' }
5245 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
5246 { { 6 /* art */ }, 'i' },
5247 { { 4 /* ars */ }, 'i' }
5250 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
5251 { { STATE_PSEXCM }, 'i' },
5252 { { STATE_PSRING }, 'i' }
5255 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
5256 { { 6 /* art */ }, 'o' },
5257 { { 4 /* ars */ }, 'i' }
5260 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
5261 { { STATE_PSEXCM }, 'i' },
5262 { { STATE_PSRING }, 'i' }
5265 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
5266 { { 6 /* art */ }, 'i' }
5269 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
5270 { { STATE_PSEXCM }, 'i' },
5271 { { STATE_PSRING }, 'i' },
5272 { { STATE_PTBASE }, 'o' },
5273 { { STATE_XTSYNC }, 'o' }
5276 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
5277 { { 6 /* art */ }, 'o' }
5280 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
5281 { { STATE_PSEXCM }, 'i' },
5282 { { STATE_PSRING }, 'i' },
5283 { { STATE_PTBASE }, 'i' },
5284 { { STATE_EXCVADDR }, 'i' }
5287 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
5288 { { 6 /* art */ }, 'm' }
5291 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
5292 { { STATE_PSEXCM }, 'i' },
5293 { { STATE_PSRING }, 'i' },
5294 { { STATE_PTBASE }, 'm' },
5295 { { STATE_EXCVADDR }, 'i' },
5296 { { STATE_XTSYNC }, 'o' }
5299 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
5300 { { 6 /* art */ }, 'o' }
5303 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
5304 { { STATE_PSEXCM }, 'i' },
5305 { { STATE_PSRING }, 'i' },
5306 { { STATE_ASID3 }, 'i' },
5307 { { STATE_ASID2 }, 'i' },
5308 { { STATE_ASID1 }, 'i' }
5311 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
5312 { { 6 /* art */ }, 'i' }
5315 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
5316 { { STATE_XTSYNC }, 'o' },
5317 { { STATE_PSEXCM }, 'i' },
5318 { { STATE_PSRING }, 'i' },
5319 { { STATE_ASID3 }, 'o' },
5320 { { STATE_ASID2 }, 'o' },
5321 { { STATE_ASID1 }, 'o' }
5324 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
5325 { { 6 /* art */ }, 'm' }
5328 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
5329 { { STATE_XTSYNC }, 'o' },
5330 { { STATE_PSEXCM }, 'i' },
5331 { { STATE_PSRING }, 'i' },
5332 { { STATE_ASID3 }, 'm' },
5333 { { STATE_ASID2 }, 'm' },
5334 { { STATE_ASID1 }, 'm' }
5337 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
5338 { { 6 /* art */ }, 'o' }
5341 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
5342 { { STATE_PSEXCM }, 'i' },
5343 { { STATE_PSRING }, 'i' },
5344 { { STATE_INSTPGSZID4 }, 'i' }
5347 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
5348 { { 6 /* art */ }, 'i' }
5351 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
5352 { { STATE_XTSYNC }, 'o' },
5353 { { STATE_PSEXCM }, 'i' },
5354 { { STATE_PSRING }, 'i' },
5355 { { STATE_INSTPGSZID4 }, 'o' }
5358 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
5359 { { 6 /* art */ }, 'm' }
5362 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
5363 { { STATE_XTSYNC }, 'o' },
5364 { { STATE_PSEXCM }, 'i' },
5365 { { STATE_PSRING }, 'i' },
5366 { { STATE_INSTPGSZID4 }, 'm' }
5369 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
5370 { { 6 /* art */ }, 'o' }
5373 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
5374 { { STATE_PSEXCM }, 'i' },
5375 { { STATE_PSRING }, 'i' },
5376 { { STATE_DATAPGSZID4 }, 'i' }
5379 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
5380 { { 6 /* art */ }, 'i' }
5383 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
5384 { { STATE_XTSYNC }, 'o' },
5385 { { STATE_PSEXCM }, 'i' },
5386 { { STATE_PSRING }, 'i' },
5387 { { STATE_DATAPGSZID4 }, 'o' }
5390 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
5391 { { 6 /* art */ }, 'm' }
5394 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
5395 { { STATE_XTSYNC }, 'o' },
5396 { { STATE_PSEXCM }, 'i' },
5397 { { STATE_PSRING }, 'i' },
5398 { { STATE_DATAPGSZID4 }, 'm' }
5401 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
5402 { { 4 /* ars */ }, 'i' }
5405 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
5406 { { STATE_PSEXCM }, 'i' },
5407 { { STATE_PSRING }, 'i' },
5408 { { STATE_XTSYNC }, 'o' }
5411 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
5412 { { 6 /* art */ }, 'o' },
5413 { { 4 /* ars */ }, 'i' }
5416 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
5417 { { STATE_PSEXCM }, 'i' },
5418 { { STATE_PSRING }, 'i' }
5421 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
5422 { { 6 /* art */ }, 'i' },
5423 { { 4 /* ars */ }, 'i' }
5426 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
5427 { { STATE_PSEXCM }, 'i' },
5428 { { STATE_PSRING }, 'i' },
5429 { { STATE_XTSYNC }, 'o' }
5432 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
5433 { { 4 /* ars */ }, 'i' }
5436 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
5437 { { STATE_PSEXCM }, 'i' },
5438 { { STATE_PSRING }, 'i' }
5441 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
5442 { { 6 /* art */ }, 'o' },
5443 { { 4 /* ars */ }, 'i' }
5446 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
5447 { { STATE_PSEXCM }, 'i' },
5448 { { STATE_PSRING }, 'i' }
5451 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
5452 { { 6 /* art */ }, 'i' },
5453 { { 4 /* ars */ }, 'i' }
5456 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
5457 { { STATE_PSEXCM }, 'i' },
5458 { { STATE_PSRING }, 'i' }
5461 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
5462 { { STATE_PTBASE }, 'i' },
5463 { { STATE_EXCVADDR }, 'i' }
5466 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
5467 { { STATE_EXCVADDR }, 'i' }
5470 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
5471 { { STATE_EXCVADDR }, 'i' }
5474 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
5475 { { 6 /* art */ }, 'o' }
5478 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
5479 { { STATE_PSEXCM }, 'i' },
5480 { { STATE_PSRING }, 'i' },
5481 { { STATE_CPENABLE }, 'i' }
5484 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
5485 { { 6 /* art */ }, 'i' }
5488 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
5489 { { STATE_PSEXCM }, 'i' },
5490 { { STATE_PSRING }, 'i' },
5491 { { STATE_CPENABLE }, 'o' }
5494 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
5495 { { 6 /* art */ }, 'm' }
5498 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
5499 { { STATE_PSEXCM }, 'i' },
5500 { { STATE_PSRING }, 'i' },
5501 { { STATE_CPENABLE }, 'm' }
5504 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
5505 { { 3 /* arr */ }, 'o' },
5506 { { 4 /* ars */ }, 'i' },
5507 { { 42 /* tp7 */ }, 'i' }
5510 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
5511 { { 3 /* arr */ }, 'o' },
5512 { { 4 /* ars */ }, 'i' },
5513 { { 6 /* art */ }, 'i' }
5516 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
5517 { { 6 /* art */ }, 'o' },
5518 { { 4 /* ars */ }, 'i' }
5521 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
5522 { { 3 /* arr */ }, 'o' },
5523 { { 4 /* ars */ }, 'i' },
5524 { { 42 /* tp7 */ }, 'i' }
5527 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
5528 { { 6 /* art */ }, 'o' },
5529 { { 4 /* ars */ }, 'i' },
5530 { { 21 /* uimm8x4 */ }, 'i' }
5533 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
5534 { { 6 /* art */ }, 'i' },
5535 { { 4 /* ars */ }, 'i' },
5536 { { 21 /* uimm8x4 */ }, 'i' }
5539 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
5540 { { 6 /* art */ }, 'm' },
5541 { { 4 /* ars */ }, 'i' },
5542 { { 21 /* uimm8x4 */ }, 'i' }
5545 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
5546 { { STATE_SCOMPARE1 }, 'i' },
5547 { { STATE_SCOMPARE1 }, 'i' }
5550 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
5551 { { 6 /* art */ }, 'o' }
5554 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
5555 { { STATE_SCOMPARE1 }, 'i' }
5558 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
5559 { { 6 /* art */ }, 'i' }
5562 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
5563 { { STATE_SCOMPARE1 }, 'o' }
5566 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
5567 { { 6 /* art */ }, 'm' }
5570 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
5571 { { STATE_SCOMPARE1 }, 'm' }
5574 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
5575 { { 3 /* arr */ }, 'o' },
5576 { { 4 /* ars */ }, 'i' },
5577 { { 6 /* art */ }, 'i' }
5580 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
5581 { { 3 /* arr */ }, 'o' },
5582 { { 4 /* ars */ }, 'i' },
5583 { { 6 /* art */ }, 'i' }
5586 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
5587 { { 3 /* arr */ }, 'o' }
5590 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
5591 { { STATE_EXPSTATE }, 'i' },
5592 { { STATE_CPENABLE }, 'i' }
5595 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
5596 { { 6 /* art */ }, 'i' }
5599 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
5600 { { STATE_EXPSTATE }, 'o' },
5601 { { STATE_CPENABLE }, 'i' }
5604 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
5605 { { 6 /* art */ }, 'o' }
5608 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
5609 { { STATE_CPENABLE }, 'i' }
5612 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
5613 0 /* IMPWIRE */
5616 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
5617 { { 91 /* bitindex */ }, 'i' }
5620 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
5621 { { STATE_EXPSTATE }, 'm' },
5622 { { STATE_CPENABLE }, 'i' }
5625 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
5626 { { 91 /* bitindex */ }, 'i' }
5629 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
5630 { { STATE_EXPSTATE }, 'm' },
5631 { { STATE_CPENABLE }, 'i' }
5634 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
5635 { { 6 /* art */ }, 'i' },
5636 { { 4 /* ars */ }, 'i' }
5639 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
5640 { { STATE_EXPSTATE }, 'm' },
5641 { { STATE_CPENABLE }, 'i' }
5644 static xtensa_iclass_internal iclasses[] = {
5645 { 0, 0 /* xt_iclass_excw */,
5646 0, 0, 0, 0 },
5647 { 0, 0 /* xt_iclass_rfe */,
5648 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5649 { 0, 0 /* xt_iclass_rfde */,
5650 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5651 { 0, 0 /* xt_iclass_syscall */,
5652 0, 0, 0, 0 },
5653 { 0, 0 /* xt_iclass_simcall */,
5654 0, 0, 0, 0 },
5655 { 2, Iclass_xt_iclass_call12_args,
5656 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5657 { 2, Iclass_xt_iclass_call8_args,
5658 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5659 { 2, Iclass_xt_iclass_call4_args,
5660 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5661 { 2, Iclass_xt_iclass_callx12_args,
5662 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5663 { 2, Iclass_xt_iclass_callx8_args,
5664 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5665 { 2, Iclass_xt_iclass_callx4_args,
5666 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5667 { 3, Iclass_xt_iclass_entry_args,
5668 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5669 { 2, Iclass_xt_iclass_movsp_args,
5670 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5671 { 1, Iclass_xt_iclass_rotw_args,
5672 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5673 { 1, Iclass_xt_iclass_retw_args,
5674 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5675 { 0, 0 /* xt_iclass_rfwou */,
5676 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5677 { 3, Iclass_xt_iclass_l32e_args,
5678 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
5679 { 3, Iclass_xt_iclass_s32e_args,
5680 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
5681 { 1, Iclass_xt_iclass_rsr_windowbase_args,
5682 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5683 { 1, Iclass_xt_iclass_wsr_windowbase_args,
5684 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5685 { 1, Iclass_xt_iclass_xsr_windowbase_args,
5686 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5687 { 1, Iclass_xt_iclass_rsr_windowstart_args,
5688 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5689 { 1, Iclass_xt_iclass_wsr_windowstart_args,
5690 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5691 { 1, Iclass_xt_iclass_xsr_windowstart_args,
5692 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5693 { 3, Iclass_xt_iclass_add_n_args,
5694 0, 0, 0, 0 },
5695 { 3, Iclass_xt_iclass_addi_n_args,
5696 0, 0, 0, 0 },
5697 { 2, Iclass_xt_iclass_bz6_args,
5698 0, 0, 0, 0 },
5699 { 0, 0 /* xt_iclass_ill_n */,
5700 0, 0, 0, 0 },
5701 { 3, Iclass_xt_iclass_loadi4_args,
5702 0, 0, 0, 0 },
5703 { 2, Iclass_xt_iclass_mov_n_args,
5704 0, 0, 0, 0 },
5705 { 2, Iclass_xt_iclass_movi_n_args,
5706 0, 0, 0, 0 },
5707 { 0, 0 /* xt_iclass_nopn */,
5708 0, 0, 0, 0 },
5709 { 1, Iclass_xt_iclass_retn_args,
5710 0, 0, 0, 0 },
5711 { 3, Iclass_xt_iclass_storei4_args,
5712 0, 0, 0, 0 },
5713 { 1, Iclass_rur_threadptr_args,
5714 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
5715 { 1, Iclass_wur_threadptr_args,
5716 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
5717 { 3, Iclass_xt_iclass_addi_args,
5718 0, 0, 0, 0 },
5719 { 3, Iclass_xt_iclass_addmi_args,
5720 0, 0, 0, 0 },
5721 { 3, Iclass_xt_iclass_addsub_args,
5722 0, 0, 0, 0 },
5723 { 3, Iclass_xt_iclass_bit_args,
5724 0, 0, 0, 0 },
5725 { 3, Iclass_xt_iclass_bsi8_args,
5726 0, 0, 0, 0 },
5727 { 3, Iclass_xt_iclass_bsi8b_args,
5728 0, 0, 0, 0 },
5729 { 3, Iclass_xt_iclass_bsi8u_args,
5730 0, 0, 0, 0 },
5731 { 3, Iclass_xt_iclass_bst8_args,
5732 0, 0, 0, 0 },
5733 { 2, Iclass_xt_iclass_bsz12_args,
5734 0, 0, 0, 0 },
5735 { 2, Iclass_xt_iclass_call0_args,
5736 0, 0, 0, 0 },
5737 { 2, Iclass_xt_iclass_callx0_args,
5738 0, 0, 0, 0 },
5739 { 4, Iclass_xt_iclass_exti_args,
5740 0, 0, 0, 0 },
5741 { 0, 0 /* xt_iclass_ill */,
5742 0, 0, 0, 0 },
5743 { 1, Iclass_xt_iclass_jump_args,
5744 0, 0, 0, 0 },
5745 { 1, Iclass_xt_iclass_jumpx_args,
5746 0, 0, 0, 0 },
5747 { 3, Iclass_xt_iclass_l16ui_args,
5748 0, 0, 0, 0 },
5749 { 3, Iclass_xt_iclass_l16si_args,
5750 0, 0, 0, 0 },
5751 { 3, Iclass_xt_iclass_l32i_args,
5752 0, 0, 0, 0 },
5753 { 2, Iclass_xt_iclass_l32r_args,
5754 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
5755 { 3, Iclass_xt_iclass_l8i_args,
5756 0, 0, 0, 0 },
5757 { 2, Iclass_xt_iclass_loop_args,
5758 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5759 { 2, Iclass_xt_iclass_loopz_args,
5760 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5761 { 2, Iclass_xt_iclass_movi_args,
5762 0, 0, 0, 0 },
5763 { 3, Iclass_xt_iclass_movz_args,
5764 0, 0, 0, 0 },
5765 { 2, Iclass_xt_iclass_neg_args,
5766 0, 0, 0, 0 },
5767 { 0, 0 /* xt_iclass_nop */,
5768 0, 0, 0, 0 },
5769 { 1, Iclass_xt_iclass_return_args,
5770 0, 0, 0, 0 },
5771 { 3, Iclass_xt_iclass_s16i_args,
5772 0, 0, 0, 0 },
5773 { 3, Iclass_xt_iclass_s32i_args,
5774 0, 0, 0, 0 },
5775 { 3, Iclass_xt_iclass_s8i_args,
5776 0, 0, 0, 0 },
5777 { 1, Iclass_xt_iclass_sar_args,
5778 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5779 { 1, Iclass_xt_iclass_sari_args,
5780 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5781 { 2, Iclass_xt_iclass_shifts_args,
5782 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5783 { 3, Iclass_xt_iclass_shiftst_args,
5784 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5785 { 2, Iclass_xt_iclass_shiftt_args,
5786 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5787 { 3, Iclass_xt_iclass_slli_args,
5788 0, 0, 0, 0 },
5789 { 3, Iclass_xt_iclass_srai_args,
5790 0, 0, 0, 0 },
5791 { 3, Iclass_xt_iclass_srli_args,
5792 0, 0, 0, 0 },
5793 { 0, 0 /* xt_iclass_memw */,
5794 0, 0, 0, 0 },
5795 { 0, 0 /* xt_iclass_extw */,
5796 0, 0, 0, 0 },
5797 { 0, 0 /* xt_iclass_isync */,
5798 0, 0, 0, 0 },
5799 { 0, 0 /* xt_iclass_sync */,
5800 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5801 { 2, Iclass_xt_iclass_rsil_args,
5802 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5803 { 1, Iclass_xt_iclass_rsr_lend_args,
5804 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5805 { 1, Iclass_xt_iclass_wsr_lend_args,
5806 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5807 { 1, Iclass_xt_iclass_xsr_lend_args,
5808 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5809 { 1, Iclass_xt_iclass_rsr_lcount_args,
5810 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5811 { 1, Iclass_xt_iclass_wsr_lcount_args,
5812 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5813 { 1, Iclass_xt_iclass_xsr_lcount_args,
5814 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5815 { 1, Iclass_xt_iclass_rsr_lbeg_args,
5816 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5817 { 1, Iclass_xt_iclass_wsr_lbeg_args,
5818 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5819 { 1, Iclass_xt_iclass_xsr_lbeg_args,
5820 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5821 { 1, Iclass_xt_iclass_rsr_sar_args,
5822 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5823 { 1, Iclass_xt_iclass_wsr_sar_args,
5824 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5825 { 1, Iclass_xt_iclass_xsr_sar_args,
5826 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5827 { 1, Iclass_xt_iclass_rsr_litbase_args,
5828 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
5829 { 1, Iclass_xt_iclass_wsr_litbase_args,
5830 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
5831 { 1, Iclass_xt_iclass_xsr_litbase_args,
5832 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
5833 { 1, Iclass_xt_iclass_rsr_176_args,
5834 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
5835 { 1, Iclass_xt_iclass_rsr_208_args,
5836 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
5837 { 1, Iclass_xt_iclass_rsr_ps_args,
5838 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5839 { 1, Iclass_xt_iclass_wsr_ps_args,
5840 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5841 { 1, Iclass_xt_iclass_xsr_ps_args,
5842 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5843 { 1, Iclass_xt_iclass_rsr_epc1_args,
5844 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5845 { 1, Iclass_xt_iclass_wsr_epc1_args,
5846 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5847 { 1, Iclass_xt_iclass_xsr_epc1_args,
5848 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5849 { 1, Iclass_xt_iclass_rsr_excsave1_args,
5850 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5851 { 1, Iclass_xt_iclass_wsr_excsave1_args,
5852 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5853 { 1, Iclass_xt_iclass_xsr_excsave1_args,
5854 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5855 { 1, Iclass_xt_iclass_rsr_epc2_args,
5856 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5857 { 1, Iclass_xt_iclass_wsr_epc2_args,
5858 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5859 { 1, Iclass_xt_iclass_xsr_epc2_args,
5860 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5861 { 1, Iclass_xt_iclass_rsr_excsave2_args,
5862 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5863 { 1, Iclass_xt_iclass_wsr_excsave2_args,
5864 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5865 { 1, Iclass_xt_iclass_xsr_excsave2_args,
5866 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5867 { 1, Iclass_xt_iclass_rsr_epc3_args,
5868 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5869 { 1, Iclass_xt_iclass_wsr_epc3_args,
5870 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5871 { 1, Iclass_xt_iclass_xsr_epc3_args,
5872 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5873 { 1, Iclass_xt_iclass_rsr_excsave3_args,
5874 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5875 { 1, Iclass_xt_iclass_wsr_excsave3_args,
5876 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5877 { 1, Iclass_xt_iclass_xsr_excsave3_args,
5878 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5879 { 1, Iclass_xt_iclass_rsr_epc4_args,
5880 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5881 { 1, Iclass_xt_iclass_wsr_epc4_args,
5882 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5883 { 1, Iclass_xt_iclass_xsr_epc4_args,
5884 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5885 { 1, Iclass_xt_iclass_rsr_excsave4_args,
5886 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5887 { 1, Iclass_xt_iclass_wsr_excsave4_args,
5888 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5889 { 1, Iclass_xt_iclass_xsr_excsave4_args,
5890 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5891 { 1, Iclass_xt_iclass_rsr_epc5_args,
5892 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5893 { 1, Iclass_xt_iclass_wsr_epc5_args,
5894 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5895 { 1, Iclass_xt_iclass_xsr_epc5_args,
5896 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5897 { 1, Iclass_xt_iclass_rsr_excsave5_args,
5898 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5899 { 1, Iclass_xt_iclass_wsr_excsave5_args,
5900 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5901 { 1, Iclass_xt_iclass_xsr_excsave5_args,
5902 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5903 { 1, Iclass_xt_iclass_rsr_epc6_args,
5904 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5905 { 1, Iclass_xt_iclass_wsr_epc6_args,
5906 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5907 { 1, Iclass_xt_iclass_xsr_epc6_args,
5908 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5909 { 1, Iclass_xt_iclass_rsr_excsave6_args,
5910 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5911 { 1, Iclass_xt_iclass_wsr_excsave6_args,
5912 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5913 { 1, Iclass_xt_iclass_xsr_excsave6_args,
5914 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5915 { 1, Iclass_xt_iclass_rsr_epc7_args,
5916 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5917 { 1, Iclass_xt_iclass_wsr_epc7_args,
5918 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5919 { 1, Iclass_xt_iclass_xsr_epc7_args,
5920 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5921 { 1, Iclass_xt_iclass_rsr_excsave7_args,
5922 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5923 { 1, Iclass_xt_iclass_wsr_excsave7_args,
5924 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5925 { 1, Iclass_xt_iclass_xsr_excsave7_args,
5926 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5927 { 1, Iclass_xt_iclass_rsr_eps2_args,
5928 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5929 { 1, Iclass_xt_iclass_wsr_eps2_args,
5930 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5931 { 1, Iclass_xt_iclass_xsr_eps2_args,
5932 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5933 { 1, Iclass_xt_iclass_rsr_eps3_args,
5934 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5935 { 1, Iclass_xt_iclass_wsr_eps3_args,
5936 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5937 { 1, Iclass_xt_iclass_xsr_eps3_args,
5938 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5939 { 1, Iclass_xt_iclass_rsr_eps4_args,
5940 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5941 { 1, Iclass_xt_iclass_wsr_eps4_args,
5942 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5943 { 1, Iclass_xt_iclass_xsr_eps4_args,
5944 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5945 { 1, Iclass_xt_iclass_rsr_eps5_args,
5946 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5947 { 1, Iclass_xt_iclass_wsr_eps5_args,
5948 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5949 { 1, Iclass_xt_iclass_xsr_eps5_args,
5950 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5951 { 1, Iclass_xt_iclass_rsr_eps6_args,
5952 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5953 { 1, Iclass_xt_iclass_wsr_eps6_args,
5954 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5955 { 1, Iclass_xt_iclass_xsr_eps6_args,
5956 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5957 { 1, Iclass_xt_iclass_rsr_eps7_args,
5958 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5959 { 1, Iclass_xt_iclass_wsr_eps7_args,
5960 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5961 { 1, Iclass_xt_iclass_xsr_eps7_args,
5962 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5963 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
5964 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5965 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
5966 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5967 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
5968 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5969 { 1, Iclass_xt_iclass_rsr_depc_args,
5970 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5971 { 1, Iclass_xt_iclass_wsr_depc_args,
5972 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5973 { 1, Iclass_xt_iclass_xsr_depc_args,
5974 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5975 { 1, Iclass_xt_iclass_rsr_exccause_args,
5976 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5977 { 1, Iclass_xt_iclass_wsr_exccause_args,
5978 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5979 { 1, Iclass_xt_iclass_xsr_exccause_args,
5980 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5981 { 1, Iclass_xt_iclass_rsr_misc0_args,
5982 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5983 { 1, Iclass_xt_iclass_wsr_misc0_args,
5984 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5985 { 1, Iclass_xt_iclass_xsr_misc0_args,
5986 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5987 { 1, Iclass_xt_iclass_rsr_misc1_args,
5988 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5989 { 1, Iclass_xt_iclass_wsr_misc1_args,
5990 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5991 { 1, Iclass_xt_iclass_xsr_misc1_args,
5992 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5993 { 1, Iclass_xt_iclass_rsr_prid_args,
5994 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
5995 { 1, Iclass_xt_iclass_rsr_vecbase_args,
5996 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5997 { 1, Iclass_xt_iclass_wsr_vecbase_args,
5998 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5999 { 1, Iclass_xt_iclass_xsr_vecbase_args,
6000 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
6001 { 2, Iclass_xt_iclass_mac16_aa_args,
6002 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
6003 { 2, Iclass_xt_iclass_mac16_ad_args,
6004 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
6005 { 2, Iclass_xt_iclass_mac16_da_args,
6006 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
6007 { 2, Iclass_xt_iclass_mac16_dd_args,
6008 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
6009 { 2, Iclass_xt_iclass_mac16a_aa_args,
6010 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
6011 { 2, Iclass_xt_iclass_mac16a_ad_args,
6012 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
6013 { 2, Iclass_xt_iclass_mac16a_da_args,
6014 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
6015 { 2, Iclass_xt_iclass_mac16a_dd_args,
6016 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
6017 { 4, Iclass_xt_iclass_mac16al_da_args,
6018 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
6019 { 4, Iclass_xt_iclass_mac16al_dd_args,
6020 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
6021 { 2, Iclass_xt_iclass_mac16_l_args,
6022 0, 0, 0, 0 },
6023 { 3, Iclass_xt_iclass_mul16_args,
6024 0, 0, 0, 0 },
6025 { 2, Iclass_xt_iclass_rsr_m0_args,
6026 0, 0, 0, 0 },
6027 { 2, Iclass_xt_iclass_wsr_m0_args,
6028 0, 0, 0, 0 },
6029 { 2, Iclass_xt_iclass_xsr_m0_args,
6030 0, 0, 0, 0 },
6031 { 2, Iclass_xt_iclass_rsr_m1_args,
6032 0, 0, 0, 0 },
6033 { 2, Iclass_xt_iclass_wsr_m1_args,
6034 0, 0, 0, 0 },
6035 { 2, Iclass_xt_iclass_xsr_m1_args,
6036 0, 0, 0, 0 },
6037 { 2, Iclass_xt_iclass_rsr_m2_args,
6038 0, 0, 0, 0 },
6039 { 2, Iclass_xt_iclass_wsr_m2_args,
6040 0, 0, 0, 0 },
6041 { 2, Iclass_xt_iclass_xsr_m2_args,
6042 0, 0, 0, 0 },
6043 { 2, Iclass_xt_iclass_rsr_m3_args,
6044 0, 0, 0, 0 },
6045 { 2, Iclass_xt_iclass_wsr_m3_args,
6046 0, 0, 0, 0 },
6047 { 2, Iclass_xt_iclass_xsr_m3_args,
6048 0, 0, 0, 0 },
6049 { 1, Iclass_xt_iclass_rsr_acclo_args,
6050 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
6051 { 1, Iclass_xt_iclass_wsr_acclo_args,
6052 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
6053 { 1, Iclass_xt_iclass_xsr_acclo_args,
6054 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
6055 { 1, Iclass_xt_iclass_rsr_acchi_args,
6056 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
6057 { 1, Iclass_xt_iclass_wsr_acchi_args,
6058 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
6059 { 1, Iclass_xt_iclass_xsr_acchi_args,
6060 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
6061 { 1, Iclass_xt_iclass_rfi_args,
6062 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
6063 { 1, Iclass_xt_iclass_wait_args,
6064 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
6065 { 1, Iclass_xt_iclass_rsr_interrupt_args,
6066 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
6067 { 1, Iclass_xt_iclass_wsr_intset_args,
6068 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
6069 { 1, Iclass_xt_iclass_wsr_intclear_args,
6070 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
6071 { 1, Iclass_xt_iclass_rsr_intenable_args,
6072 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
6073 { 1, Iclass_xt_iclass_wsr_intenable_args,
6074 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
6075 { 1, Iclass_xt_iclass_xsr_intenable_args,
6076 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
6077 { 2, Iclass_xt_iclass_break_args,
6078 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
6079 { 1, Iclass_xt_iclass_break_n_args,
6080 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
6081 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
6082 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
6083 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
6084 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
6085 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
6086 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
6087 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
6088 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
6089 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
6090 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
6091 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
6092 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
6093 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
6094 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
6095 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
6096 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
6097 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
6098 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
6099 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
6100 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
6101 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
6102 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
6103 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
6104 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
6105 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
6106 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
6107 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
6108 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
6109 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
6110 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
6111 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
6112 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
6113 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
6114 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
6115 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
6116 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
6117 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
6118 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
6119 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
6120 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
6121 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
6122 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
6123 { 1, Iclass_xt_iclass_rsr_debugcause_args,
6124 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
6125 { 1, Iclass_xt_iclass_wsr_debugcause_args,
6126 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
6127 { 1, Iclass_xt_iclass_xsr_debugcause_args,
6128 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
6129 { 1, Iclass_xt_iclass_rsr_icount_args,
6130 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
6131 { 1, Iclass_xt_iclass_wsr_icount_args,
6132 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
6133 { 1, Iclass_xt_iclass_xsr_icount_args,
6134 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
6135 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
6136 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
6137 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
6138 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
6139 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
6140 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
6141 { 1, Iclass_xt_iclass_rsr_ddr_args,
6142 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
6143 { 1, Iclass_xt_iclass_wsr_ddr_args,
6144 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
6145 { 1, Iclass_xt_iclass_xsr_ddr_args,
6146 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
6147 { 1, Iclass_xt_iclass_rfdo_args,
6148 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
6149 { 0, 0 /* xt_iclass_rfdd */,
6150 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
6151 { 1, Iclass_xt_iclass_wsr_mmid_args,
6152 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
6153 { 1, Iclass_xt_iclass_rsr_ccount_args,
6154 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
6155 { 1, Iclass_xt_iclass_wsr_ccount_args,
6156 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
6157 { 1, Iclass_xt_iclass_xsr_ccount_args,
6158 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
6159 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
6160 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
6161 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
6162 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
6163 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
6164 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
6165 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
6166 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
6167 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
6168 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
6169 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
6170 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
6171 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
6172 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
6173 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
6174 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
6175 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
6176 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
6177 { 2, Iclass_xt_iclass_icache_args,
6178 0, 0, 0, 0 },
6179 { 2, Iclass_xt_iclass_icache_lock_args,
6180 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
6181 { 2, Iclass_xt_iclass_icache_inv_args,
6182 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
6183 { 2, Iclass_xt_iclass_licx_args,
6184 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
6185 { 2, Iclass_xt_iclass_sicx_args,
6186 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
6187 { 2, Iclass_xt_iclass_dcache_args,
6188 0, 0, 0, 0 },
6189 { 2, Iclass_xt_iclass_dcache_ind_args,
6190 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
6191 { 2, Iclass_xt_iclass_dcache_inv_args,
6192 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
6193 { 2, Iclass_xt_iclass_dpf_args,
6194 0, 0, 0, 0 },
6195 { 2, Iclass_xt_iclass_dcache_lock_args,
6196 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
6197 { 2, Iclass_xt_iclass_sdct_args,
6198 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
6199 { 2, Iclass_xt_iclass_ldct_args,
6200 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
6201 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
6202 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
6203 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
6204 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
6205 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
6206 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
6207 { 1, Iclass_xt_iclass_rsr_rasid_args,
6208 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
6209 { 1, Iclass_xt_iclass_wsr_rasid_args,
6210 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
6211 { 1, Iclass_xt_iclass_xsr_rasid_args,
6212 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
6213 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
6214 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
6215 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
6216 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
6217 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
6218 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
6219 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
6220 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
6221 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
6222 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
6223 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
6224 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
6225 { 1, Iclass_xt_iclass_idtlb_args,
6226 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
6227 { 2, Iclass_xt_iclass_rdtlb_args,
6228 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
6229 { 2, Iclass_xt_iclass_wdtlb_args,
6230 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
6231 { 1, Iclass_xt_iclass_iitlb_args,
6232 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
6233 { 2, Iclass_xt_iclass_ritlb_args,
6234 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
6235 { 2, Iclass_xt_iclass_witlb_args,
6236 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
6237 { 0, 0 /* xt_iclass_ldpte */,
6238 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
6239 { 0, 0 /* xt_iclass_hwwitlba */,
6240 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
6241 { 0, 0 /* xt_iclass_hwwdtlba */,
6242 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
6243 { 1, Iclass_xt_iclass_rsr_cpenable_args,
6244 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
6245 { 1, Iclass_xt_iclass_wsr_cpenable_args,
6246 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
6247 { 1, Iclass_xt_iclass_xsr_cpenable_args,
6248 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
6249 { 3, Iclass_xt_iclass_clamp_args,
6250 0, 0, 0, 0 },
6251 { 3, Iclass_xt_iclass_minmax_args,
6252 0, 0, 0, 0 },
6253 { 2, Iclass_xt_iclass_nsa_args,
6254 0, 0, 0, 0 },
6255 { 3, Iclass_xt_iclass_sx_args,
6256 0, 0, 0, 0 },
6257 { 3, Iclass_xt_iclass_l32ai_args,
6258 0, 0, 0, 0 },
6259 { 3, Iclass_xt_iclass_s32ri_args,
6260 0, 0, 0, 0 },
6261 { 3, Iclass_xt_iclass_s32c1i_args,
6262 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6263 { 1, Iclass_xt_iclass_rsr_scompare1_args,
6264 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6265 { 1, Iclass_xt_iclass_wsr_scompare1_args,
6266 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6267 { 1, Iclass_xt_iclass_xsr_scompare1_args,
6268 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6269 { 3, Iclass_xt_iclass_div_args,
6270 0, 0, 0, 0 },
6271 { 3, Iclass_xt_mul32_args,
6272 0, 0, 0, 0 },
6273 { 1, Iclass_rur_expstate_args,
6274 2, Iclass_rur_expstate_stateArgs, 0, 0 },
6275 { 1, Iclass_wur_expstate_args,
6276 2, Iclass_wur_expstate_stateArgs, 0, 0 },
6277 { 1, Iclass_iclass_READ_IMPWIRE_args,
6278 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
6279 { 1, Iclass_iclass_SETB_EXPSTATE_args,
6280 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6281 { 1, Iclass_iclass_CLRB_EXPSTATE_args,
6282 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6283 { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
6284 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6288 /* Opcode encodings. */
6290 static void
6291 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6293 slotbuf[0] = 0x2080;
6296 static void
6297 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
6299 slotbuf[0] = 0x3000;
6302 static void
6303 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
6305 slotbuf[0] = 0x3200;
6308 static void
6309 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6311 slotbuf[0] = 0x5000;
6314 static void
6315 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6317 slotbuf[0] = 0x5100;
6320 static void
6321 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6323 slotbuf[0] = 0x35;
6326 static void
6327 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6329 slotbuf[0] = 0x25;
6332 static void
6333 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6335 slotbuf[0] = 0x15;
6338 static void
6339 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6341 slotbuf[0] = 0xf0;
6344 static void
6345 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6347 slotbuf[0] = 0xe0;
6350 static void
6351 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6353 slotbuf[0] = 0xd0;
6356 static void
6357 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
6359 slotbuf[0] = 0x36;
6362 static void
6363 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
6365 slotbuf[0] = 0x1000;
6368 static void
6369 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6371 slotbuf[0] = 0x408000;
6374 static void
6375 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6377 slotbuf[0] = 0x90;
6380 static void
6381 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6383 slotbuf[0] = 0xf01d;
6386 static void
6387 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6389 slotbuf[0] = 0x3400;
6392 static void
6393 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6395 slotbuf[0] = 0x3500;
6398 static void
6399 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6401 slotbuf[0] = 0x90000;
6404 static void
6405 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6407 slotbuf[0] = 0x490000;
6410 static void
6411 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6413 slotbuf[0] = 0x34800;
6416 static void
6417 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6419 slotbuf[0] = 0x134800;
6422 static void
6423 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6425 slotbuf[0] = 0x614800;
6428 static void
6429 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6431 slotbuf[0] = 0x34900;
6434 static void
6435 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6437 slotbuf[0] = 0x134900;
6440 static void
6441 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6443 slotbuf[0] = 0x614900;
6446 static void
6447 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6449 slotbuf[0] = 0xa;
6452 static void
6453 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6455 slotbuf[0] = 0xb;
6458 static void
6459 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6461 slotbuf[0] = 0x8c;
6464 static void
6465 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6467 slotbuf[0] = 0xcc;
6470 static void
6471 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6473 slotbuf[0] = 0xf06d;
6476 static void
6477 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6479 slotbuf[0] = 0x8;
6482 static void
6483 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6485 slotbuf[0] = 0xd;
6488 static void
6489 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6491 slotbuf[0] = 0xc;
6494 static void
6495 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6497 slotbuf[0] = 0xf03d;
6500 static void
6501 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6503 slotbuf[0] = 0xf00d;
6506 static void
6507 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6509 slotbuf[0] = 0x9;
6512 static void
6513 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6515 slotbuf[0] = 0xe30e70;
6518 static void
6519 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6521 slotbuf[0] = 0xf3e700;
6524 static void
6525 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6527 slotbuf[0] = 0xc002;
6530 static void
6531 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6533 slotbuf[0] = 0xd002;
6536 static void
6537 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
6539 slotbuf[0] = 0x800000;
6542 static void
6543 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
6545 slotbuf[0] = 0xc00000;
6548 static void
6549 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6551 slotbuf[0] = 0x900000;
6554 static void
6555 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6557 slotbuf[0] = 0xa00000;
6560 static void
6561 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6563 slotbuf[0] = 0xb00000;
6566 static void
6567 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6569 slotbuf[0] = 0xd00000;
6572 static void
6573 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6575 slotbuf[0] = 0xe00000;
6578 static void
6579 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6581 slotbuf[0] = 0xf00000;
6584 static void
6585 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
6587 slotbuf[0] = 0x100000;
6590 static void
6591 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
6593 slotbuf[0] = 0x200000;
6596 static void
6597 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
6599 slotbuf[0] = 0x300000;
6602 static void
6603 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6605 slotbuf[0] = 0x26;
6608 static void
6609 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6611 slotbuf[0] = 0x66;
6614 static void
6615 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6617 slotbuf[0] = 0xe6;
6620 static void
6621 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6623 slotbuf[0] = 0xa6;
6626 static void
6627 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
6629 slotbuf[0] = 0x6007;
6632 static void
6633 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6635 slotbuf[0] = 0xe007;
6638 static void
6639 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6641 slotbuf[0] = 0xf6;
6644 static void
6645 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6647 slotbuf[0] = 0xb6;
6650 static void
6651 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
6653 slotbuf[0] = 0x1007;
6656 static void
6657 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
6659 slotbuf[0] = 0x9007;
6662 static void
6663 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
6665 slotbuf[0] = 0xa007;
6668 static void
6669 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6671 slotbuf[0] = 0x2007;
6674 static void
6675 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6677 slotbuf[0] = 0xb007;
6680 static void
6681 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6683 slotbuf[0] = 0x3007;
6686 static void
6687 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
6689 slotbuf[0] = 0x8007;
6692 static void
6693 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
6695 slotbuf[0] = 0x7;
6698 static void
6699 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
6701 slotbuf[0] = 0x4007;
6704 static void
6705 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6707 slotbuf[0] = 0xc007;
6710 static void
6711 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6713 slotbuf[0] = 0x5007;
6716 static void
6717 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6719 slotbuf[0] = 0xd007;
6722 static void
6723 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6725 slotbuf[0] = 0x16;
6728 static void
6729 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6731 slotbuf[0] = 0x56;
6734 static void
6735 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6737 slotbuf[0] = 0xd6;
6740 static void
6741 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6743 slotbuf[0] = 0x96;
6746 static void
6747 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6749 slotbuf[0] = 0x5;
6752 static void
6753 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6755 slotbuf[0] = 0xc0;
6758 static void
6759 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6761 slotbuf[0] = 0x40000;
6764 static void
6765 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
6767 slotbuf[0] = 0;
6770 static void
6771 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
6773 slotbuf[0] = 0x6;
6776 static void
6777 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
6779 slotbuf[0] = 0xa0;
6782 static void
6783 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6785 slotbuf[0] = 0x1002;
6788 static void
6789 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
6791 slotbuf[0] = 0x9002;
6794 static void
6795 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6797 slotbuf[0] = 0x2002;
6800 static void
6801 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
6803 slotbuf[0] = 0x1;
6806 static void
6807 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6809 slotbuf[0] = 0x2;
6812 static void
6813 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6815 slotbuf[0] = 0x8076;
6818 static void
6819 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6821 slotbuf[0] = 0x9076;
6824 static void
6825 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6827 slotbuf[0] = 0xa076;
6830 static void
6831 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6833 slotbuf[0] = 0xa002;
6836 static void
6837 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6839 slotbuf[0] = 0x830000;
6842 static void
6843 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6845 slotbuf[0] = 0x930000;
6848 static void
6849 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6851 slotbuf[0] = 0xa30000;
6854 static void
6855 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6857 slotbuf[0] = 0xb30000;
6860 static void
6861 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6863 slotbuf[0] = 0x600000;
6866 static void
6867 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6869 slotbuf[0] = 0x600100;
6872 static void
6873 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6875 slotbuf[0] = 0x20f0;
6878 static void
6879 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
6881 slotbuf[0] = 0x80;
6884 static void
6885 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6887 slotbuf[0] = 0x5002;
6890 static void
6891 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6893 slotbuf[0] = 0x6002;
6896 static void
6897 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6899 slotbuf[0] = 0x4002;
6902 static void
6903 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6905 slotbuf[0] = 0x400000;
6908 static void
6909 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6911 slotbuf[0] = 0x401000;
6914 static void
6915 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
6917 slotbuf[0] = 0x402000;
6920 static void
6921 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
6923 slotbuf[0] = 0x403000;
6926 static void
6927 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6929 slotbuf[0] = 0x404000;
6932 static void
6933 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
6935 slotbuf[0] = 0xa10000;
6938 static void
6939 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
6941 slotbuf[0] = 0x810000;
6944 static void
6945 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6947 slotbuf[0] = 0x910000;
6950 static void
6951 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
6953 slotbuf[0] = 0xb10000;
6956 static void
6957 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6959 slotbuf[0] = 0x10000;
6962 static void
6963 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6965 slotbuf[0] = 0x210000;
6968 static void
6969 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6971 slotbuf[0] = 0x410000;
6974 static void
6975 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6977 slotbuf[0] = 0x20c0;
6980 static void
6981 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6983 slotbuf[0] = 0x20d0;
6986 static void
6987 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6989 slotbuf[0] = 0x2000;
6992 static void
6993 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6995 slotbuf[0] = 0x2010;
6998 static void
6999 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7001 slotbuf[0] = 0x2020;
7004 static void
7005 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7007 slotbuf[0] = 0x2030;
7010 static void
7011 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
7013 slotbuf[0] = 0x6000;
7016 static void
7017 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7019 slotbuf[0] = 0x30100;
7022 static void
7023 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7025 slotbuf[0] = 0x130100;
7028 static void
7029 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7031 slotbuf[0] = 0x610100;
7034 static void
7035 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7037 slotbuf[0] = 0x30200;
7040 static void
7041 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7043 slotbuf[0] = 0x130200;
7046 static void
7047 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7049 slotbuf[0] = 0x610200;
7052 static void
7053 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7055 slotbuf[0] = 0x30000;
7058 static void
7059 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7061 slotbuf[0] = 0x130000;
7064 static void
7065 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7067 slotbuf[0] = 0x610000;
7070 static void
7071 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7073 slotbuf[0] = 0x30300;
7076 static void
7077 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7079 slotbuf[0] = 0x130300;
7082 static void
7083 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7085 slotbuf[0] = 0x610300;
7088 static void
7089 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7091 slotbuf[0] = 0x30500;
7094 static void
7095 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7097 slotbuf[0] = 0x130500;
7100 static void
7101 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7103 slotbuf[0] = 0x610500;
7106 static void
7107 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
7109 slotbuf[0] = 0x3b000;
7112 static void
7113 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
7115 slotbuf[0] = 0x3d000;
7118 static void
7119 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7121 slotbuf[0] = 0x3e600;
7124 static void
7125 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7127 slotbuf[0] = 0x13e600;
7130 static void
7131 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7133 slotbuf[0] = 0x61e600;
7136 static void
7137 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7139 slotbuf[0] = 0x3b100;
7142 static void
7143 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7145 slotbuf[0] = 0x13b100;
7148 static void
7149 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7151 slotbuf[0] = 0x61b100;
7154 static void
7155 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7157 slotbuf[0] = 0x3d100;
7160 static void
7161 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7163 slotbuf[0] = 0x13d100;
7166 static void
7167 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7169 slotbuf[0] = 0x61d100;
7172 static void
7173 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7175 slotbuf[0] = 0x3b200;
7178 static void
7179 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7181 slotbuf[0] = 0x13b200;
7184 static void
7185 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7187 slotbuf[0] = 0x61b200;
7190 static void
7191 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7193 slotbuf[0] = 0x3d200;
7196 static void
7197 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7199 slotbuf[0] = 0x13d200;
7202 static void
7203 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7205 slotbuf[0] = 0x61d200;
7208 static void
7209 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7211 slotbuf[0] = 0x3b300;
7214 static void
7215 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7217 slotbuf[0] = 0x13b300;
7220 static void
7221 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7223 slotbuf[0] = 0x61b300;
7226 static void
7227 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7229 slotbuf[0] = 0x3d300;
7232 static void
7233 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7235 slotbuf[0] = 0x13d300;
7238 static void
7239 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7241 slotbuf[0] = 0x61d300;
7244 static void
7245 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7247 slotbuf[0] = 0x3b400;
7250 static void
7251 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7253 slotbuf[0] = 0x13b400;
7256 static void
7257 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7259 slotbuf[0] = 0x61b400;
7262 static void
7263 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7265 slotbuf[0] = 0x3d400;
7268 static void
7269 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7271 slotbuf[0] = 0x13d400;
7274 static void
7275 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7277 slotbuf[0] = 0x61d400;
7280 static void
7281 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7283 slotbuf[0] = 0x3b500;
7286 static void
7287 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7289 slotbuf[0] = 0x13b500;
7292 static void
7293 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7295 slotbuf[0] = 0x61b500;
7298 static void
7299 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7301 slotbuf[0] = 0x3d500;
7304 static void
7305 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7307 slotbuf[0] = 0x13d500;
7310 static void
7311 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7313 slotbuf[0] = 0x61d500;
7316 static void
7317 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7319 slotbuf[0] = 0x3b600;
7322 static void
7323 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7325 slotbuf[0] = 0x13b600;
7328 static void
7329 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7331 slotbuf[0] = 0x61b600;
7334 static void
7335 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7337 slotbuf[0] = 0x3d600;
7340 static void
7341 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7343 slotbuf[0] = 0x13d600;
7346 static void
7347 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7349 slotbuf[0] = 0x61d600;
7352 static void
7353 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7355 slotbuf[0] = 0x3b700;
7358 static void
7359 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7361 slotbuf[0] = 0x13b700;
7364 static void
7365 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7367 slotbuf[0] = 0x61b700;
7370 static void
7371 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7373 slotbuf[0] = 0x3d700;
7376 static void
7377 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7379 slotbuf[0] = 0x13d700;
7382 static void
7383 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7385 slotbuf[0] = 0x61d700;
7388 static void
7389 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7391 slotbuf[0] = 0x3c200;
7394 static void
7395 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7397 slotbuf[0] = 0x13c200;
7400 static void
7401 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7403 slotbuf[0] = 0x61c200;
7406 static void
7407 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7409 slotbuf[0] = 0x3c300;
7412 static void
7413 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7415 slotbuf[0] = 0x13c300;
7418 static void
7419 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7421 slotbuf[0] = 0x61c300;
7424 static void
7425 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7427 slotbuf[0] = 0x3c400;
7430 static void
7431 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7433 slotbuf[0] = 0x13c400;
7436 static void
7437 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7439 slotbuf[0] = 0x61c400;
7442 static void
7443 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7445 slotbuf[0] = 0x3c500;
7448 static void
7449 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7451 slotbuf[0] = 0x13c500;
7454 static void
7455 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7457 slotbuf[0] = 0x61c500;
7460 static void
7461 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7463 slotbuf[0] = 0x3c600;
7466 static void
7467 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7469 slotbuf[0] = 0x13c600;
7472 static void
7473 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7475 slotbuf[0] = 0x61c600;
7478 static void
7479 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7481 slotbuf[0] = 0x3c700;
7484 static void
7485 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7487 slotbuf[0] = 0x13c700;
7490 static void
7491 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7493 slotbuf[0] = 0x61c700;
7496 static void
7497 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7499 slotbuf[0] = 0x3ee00;
7502 static void
7503 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7505 slotbuf[0] = 0x13ee00;
7508 static void
7509 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7511 slotbuf[0] = 0x61ee00;
7514 static void
7515 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7517 slotbuf[0] = 0x3c000;
7520 static void
7521 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7523 slotbuf[0] = 0x13c000;
7526 static void
7527 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7529 slotbuf[0] = 0x61c000;
7532 static void
7533 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7535 slotbuf[0] = 0x3e800;
7538 static void
7539 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7541 slotbuf[0] = 0x13e800;
7544 static void
7545 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7547 slotbuf[0] = 0x61e800;
7550 static void
7551 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7553 slotbuf[0] = 0x3f400;
7556 static void
7557 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7559 slotbuf[0] = 0x13f400;
7562 static void
7563 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7565 slotbuf[0] = 0x61f400;
7568 static void
7569 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7571 slotbuf[0] = 0x3f500;
7574 static void
7575 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7577 slotbuf[0] = 0x13f500;
7580 static void
7581 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7583 slotbuf[0] = 0x61f500;
7586 static void
7587 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7589 slotbuf[0] = 0x3eb00;
7592 static void
7593 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7595 slotbuf[0] = 0x3e700;
7598 static void
7599 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7601 slotbuf[0] = 0x13e700;
7604 static void
7605 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7607 slotbuf[0] = 0x61e700;
7610 static void
7611 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7613 slotbuf[0] = 0x740004;
7616 static void
7617 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7619 slotbuf[0] = 0x750004;
7622 static void
7623 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7625 slotbuf[0] = 0x760004;
7628 static void
7629 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7631 slotbuf[0] = 0x770004;
7634 static void
7635 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7637 slotbuf[0] = 0x700004;
7640 static void
7641 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7643 slotbuf[0] = 0x710004;
7646 static void
7647 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7649 slotbuf[0] = 0x720004;
7652 static void
7653 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7655 slotbuf[0] = 0x730004;
7658 static void
7659 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7661 slotbuf[0] = 0x340004;
7664 static void
7665 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7667 slotbuf[0] = 0x350004;
7670 static void
7671 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7673 slotbuf[0] = 0x360004;
7676 static void
7677 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7679 slotbuf[0] = 0x370004;
7682 static void
7683 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7685 slotbuf[0] = 0x640004;
7688 static void
7689 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7691 slotbuf[0] = 0x650004;
7694 static void
7695 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7697 slotbuf[0] = 0x660004;
7700 static void
7701 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7703 slotbuf[0] = 0x670004;
7706 static void
7707 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7709 slotbuf[0] = 0x240004;
7712 static void
7713 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7715 slotbuf[0] = 0x250004;
7718 static void
7719 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7721 slotbuf[0] = 0x260004;
7724 static void
7725 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7727 slotbuf[0] = 0x270004;
7730 static void
7731 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7733 slotbuf[0] = 0x780004;
7736 static void
7737 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7739 slotbuf[0] = 0x790004;
7742 static void
7743 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7745 slotbuf[0] = 0x7a0004;
7748 static void
7749 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7751 slotbuf[0] = 0x7b0004;
7754 static void
7755 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7757 slotbuf[0] = 0x7c0004;
7760 static void
7761 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7763 slotbuf[0] = 0x7d0004;
7766 static void
7767 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7769 slotbuf[0] = 0x7e0004;
7772 static void
7773 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7775 slotbuf[0] = 0x7f0004;
7778 static void
7779 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7781 slotbuf[0] = 0x380004;
7784 static void
7785 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7787 slotbuf[0] = 0x390004;
7790 static void
7791 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7793 slotbuf[0] = 0x3a0004;
7796 static void
7797 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7799 slotbuf[0] = 0x3b0004;
7802 static void
7803 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7805 slotbuf[0] = 0x3c0004;
7808 static void
7809 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7811 slotbuf[0] = 0x3d0004;
7814 static void
7815 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7817 slotbuf[0] = 0x3e0004;
7820 static void
7821 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7823 slotbuf[0] = 0x3f0004;
7826 static void
7827 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7829 slotbuf[0] = 0x680004;
7832 static void
7833 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7835 slotbuf[0] = 0x690004;
7838 static void
7839 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7841 slotbuf[0] = 0x6a0004;
7844 static void
7845 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7847 slotbuf[0] = 0x6b0004;
7850 static void
7851 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7853 slotbuf[0] = 0x6c0004;
7856 static void
7857 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7859 slotbuf[0] = 0x6d0004;
7862 static void
7863 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7865 slotbuf[0] = 0x6e0004;
7868 static void
7869 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7871 slotbuf[0] = 0x6f0004;
7874 static void
7875 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7877 slotbuf[0] = 0x280004;
7880 static void
7881 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7883 slotbuf[0] = 0x290004;
7886 static void
7887 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7889 slotbuf[0] = 0x2a0004;
7892 static void
7893 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7895 slotbuf[0] = 0x2b0004;
7898 static void
7899 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7901 slotbuf[0] = 0x2c0004;
7904 static void
7905 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7907 slotbuf[0] = 0x2d0004;
7910 static void
7911 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7913 slotbuf[0] = 0x2e0004;
7916 static void
7917 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7919 slotbuf[0] = 0x2f0004;
7922 static void
7923 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7925 slotbuf[0] = 0x580004;
7928 static void
7929 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7931 slotbuf[0] = 0x480004;
7934 static void
7935 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7937 slotbuf[0] = 0x590004;
7940 static void
7941 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7943 slotbuf[0] = 0x490004;
7946 static void
7947 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7949 slotbuf[0] = 0x5a0004;
7952 static void
7953 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7955 slotbuf[0] = 0x4a0004;
7958 static void
7959 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7961 slotbuf[0] = 0x5b0004;
7964 static void
7965 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7967 slotbuf[0] = 0x4b0004;
7970 static void
7971 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7973 slotbuf[0] = 0x180004;
7976 static void
7977 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7979 slotbuf[0] = 0x80004;
7982 static void
7983 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7985 slotbuf[0] = 0x190004;
7988 static void
7989 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7991 slotbuf[0] = 0x90004;
7994 static void
7995 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
7997 slotbuf[0] = 0x1a0004;
8000 static void
8001 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8003 slotbuf[0] = 0xa0004;
8006 static void
8007 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8009 slotbuf[0] = 0x1b0004;
8012 static void
8013 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8015 slotbuf[0] = 0xb0004;
8018 static void
8019 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8021 slotbuf[0] = 0x900004;
8024 static void
8025 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8027 slotbuf[0] = 0x800004;
8030 static void
8031 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
8033 slotbuf[0] = 0xc10000;
8036 static void
8037 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
8039 slotbuf[0] = 0xd10000;
8042 static void
8043 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8045 slotbuf[0] = 0x32000;
8048 static void
8049 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8051 slotbuf[0] = 0x132000;
8054 static void
8055 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8057 slotbuf[0] = 0x612000;
8060 static void
8061 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8063 slotbuf[0] = 0x32100;
8066 static void
8067 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8069 slotbuf[0] = 0x132100;
8072 static void
8073 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8075 slotbuf[0] = 0x612100;
8078 static void
8079 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8081 slotbuf[0] = 0x32200;
8084 static void
8085 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8087 slotbuf[0] = 0x132200;
8090 static void
8091 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8093 slotbuf[0] = 0x612200;
8096 static void
8097 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8099 slotbuf[0] = 0x32300;
8102 static void
8103 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8105 slotbuf[0] = 0x132300;
8108 static void
8109 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8111 slotbuf[0] = 0x612300;
8114 static void
8115 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8117 slotbuf[0] = 0x31000;
8120 static void
8121 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8123 slotbuf[0] = 0x131000;
8126 static void
8127 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8129 slotbuf[0] = 0x611000;
8132 static void
8133 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8135 slotbuf[0] = 0x31100;
8138 static void
8139 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8141 slotbuf[0] = 0x131100;
8144 static void
8145 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8147 slotbuf[0] = 0x611100;
8150 static void
8151 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8153 slotbuf[0] = 0x3010;
8156 static void
8157 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
8159 slotbuf[0] = 0x7000;
8162 static void
8163 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
8165 slotbuf[0] = 0x3e200;
8168 static void
8169 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
8171 slotbuf[0] = 0x13e200;
8174 static void
8175 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
8177 slotbuf[0] = 0x13e300;
8180 static void
8181 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8183 slotbuf[0] = 0x3e400;
8186 static void
8187 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8189 slotbuf[0] = 0x13e400;
8192 static void
8193 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8195 slotbuf[0] = 0x61e400;
8198 static void
8199 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
8201 slotbuf[0] = 0x4000;
8204 static void
8205 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
8207 slotbuf[0] = 0xf02d;
8210 static void
8211 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8213 slotbuf[0] = 0x39000;
8216 static void
8217 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8219 slotbuf[0] = 0x139000;
8222 static void
8223 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8225 slotbuf[0] = 0x619000;
8228 static void
8229 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8231 slotbuf[0] = 0x3a000;
8234 static void
8235 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8237 slotbuf[0] = 0x13a000;
8240 static void
8241 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8243 slotbuf[0] = 0x61a000;
8246 static void
8247 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8249 slotbuf[0] = 0x39100;
8252 static void
8253 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8255 slotbuf[0] = 0x139100;
8258 static void
8259 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8261 slotbuf[0] = 0x619100;
8264 static void
8265 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8267 slotbuf[0] = 0x3a100;
8270 static void
8271 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8273 slotbuf[0] = 0x13a100;
8276 static void
8277 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8279 slotbuf[0] = 0x61a100;
8282 static void
8283 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8285 slotbuf[0] = 0x38000;
8288 static void
8289 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8291 slotbuf[0] = 0x138000;
8294 static void
8295 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8297 slotbuf[0] = 0x618000;
8300 static void
8301 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8303 slotbuf[0] = 0x38100;
8306 static void
8307 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8309 slotbuf[0] = 0x138100;
8312 static void
8313 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8315 slotbuf[0] = 0x618100;
8318 static void
8319 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8321 slotbuf[0] = 0x36000;
8324 static void
8325 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8327 slotbuf[0] = 0x136000;
8330 static void
8331 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8333 slotbuf[0] = 0x616000;
8336 static void
8337 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8339 slotbuf[0] = 0x3e900;
8342 static void
8343 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8345 slotbuf[0] = 0x13e900;
8348 static void
8349 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8351 slotbuf[0] = 0x61e900;
8354 static void
8355 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8357 slotbuf[0] = 0x3ec00;
8360 static void
8361 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8363 slotbuf[0] = 0x13ec00;
8366 static void
8367 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8369 slotbuf[0] = 0x61ec00;
8372 static void
8373 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8375 slotbuf[0] = 0x3ed00;
8378 static void
8379 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8381 slotbuf[0] = 0x13ed00;
8384 static void
8385 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8387 slotbuf[0] = 0x61ed00;
8390 static void
8391 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8393 slotbuf[0] = 0x36800;
8396 static void
8397 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8399 slotbuf[0] = 0x136800;
8402 static void
8403 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8405 slotbuf[0] = 0x616800;
8408 static void
8409 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8411 slotbuf[0] = 0xf1e000;
8414 static void
8415 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
8417 slotbuf[0] = 0xf1e010;
8420 static void
8421 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8423 slotbuf[0] = 0x135900;
8426 static void
8427 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8429 slotbuf[0] = 0x3ea00;
8432 static void
8433 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8435 slotbuf[0] = 0x13ea00;
8438 static void
8439 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8441 slotbuf[0] = 0x61ea00;
8444 static void
8445 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8447 slotbuf[0] = 0x3f000;
8450 static void
8451 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8453 slotbuf[0] = 0x13f000;
8456 static void
8457 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8459 slotbuf[0] = 0x61f000;
8462 static void
8463 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8465 slotbuf[0] = 0x3f100;
8468 static void
8469 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8471 slotbuf[0] = 0x13f100;
8474 static void
8475 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8477 slotbuf[0] = 0x61f100;
8480 static void
8481 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8483 slotbuf[0] = 0x3f200;
8486 static void
8487 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8489 slotbuf[0] = 0x13f200;
8492 static void
8493 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8495 slotbuf[0] = 0x61f200;
8498 static void
8499 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
8501 slotbuf[0] = 0x70c2;
8504 static void
8505 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8507 slotbuf[0] = 0x70e2;
8510 static void
8511 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8513 slotbuf[0] = 0x70d2;
8516 static void
8517 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8519 slotbuf[0] = 0x270d2;
8522 static void
8523 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8525 slotbuf[0] = 0x370d2;
8528 static void
8529 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8531 slotbuf[0] = 0x70f2;
8534 static void
8535 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8537 slotbuf[0] = 0xf10000;
8540 static void
8541 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8543 slotbuf[0] = 0xf12000;
8546 static void
8547 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8549 slotbuf[0] = 0xf11000;
8552 static void
8553 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8555 slotbuf[0] = 0xf13000;
8558 static void
8559 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8561 slotbuf[0] = 0x7042;
8564 static void
8565 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8567 slotbuf[0] = 0x7052;
8570 static void
8571 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8573 slotbuf[0] = 0x47082;
8576 static void
8577 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8579 slotbuf[0] = 0x57082;
8582 static void
8583 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8585 slotbuf[0] = 0x7062;
8588 static void
8589 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8591 slotbuf[0] = 0x7072;
8594 static void
8595 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8597 slotbuf[0] = 0x7002;
8600 static void
8601 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8603 slotbuf[0] = 0x7012;
8606 static void
8607 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
8609 slotbuf[0] = 0x7022;
8612 static void
8613 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8615 slotbuf[0] = 0x7032;
8618 static void
8619 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8621 slotbuf[0] = 0x7082;
8624 static void
8625 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8627 slotbuf[0] = 0x27082;
8630 static void
8631 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8633 slotbuf[0] = 0x37082;
8636 static void
8637 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8639 slotbuf[0] = 0xf19000;
8642 static void
8643 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8645 slotbuf[0] = 0xf18000;
8648 static void
8649 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8651 slotbuf[0] = 0x135300;
8654 static void
8655 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8657 slotbuf[0] = 0x35300;
8660 static void
8661 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8663 slotbuf[0] = 0x615300;
8666 static void
8667 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8669 slotbuf[0] = 0x35a00;
8672 static void
8673 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8675 slotbuf[0] = 0x135a00;
8678 static void
8679 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8681 slotbuf[0] = 0x615a00;
8684 static void
8685 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8687 slotbuf[0] = 0x35b00;
8690 static void
8691 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8693 slotbuf[0] = 0x135b00;
8696 static void
8697 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8699 slotbuf[0] = 0x615b00;
8702 static void
8703 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8705 slotbuf[0] = 0x35c00;
8708 static void
8709 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8711 slotbuf[0] = 0x135c00;
8714 static void
8715 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
8717 slotbuf[0] = 0x615c00;
8720 static void
8721 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8723 slotbuf[0] = 0x50c000;
8726 static void
8727 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8729 slotbuf[0] = 0x50d000;
8732 static void
8733 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8735 slotbuf[0] = 0x50b000;
8738 static void
8739 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8741 slotbuf[0] = 0x50f000;
8744 static void
8745 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8747 slotbuf[0] = 0x50e000;
8750 static void
8751 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8753 slotbuf[0] = 0x504000;
8756 static void
8757 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8759 slotbuf[0] = 0x505000;
8762 static void
8763 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8765 slotbuf[0] = 0x503000;
8768 static void
8769 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8771 slotbuf[0] = 0x507000;
8774 static void
8775 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8777 slotbuf[0] = 0x506000;
8780 static void
8781 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
8783 slotbuf[0] = 0xf1f000;
8786 static void
8787 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
8789 slotbuf[0] = 0x501000;
8792 static void
8793 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
8795 slotbuf[0] = 0x509000;
8798 static void
8799 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8801 slotbuf[0] = 0x3e000;
8804 static void
8805 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8807 slotbuf[0] = 0x13e000;
8810 static void
8811 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8813 slotbuf[0] = 0x61e000;
8816 static void
8817 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
8819 slotbuf[0] = 0x330000;
8822 static void
8823 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
8825 slotbuf[0] = 0x430000;
8828 static void
8829 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
8831 slotbuf[0] = 0x530000;
8834 static void
8835 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8837 slotbuf[0] = 0x630000;
8840 static void
8841 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8843 slotbuf[0] = 0x730000;
8846 static void
8847 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
8849 slotbuf[0] = 0x40e000;
8852 static void
8853 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
8855 slotbuf[0] = 0x40f000;
8858 static void
8859 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
8861 slotbuf[0] = 0x230000;
8864 static void
8865 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
8867 slotbuf[0] = 0xb002;
8870 static void
8871 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
8873 slotbuf[0] = 0xf002;
8876 static void
8877 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
8879 slotbuf[0] = 0xe002;
8882 static void
8883 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8885 slotbuf[0] = 0x30c00;
8888 static void
8889 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8891 slotbuf[0] = 0x130c00;
8894 static void
8895 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8897 slotbuf[0] = 0x610c00;
8900 static void
8901 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
8903 slotbuf[0] = 0xc20000;
8906 static void
8907 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
8909 slotbuf[0] = 0xd20000;
8912 static void
8913 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8915 slotbuf[0] = 0xe20000;
8918 static void
8919 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
8921 slotbuf[0] = 0xf20000;
8924 static void
8925 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
8927 slotbuf[0] = 0x820000;
8930 static void
8931 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8933 slotbuf[0] = 0xe30e60;
8936 static void
8937 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8939 slotbuf[0] = 0xf3e600;
8942 static void
8943 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
8945 slotbuf[0] = 0xe0000;
8948 static void
8949 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8951 slotbuf[0] = 0xe1000;
8954 static void
8955 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8957 slotbuf[0] = 0xe1200;
8960 static void
8961 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8963 slotbuf[0] = 0xe2000;
8966 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
8967 Opcode_excw_Slot_inst_encode, 0, 0
8970 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
8971 Opcode_rfe_Slot_inst_encode, 0, 0
8974 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
8975 Opcode_rfde_Slot_inst_encode, 0, 0
8978 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
8979 Opcode_syscall_Slot_inst_encode, 0, 0
8982 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
8983 Opcode_simcall_Slot_inst_encode, 0, 0
8986 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
8987 Opcode_call12_Slot_inst_encode, 0, 0
8990 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
8991 Opcode_call8_Slot_inst_encode, 0, 0
8994 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
8995 Opcode_call4_Slot_inst_encode, 0, 0
8998 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
8999 Opcode_callx12_Slot_inst_encode, 0, 0
9002 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
9003 Opcode_callx8_Slot_inst_encode, 0, 0
9006 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
9007 Opcode_callx4_Slot_inst_encode, 0, 0
9010 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
9011 Opcode_entry_Slot_inst_encode, 0, 0
9014 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
9015 Opcode_movsp_Slot_inst_encode, 0, 0
9018 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
9019 Opcode_rotw_Slot_inst_encode, 0, 0
9022 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
9023 Opcode_retw_Slot_inst_encode, 0, 0
9026 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
9027 0, 0, Opcode_retw_n_Slot_inst16b_encode
9030 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
9031 Opcode_rfwo_Slot_inst_encode, 0, 0
9034 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
9035 Opcode_rfwu_Slot_inst_encode, 0, 0
9038 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
9039 Opcode_l32e_Slot_inst_encode, 0, 0
9042 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
9043 Opcode_s32e_Slot_inst_encode, 0, 0
9046 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
9047 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9050 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
9051 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9054 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
9055 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9058 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
9059 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9062 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
9063 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9066 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
9067 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9070 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
9071 0, Opcode_add_n_Slot_inst16a_encode, 0
9074 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
9075 0, Opcode_addi_n_Slot_inst16a_encode, 0
9078 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
9079 0, 0, Opcode_beqz_n_Slot_inst16b_encode
9082 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
9083 0, 0, Opcode_bnez_n_Slot_inst16b_encode
9086 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
9087 0, 0, Opcode_ill_n_Slot_inst16b_encode
9090 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
9091 0, Opcode_l32i_n_Slot_inst16a_encode, 0
9094 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
9095 0, 0, Opcode_mov_n_Slot_inst16b_encode
9098 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
9099 0, 0, Opcode_movi_n_Slot_inst16b_encode
9102 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
9103 0, 0, Opcode_nop_n_Slot_inst16b_encode
9106 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
9107 0, 0, Opcode_ret_n_Slot_inst16b_encode
9110 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
9111 0, Opcode_s32i_n_Slot_inst16a_encode, 0
9114 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
9115 Opcode_rur_threadptr_Slot_inst_encode, 0, 0
9118 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
9119 Opcode_wur_threadptr_Slot_inst_encode, 0, 0
9122 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
9123 Opcode_addi_Slot_inst_encode, 0, 0
9126 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
9127 Opcode_addmi_Slot_inst_encode, 0, 0
9130 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
9131 Opcode_add_Slot_inst_encode, 0, 0
9134 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
9135 Opcode_sub_Slot_inst_encode, 0, 0
9138 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
9139 Opcode_addx2_Slot_inst_encode, 0, 0
9142 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
9143 Opcode_addx4_Slot_inst_encode, 0, 0
9146 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
9147 Opcode_addx8_Slot_inst_encode, 0, 0
9150 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
9151 Opcode_subx2_Slot_inst_encode, 0, 0
9154 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
9155 Opcode_subx4_Slot_inst_encode, 0, 0
9158 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
9159 Opcode_subx8_Slot_inst_encode, 0, 0
9162 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
9163 Opcode_and_Slot_inst_encode, 0, 0
9166 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
9167 Opcode_or_Slot_inst_encode, 0, 0
9170 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
9171 Opcode_xor_Slot_inst_encode, 0, 0
9174 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
9175 Opcode_beqi_Slot_inst_encode, 0, 0
9178 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
9179 Opcode_bnei_Slot_inst_encode, 0, 0
9182 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
9183 Opcode_bgei_Slot_inst_encode, 0, 0
9186 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
9187 Opcode_blti_Slot_inst_encode, 0, 0
9190 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
9191 Opcode_bbci_Slot_inst_encode, 0, 0
9194 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
9195 Opcode_bbsi_Slot_inst_encode, 0, 0
9198 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
9199 Opcode_bgeui_Slot_inst_encode, 0, 0
9202 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
9203 Opcode_bltui_Slot_inst_encode, 0, 0
9206 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
9207 Opcode_beq_Slot_inst_encode, 0, 0
9210 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
9211 Opcode_bne_Slot_inst_encode, 0, 0
9214 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
9215 Opcode_bge_Slot_inst_encode, 0, 0
9218 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
9219 Opcode_blt_Slot_inst_encode, 0, 0
9222 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
9223 Opcode_bgeu_Slot_inst_encode, 0, 0
9226 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
9227 Opcode_bltu_Slot_inst_encode, 0, 0
9230 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
9231 Opcode_bany_Slot_inst_encode, 0, 0
9234 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
9235 Opcode_bnone_Slot_inst_encode, 0, 0
9238 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
9239 Opcode_ball_Slot_inst_encode, 0, 0
9242 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
9243 Opcode_bnall_Slot_inst_encode, 0, 0
9246 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
9247 Opcode_bbc_Slot_inst_encode, 0, 0
9250 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
9251 Opcode_bbs_Slot_inst_encode, 0, 0
9254 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
9255 Opcode_beqz_Slot_inst_encode, 0, 0
9258 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
9259 Opcode_bnez_Slot_inst_encode, 0, 0
9262 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
9263 Opcode_bgez_Slot_inst_encode, 0, 0
9266 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
9267 Opcode_bltz_Slot_inst_encode, 0, 0
9270 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
9271 Opcode_call0_Slot_inst_encode, 0, 0
9274 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
9275 Opcode_callx0_Slot_inst_encode, 0, 0
9278 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
9279 Opcode_extui_Slot_inst_encode, 0, 0
9282 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
9283 Opcode_ill_Slot_inst_encode, 0, 0
9286 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
9287 Opcode_j_Slot_inst_encode, 0, 0
9290 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
9291 Opcode_jx_Slot_inst_encode, 0, 0
9294 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
9295 Opcode_l16ui_Slot_inst_encode, 0, 0
9298 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
9299 Opcode_l16si_Slot_inst_encode, 0, 0
9302 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
9303 Opcode_l32i_Slot_inst_encode, 0, 0
9306 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
9307 Opcode_l32r_Slot_inst_encode, 0, 0
9310 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
9311 Opcode_l8ui_Slot_inst_encode, 0, 0
9314 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
9315 Opcode_loop_Slot_inst_encode, 0, 0
9318 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
9319 Opcode_loopnez_Slot_inst_encode, 0, 0
9322 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
9323 Opcode_loopgtz_Slot_inst_encode, 0, 0
9326 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
9327 Opcode_movi_Slot_inst_encode, 0, 0
9330 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
9331 Opcode_moveqz_Slot_inst_encode, 0, 0
9334 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
9335 Opcode_movnez_Slot_inst_encode, 0, 0
9338 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
9339 Opcode_movltz_Slot_inst_encode, 0, 0
9342 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
9343 Opcode_movgez_Slot_inst_encode, 0, 0
9346 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
9347 Opcode_neg_Slot_inst_encode, 0, 0
9350 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
9351 Opcode_abs_Slot_inst_encode, 0, 0
9354 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
9355 Opcode_nop_Slot_inst_encode, 0, 0
9358 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
9359 Opcode_ret_Slot_inst_encode, 0, 0
9362 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
9363 Opcode_s16i_Slot_inst_encode, 0, 0
9366 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
9367 Opcode_s32i_Slot_inst_encode, 0, 0
9370 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
9371 Opcode_s8i_Slot_inst_encode, 0, 0
9374 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
9375 Opcode_ssr_Slot_inst_encode, 0, 0
9378 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
9379 Opcode_ssl_Slot_inst_encode, 0, 0
9382 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
9383 Opcode_ssa8l_Slot_inst_encode, 0, 0
9386 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
9387 Opcode_ssa8b_Slot_inst_encode, 0, 0
9390 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
9391 Opcode_ssai_Slot_inst_encode, 0, 0
9394 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
9395 Opcode_sll_Slot_inst_encode, 0, 0
9398 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
9399 Opcode_src_Slot_inst_encode, 0, 0
9402 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
9403 Opcode_srl_Slot_inst_encode, 0, 0
9406 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
9407 Opcode_sra_Slot_inst_encode, 0, 0
9410 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
9411 Opcode_slli_Slot_inst_encode, 0, 0
9414 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
9415 Opcode_srai_Slot_inst_encode, 0, 0
9418 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
9419 Opcode_srli_Slot_inst_encode, 0, 0
9422 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
9423 Opcode_memw_Slot_inst_encode, 0, 0
9426 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
9427 Opcode_extw_Slot_inst_encode, 0, 0
9430 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
9431 Opcode_isync_Slot_inst_encode, 0, 0
9434 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
9435 Opcode_rsync_Slot_inst_encode, 0, 0
9438 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
9439 Opcode_esync_Slot_inst_encode, 0, 0
9442 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
9443 Opcode_dsync_Slot_inst_encode, 0, 0
9446 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
9447 Opcode_rsil_Slot_inst_encode, 0, 0
9450 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
9451 Opcode_rsr_lend_Slot_inst_encode, 0, 0
9454 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
9455 Opcode_wsr_lend_Slot_inst_encode, 0, 0
9458 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
9459 Opcode_xsr_lend_Slot_inst_encode, 0, 0
9462 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
9463 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
9466 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
9467 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
9470 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
9471 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
9474 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
9475 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
9478 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
9479 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
9482 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
9483 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
9486 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
9487 Opcode_rsr_sar_Slot_inst_encode, 0, 0
9490 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
9491 Opcode_wsr_sar_Slot_inst_encode, 0, 0
9494 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
9495 Opcode_xsr_sar_Slot_inst_encode, 0, 0
9498 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
9499 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
9502 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
9503 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
9506 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
9507 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
9510 static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
9511 Opcode_rsr_176_Slot_inst_encode, 0, 0
9514 static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
9515 Opcode_rsr_208_Slot_inst_encode, 0, 0
9518 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
9519 Opcode_rsr_ps_Slot_inst_encode, 0, 0
9522 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
9523 Opcode_wsr_ps_Slot_inst_encode, 0, 0
9526 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
9527 Opcode_xsr_ps_Slot_inst_encode, 0, 0
9530 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
9531 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
9534 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
9535 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
9538 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
9539 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
9542 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
9543 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
9546 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
9547 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
9550 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
9551 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
9554 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
9555 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
9558 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
9559 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
9562 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
9563 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
9566 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
9567 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
9570 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
9571 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
9574 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
9575 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
9578 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
9579 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
9582 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
9583 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
9586 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
9587 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
9590 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
9591 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
9594 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
9595 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
9598 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
9599 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
9602 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
9603 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
9606 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
9607 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
9610 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
9611 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
9614 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
9615 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
9618 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
9619 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
9622 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
9623 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
9626 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
9627 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
9630 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
9631 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
9634 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
9635 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
9638 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
9639 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
9642 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
9643 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
9646 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
9647 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
9650 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
9651 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
9654 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
9655 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
9658 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
9659 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
9662 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
9663 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
9666 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
9667 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
9670 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
9671 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
9674 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
9675 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
9678 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
9679 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
9682 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
9683 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
9686 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
9687 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
9690 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
9691 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
9694 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
9695 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
9698 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
9699 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
9702 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
9703 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
9706 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
9707 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
9710 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
9711 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
9714 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
9715 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
9718 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
9719 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
9722 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
9723 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
9726 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
9727 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
9730 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
9731 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
9734 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
9735 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
9738 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
9739 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
9742 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
9743 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
9746 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
9747 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
9750 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
9751 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
9754 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
9755 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
9758 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
9759 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
9762 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
9763 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
9766 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
9767 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
9770 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
9771 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
9774 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
9775 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
9778 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
9779 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
9782 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
9783 Opcode_rsr_depc_Slot_inst_encode, 0, 0
9786 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
9787 Opcode_wsr_depc_Slot_inst_encode, 0, 0
9790 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
9791 Opcode_xsr_depc_Slot_inst_encode, 0, 0
9794 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
9795 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
9798 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
9799 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
9802 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
9803 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
9806 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
9807 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
9810 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
9811 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
9814 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
9815 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
9818 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
9819 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
9822 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
9823 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
9826 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
9827 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
9830 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
9831 Opcode_rsr_prid_Slot_inst_encode, 0, 0
9834 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
9835 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
9838 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
9839 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
9842 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
9843 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
9846 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
9847 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
9850 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
9851 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
9854 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
9855 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
9858 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
9859 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
9862 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
9863 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
9866 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
9867 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
9870 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
9871 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
9874 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
9875 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
9878 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
9879 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
9882 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
9883 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
9886 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
9887 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
9890 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
9891 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
9894 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
9895 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
9898 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
9899 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
9902 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
9903 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
9906 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
9907 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
9910 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
9911 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
9914 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
9915 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
9918 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
9919 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
9922 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
9923 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
9926 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
9927 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
9930 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
9931 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
9934 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
9935 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
9938 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
9939 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
9942 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
9943 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
9946 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
9947 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
9950 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
9951 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
9954 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
9955 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
9958 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
9959 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
9962 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
9963 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
9966 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
9967 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
9970 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
9971 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
9974 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
9975 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
9978 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
9979 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
9982 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
9983 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
9986 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
9987 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
9990 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
9991 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
9994 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
9995 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
9998 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
9999 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10002 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
10003 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10006 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
10007 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10010 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
10011 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10014 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
10015 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10018 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
10019 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10022 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
10023 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10026 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
10027 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10030 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
10031 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10034 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
10035 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10038 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
10039 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10042 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
10043 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10046 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
10047 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10050 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
10051 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10054 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
10055 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10058 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
10059 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10062 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
10063 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10066 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
10067 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10070 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
10071 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10074 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
10075 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10078 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
10079 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10082 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
10083 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10086 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
10087 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10090 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
10091 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10094 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
10095 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10098 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
10099 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10102 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
10103 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10106 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
10107 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10110 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
10111 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10114 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
10115 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10118 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
10119 Opcode_lddec_Slot_inst_encode, 0, 0
10122 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
10123 Opcode_ldinc_Slot_inst_encode, 0, 0
10126 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
10127 Opcode_mul16u_Slot_inst_encode, 0, 0
10130 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
10131 Opcode_mul16s_Slot_inst_encode, 0, 0
10134 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
10135 Opcode_rsr_m0_Slot_inst_encode, 0, 0
10138 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
10139 Opcode_wsr_m0_Slot_inst_encode, 0, 0
10142 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
10143 Opcode_xsr_m0_Slot_inst_encode, 0, 0
10146 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
10147 Opcode_rsr_m1_Slot_inst_encode, 0, 0
10150 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
10151 Opcode_wsr_m1_Slot_inst_encode, 0, 0
10154 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
10155 Opcode_xsr_m1_Slot_inst_encode, 0, 0
10158 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
10159 Opcode_rsr_m2_Slot_inst_encode, 0, 0
10162 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
10163 Opcode_wsr_m2_Slot_inst_encode, 0, 0
10166 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
10167 Opcode_xsr_m2_Slot_inst_encode, 0, 0
10170 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
10171 Opcode_rsr_m3_Slot_inst_encode, 0, 0
10174 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
10175 Opcode_wsr_m3_Slot_inst_encode, 0, 0
10178 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
10179 Opcode_xsr_m3_Slot_inst_encode, 0, 0
10182 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
10183 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10186 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
10187 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10190 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
10191 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10194 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
10195 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10198 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
10199 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10202 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
10203 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10206 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
10207 Opcode_rfi_Slot_inst_encode, 0, 0
10210 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
10211 Opcode_waiti_Slot_inst_encode, 0, 0
10214 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
10215 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10218 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
10219 Opcode_wsr_intset_Slot_inst_encode, 0, 0
10222 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
10223 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10226 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
10227 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10230 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
10231 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10234 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
10235 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10238 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
10239 Opcode_break_Slot_inst_encode, 0, 0
10242 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
10243 0, 0, Opcode_break_n_Slot_inst16b_encode
10246 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
10247 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10250 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
10251 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10254 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
10255 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10258 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
10259 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10262 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
10263 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10266 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
10267 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10270 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
10271 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10274 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
10275 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10278 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
10279 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10282 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
10283 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10286 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
10287 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10290 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
10291 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10294 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
10295 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10298 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
10299 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10302 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
10303 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10306 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
10307 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10310 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
10311 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10314 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
10315 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10318 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
10319 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10322 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
10323 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10326 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
10327 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10330 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
10331 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10334 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
10335 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10338 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
10339 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10342 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
10343 Opcode_rsr_icount_Slot_inst_encode, 0, 0
10346 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
10347 Opcode_wsr_icount_Slot_inst_encode, 0, 0
10350 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
10351 Opcode_xsr_icount_Slot_inst_encode, 0, 0
10354 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
10355 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10358 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
10359 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10362 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
10363 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10366 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
10367 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10370 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
10371 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
10374 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
10375 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
10378 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
10379 Opcode_rfdo_Slot_inst_encode, 0, 0
10382 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
10383 Opcode_rfdd_Slot_inst_encode, 0, 0
10386 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
10387 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
10390 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
10391 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
10394 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
10395 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
10398 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
10399 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
10402 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
10403 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
10406 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
10407 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
10410 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
10411 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
10414 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
10415 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
10418 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
10419 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
10422 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
10423 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
10426 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
10427 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
10430 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
10431 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
10434 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
10435 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
10438 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
10439 Opcode_ipf_Slot_inst_encode, 0, 0
10442 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
10443 Opcode_ihi_Slot_inst_encode, 0, 0
10446 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
10447 Opcode_ipfl_Slot_inst_encode, 0, 0
10450 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
10451 Opcode_ihu_Slot_inst_encode, 0, 0
10454 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
10455 Opcode_iiu_Slot_inst_encode, 0, 0
10458 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
10459 Opcode_iii_Slot_inst_encode, 0, 0
10462 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
10463 Opcode_lict_Slot_inst_encode, 0, 0
10466 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
10467 Opcode_licw_Slot_inst_encode, 0, 0
10470 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
10471 Opcode_sict_Slot_inst_encode, 0, 0
10474 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
10475 Opcode_sicw_Slot_inst_encode, 0, 0
10478 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
10479 Opcode_dhwb_Slot_inst_encode, 0, 0
10482 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
10483 Opcode_dhwbi_Slot_inst_encode, 0, 0
10486 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
10487 Opcode_diwb_Slot_inst_encode, 0, 0
10490 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
10491 Opcode_diwbi_Slot_inst_encode, 0, 0
10494 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
10495 Opcode_dhi_Slot_inst_encode, 0, 0
10498 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
10499 Opcode_dii_Slot_inst_encode, 0, 0
10502 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
10503 Opcode_dpfr_Slot_inst_encode, 0, 0
10506 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
10507 Opcode_dpfw_Slot_inst_encode, 0, 0
10510 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
10511 Opcode_dpfro_Slot_inst_encode, 0, 0
10514 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
10515 Opcode_dpfwo_Slot_inst_encode, 0, 0
10518 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
10519 Opcode_dpfl_Slot_inst_encode, 0, 0
10522 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
10523 Opcode_dhu_Slot_inst_encode, 0, 0
10526 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
10527 Opcode_diu_Slot_inst_encode, 0, 0
10530 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
10531 Opcode_sdct_Slot_inst_encode, 0, 0
10534 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
10535 Opcode_ldct_Slot_inst_encode, 0, 0
10538 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
10539 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
10542 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
10543 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
10546 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
10547 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
10550 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
10551 Opcode_rsr_rasid_Slot_inst_encode, 0, 0
10554 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
10555 Opcode_wsr_rasid_Slot_inst_encode, 0, 0
10558 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
10559 Opcode_xsr_rasid_Slot_inst_encode, 0, 0
10562 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
10563 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
10566 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
10567 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
10570 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
10571 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
10574 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
10575 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
10578 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
10579 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
10582 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
10583 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
10586 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
10587 Opcode_idtlb_Slot_inst_encode, 0, 0
10590 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
10591 Opcode_pdtlb_Slot_inst_encode, 0, 0
10594 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
10595 Opcode_rdtlb0_Slot_inst_encode, 0, 0
10598 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
10599 Opcode_rdtlb1_Slot_inst_encode, 0, 0
10602 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
10603 Opcode_wdtlb_Slot_inst_encode, 0, 0
10606 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
10607 Opcode_iitlb_Slot_inst_encode, 0, 0
10610 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
10611 Opcode_pitlb_Slot_inst_encode, 0, 0
10614 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
10615 Opcode_ritlb0_Slot_inst_encode, 0, 0
10618 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
10619 Opcode_ritlb1_Slot_inst_encode, 0, 0
10622 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
10623 Opcode_witlb_Slot_inst_encode, 0, 0
10626 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
10627 Opcode_ldpte_Slot_inst_encode, 0, 0
10630 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
10631 Opcode_hwwitlba_Slot_inst_encode, 0, 0
10634 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
10635 Opcode_hwwdtlba_Slot_inst_encode, 0, 0
10638 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
10639 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
10642 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
10643 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
10646 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
10647 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
10650 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
10651 Opcode_clamps_Slot_inst_encode, 0, 0
10654 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
10655 Opcode_min_Slot_inst_encode, 0, 0
10658 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
10659 Opcode_max_Slot_inst_encode, 0, 0
10662 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
10663 Opcode_minu_Slot_inst_encode, 0, 0
10666 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
10667 Opcode_maxu_Slot_inst_encode, 0, 0
10670 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
10671 Opcode_nsa_Slot_inst_encode, 0, 0
10674 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
10675 Opcode_nsau_Slot_inst_encode, 0, 0
10678 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
10679 Opcode_sext_Slot_inst_encode, 0, 0
10682 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
10683 Opcode_l32ai_Slot_inst_encode, 0, 0
10686 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
10687 Opcode_s32ri_Slot_inst_encode, 0, 0
10690 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
10691 Opcode_s32c1i_Slot_inst_encode, 0, 0
10694 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
10695 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
10698 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
10699 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
10702 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
10703 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
10706 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
10707 Opcode_quou_Slot_inst_encode, 0, 0
10710 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
10711 Opcode_quos_Slot_inst_encode, 0, 0
10714 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
10715 Opcode_remu_Slot_inst_encode, 0, 0
10718 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
10719 Opcode_rems_Slot_inst_encode, 0, 0
10722 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
10723 Opcode_mull_Slot_inst_encode, 0, 0
10726 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
10727 Opcode_rur_expstate_Slot_inst_encode, 0, 0
10730 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
10731 Opcode_wur_expstate_Slot_inst_encode, 0, 0
10734 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
10735 Opcode_read_impwire_Slot_inst_encode, 0, 0
10738 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
10739 Opcode_setb_expstate_Slot_inst_encode, 0, 0
10742 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
10743 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
10746 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
10747 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
10751 /* Opcode table. */
10753 static xtensa_opcode_internal opcodes[] = {
10754 { "excw", 0 /* xt_iclass_excw */,
10756 Opcode_excw_encode_fns, 0, 0 },
10757 { "rfe", 1 /* xt_iclass_rfe */,
10758 XTENSA_OPCODE_IS_JUMP,
10759 Opcode_rfe_encode_fns, 0, 0 },
10760 { "rfde", 2 /* xt_iclass_rfde */,
10761 XTENSA_OPCODE_IS_JUMP,
10762 Opcode_rfde_encode_fns, 0, 0 },
10763 { "syscall", 3 /* xt_iclass_syscall */,
10765 Opcode_syscall_encode_fns, 0, 0 },
10766 { "simcall", 4 /* xt_iclass_simcall */,
10768 Opcode_simcall_encode_fns, 0, 0 },
10769 { "call12", 5 /* xt_iclass_call12 */,
10770 XTENSA_OPCODE_IS_CALL,
10771 Opcode_call12_encode_fns, 0, 0 },
10772 { "call8", 6 /* xt_iclass_call8 */,
10773 XTENSA_OPCODE_IS_CALL,
10774 Opcode_call8_encode_fns, 0, 0 },
10775 { "call4", 7 /* xt_iclass_call4 */,
10776 XTENSA_OPCODE_IS_CALL,
10777 Opcode_call4_encode_fns, 0, 0 },
10778 { "callx12", 8 /* xt_iclass_callx12 */,
10779 XTENSA_OPCODE_IS_CALL,
10780 Opcode_callx12_encode_fns, 0, 0 },
10781 { "callx8", 9 /* xt_iclass_callx8 */,
10782 XTENSA_OPCODE_IS_CALL,
10783 Opcode_callx8_encode_fns, 0, 0 },
10784 { "callx4", 10 /* xt_iclass_callx4 */,
10785 XTENSA_OPCODE_IS_CALL,
10786 Opcode_callx4_encode_fns, 0, 0 },
10787 { "entry", 11 /* xt_iclass_entry */,
10789 Opcode_entry_encode_fns, 0, 0 },
10790 { "movsp", 12 /* xt_iclass_movsp */,
10792 Opcode_movsp_encode_fns, 0, 0 },
10793 { "rotw", 13 /* xt_iclass_rotw */,
10795 Opcode_rotw_encode_fns, 0, 0 },
10796 { "retw", 14 /* xt_iclass_retw */,
10797 XTENSA_OPCODE_IS_JUMP,
10798 Opcode_retw_encode_fns, 0, 0 },
10799 { "retw.n", 14 /* xt_iclass_retw */,
10800 XTENSA_OPCODE_IS_JUMP,
10801 Opcode_retw_n_encode_fns, 0, 0 },
10802 { "rfwo", 15 /* xt_iclass_rfwou */,
10803 XTENSA_OPCODE_IS_JUMP,
10804 Opcode_rfwo_encode_fns, 0, 0 },
10805 { "rfwu", 15 /* xt_iclass_rfwou */,
10806 XTENSA_OPCODE_IS_JUMP,
10807 Opcode_rfwu_encode_fns, 0, 0 },
10808 { "l32e", 16 /* xt_iclass_l32e */,
10810 Opcode_l32e_encode_fns, 0, 0 },
10811 { "s32e", 17 /* xt_iclass_s32e */,
10813 Opcode_s32e_encode_fns, 0, 0 },
10814 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
10816 Opcode_rsr_windowbase_encode_fns, 0, 0 },
10817 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
10819 Opcode_wsr_windowbase_encode_fns, 0, 0 },
10820 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
10822 Opcode_xsr_windowbase_encode_fns, 0, 0 },
10823 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
10825 Opcode_rsr_windowstart_encode_fns, 0, 0 },
10826 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
10828 Opcode_wsr_windowstart_encode_fns, 0, 0 },
10829 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
10831 Opcode_xsr_windowstart_encode_fns, 0, 0 },
10832 { "add.n", 24 /* xt_iclass_add.n */,
10834 Opcode_add_n_encode_fns, 0, 0 },
10835 { "addi.n", 25 /* xt_iclass_addi.n */,
10837 Opcode_addi_n_encode_fns, 0, 0 },
10838 { "beqz.n", 26 /* xt_iclass_bz6 */,
10839 XTENSA_OPCODE_IS_BRANCH,
10840 Opcode_beqz_n_encode_fns, 0, 0 },
10841 { "bnez.n", 26 /* xt_iclass_bz6 */,
10842 XTENSA_OPCODE_IS_BRANCH,
10843 Opcode_bnez_n_encode_fns, 0, 0 },
10844 { "ill.n", 27 /* xt_iclass_ill.n */,
10846 Opcode_ill_n_encode_fns, 0, 0 },
10847 { "l32i.n", 28 /* xt_iclass_loadi4 */,
10849 Opcode_l32i_n_encode_fns, 0, 0 },
10850 { "mov.n", 29 /* xt_iclass_mov.n */,
10852 Opcode_mov_n_encode_fns, 0, 0 },
10853 { "movi.n", 30 /* xt_iclass_movi.n */,
10855 Opcode_movi_n_encode_fns, 0, 0 },
10856 { "nop.n", 31 /* xt_iclass_nopn */,
10858 Opcode_nop_n_encode_fns, 0, 0 },
10859 { "ret.n", 32 /* xt_iclass_retn */,
10860 XTENSA_OPCODE_IS_JUMP,
10861 Opcode_ret_n_encode_fns, 0, 0 },
10862 { "s32i.n", 33 /* xt_iclass_storei4 */,
10864 Opcode_s32i_n_encode_fns, 0, 0 },
10865 { "rur.threadptr", 34 /* rur_threadptr */,
10867 Opcode_rur_threadptr_encode_fns, 0, 0 },
10868 { "wur.threadptr", 35 /* wur_threadptr */,
10870 Opcode_wur_threadptr_encode_fns, 0, 0 },
10871 { "addi", 36 /* xt_iclass_addi */,
10873 Opcode_addi_encode_fns, 0, 0 },
10874 { "addmi", 37 /* xt_iclass_addmi */,
10876 Opcode_addmi_encode_fns, 0, 0 },
10877 { "add", 38 /* xt_iclass_addsub */,
10879 Opcode_add_encode_fns, 0, 0 },
10880 { "sub", 38 /* xt_iclass_addsub */,
10882 Opcode_sub_encode_fns, 0, 0 },
10883 { "addx2", 38 /* xt_iclass_addsub */,
10885 Opcode_addx2_encode_fns, 0, 0 },
10886 { "addx4", 38 /* xt_iclass_addsub */,
10888 Opcode_addx4_encode_fns, 0, 0 },
10889 { "addx8", 38 /* xt_iclass_addsub */,
10891 Opcode_addx8_encode_fns, 0, 0 },
10892 { "subx2", 38 /* xt_iclass_addsub */,
10894 Opcode_subx2_encode_fns, 0, 0 },
10895 { "subx4", 38 /* xt_iclass_addsub */,
10897 Opcode_subx4_encode_fns, 0, 0 },
10898 { "subx8", 38 /* xt_iclass_addsub */,
10900 Opcode_subx8_encode_fns, 0, 0 },
10901 { "and", 39 /* xt_iclass_bit */,
10903 Opcode_and_encode_fns, 0, 0 },
10904 { "or", 39 /* xt_iclass_bit */,
10906 Opcode_or_encode_fns, 0, 0 },
10907 { "xor", 39 /* xt_iclass_bit */,
10909 Opcode_xor_encode_fns, 0, 0 },
10910 { "beqi", 40 /* xt_iclass_bsi8 */,
10911 XTENSA_OPCODE_IS_BRANCH,
10912 Opcode_beqi_encode_fns, 0, 0 },
10913 { "bnei", 40 /* xt_iclass_bsi8 */,
10914 XTENSA_OPCODE_IS_BRANCH,
10915 Opcode_bnei_encode_fns, 0, 0 },
10916 { "bgei", 40 /* xt_iclass_bsi8 */,
10917 XTENSA_OPCODE_IS_BRANCH,
10918 Opcode_bgei_encode_fns, 0, 0 },
10919 { "blti", 40 /* xt_iclass_bsi8 */,
10920 XTENSA_OPCODE_IS_BRANCH,
10921 Opcode_blti_encode_fns, 0, 0 },
10922 { "bbci", 41 /* xt_iclass_bsi8b */,
10923 XTENSA_OPCODE_IS_BRANCH,
10924 Opcode_bbci_encode_fns, 0, 0 },
10925 { "bbsi", 41 /* xt_iclass_bsi8b */,
10926 XTENSA_OPCODE_IS_BRANCH,
10927 Opcode_bbsi_encode_fns, 0, 0 },
10928 { "bgeui", 42 /* xt_iclass_bsi8u */,
10929 XTENSA_OPCODE_IS_BRANCH,
10930 Opcode_bgeui_encode_fns, 0, 0 },
10931 { "bltui", 42 /* xt_iclass_bsi8u */,
10932 XTENSA_OPCODE_IS_BRANCH,
10933 Opcode_bltui_encode_fns, 0, 0 },
10934 { "beq", 43 /* xt_iclass_bst8 */,
10935 XTENSA_OPCODE_IS_BRANCH,
10936 Opcode_beq_encode_fns, 0, 0 },
10937 { "bne", 43 /* xt_iclass_bst8 */,
10938 XTENSA_OPCODE_IS_BRANCH,
10939 Opcode_bne_encode_fns, 0, 0 },
10940 { "bge", 43 /* xt_iclass_bst8 */,
10941 XTENSA_OPCODE_IS_BRANCH,
10942 Opcode_bge_encode_fns, 0, 0 },
10943 { "blt", 43 /* xt_iclass_bst8 */,
10944 XTENSA_OPCODE_IS_BRANCH,
10945 Opcode_blt_encode_fns, 0, 0 },
10946 { "bgeu", 43 /* xt_iclass_bst8 */,
10947 XTENSA_OPCODE_IS_BRANCH,
10948 Opcode_bgeu_encode_fns, 0, 0 },
10949 { "bltu", 43 /* xt_iclass_bst8 */,
10950 XTENSA_OPCODE_IS_BRANCH,
10951 Opcode_bltu_encode_fns, 0, 0 },
10952 { "bany", 43 /* xt_iclass_bst8 */,
10953 XTENSA_OPCODE_IS_BRANCH,
10954 Opcode_bany_encode_fns, 0, 0 },
10955 { "bnone", 43 /* xt_iclass_bst8 */,
10956 XTENSA_OPCODE_IS_BRANCH,
10957 Opcode_bnone_encode_fns, 0, 0 },
10958 { "ball", 43 /* xt_iclass_bst8 */,
10959 XTENSA_OPCODE_IS_BRANCH,
10960 Opcode_ball_encode_fns, 0, 0 },
10961 { "bnall", 43 /* xt_iclass_bst8 */,
10962 XTENSA_OPCODE_IS_BRANCH,
10963 Opcode_bnall_encode_fns, 0, 0 },
10964 { "bbc", 43 /* xt_iclass_bst8 */,
10965 XTENSA_OPCODE_IS_BRANCH,
10966 Opcode_bbc_encode_fns, 0, 0 },
10967 { "bbs", 43 /* xt_iclass_bst8 */,
10968 XTENSA_OPCODE_IS_BRANCH,
10969 Opcode_bbs_encode_fns, 0, 0 },
10970 { "beqz", 44 /* xt_iclass_bsz12 */,
10971 XTENSA_OPCODE_IS_BRANCH,
10972 Opcode_beqz_encode_fns, 0, 0 },
10973 { "bnez", 44 /* xt_iclass_bsz12 */,
10974 XTENSA_OPCODE_IS_BRANCH,
10975 Opcode_bnez_encode_fns, 0, 0 },
10976 { "bgez", 44 /* xt_iclass_bsz12 */,
10977 XTENSA_OPCODE_IS_BRANCH,
10978 Opcode_bgez_encode_fns, 0, 0 },
10979 { "bltz", 44 /* xt_iclass_bsz12 */,
10980 XTENSA_OPCODE_IS_BRANCH,
10981 Opcode_bltz_encode_fns, 0, 0 },
10982 { "call0", 45 /* xt_iclass_call0 */,
10983 XTENSA_OPCODE_IS_CALL,
10984 Opcode_call0_encode_fns, 0, 0 },
10985 { "callx0", 46 /* xt_iclass_callx0 */,
10986 XTENSA_OPCODE_IS_CALL,
10987 Opcode_callx0_encode_fns, 0, 0 },
10988 { "extui", 47 /* xt_iclass_exti */,
10990 Opcode_extui_encode_fns, 0, 0 },
10991 { "ill", 48 /* xt_iclass_ill */,
10993 Opcode_ill_encode_fns, 0, 0 },
10994 { "j", 49 /* xt_iclass_jump */,
10995 XTENSA_OPCODE_IS_JUMP,
10996 Opcode_j_encode_fns, 0, 0 },
10997 { "jx", 50 /* xt_iclass_jumpx */,
10998 XTENSA_OPCODE_IS_JUMP,
10999 Opcode_jx_encode_fns, 0, 0 },
11000 { "l16ui", 51 /* xt_iclass_l16ui */,
11002 Opcode_l16ui_encode_fns, 0, 0 },
11003 { "l16si", 52 /* xt_iclass_l16si */,
11005 Opcode_l16si_encode_fns, 0, 0 },
11006 { "l32i", 53 /* xt_iclass_l32i */,
11008 Opcode_l32i_encode_fns, 0, 0 },
11009 { "l32r", 54 /* xt_iclass_l32r */,
11011 Opcode_l32r_encode_fns, 0, 0 },
11012 { "l8ui", 55 /* xt_iclass_l8i */,
11014 Opcode_l8ui_encode_fns, 0, 0 },
11015 { "loop", 56 /* xt_iclass_loop */,
11016 XTENSA_OPCODE_IS_LOOP,
11017 Opcode_loop_encode_fns, 0, 0 },
11018 { "loopnez", 57 /* xt_iclass_loopz */,
11019 XTENSA_OPCODE_IS_LOOP,
11020 Opcode_loopnez_encode_fns, 0, 0 },
11021 { "loopgtz", 57 /* xt_iclass_loopz */,
11022 XTENSA_OPCODE_IS_LOOP,
11023 Opcode_loopgtz_encode_fns, 0, 0 },
11024 { "movi", 58 /* xt_iclass_movi */,
11026 Opcode_movi_encode_fns, 0, 0 },
11027 { "moveqz", 59 /* xt_iclass_movz */,
11029 Opcode_moveqz_encode_fns, 0, 0 },
11030 { "movnez", 59 /* xt_iclass_movz */,
11032 Opcode_movnez_encode_fns, 0, 0 },
11033 { "movltz", 59 /* xt_iclass_movz */,
11035 Opcode_movltz_encode_fns, 0, 0 },
11036 { "movgez", 59 /* xt_iclass_movz */,
11038 Opcode_movgez_encode_fns, 0, 0 },
11039 { "neg", 60 /* xt_iclass_neg */,
11041 Opcode_neg_encode_fns, 0, 0 },
11042 { "abs", 60 /* xt_iclass_neg */,
11044 Opcode_abs_encode_fns, 0, 0 },
11045 { "nop", 61 /* xt_iclass_nop */,
11047 Opcode_nop_encode_fns, 0, 0 },
11048 { "ret", 62 /* xt_iclass_return */,
11049 XTENSA_OPCODE_IS_JUMP,
11050 Opcode_ret_encode_fns, 0, 0 },
11051 { "s16i", 63 /* xt_iclass_s16i */,
11053 Opcode_s16i_encode_fns, 0, 0 },
11054 { "s32i", 64 /* xt_iclass_s32i */,
11056 Opcode_s32i_encode_fns, 0, 0 },
11057 { "s8i", 65 /* xt_iclass_s8i */,
11059 Opcode_s8i_encode_fns, 0, 0 },
11060 { "ssr", 66 /* xt_iclass_sar */,
11062 Opcode_ssr_encode_fns, 0, 0 },
11063 { "ssl", 66 /* xt_iclass_sar */,
11065 Opcode_ssl_encode_fns, 0, 0 },
11066 { "ssa8l", 66 /* xt_iclass_sar */,
11068 Opcode_ssa8l_encode_fns, 0, 0 },
11069 { "ssa8b", 66 /* xt_iclass_sar */,
11071 Opcode_ssa8b_encode_fns, 0, 0 },
11072 { "ssai", 67 /* xt_iclass_sari */,
11074 Opcode_ssai_encode_fns, 0, 0 },
11075 { "sll", 68 /* xt_iclass_shifts */,
11077 Opcode_sll_encode_fns, 0, 0 },
11078 { "src", 69 /* xt_iclass_shiftst */,
11080 Opcode_src_encode_fns, 0, 0 },
11081 { "srl", 70 /* xt_iclass_shiftt */,
11083 Opcode_srl_encode_fns, 0, 0 },
11084 { "sra", 70 /* xt_iclass_shiftt */,
11086 Opcode_sra_encode_fns, 0, 0 },
11087 { "slli", 71 /* xt_iclass_slli */,
11089 Opcode_slli_encode_fns, 0, 0 },
11090 { "srai", 72 /* xt_iclass_srai */,
11092 Opcode_srai_encode_fns, 0, 0 },
11093 { "srli", 73 /* xt_iclass_srli */,
11095 Opcode_srli_encode_fns, 0, 0 },
11096 { "memw", 74 /* xt_iclass_memw */,
11098 Opcode_memw_encode_fns, 0, 0 },
11099 { "extw", 75 /* xt_iclass_extw */,
11101 Opcode_extw_encode_fns, 0, 0 },
11102 { "isync", 76 /* xt_iclass_isync */,
11104 Opcode_isync_encode_fns, 0, 0 },
11105 { "rsync", 77 /* xt_iclass_sync */,
11107 Opcode_rsync_encode_fns, 0, 0 },
11108 { "esync", 77 /* xt_iclass_sync */,
11110 Opcode_esync_encode_fns, 0, 0 },
11111 { "dsync", 77 /* xt_iclass_sync */,
11113 Opcode_dsync_encode_fns, 0, 0 },
11114 { "rsil", 78 /* xt_iclass_rsil */,
11116 Opcode_rsil_encode_fns, 0, 0 },
11117 { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
11119 Opcode_rsr_lend_encode_fns, 0, 0 },
11120 { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
11122 Opcode_wsr_lend_encode_fns, 0, 0 },
11123 { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
11125 Opcode_xsr_lend_encode_fns, 0, 0 },
11126 { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
11128 Opcode_rsr_lcount_encode_fns, 0, 0 },
11129 { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
11131 Opcode_wsr_lcount_encode_fns, 0, 0 },
11132 { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
11134 Opcode_xsr_lcount_encode_fns, 0, 0 },
11135 { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
11137 Opcode_rsr_lbeg_encode_fns, 0, 0 },
11138 { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
11140 Opcode_wsr_lbeg_encode_fns, 0, 0 },
11141 { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
11143 Opcode_xsr_lbeg_encode_fns, 0, 0 },
11144 { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
11146 Opcode_rsr_sar_encode_fns, 0, 0 },
11147 { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
11149 Opcode_wsr_sar_encode_fns, 0, 0 },
11150 { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
11152 Opcode_xsr_sar_encode_fns, 0, 0 },
11153 { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
11155 Opcode_rsr_litbase_encode_fns, 0, 0 },
11156 { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
11158 Opcode_wsr_litbase_encode_fns, 0, 0 },
11159 { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
11161 Opcode_xsr_litbase_encode_fns, 0, 0 },
11162 { "rsr.176", 94 /* xt_iclass_rsr.176 */,
11164 Opcode_rsr_176_encode_fns, 0, 0 },
11165 { "rsr.208", 95 /* xt_iclass_rsr.208 */,
11167 Opcode_rsr_208_encode_fns, 0, 0 },
11168 { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
11170 Opcode_rsr_ps_encode_fns, 0, 0 },
11171 { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
11173 Opcode_wsr_ps_encode_fns, 0, 0 },
11174 { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
11176 Opcode_xsr_ps_encode_fns, 0, 0 },
11177 { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
11179 Opcode_rsr_epc1_encode_fns, 0, 0 },
11180 { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
11182 Opcode_wsr_epc1_encode_fns, 0, 0 },
11183 { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
11185 Opcode_xsr_epc1_encode_fns, 0, 0 },
11186 { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
11188 Opcode_rsr_excsave1_encode_fns, 0, 0 },
11189 { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
11191 Opcode_wsr_excsave1_encode_fns, 0, 0 },
11192 { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
11194 Opcode_xsr_excsave1_encode_fns, 0, 0 },
11195 { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
11197 Opcode_rsr_epc2_encode_fns, 0, 0 },
11198 { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
11200 Opcode_wsr_epc2_encode_fns, 0, 0 },
11201 { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
11203 Opcode_xsr_epc2_encode_fns, 0, 0 },
11204 { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
11206 Opcode_rsr_excsave2_encode_fns, 0, 0 },
11207 { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
11209 Opcode_wsr_excsave2_encode_fns, 0, 0 },
11210 { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
11212 Opcode_xsr_excsave2_encode_fns, 0, 0 },
11213 { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
11215 Opcode_rsr_epc3_encode_fns, 0, 0 },
11216 { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
11218 Opcode_wsr_epc3_encode_fns, 0, 0 },
11219 { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
11221 Opcode_xsr_epc3_encode_fns, 0, 0 },
11222 { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
11224 Opcode_rsr_excsave3_encode_fns, 0, 0 },
11225 { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
11227 Opcode_wsr_excsave3_encode_fns, 0, 0 },
11228 { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
11230 Opcode_xsr_excsave3_encode_fns, 0, 0 },
11231 { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
11233 Opcode_rsr_epc4_encode_fns, 0, 0 },
11234 { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
11236 Opcode_wsr_epc4_encode_fns, 0, 0 },
11237 { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
11239 Opcode_xsr_epc4_encode_fns, 0, 0 },
11240 { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
11242 Opcode_rsr_excsave4_encode_fns, 0, 0 },
11243 { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
11245 Opcode_wsr_excsave4_encode_fns, 0, 0 },
11246 { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
11248 Opcode_xsr_excsave4_encode_fns, 0, 0 },
11249 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
11251 Opcode_rsr_epc5_encode_fns, 0, 0 },
11252 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
11254 Opcode_wsr_epc5_encode_fns, 0, 0 },
11255 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
11257 Opcode_xsr_epc5_encode_fns, 0, 0 },
11258 { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
11260 Opcode_rsr_excsave5_encode_fns, 0, 0 },
11261 { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
11263 Opcode_wsr_excsave5_encode_fns, 0, 0 },
11264 { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
11266 Opcode_xsr_excsave5_encode_fns, 0, 0 },
11267 { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
11269 Opcode_rsr_epc6_encode_fns, 0, 0 },
11270 { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
11272 Opcode_wsr_epc6_encode_fns, 0, 0 },
11273 { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
11275 Opcode_xsr_epc6_encode_fns, 0, 0 },
11276 { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
11278 Opcode_rsr_excsave6_encode_fns, 0, 0 },
11279 { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
11281 Opcode_wsr_excsave6_encode_fns, 0, 0 },
11282 { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
11284 Opcode_xsr_excsave6_encode_fns, 0, 0 },
11285 { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
11287 Opcode_rsr_epc7_encode_fns, 0, 0 },
11288 { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
11290 Opcode_wsr_epc7_encode_fns, 0, 0 },
11291 { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
11293 Opcode_xsr_epc7_encode_fns, 0, 0 },
11294 { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
11296 Opcode_rsr_excsave7_encode_fns, 0, 0 },
11297 { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
11299 Opcode_wsr_excsave7_encode_fns, 0, 0 },
11300 { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
11302 Opcode_xsr_excsave7_encode_fns, 0, 0 },
11303 { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
11305 Opcode_rsr_eps2_encode_fns, 0, 0 },
11306 { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
11308 Opcode_wsr_eps2_encode_fns, 0, 0 },
11309 { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
11311 Opcode_xsr_eps2_encode_fns, 0, 0 },
11312 { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
11314 Opcode_rsr_eps3_encode_fns, 0, 0 },
11315 { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
11317 Opcode_wsr_eps3_encode_fns, 0, 0 },
11318 { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
11320 Opcode_xsr_eps3_encode_fns, 0, 0 },
11321 { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
11323 Opcode_rsr_eps4_encode_fns, 0, 0 },
11324 { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
11326 Opcode_wsr_eps4_encode_fns, 0, 0 },
11327 { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
11329 Opcode_xsr_eps4_encode_fns, 0, 0 },
11330 { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
11332 Opcode_rsr_eps5_encode_fns, 0, 0 },
11333 { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
11335 Opcode_wsr_eps5_encode_fns, 0, 0 },
11336 { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
11338 Opcode_xsr_eps5_encode_fns, 0, 0 },
11339 { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
11341 Opcode_rsr_eps6_encode_fns, 0, 0 },
11342 { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
11344 Opcode_wsr_eps6_encode_fns, 0, 0 },
11345 { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
11347 Opcode_xsr_eps6_encode_fns, 0, 0 },
11348 { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
11350 Opcode_rsr_eps7_encode_fns, 0, 0 },
11351 { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
11353 Opcode_wsr_eps7_encode_fns, 0, 0 },
11354 { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
11356 Opcode_xsr_eps7_encode_fns, 0, 0 },
11357 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
11359 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
11360 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
11362 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
11363 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
11365 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
11366 { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
11368 Opcode_rsr_depc_encode_fns, 0, 0 },
11369 { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
11371 Opcode_wsr_depc_encode_fns, 0, 0 },
11372 { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
11374 Opcode_xsr_depc_encode_fns, 0, 0 },
11375 { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
11377 Opcode_rsr_exccause_encode_fns, 0, 0 },
11378 { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
11380 Opcode_wsr_exccause_encode_fns, 0, 0 },
11381 { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
11383 Opcode_xsr_exccause_encode_fns, 0, 0 },
11384 { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
11386 Opcode_rsr_misc0_encode_fns, 0, 0 },
11387 { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
11389 Opcode_wsr_misc0_encode_fns, 0, 0 },
11390 { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
11392 Opcode_xsr_misc0_encode_fns, 0, 0 },
11393 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
11395 Opcode_rsr_misc1_encode_fns, 0, 0 },
11396 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
11398 Opcode_wsr_misc1_encode_fns, 0, 0 },
11399 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
11401 Opcode_xsr_misc1_encode_fns, 0, 0 },
11402 { "rsr.prid", 174 /* xt_iclass_rsr.prid */,
11404 Opcode_rsr_prid_encode_fns, 0, 0 },
11405 { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
11407 Opcode_rsr_vecbase_encode_fns, 0, 0 },
11408 { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
11410 Opcode_wsr_vecbase_encode_fns, 0, 0 },
11411 { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
11413 Opcode_xsr_vecbase_encode_fns, 0, 0 },
11414 { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */,
11416 Opcode_mul_aa_ll_encode_fns, 0, 0 },
11417 { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */,
11419 Opcode_mul_aa_hl_encode_fns, 0, 0 },
11420 { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */,
11422 Opcode_mul_aa_lh_encode_fns, 0, 0 },
11423 { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */,
11425 Opcode_mul_aa_hh_encode_fns, 0, 0 },
11426 { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */,
11428 Opcode_umul_aa_ll_encode_fns, 0, 0 },
11429 { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */,
11431 Opcode_umul_aa_hl_encode_fns, 0, 0 },
11432 { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */,
11434 Opcode_umul_aa_lh_encode_fns, 0, 0 },
11435 { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */,
11437 Opcode_umul_aa_hh_encode_fns, 0, 0 },
11438 { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */,
11440 Opcode_mul_ad_ll_encode_fns, 0, 0 },
11441 { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */,
11443 Opcode_mul_ad_hl_encode_fns, 0, 0 },
11444 { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */,
11446 Opcode_mul_ad_lh_encode_fns, 0, 0 },
11447 { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */,
11449 Opcode_mul_ad_hh_encode_fns, 0, 0 },
11450 { "mul.da.ll", 180 /* xt_iclass_mac16_da */,
11452 Opcode_mul_da_ll_encode_fns, 0, 0 },
11453 { "mul.da.hl", 180 /* xt_iclass_mac16_da */,
11455 Opcode_mul_da_hl_encode_fns, 0, 0 },
11456 { "mul.da.lh", 180 /* xt_iclass_mac16_da */,
11458 Opcode_mul_da_lh_encode_fns, 0, 0 },
11459 { "mul.da.hh", 180 /* xt_iclass_mac16_da */,
11461 Opcode_mul_da_hh_encode_fns, 0, 0 },
11462 { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */,
11464 Opcode_mul_dd_ll_encode_fns, 0, 0 },
11465 { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */,
11467 Opcode_mul_dd_hl_encode_fns, 0, 0 },
11468 { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */,
11470 Opcode_mul_dd_lh_encode_fns, 0, 0 },
11471 { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */,
11473 Opcode_mul_dd_hh_encode_fns, 0, 0 },
11474 { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */,
11476 Opcode_mula_aa_ll_encode_fns, 0, 0 },
11477 { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */,
11479 Opcode_mula_aa_hl_encode_fns, 0, 0 },
11480 { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */,
11482 Opcode_mula_aa_lh_encode_fns, 0, 0 },
11483 { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */,
11485 Opcode_mula_aa_hh_encode_fns, 0, 0 },
11486 { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */,
11488 Opcode_muls_aa_ll_encode_fns, 0, 0 },
11489 { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */,
11491 Opcode_muls_aa_hl_encode_fns, 0, 0 },
11492 { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */,
11494 Opcode_muls_aa_lh_encode_fns, 0, 0 },
11495 { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */,
11497 Opcode_muls_aa_hh_encode_fns, 0, 0 },
11498 { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */,
11500 Opcode_mula_ad_ll_encode_fns, 0, 0 },
11501 { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */,
11503 Opcode_mula_ad_hl_encode_fns, 0, 0 },
11504 { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */,
11506 Opcode_mula_ad_lh_encode_fns, 0, 0 },
11507 { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */,
11509 Opcode_mula_ad_hh_encode_fns, 0, 0 },
11510 { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */,
11512 Opcode_muls_ad_ll_encode_fns, 0, 0 },
11513 { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */,
11515 Opcode_muls_ad_hl_encode_fns, 0, 0 },
11516 { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */,
11518 Opcode_muls_ad_lh_encode_fns, 0, 0 },
11519 { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */,
11521 Opcode_muls_ad_hh_encode_fns, 0, 0 },
11522 { "mula.da.ll", 184 /* xt_iclass_mac16a_da */,
11524 Opcode_mula_da_ll_encode_fns, 0, 0 },
11525 { "mula.da.hl", 184 /* xt_iclass_mac16a_da */,
11527 Opcode_mula_da_hl_encode_fns, 0, 0 },
11528 { "mula.da.lh", 184 /* xt_iclass_mac16a_da */,
11530 Opcode_mula_da_lh_encode_fns, 0, 0 },
11531 { "mula.da.hh", 184 /* xt_iclass_mac16a_da */,
11533 Opcode_mula_da_hh_encode_fns, 0, 0 },
11534 { "muls.da.ll", 184 /* xt_iclass_mac16a_da */,
11536 Opcode_muls_da_ll_encode_fns, 0, 0 },
11537 { "muls.da.hl", 184 /* xt_iclass_mac16a_da */,
11539 Opcode_muls_da_hl_encode_fns, 0, 0 },
11540 { "muls.da.lh", 184 /* xt_iclass_mac16a_da */,
11542 Opcode_muls_da_lh_encode_fns, 0, 0 },
11543 { "muls.da.hh", 184 /* xt_iclass_mac16a_da */,
11545 Opcode_muls_da_hh_encode_fns, 0, 0 },
11546 { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */,
11548 Opcode_mula_dd_ll_encode_fns, 0, 0 },
11549 { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */,
11551 Opcode_mula_dd_hl_encode_fns, 0, 0 },
11552 { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */,
11554 Opcode_mula_dd_lh_encode_fns, 0, 0 },
11555 { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */,
11557 Opcode_mula_dd_hh_encode_fns, 0, 0 },
11558 { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */,
11560 Opcode_muls_dd_ll_encode_fns, 0, 0 },
11561 { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */,
11563 Opcode_muls_dd_hl_encode_fns, 0, 0 },
11564 { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */,
11566 Opcode_muls_dd_lh_encode_fns, 0, 0 },
11567 { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */,
11569 Opcode_muls_dd_hh_encode_fns, 0, 0 },
11570 { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */,
11572 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
11573 { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */,
11575 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
11576 { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */,
11578 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
11579 { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */,
11581 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
11582 { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */,
11584 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
11585 { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */,
11587 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
11588 { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */,
11590 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
11591 { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */,
11593 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
11594 { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */,
11596 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
11597 { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */,
11599 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
11600 { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */,
11602 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
11603 { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */,
11605 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
11606 { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */,
11608 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
11609 { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */,
11611 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
11612 { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */,
11614 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
11615 { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */,
11617 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
11618 { "lddec", 188 /* xt_iclass_mac16_l */,
11620 Opcode_lddec_encode_fns, 0, 0 },
11621 { "ldinc", 188 /* xt_iclass_mac16_l */,
11623 Opcode_ldinc_encode_fns, 0, 0 },
11624 { "mul16u", 189 /* xt_iclass_mul16 */,
11626 Opcode_mul16u_encode_fns, 0, 0 },
11627 { "mul16s", 189 /* xt_iclass_mul16 */,
11629 Opcode_mul16s_encode_fns, 0, 0 },
11630 { "rsr.m0", 190 /* xt_iclass_rsr.m0 */,
11632 Opcode_rsr_m0_encode_fns, 0, 0 },
11633 { "wsr.m0", 191 /* xt_iclass_wsr.m0 */,
11635 Opcode_wsr_m0_encode_fns, 0, 0 },
11636 { "xsr.m0", 192 /* xt_iclass_xsr.m0 */,
11638 Opcode_xsr_m0_encode_fns, 0, 0 },
11639 { "rsr.m1", 193 /* xt_iclass_rsr.m1 */,
11641 Opcode_rsr_m1_encode_fns, 0, 0 },
11642 { "wsr.m1", 194 /* xt_iclass_wsr.m1 */,
11644 Opcode_wsr_m1_encode_fns, 0, 0 },
11645 { "xsr.m1", 195 /* xt_iclass_xsr.m1 */,
11647 Opcode_xsr_m1_encode_fns, 0, 0 },
11648 { "rsr.m2", 196 /* xt_iclass_rsr.m2 */,
11650 Opcode_rsr_m2_encode_fns, 0, 0 },
11651 { "wsr.m2", 197 /* xt_iclass_wsr.m2 */,
11653 Opcode_wsr_m2_encode_fns, 0, 0 },
11654 { "xsr.m2", 198 /* xt_iclass_xsr.m2 */,
11656 Opcode_xsr_m2_encode_fns, 0, 0 },
11657 { "rsr.m3", 199 /* xt_iclass_rsr.m3 */,
11659 Opcode_rsr_m3_encode_fns, 0, 0 },
11660 { "wsr.m3", 200 /* xt_iclass_wsr.m3 */,
11662 Opcode_wsr_m3_encode_fns, 0, 0 },
11663 { "xsr.m3", 201 /* xt_iclass_xsr.m3 */,
11665 Opcode_xsr_m3_encode_fns, 0, 0 },
11666 { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */,
11668 Opcode_rsr_acclo_encode_fns, 0, 0 },
11669 { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */,
11671 Opcode_wsr_acclo_encode_fns, 0, 0 },
11672 { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */,
11674 Opcode_xsr_acclo_encode_fns, 0, 0 },
11675 { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */,
11677 Opcode_rsr_acchi_encode_fns, 0, 0 },
11678 { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */,
11680 Opcode_wsr_acchi_encode_fns, 0, 0 },
11681 { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */,
11683 Opcode_xsr_acchi_encode_fns, 0, 0 },
11684 { "rfi", 208 /* xt_iclass_rfi */,
11685 XTENSA_OPCODE_IS_JUMP,
11686 Opcode_rfi_encode_fns, 0, 0 },
11687 { "waiti", 209 /* xt_iclass_wait */,
11689 Opcode_waiti_encode_fns, 0, 0 },
11690 { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */,
11692 Opcode_rsr_interrupt_encode_fns, 0, 0 },
11693 { "wsr.intset", 211 /* xt_iclass_wsr.intset */,
11695 Opcode_wsr_intset_encode_fns, 0, 0 },
11696 { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */,
11698 Opcode_wsr_intclear_encode_fns, 0, 0 },
11699 { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */,
11701 Opcode_rsr_intenable_encode_fns, 0, 0 },
11702 { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */,
11704 Opcode_wsr_intenable_encode_fns, 0, 0 },
11705 { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */,
11707 Opcode_xsr_intenable_encode_fns, 0, 0 },
11708 { "break", 216 /* xt_iclass_break */,
11710 Opcode_break_encode_fns, 0, 0 },
11711 { "break.n", 217 /* xt_iclass_break.n */,
11713 Opcode_break_n_encode_fns, 0, 0 },
11714 { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */,
11716 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
11717 { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */,
11719 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
11720 { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */,
11722 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
11723 { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */,
11725 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
11726 { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */,
11728 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
11729 { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */,
11731 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
11732 { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */,
11734 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
11735 { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */,
11737 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
11738 { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */,
11740 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
11741 { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */,
11743 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
11744 { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */,
11746 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
11747 { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */,
11749 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
11750 { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */,
11752 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
11753 { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */,
11755 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
11756 { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */,
11758 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
11759 { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */,
11761 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
11762 { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */,
11764 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
11765 { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */,
11767 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
11768 { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */,
11770 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
11771 { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */,
11773 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
11774 { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */,
11776 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
11777 { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */,
11779 Opcode_rsr_debugcause_encode_fns, 0, 0 },
11780 { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */,
11782 Opcode_wsr_debugcause_encode_fns, 0, 0 },
11783 { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */,
11785 Opcode_xsr_debugcause_encode_fns, 0, 0 },
11786 { "rsr.icount", 242 /* xt_iclass_rsr.icount */,
11788 Opcode_rsr_icount_encode_fns, 0, 0 },
11789 { "wsr.icount", 243 /* xt_iclass_wsr.icount */,
11791 Opcode_wsr_icount_encode_fns, 0, 0 },
11792 { "xsr.icount", 244 /* xt_iclass_xsr.icount */,
11794 Opcode_xsr_icount_encode_fns, 0, 0 },
11795 { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */,
11797 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
11798 { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */,
11800 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
11801 { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */,
11803 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
11804 { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */,
11806 Opcode_rsr_ddr_encode_fns, 0, 0 },
11807 { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */,
11809 Opcode_wsr_ddr_encode_fns, 0, 0 },
11810 { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */,
11812 Opcode_xsr_ddr_encode_fns, 0, 0 },
11813 { "rfdo", 251 /* xt_iclass_rfdo */,
11814 XTENSA_OPCODE_IS_JUMP,
11815 Opcode_rfdo_encode_fns, 0, 0 },
11816 { "rfdd", 252 /* xt_iclass_rfdd */,
11817 XTENSA_OPCODE_IS_JUMP,
11818 Opcode_rfdd_encode_fns, 0, 0 },
11819 { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */,
11821 Opcode_wsr_mmid_encode_fns, 0, 0 },
11822 { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */,
11824 Opcode_rsr_ccount_encode_fns, 0, 0 },
11825 { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */,
11827 Opcode_wsr_ccount_encode_fns, 0, 0 },
11828 { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */,
11830 Opcode_xsr_ccount_encode_fns, 0, 0 },
11831 { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */,
11833 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
11834 { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */,
11836 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
11837 { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */,
11839 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
11840 { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */,
11842 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
11843 { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */,
11845 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
11846 { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */,
11848 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
11849 { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */,
11851 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
11852 { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */,
11854 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
11855 { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */,
11857 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
11858 { "ipf", 266 /* xt_iclass_icache */,
11860 Opcode_ipf_encode_fns, 0, 0 },
11861 { "ihi", 266 /* xt_iclass_icache */,
11863 Opcode_ihi_encode_fns, 0, 0 },
11864 { "ipfl", 267 /* xt_iclass_icache_lock */,
11866 Opcode_ipfl_encode_fns, 0, 0 },
11867 { "ihu", 267 /* xt_iclass_icache_lock */,
11869 Opcode_ihu_encode_fns, 0, 0 },
11870 { "iiu", 267 /* xt_iclass_icache_lock */,
11872 Opcode_iiu_encode_fns, 0, 0 },
11873 { "iii", 268 /* xt_iclass_icache_inv */,
11875 Opcode_iii_encode_fns, 0, 0 },
11876 { "lict", 269 /* xt_iclass_licx */,
11878 Opcode_lict_encode_fns, 0, 0 },
11879 { "licw", 269 /* xt_iclass_licx */,
11881 Opcode_licw_encode_fns, 0, 0 },
11882 { "sict", 270 /* xt_iclass_sicx */,
11884 Opcode_sict_encode_fns, 0, 0 },
11885 { "sicw", 270 /* xt_iclass_sicx */,
11887 Opcode_sicw_encode_fns, 0, 0 },
11888 { "dhwb", 271 /* xt_iclass_dcache */,
11890 Opcode_dhwb_encode_fns, 0, 0 },
11891 { "dhwbi", 271 /* xt_iclass_dcache */,
11893 Opcode_dhwbi_encode_fns, 0, 0 },
11894 { "diwb", 272 /* xt_iclass_dcache_ind */,
11896 Opcode_diwb_encode_fns, 0, 0 },
11897 { "diwbi", 272 /* xt_iclass_dcache_ind */,
11899 Opcode_diwbi_encode_fns, 0, 0 },
11900 { "dhi", 273 /* xt_iclass_dcache_inv */,
11902 Opcode_dhi_encode_fns, 0, 0 },
11903 { "dii", 273 /* xt_iclass_dcache_inv */,
11905 Opcode_dii_encode_fns, 0, 0 },
11906 { "dpfr", 274 /* xt_iclass_dpf */,
11908 Opcode_dpfr_encode_fns, 0, 0 },
11909 { "dpfw", 274 /* xt_iclass_dpf */,
11911 Opcode_dpfw_encode_fns, 0, 0 },
11912 { "dpfro", 274 /* xt_iclass_dpf */,
11914 Opcode_dpfro_encode_fns, 0, 0 },
11915 { "dpfwo", 274 /* xt_iclass_dpf */,
11917 Opcode_dpfwo_encode_fns, 0, 0 },
11918 { "dpfl", 275 /* xt_iclass_dcache_lock */,
11920 Opcode_dpfl_encode_fns, 0, 0 },
11921 { "dhu", 275 /* xt_iclass_dcache_lock */,
11923 Opcode_dhu_encode_fns, 0, 0 },
11924 { "diu", 275 /* xt_iclass_dcache_lock */,
11926 Opcode_diu_encode_fns, 0, 0 },
11927 { "sdct", 276 /* xt_iclass_sdct */,
11929 Opcode_sdct_encode_fns, 0, 0 },
11930 { "ldct", 277 /* xt_iclass_ldct */,
11932 Opcode_ldct_encode_fns, 0, 0 },
11933 { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */,
11935 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
11936 { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */,
11938 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
11939 { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */,
11941 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
11942 { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */,
11944 Opcode_rsr_rasid_encode_fns, 0, 0 },
11945 { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */,
11947 Opcode_wsr_rasid_encode_fns, 0, 0 },
11948 { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */,
11950 Opcode_xsr_rasid_encode_fns, 0, 0 },
11951 { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */,
11953 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
11954 { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */,
11956 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
11957 { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */,
11959 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
11960 { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */,
11962 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
11963 { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */,
11965 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
11966 { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */,
11968 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
11969 { "idtlb", 290 /* xt_iclass_idtlb */,
11971 Opcode_idtlb_encode_fns, 0, 0 },
11972 { "pdtlb", 291 /* xt_iclass_rdtlb */,
11974 Opcode_pdtlb_encode_fns, 0, 0 },
11975 { "rdtlb0", 291 /* xt_iclass_rdtlb */,
11977 Opcode_rdtlb0_encode_fns, 0, 0 },
11978 { "rdtlb1", 291 /* xt_iclass_rdtlb */,
11980 Opcode_rdtlb1_encode_fns, 0, 0 },
11981 { "wdtlb", 292 /* xt_iclass_wdtlb */,
11983 Opcode_wdtlb_encode_fns, 0, 0 },
11984 { "iitlb", 293 /* xt_iclass_iitlb */,
11986 Opcode_iitlb_encode_fns, 0, 0 },
11987 { "pitlb", 294 /* xt_iclass_ritlb */,
11989 Opcode_pitlb_encode_fns, 0, 0 },
11990 { "ritlb0", 294 /* xt_iclass_ritlb */,
11992 Opcode_ritlb0_encode_fns, 0, 0 },
11993 { "ritlb1", 294 /* xt_iclass_ritlb */,
11995 Opcode_ritlb1_encode_fns, 0, 0 },
11996 { "witlb", 295 /* xt_iclass_witlb */,
11998 Opcode_witlb_encode_fns, 0, 0 },
11999 { "ldpte", 296 /* xt_iclass_ldpte */,
12001 Opcode_ldpte_encode_fns, 0, 0 },
12002 { "hwwitlba", 297 /* xt_iclass_hwwitlba */,
12003 XTENSA_OPCODE_IS_BRANCH,
12004 Opcode_hwwitlba_encode_fns, 0, 0 },
12005 { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */,
12007 Opcode_hwwdtlba_encode_fns, 0, 0 },
12008 { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */,
12010 Opcode_rsr_cpenable_encode_fns, 0, 0 },
12011 { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */,
12013 Opcode_wsr_cpenable_encode_fns, 0, 0 },
12014 { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */,
12016 Opcode_xsr_cpenable_encode_fns, 0, 0 },
12017 { "clamps", 302 /* xt_iclass_clamp */,
12019 Opcode_clamps_encode_fns, 0, 0 },
12020 { "min", 303 /* xt_iclass_minmax */,
12022 Opcode_min_encode_fns, 0, 0 },
12023 { "max", 303 /* xt_iclass_minmax */,
12025 Opcode_max_encode_fns, 0, 0 },
12026 { "minu", 303 /* xt_iclass_minmax */,
12028 Opcode_minu_encode_fns, 0, 0 },
12029 { "maxu", 303 /* xt_iclass_minmax */,
12031 Opcode_maxu_encode_fns, 0, 0 },
12032 { "nsa", 304 /* xt_iclass_nsa */,
12034 Opcode_nsa_encode_fns, 0, 0 },
12035 { "nsau", 304 /* xt_iclass_nsa */,
12037 Opcode_nsau_encode_fns, 0, 0 },
12038 { "sext", 305 /* xt_iclass_sx */,
12040 Opcode_sext_encode_fns, 0, 0 },
12041 { "l32ai", 306 /* xt_iclass_l32ai */,
12043 Opcode_l32ai_encode_fns, 0, 0 },
12044 { "s32ri", 307 /* xt_iclass_s32ri */,
12046 Opcode_s32ri_encode_fns, 0, 0 },
12047 { "s32c1i", 308 /* xt_iclass_s32c1i */,
12049 Opcode_s32c1i_encode_fns, 0, 0 },
12050 { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */,
12052 Opcode_rsr_scompare1_encode_fns, 0, 0 },
12053 { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */,
12055 Opcode_wsr_scompare1_encode_fns, 0, 0 },
12056 { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */,
12058 Opcode_xsr_scompare1_encode_fns, 0, 0 },
12059 { "quou", 312 /* xt_iclass_div */,
12061 Opcode_quou_encode_fns, 0, 0 },
12062 { "quos", 312 /* xt_iclass_div */,
12064 Opcode_quos_encode_fns, 0, 0 },
12065 { "remu", 312 /* xt_iclass_div */,
12067 Opcode_remu_encode_fns, 0, 0 },
12068 { "rems", 312 /* xt_iclass_div */,
12070 Opcode_rems_encode_fns, 0, 0 },
12071 { "mull", 313 /* xt_mul32 */,
12073 Opcode_mull_encode_fns, 0, 0 },
12074 { "rur.expstate", 314 /* rur_expstate */,
12076 Opcode_rur_expstate_encode_fns, 0, 0 },
12077 { "wur.expstate", 315 /* wur_expstate */,
12079 Opcode_wur_expstate_encode_fns, 0, 0 },
12080 { "read_impwire", 316 /* iclass_READ_IMPWIRE */,
12082 Opcode_read_impwire_encode_fns, 0, 0 },
12083 { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */,
12085 Opcode_setb_expstate_encode_fns, 0, 0 },
12086 { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */,
12088 Opcode_clrb_expstate_encode_fns, 0, 0 },
12089 { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */,
12091 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
12095 /* Slot-specific opcode decode functions. */
12097 static int
12098 Slot_inst_decode (const xtensa_insnbuf insn)
12100 switch (Field_op0_Slot_inst_get (insn))
12102 case 0:
12103 switch (Field_op1_Slot_inst_get (insn))
12105 case 0:
12106 switch (Field_op2_Slot_inst_get (insn))
12108 case 0:
12109 switch (Field_r_Slot_inst_get (insn))
12111 case 0:
12112 switch (Field_m_Slot_inst_get (insn))
12114 case 0:
12115 if (Field_s_Slot_inst_get (insn) == 0 &&
12116 Field_n_Slot_inst_get (insn) == 0)
12117 return 79; /* ill */
12118 break;
12119 case 2:
12120 switch (Field_n_Slot_inst_get (insn))
12122 case 0:
12123 return 98; /* ret */
12124 case 1:
12125 return 14; /* retw */
12126 case 2:
12127 return 81; /* jx */
12129 break;
12130 case 3:
12131 switch (Field_n_Slot_inst_get (insn))
12133 case 0:
12134 return 77; /* callx0 */
12135 case 1:
12136 return 10; /* callx4 */
12137 case 2:
12138 return 9; /* callx8 */
12139 case 3:
12140 return 8; /* callx12 */
12142 break;
12144 break;
12145 case 1:
12146 return 12; /* movsp */
12147 case 2:
12148 if (Field_s_Slot_inst_get (insn) == 0)
12150 switch (Field_t_Slot_inst_get (insn))
12152 case 0:
12153 return 116; /* isync */
12154 case 1:
12155 return 117; /* rsync */
12156 case 2:
12157 return 118; /* esync */
12158 case 3:
12159 return 119; /* dsync */
12160 case 8:
12161 return 0; /* excw */
12162 case 12:
12163 return 114; /* memw */
12164 case 13:
12165 return 115; /* extw */
12166 case 15:
12167 return 97; /* nop */
12170 break;
12171 case 3:
12172 switch (Field_t_Slot_inst_get (insn))
12174 case 0:
12175 switch (Field_s_Slot_inst_get (insn))
12177 case 0:
12178 return 1; /* rfe */
12179 case 2:
12180 return 2; /* rfde */
12181 case 4:
12182 return 16; /* rfwo */
12183 case 5:
12184 return 17; /* rfwu */
12186 break;
12187 case 1:
12188 return 310; /* rfi */
12190 break;
12191 case 4:
12192 return 318; /* break */
12193 case 5:
12194 switch (Field_s_Slot_inst_get (insn))
12196 case 0:
12197 if (Field_t_Slot_inst_get (insn) == 0)
12198 return 3; /* syscall */
12199 break;
12200 case 1:
12201 if (Field_t_Slot_inst_get (insn) == 0)
12202 return 4; /* simcall */
12203 break;
12205 break;
12206 case 6:
12207 return 120; /* rsil */
12208 case 7:
12209 if (Field_t_Slot_inst_get (insn) == 0)
12210 return 311; /* waiti */
12211 break;
12213 break;
12214 case 1:
12215 return 49; /* and */
12216 case 2:
12217 return 50; /* or */
12218 case 3:
12219 return 51; /* xor */
12220 case 4:
12221 switch (Field_r_Slot_inst_get (insn))
12223 case 0:
12224 if (Field_t_Slot_inst_get (insn) == 0)
12225 return 102; /* ssr */
12226 break;
12227 case 1:
12228 if (Field_t_Slot_inst_get (insn) == 0)
12229 return 103; /* ssl */
12230 break;
12231 case 2:
12232 if (Field_t_Slot_inst_get (insn) == 0)
12233 return 104; /* ssa8l */
12234 break;
12235 case 3:
12236 if (Field_t_Slot_inst_get (insn) == 0)
12237 return 105; /* ssa8b */
12238 break;
12239 case 4:
12240 if (Field_thi3_Slot_inst_get (insn) == 0)
12241 return 106; /* ssai */
12242 break;
12243 case 8:
12244 if (Field_s_Slot_inst_get (insn) == 0)
12245 return 13; /* rotw */
12246 break;
12247 case 14:
12248 return 426; /* nsa */
12249 case 15:
12250 return 427; /* nsau */
12252 break;
12253 case 5:
12254 switch (Field_r_Slot_inst_get (insn))
12256 case 1:
12257 return 416; /* hwwitlba */
12258 case 3:
12259 return 412; /* ritlb0 */
12260 case 4:
12261 if (Field_t_Slot_inst_get (insn) == 0)
12262 return 410; /* iitlb */
12263 break;
12264 case 5:
12265 return 411; /* pitlb */
12266 case 6:
12267 return 414; /* witlb */
12268 case 7:
12269 return 413; /* ritlb1 */
12270 case 9:
12271 return 417; /* hwwdtlba */
12272 case 11:
12273 return 407; /* rdtlb0 */
12274 case 12:
12275 if (Field_t_Slot_inst_get (insn) == 0)
12276 return 405; /* idtlb */
12277 break;
12278 case 13:
12279 return 406; /* pdtlb */
12280 case 14:
12281 return 409; /* wdtlb */
12282 case 15:
12283 return 408; /* rdtlb1 */
12285 break;
12286 case 6:
12287 switch (Field_s_Slot_inst_get (insn))
12289 case 0:
12290 return 95; /* neg */
12291 case 1:
12292 return 96; /* abs */
12294 break;
12295 case 8:
12296 return 41; /* add */
12297 case 9:
12298 return 43; /* addx2 */
12299 case 10:
12300 return 44; /* addx4 */
12301 case 11:
12302 return 45; /* addx8 */
12303 case 12:
12304 return 42; /* sub */
12305 case 13:
12306 return 46; /* subx2 */
12307 case 14:
12308 return 47; /* subx4 */
12309 case 15:
12310 return 48; /* subx8 */
12312 break;
12313 case 1:
12314 switch (Field_op2_Slot_inst_get (insn))
12316 case 0:
12317 case 1:
12318 return 111; /* slli */
12319 case 2:
12320 case 3:
12321 return 112; /* srai */
12322 case 4:
12323 return 113; /* srli */
12324 case 6:
12325 switch (Field_sr_Slot_inst_get (insn))
12327 case 0:
12328 return 129; /* xsr.lbeg */
12329 case 1:
12330 return 123; /* xsr.lend */
12331 case 2:
12332 return 126; /* xsr.lcount */
12333 case 3:
12334 return 132; /* xsr.sar */
12335 case 5:
12336 return 135; /* xsr.litbase */
12337 case 12:
12338 return 434; /* xsr.scompare1 */
12339 case 16:
12340 return 306; /* xsr.acclo */
12341 case 17:
12342 return 309; /* xsr.acchi */
12343 case 32:
12344 return 294; /* xsr.m0 */
12345 case 33:
12346 return 297; /* xsr.m1 */
12347 case 34:
12348 return 300; /* xsr.m2 */
12349 case 35:
12350 return 303; /* xsr.m3 */
12351 case 72:
12352 return 22; /* xsr.windowbase */
12353 case 73:
12354 return 25; /* xsr.windowstart */
12355 case 83:
12356 return 395; /* xsr.ptevaddr */
12357 case 90:
12358 return 398; /* xsr.rasid */
12359 case 91:
12360 return 401; /* xsr.itlbcfg */
12361 case 92:
12362 return 404; /* xsr.dtlbcfg */
12363 case 96:
12364 return 340; /* xsr.ibreakenable */
12365 case 104:
12366 return 352; /* xsr.ddr */
12367 case 128:
12368 return 334; /* xsr.ibreaka0 */
12369 case 129:
12370 return 337; /* xsr.ibreaka1 */
12371 case 144:
12372 return 322; /* xsr.dbreaka0 */
12373 case 145:
12374 return 328; /* xsr.dbreaka1 */
12375 case 160:
12376 return 325; /* xsr.dbreakc0 */
12377 case 161:
12378 return 331; /* xsr.dbreakc1 */
12379 case 177:
12380 return 143; /* xsr.epc1 */
12381 case 178:
12382 return 149; /* xsr.epc2 */
12383 case 179:
12384 return 155; /* xsr.epc3 */
12385 case 180:
12386 return 161; /* xsr.epc4 */
12387 case 181:
12388 return 167; /* xsr.epc5 */
12389 case 182:
12390 return 173; /* xsr.epc6 */
12391 case 183:
12392 return 179; /* xsr.epc7 */
12393 case 192:
12394 return 206; /* xsr.depc */
12395 case 194:
12396 return 185; /* xsr.eps2 */
12397 case 195:
12398 return 188; /* xsr.eps3 */
12399 case 196:
12400 return 191; /* xsr.eps4 */
12401 case 197:
12402 return 194; /* xsr.eps5 */
12403 case 198:
12404 return 197; /* xsr.eps6 */
12405 case 199:
12406 return 200; /* xsr.eps7 */
12407 case 209:
12408 return 146; /* xsr.excsave1 */
12409 case 210:
12410 return 152; /* xsr.excsave2 */
12411 case 211:
12412 return 158; /* xsr.excsave3 */
12413 case 212:
12414 return 164; /* xsr.excsave4 */
12415 case 213:
12416 return 170; /* xsr.excsave5 */
12417 case 214:
12418 return 176; /* xsr.excsave6 */
12419 case 215:
12420 return 182; /* xsr.excsave7 */
12421 case 224:
12422 return 420; /* xsr.cpenable */
12423 case 228:
12424 return 317; /* xsr.intenable */
12425 case 230:
12426 return 140; /* xsr.ps */
12427 case 231:
12428 return 219; /* xsr.vecbase */
12429 case 232:
12430 return 209; /* xsr.exccause */
12431 case 233:
12432 return 343; /* xsr.debugcause */
12433 case 234:
12434 return 358; /* xsr.ccount */
12435 case 236:
12436 return 346; /* xsr.icount */
12437 case 237:
12438 return 349; /* xsr.icountlevel */
12439 case 238:
12440 return 203; /* xsr.excvaddr */
12441 case 240:
12442 return 361; /* xsr.ccompare0 */
12443 case 241:
12444 return 364; /* xsr.ccompare1 */
12445 case 242:
12446 return 367; /* xsr.ccompare2 */
12447 case 244:
12448 return 212; /* xsr.misc0 */
12449 case 245:
12450 return 215; /* xsr.misc1 */
12452 break;
12453 case 8:
12454 return 108; /* src */
12455 case 9:
12456 if (Field_s_Slot_inst_get (insn) == 0)
12457 return 109; /* srl */
12458 break;
12459 case 10:
12460 if (Field_t_Slot_inst_get (insn) == 0)
12461 return 107; /* sll */
12462 break;
12463 case 11:
12464 if (Field_s_Slot_inst_get (insn) == 0)
12465 return 110; /* sra */
12466 break;
12467 case 12:
12468 return 290; /* mul16u */
12469 case 13:
12470 return 291; /* mul16s */
12471 case 15:
12472 switch (Field_r_Slot_inst_get (insn))
12474 case 0:
12475 return 374; /* lict */
12476 case 1:
12477 return 376; /* sict */
12478 case 2:
12479 return 375; /* licw */
12480 case 3:
12481 return 377; /* sicw */
12482 case 8:
12483 return 392; /* ldct */
12484 case 9:
12485 return 391; /* sdct */
12486 case 14:
12487 if (Field_t_Slot_inst_get (insn) == 0)
12488 return 353; /* rfdo */
12489 if (Field_t_Slot_inst_get (insn) == 1)
12490 return 354; /* rfdd */
12491 break;
12492 case 15:
12493 return 415; /* ldpte */
12495 break;
12497 break;
12498 case 2:
12499 switch (Field_op2_Slot_inst_get (insn))
12501 case 8:
12502 return 439; /* mull */
12503 case 12:
12504 return 435; /* quou */
12505 case 13:
12506 return 436; /* quos */
12507 case 14:
12508 return 437; /* remu */
12509 case 15:
12510 return 438; /* rems */
12512 break;
12513 case 3:
12514 switch (Field_op2_Slot_inst_get (insn))
12516 case 0:
12517 switch (Field_sr_Slot_inst_get (insn))
12519 case 0:
12520 return 127; /* rsr.lbeg */
12521 case 1:
12522 return 121; /* rsr.lend */
12523 case 2:
12524 return 124; /* rsr.lcount */
12525 case 3:
12526 return 130; /* rsr.sar */
12527 case 5:
12528 return 133; /* rsr.litbase */
12529 case 12:
12530 return 432; /* rsr.scompare1 */
12531 case 16:
12532 return 304; /* rsr.acclo */
12533 case 17:
12534 return 307; /* rsr.acchi */
12535 case 32:
12536 return 292; /* rsr.m0 */
12537 case 33:
12538 return 295; /* rsr.m1 */
12539 case 34:
12540 return 298; /* rsr.m2 */
12541 case 35:
12542 return 301; /* rsr.m3 */
12543 case 72:
12544 return 20; /* rsr.windowbase */
12545 case 73:
12546 return 23; /* rsr.windowstart */
12547 case 83:
12548 return 394; /* rsr.ptevaddr */
12549 case 90:
12550 return 396; /* rsr.rasid */
12551 case 91:
12552 return 399; /* rsr.itlbcfg */
12553 case 92:
12554 return 402; /* rsr.dtlbcfg */
12555 case 96:
12556 return 338; /* rsr.ibreakenable */
12557 case 104:
12558 return 350; /* rsr.ddr */
12559 case 128:
12560 return 332; /* rsr.ibreaka0 */
12561 case 129:
12562 return 335; /* rsr.ibreaka1 */
12563 case 144:
12564 return 320; /* rsr.dbreaka0 */
12565 case 145:
12566 return 326; /* rsr.dbreaka1 */
12567 case 160:
12568 return 323; /* rsr.dbreakc0 */
12569 case 161:
12570 return 329; /* rsr.dbreakc1 */
12571 case 176:
12572 return 136; /* rsr.176 */
12573 case 177:
12574 return 141; /* rsr.epc1 */
12575 case 178:
12576 return 147; /* rsr.epc2 */
12577 case 179:
12578 return 153; /* rsr.epc3 */
12579 case 180:
12580 return 159; /* rsr.epc4 */
12581 case 181:
12582 return 165; /* rsr.epc5 */
12583 case 182:
12584 return 171; /* rsr.epc6 */
12585 case 183:
12586 return 177; /* rsr.epc7 */
12587 case 192:
12588 return 204; /* rsr.depc */
12589 case 194:
12590 return 183; /* rsr.eps2 */
12591 case 195:
12592 return 186; /* rsr.eps3 */
12593 case 196:
12594 return 189; /* rsr.eps4 */
12595 case 197:
12596 return 192; /* rsr.eps5 */
12597 case 198:
12598 return 195; /* rsr.eps6 */
12599 case 199:
12600 return 198; /* rsr.eps7 */
12601 case 208:
12602 return 137; /* rsr.208 */
12603 case 209:
12604 return 144; /* rsr.excsave1 */
12605 case 210:
12606 return 150; /* rsr.excsave2 */
12607 case 211:
12608 return 156; /* rsr.excsave3 */
12609 case 212:
12610 return 162; /* rsr.excsave4 */
12611 case 213:
12612 return 168; /* rsr.excsave5 */
12613 case 214:
12614 return 174; /* rsr.excsave6 */
12615 case 215:
12616 return 180; /* rsr.excsave7 */
12617 case 224:
12618 return 418; /* rsr.cpenable */
12619 case 226:
12620 return 312; /* rsr.interrupt */
12621 case 228:
12622 return 315; /* rsr.intenable */
12623 case 230:
12624 return 138; /* rsr.ps */
12625 case 231:
12626 return 217; /* rsr.vecbase */
12627 case 232:
12628 return 207; /* rsr.exccause */
12629 case 233:
12630 return 341; /* rsr.debugcause */
12631 case 234:
12632 return 356; /* rsr.ccount */
12633 case 235:
12634 return 216; /* rsr.prid */
12635 case 236:
12636 return 344; /* rsr.icount */
12637 case 237:
12638 return 347; /* rsr.icountlevel */
12639 case 238:
12640 return 201; /* rsr.excvaddr */
12641 case 240:
12642 return 359; /* rsr.ccompare0 */
12643 case 241:
12644 return 362; /* rsr.ccompare1 */
12645 case 242:
12646 return 365; /* rsr.ccompare2 */
12647 case 244:
12648 return 210; /* rsr.misc0 */
12649 case 245:
12650 return 213; /* rsr.misc1 */
12652 break;
12653 case 1:
12654 switch (Field_sr_Slot_inst_get (insn))
12656 case 0:
12657 return 128; /* wsr.lbeg */
12658 case 1:
12659 return 122; /* wsr.lend */
12660 case 2:
12661 return 125; /* wsr.lcount */
12662 case 3:
12663 return 131; /* wsr.sar */
12664 case 5:
12665 return 134; /* wsr.litbase */
12666 case 12:
12667 return 433; /* wsr.scompare1 */
12668 case 16:
12669 return 305; /* wsr.acclo */
12670 case 17:
12671 return 308; /* wsr.acchi */
12672 case 32:
12673 return 293; /* wsr.m0 */
12674 case 33:
12675 return 296; /* wsr.m1 */
12676 case 34:
12677 return 299; /* wsr.m2 */
12678 case 35:
12679 return 302; /* wsr.m3 */
12680 case 72:
12681 return 21; /* wsr.windowbase */
12682 case 73:
12683 return 24; /* wsr.windowstart */
12684 case 83:
12685 return 393; /* wsr.ptevaddr */
12686 case 89:
12687 return 355; /* wsr.mmid */
12688 case 90:
12689 return 397; /* wsr.rasid */
12690 case 91:
12691 return 400; /* wsr.itlbcfg */
12692 case 92:
12693 return 403; /* wsr.dtlbcfg */
12694 case 96:
12695 return 339; /* wsr.ibreakenable */
12696 case 104:
12697 return 351; /* wsr.ddr */
12698 case 128:
12699 return 333; /* wsr.ibreaka0 */
12700 case 129:
12701 return 336; /* wsr.ibreaka1 */
12702 case 144:
12703 return 321; /* wsr.dbreaka0 */
12704 case 145:
12705 return 327; /* wsr.dbreaka1 */
12706 case 160:
12707 return 324; /* wsr.dbreakc0 */
12708 case 161:
12709 return 330; /* wsr.dbreakc1 */
12710 case 177:
12711 return 142; /* wsr.epc1 */
12712 case 178:
12713 return 148; /* wsr.epc2 */
12714 case 179:
12715 return 154; /* wsr.epc3 */
12716 case 180:
12717 return 160; /* wsr.epc4 */
12718 case 181:
12719 return 166; /* wsr.epc5 */
12720 case 182:
12721 return 172; /* wsr.epc6 */
12722 case 183:
12723 return 178; /* wsr.epc7 */
12724 case 192:
12725 return 205; /* wsr.depc */
12726 case 194:
12727 return 184; /* wsr.eps2 */
12728 case 195:
12729 return 187; /* wsr.eps3 */
12730 case 196:
12731 return 190; /* wsr.eps4 */
12732 case 197:
12733 return 193; /* wsr.eps5 */
12734 case 198:
12735 return 196; /* wsr.eps6 */
12736 case 199:
12737 return 199; /* wsr.eps7 */
12738 case 209:
12739 return 145; /* wsr.excsave1 */
12740 case 210:
12741 return 151; /* wsr.excsave2 */
12742 case 211:
12743 return 157; /* wsr.excsave3 */
12744 case 212:
12745 return 163; /* wsr.excsave4 */
12746 case 213:
12747 return 169; /* wsr.excsave5 */
12748 case 214:
12749 return 175; /* wsr.excsave6 */
12750 case 215:
12751 return 181; /* wsr.excsave7 */
12752 case 224:
12753 return 419; /* wsr.cpenable */
12754 case 226:
12755 return 313; /* wsr.intset */
12756 case 227:
12757 return 314; /* wsr.intclear */
12758 case 228:
12759 return 316; /* wsr.intenable */
12760 case 230:
12761 return 139; /* wsr.ps */
12762 case 231:
12763 return 218; /* wsr.vecbase */
12764 case 232:
12765 return 208; /* wsr.exccause */
12766 case 233:
12767 return 342; /* wsr.debugcause */
12768 case 234:
12769 return 357; /* wsr.ccount */
12770 case 236:
12771 return 345; /* wsr.icount */
12772 case 237:
12773 return 348; /* wsr.icountlevel */
12774 case 238:
12775 return 202; /* wsr.excvaddr */
12776 case 240:
12777 return 360; /* wsr.ccompare0 */
12778 case 241:
12779 return 363; /* wsr.ccompare1 */
12780 case 242:
12781 return 366; /* wsr.ccompare2 */
12782 case 244:
12783 return 211; /* wsr.misc0 */
12784 case 245:
12785 return 214; /* wsr.misc1 */
12787 break;
12788 case 2:
12789 return 428; /* sext */
12790 case 3:
12791 return 421; /* clamps */
12792 case 4:
12793 return 422; /* min */
12794 case 5:
12795 return 423; /* max */
12796 case 6:
12797 return 424; /* minu */
12798 case 7:
12799 return 425; /* maxu */
12800 case 8:
12801 return 91; /* moveqz */
12802 case 9:
12803 return 92; /* movnez */
12804 case 10:
12805 return 93; /* movltz */
12806 case 11:
12807 return 94; /* movgez */
12808 case 14:
12809 switch (Field_st_Slot_inst_get (insn))
12811 case 230:
12812 return 440; /* rur.expstate */
12813 case 231:
12814 return 37; /* rur.threadptr */
12816 break;
12817 case 15:
12818 switch (Field_sr_Slot_inst_get (insn))
12820 case 230:
12821 return 441; /* wur.expstate */
12822 case 231:
12823 return 38; /* wur.threadptr */
12825 break;
12827 break;
12828 case 4:
12829 case 5:
12830 return 78; /* extui */
12831 case 9:
12832 switch (Field_op2_Slot_inst_get (insn))
12834 case 0:
12835 return 18; /* l32e */
12836 case 4:
12837 return 19; /* s32e */
12839 break;
12841 switch (Field_r_Slot_inst_get (insn))
12843 case 0:
12844 if (Field_s_Slot_inst_get (insn) == 0 &&
12845 Field_op2_Slot_inst_get (insn) == 0 &&
12846 Field_op1_Slot_inst_get (insn) == 14)
12847 return 442; /* read_impwire */
12848 break;
12849 case 1:
12850 if (Field_s3to1_Slot_inst_get (insn) == 0 &&
12851 Field_op2_Slot_inst_get (insn) == 0 &&
12852 Field_op1_Slot_inst_get (insn) == 14)
12853 return 443; /* setb_expstate */
12854 if (Field_s3to1_Slot_inst_get (insn) == 1 &&
12855 Field_op2_Slot_inst_get (insn) == 0 &&
12856 Field_op1_Slot_inst_get (insn) == 14)
12857 return 444; /* clrb_expstate */
12858 break;
12859 case 2:
12860 if (Field_op2_Slot_inst_get (insn) == 0 &&
12861 Field_op1_Slot_inst_get (insn) == 14)
12862 return 445; /* wrmsk_expstate */
12863 break;
12865 break;
12866 case 1:
12867 return 85; /* l32r */
12868 case 2:
12869 switch (Field_r_Slot_inst_get (insn))
12871 case 0:
12872 return 86; /* l8ui */
12873 case 1:
12874 return 82; /* l16ui */
12875 case 2:
12876 return 84; /* l32i */
12877 case 4:
12878 return 101; /* s8i */
12879 case 5:
12880 return 99; /* s16i */
12881 case 6:
12882 return 100; /* s32i */
12883 case 7:
12884 switch (Field_t_Slot_inst_get (insn))
12886 case 0:
12887 return 384; /* dpfr */
12888 case 1:
12889 return 385; /* dpfw */
12890 case 2:
12891 return 386; /* dpfro */
12892 case 3:
12893 return 387; /* dpfwo */
12894 case 4:
12895 return 378; /* dhwb */
12896 case 5:
12897 return 379; /* dhwbi */
12898 case 6:
12899 return 382; /* dhi */
12900 case 7:
12901 return 383; /* dii */
12902 case 8:
12903 switch (Field_op1_Slot_inst_get (insn))
12905 case 0:
12906 return 388; /* dpfl */
12907 case 2:
12908 return 389; /* dhu */
12909 case 3:
12910 return 390; /* diu */
12911 case 4:
12912 return 380; /* diwb */
12913 case 5:
12914 return 381; /* diwbi */
12916 break;
12917 case 12:
12918 return 368; /* ipf */
12919 case 13:
12920 switch (Field_op1_Slot_inst_get (insn))
12922 case 0:
12923 return 370; /* ipfl */
12924 case 2:
12925 return 371; /* ihu */
12926 case 3:
12927 return 372; /* iiu */
12929 break;
12930 case 14:
12931 return 369; /* ihi */
12932 case 15:
12933 return 373; /* iii */
12935 break;
12936 case 9:
12937 return 83; /* l16si */
12938 case 10:
12939 return 90; /* movi */
12940 case 11:
12941 return 429; /* l32ai */
12942 case 12:
12943 return 39; /* addi */
12944 case 13:
12945 return 40; /* addmi */
12946 case 14:
12947 return 431; /* s32c1i */
12948 case 15:
12949 return 430; /* s32ri */
12951 break;
12952 case 4:
12953 switch (Field_op2_Slot_inst_get (insn))
12955 case 0:
12956 switch (Field_op1_Slot_inst_get (insn))
12958 case 8:
12959 if (Field_t3_Slot_inst_get (insn) == 0 &&
12960 Field_tlo_Slot_inst_get (insn) == 0 &&
12961 Field_r3_Slot_inst_get (insn) == 0)
12962 return 281; /* mula.dd.ll.ldinc */
12963 break;
12964 case 9:
12965 if (Field_t3_Slot_inst_get (insn) == 0 &&
12966 Field_tlo_Slot_inst_get (insn) == 0 &&
12967 Field_r3_Slot_inst_get (insn) == 0)
12968 return 283; /* mula.dd.hl.ldinc */
12969 break;
12970 case 10:
12971 if (Field_t3_Slot_inst_get (insn) == 0 &&
12972 Field_tlo_Slot_inst_get (insn) == 0 &&
12973 Field_r3_Slot_inst_get (insn) == 0)
12974 return 285; /* mula.dd.lh.ldinc */
12975 break;
12976 case 11:
12977 if (Field_t3_Slot_inst_get (insn) == 0 &&
12978 Field_tlo_Slot_inst_get (insn) == 0 &&
12979 Field_r3_Slot_inst_get (insn) == 0)
12980 return 287; /* mula.dd.hh.ldinc */
12981 break;
12983 break;
12984 case 1:
12985 switch (Field_op1_Slot_inst_get (insn))
12987 case 8:
12988 if (Field_t3_Slot_inst_get (insn) == 0 &&
12989 Field_tlo_Slot_inst_get (insn) == 0 &&
12990 Field_r3_Slot_inst_get (insn) == 0)
12991 return 280; /* mula.dd.ll.lddec */
12992 break;
12993 case 9:
12994 if (Field_t3_Slot_inst_get (insn) == 0 &&
12995 Field_tlo_Slot_inst_get (insn) == 0 &&
12996 Field_r3_Slot_inst_get (insn) == 0)
12997 return 282; /* mula.dd.hl.lddec */
12998 break;
12999 case 10:
13000 if (Field_t3_Slot_inst_get (insn) == 0 &&
13001 Field_tlo_Slot_inst_get (insn) == 0 &&
13002 Field_r3_Slot_inst_get (insn) == 0)
13003 return 284; /* mula.dd.lh.lddec */
13004 break;
13005 case 11:
13006 if (Field_t3_Slot_inst_get (insn) == 0 &&
13007 Field_tlo_Slot_inst_get (insn) == 0 &&
13008 Field_r3_Slot_inst_get (insn) == 0)
13009 return 286; /* mula.dd.hh.lddec */
13010 break;
13012 break;
13013 case 2:
13014 switch (Field_op1_Slot_inst_get (insn))
13016 case 4:
13017 if (Field_s_Slot_inst_get (insn) == 0 &&
13018 Field_w_Slot_inst_get (insn) == 0 &&
13019 Field_r3_Slot_inst_get (insn) == 0 &&
13020 Field_t3_Slot_inst_get (insn) == 0 &&
13021 Field_tlo_Slot_inst_get (insn) == 0)
13022 return 236; /* mul.dd.ll */
13023 break;
13024 case 5:
13025 if (Field_s_Slot_inst_get (insn) == 0 &&
13026 Field_w_Slot_inst_get (insn) == 0 &&
13027 Field_r3_Slot_inst_get (insn) == 0 &&
13028 Field_t3_Slot_inst_get (insn) == 0 &&
13029 Field_tlo_Slot_inst_get (insn) == 0)
13030 return 237; /* mul.dd.hl */
13031 break;
13032 case 6:
13033 if (Field_s_Slot_inst_get (insn) == 0 &&
13034 Field_w_Slot_inst_get (insn) == 0 &&
13035 Field_r3_Slot_inst_get (insn) == 0 &&
13036 Field_t3_Slot_inst_get (insn) == 0 &&
13037 Field_tlo_Slot_inst_get (insn) == 0)
13038 return 238; /* mul.dd.lh */
13039 break;
13040 case 7:
13041 if (Field_s_Slot_inst_get (insn) == 0 &&
13042 Field_w_Slot_inst_get (insn) == 0 &&
13043 Field_r3_Slot_inst_get (insn) == 0 &&
13044 Field_t3_Slot_inst_get (insn) == 0 &&
13045 Field_tlo_Slot_inst_get (insn) == 0)
13046 return 239; /* mul.dd.hh */
13047 break;
13048 case 8:
13049 if (Field_s_Slot_inst_get (insn) == 0 &&
13050 Field_w_Slot_inst_get (insn) == 0 &&
13051 Field_r3_Slot_inst_get (insn) == 0 &&
13052 Field_t3_Slot_inst_get (insn) == 0 &&
13053 Field_tlo_Slot_inst_get (insn) == 0)
13054 return 264; /* mula.dd.ll */
13055 break;
13056 case 9:
13057 if (Field_s_Slot_inst_get (insn) == 0 &&
13058 Field_w_Slot_inst_get (insn) == 0 &&
13059 Field_r3_Slot_inst_get (insn) == 0 &&
13060 Field_t3_Slot_inst_get (insn) == 0 &&
13061 Field_tlo_Slot_inst_get (insn) == 0)
13062 return 265; /* mula.dd.hl */
13063 break;
13064 case 10:
13065 if (Field_s_Slot_inst_get (insn) == 0 &&
13066 Field_w_Slot_inst_get (insn) == 0 &&
13067 Field_r3_Slot_inst_get (insn) == 0 &&
13068 Field_t3_Slot_inst_get (insn) == 0 &&
13069 Field_tlo_Slot_inst_get (insn) == 0)
13070 return 266; /* mula.dd.lh */
13071 break;
13072 case 11:
13073 if (Field_s_Slot_inst_get (insn) == 0 &&
13074 Field_w_Slot_inst_get (insn) == 0 &&
13075 Field_r3_Slot_inst_get (insn) == 0 &&
13076 Field_t3_Slot_inst_get (insn) == 0 &&
13077 Field_tlo_Slot_inst_get (insn) == 0)
13078 return 267; /* mula.dd.hh */
13079 break;
13080 case 12:
13081 if (Field_s_Slot_inst_get (insn) == 0 &&
13082 Field_w_Slot_inst_get (insn) == 0 &&
13083 Field_r3_Slot_inst_get (insn) == 0 &&
13084 Field_t3_Slot_inst_get (insn) == 0 &&
13085 Field_tlo_Slot_inst_get (insn) == 0)
13086 return 268; /* muls.dd.ll */
13087 break;
13088 case 13:
13089 if (Field_s_Slot_inst_get (insn) == 0 &&
13090 Field_w_Slot_inst_get (insn) == 0 &&
13091 Field_r3_Slot_inst_get (insn) == 0 &&
13092 Field_t3_Slot_inst_get (insn) == 0 &&
13093 Field_tlo_Slot_inst_get (insn) == 0)
13094 return 269; /* muls.dd.hl */
13095 break;
13096 case 14:
13097 if (Field_s_Slot_inst_get (insn) == 0 &&
13098 Field_w_Slot_inst_get (insn) == 0 &&
13099 Field_r3_Slot_inst_get (insn) == 0 &&
13100 Field_t3_Slot_inst_get (insn) == 0 &&
13101 Field_tlo_Slot_inst_get (insn) == 0)
13102 return 270; /* muls.dd.lh */
13103 break;
13104 case 15:
13105 if (Field_s_Slot_inst_get (insn) == 0 &&
13106 Field_w_Slot_inst_get (insn) == 0 &&
13107 Field_r3_Slot_inst_get (insn) == 0 &&
13108 Field_t3_Slot_inst_get (insn) == 0 &&
13109 Field_tlo_Slot_inst_get (insn) == 0)
13110 return 271; /* muls.dd.hh */
13111 break;
13113 break;
13114 case 3:
13115 switch (Field_op1_Slot_inst_get (insn))
13117 case 4:
13118 if (Field_r_Slot_inst_get (insn) == 0 &&
13119 Field_t3_Slot_inst_get (insn) == 0 &&
13120 Field_tlo_Slot_inst_get (insn) == 0)
13121 return 228; /* mul.ad.ll */
13122 break;
13123 case 5:
13124 if (Field_r_Slot_inst_get (insn) == 0 &&
13125 Field_t3_Slot_inst_get (insn) == 0 &&
13126 Field_tlo_Slot_inst_get (insn) == 0)
13127 return 229; /* mul.ad.hl */
13128 break;
13129 case 6:
13130 if (Field_r_Slot_inst_get (insn) == 0 &&
13131 Field_t3_Slot_inst_get (insn) == 0 &&
13132 Field_tlo_Slot_inst_get (insn) == 0)
13133 return 230; /* mul.ad.lh */
13134 break;
13135 case 7:
13136 if (Field_r_Slot_inst_get (insn) == 0 &&
13137 Field_t3_Slot_inst_get (insn) == 0 &&
13138 Field_tlo_Slot_inst_get (insn) == 0)
13139 return 231; /* mul.ad.hh */
13140 break;
13141 case 8:
13142 if (Field_r_Slot_inst_get (insn) == 0 &&
13143 Field_t3_Slot_inst_get (insn) == 0 &&
13144 Field_tlo_Slot_inst_get (insn) == 0)
13145 return 248; /* mula.ad.ll */
13146 break;
13147 case 9:
13148 if (Field_r_Slot_inst_get (insn) == 0 &&
13149 Field_t3_Slot_inst_get (insn) == 0 &&
13150 Field_tlo_Slot_inst_get (insn) == 0)
13151 return 249; /* mula.ad.hl */
13152 break;
13153 case 10:
13154 if (Field_r_Slot_inst_get (insn) == 0 &&
13155 Field_t3_Slot_inst_get (insn) == 0 &&
13156 Field_tlo_Slot_inst_get (insn) == 0)
13157 return 250; /* mula.ad.lh */
13158 break;
13159 case 11:
13160 if (Field_r_Slot_inst_get (insn) == 0 &&
13161 Field_t3_Slot_inst_get (insn) == 0 &&
13162 Field_tlo_Slot_inst_get (insn) == 0)
13163 return 251; /* mula.ad.hh */
13164 break;
13165 case 12:
13166 if (Field_r_Slot_inst_get (insn) == 0 &&
13167 Field_t3_Slot_inst_get (insn) == 0 &&
13168 Field_tlo_Slot_inst_get (insn) == 0)
13169 return 252; /* muls.ad.ll */
13170 break;
13171 case 13:
13172 if (Field_r_Slot_inst_get (insn) == 0 &&
13173 Field_t3_Slot_inst_get (insn) == 0 &&
13174 Field_tlo_Slot_inst_get (insn) == 0)
13175 return 253; /* muls.ad.hl */
13176 break;
13177 case 14:
13178 if (Field_r_Slot_inst_get (insn) == 0 &&
13179 Field_t3_Slot_inst_get (insn) == 0 &&
13180 Field_tlo_Slot_inst_get (insn) == 0)
13181 return 254; /* muls.ad.lh */
13182 break;
13183 case 15:
13184 if (Field_r_Slot_inst_get (insn) == 0 &&
13185 Field_t3_Slot_inst_get (insn) == 0 &&
13186 Field_tlo_Slot_inst_get (insn) == 0)
13187 return 255; /* muls.ad.hh */
13188 break;
13190 break;
13191 case 4:
13192 switch (Field_op1_Slot_inst_get (insn))
13194 case 8:
13195 if (Field_r3_Slot_inst_get (insn) == 0)
13196 return 273; /* mula.da.ll.ldinc */
13197 break;
13198 case 9:
13199 if (Field_r3_Slot_inst_get (insn) == 0)
13200 return 275; /* mula.da.hl.ldinc */
13201 break;
13202 case 10:
13203 if (Field_r3_Slot_inst_get (insn) == 0)
13204 return 277; /* mula.da.lh.ldinc */
13205 break;
13206 case 11:
13207 if (Field_r3_Slot_inst_get (insn) == 0)
13208 return 279; /* mula.da.hh.ldinc */
13209 break;
13211 break;
13212 case 5:
13213 switch (Field_op1_Slot_inst_get (insn))
13215 case 8:
13216 if (Field_r3_Slot_inst_get (insn) == 0)
13217 return 272; /* mula.da.ll.lddec */
13218 break;
13219 case 9:
13220 if (Field_r3_Slot_inst_get (insn) == 0)
13221 return 274; /* mula.da.hl.lddec */
13222 break;
13223 case 10:
13224 if (Field_r3_Slot_inst_get (insn) == 0)
13225 return 276; /* mula.da.lh.lddec */
13226 break;
13227 case 11:
13228 if (Field_r3_Slot_inst_get (insn) == 0)
13229 return 278; /* mula.da.hh.lddec */
13230 break;
13232 break;
13233 case 6:
13234 switch (Field_op1_Slot_inst_get (insn))
13236 case 4:
13237 if (Field_s_Slot_inst_get (insn) == 0 &&
13238 Field_w_Slot_inst_get (insn) == 0 &&
13239 Field_r3_Slot_inst_get (insn) == 0)
13240 return 232; /* mul.da.ll */
13241 break;
13242 case 5:
13243 if (Field_s_Slot_inst_get (insn) == 0 &&
13244 Field_w_Slot_inst_get (insn) == 0 &&
13245 Field_r3_Slot_inst_get (insn) == 0)
13246 return 233; /* mul.da.hl */
13247 break;
13248 case 6:
13249 if (Field_s_Slot_inst_get (insn) == 0 &&
13250 Field_w_Slot_inst_get (insn) == 0 &&
13251 Field_r3_Slot_inst_get (insn) == 0)
13252 return 234; /* mul.da.lh */
13253 break;
13254 case 7:
13255 if (Field_s_Slot_inst_get (insn) == 0 &&
13256 Field_w_Slot_inst_get (insn) == 0 &&
13257 Field_r3_Slot_inst_get (insn) == 0)
13258 return 235; /* mul.da.hh */
13259 break;
13260 case 8:
13261 if (Field_s_Slot_inst_get (insn) == 0 &&
13262 Field_w_Slot_inst_get (insn) == 0 &&
13263 Field_r3_Slot_inst_get (insn) == 0)
13264 return 256; /* mula.da.ll */
13265 break;
13266 case 9:
13267 if (Field_s_Slot_inst_get (insn) == 0 &&
13268 Field_w_Slot_inst_get (insn) == 0 &&
13269 Field_r3_Slot_inst_get (insn) == 0)
13270 return 257; /* mula.da.hl */
13271 break;
13272 case 10:
13273 if (Field_s_Slot_inst_get (insn) == 0 &&
13274 Field_w_Slot_inst_get (insn) == 0 &&
13275 Field_r3_Slot_inst_get (insn) == 0)
13276 return 258; /* mula.da.lh */
13277 break;
13278 case 11:
13279 if (Field_s_Slot_inst_get (insn) == 0 &&
13280 Field_w_Slot_inst_get (insn) == 0 &&
13281 Field_r3_Slot_inst_get (insn) == 0)
13282 return 259; /* mula.da.hh */
13283 break;
13284 case 12:
13285 if (Field_s_Slot_inst_get (insn) == 0 &&
13286 Field_w_Slot_inst_get (insn) == 0 &&
13287 Field_r3_Slot_inst_get (insn) == 0)
13288 return 260; /* muls.da.ll */
13289 break;
13290 case 13:
13291 if (Field_s_Slot_inst_get (insn) == 0 &&
13292 Field_w_Slot_inst_get (insn) == 0 &&
13293 Field_r3_Slot_inst_get (insn) == 0)
13294 return 261; /* muls.da.hl */
13295 break;
13296 case 14:
13297 if (Field_s_Slot_inst_get (insn) == 0 &&
13298 Field_w_Slot_inst_get (insn) == 0 &&
13299 Field_r3_Slot_inst_get (insn) == 0)
13300 return 262; /* muls.da.lh */
13301 break;
13302 case 15:
13303 if (Field_s_Slot_inst_get (insn) == 0 &&
13304 Field_w_Slot_inst_get (insn) == 0 &&
13305 Field_r3_Slot_inst_get (insn) == 0)
13306 return 263; /* muls.da.hh */
13307 break;
13309 break;
13310 case 7:
13311 switch (Field_op1_Slot_inst_get (insn))
13313 case 0:
13314 if (Field_r_Slot_inst_get (insn) == 0)
13315 return 224; /* umul.aa.ll */
13316 break;
13317 case 1:
13318 if (Field_r_Slot_inst_get (insn) == 0)
13319 return 225; /* umul.aa.hl */
13320 break;
13321 case 2:
13322 if (Field_r_Slot_inst_get (insn) == 0)
13323 return 226; /* umul.aa.lh */
13324 break;
13325 case 3:
13326 if (Field_r_Slot_inst_get (insn) == 0)
13327 return 227; /* umul.aa.hh */
13328 break;
13329 case 4:
13330 if (Field_r_Slot_inst_get (insn) == 0)
13331 return 220; /* mul.aa.ll */
13332 break;
13333 case 5:
13334 if (Field_r_Slot_inst_get (insn) == 0)
13335 return 221; /* mul.aa.hl */
13336 break;
13337 case 6:
13338 if (Field_r_Slot_inst_get (insn) == 0)
13339 return 222; /* mul.aa.lh */
13340 break;
13341 case 7:
13342 if (Field_r_Slot_inst_get (insn) == 0)
13343 return 223; /* mul.aa.hh */
13344 break;
13345 case 8:
13346 if (Field_r_Slot_inst_get (insn) == 0)
13347 return 240; /* mula.aa.ll */
13348 break;
13349 case 9:
13350 if (Field_r_Slot_inst_get (insn) == 0)
13351 return 241; /* mula.aa.hl */
13352 break;
13353 case 10:
13354 if (Field_r_Slot_inst_get (insn) == 0)
13355 return 242; /* mula.aa.lh */
13356 break;
13357 case 11:
13358 if (Field_r_Slot_inst_get (insn) == 0)
13359 return 243; /* mula.aa.hh */
13360 break;
13361 case 12:
13362 if (Field_r_Slot_inst_get (insn) == 0)
13363 return 244; /* muls.aa.ll */
13364 break;
13365 case 13:
13366 if (Field_r_Slot_inst_get (insn) == 0)
13367 return 245; /* muls.aa.hl */
13368 break;
13369 case 14:
13370 if (Field_r_Slot_inst_get (insn) == 0)
13371 return 246; /* muls.aa.lh */
13372 break;
13373 case 15:
13374 if (Field_r_Slot_inst_get (insn) == 0)
13375 return 247; /* muls.aa.hh */
13376 break;
13378 break;
13379 case 8:
13380 if (Field_op1_Slot_inst_get (insn) == 0 &&
13381 Field_t_Slot_inst_get (insn) == 0 &&
13382 Field_rhi_Slot_inst_get (insn) == 0)
13383 return 289; /* ldinc */
13384 break;
13385 case 9:
13386 if (Field_op1_Slot_inst_get (insn) == 0 &&
13387 Field_t_Slot_inst_get (insn) == 0 &&
13388 Field_rhi_Slot_inst_get (insn) == 0)
13389 return 288; /* lddec */
13390 break;
13392 break;
13393 case 5:
13394 switch (Field_n_Slot_inst_get (insn))
13396 case 0:
13397 return 76; /* call0 */
13398 case 1:
13399 return 7; /* call4 */
13400 case 2:
13401 return 6; /* call8 */
13402 case 3:
13403 return 5; /* call12 */
13405 break;
13406 case 6:
13407 switch (Field_n_Slot_inst_get (insn))
13409 case 0:
13410 return 80; /* j */
13411 case 1:
13412 switch (Field_m_Slot_inst_get (insn))
13414 case 0:
13415 return 72; /* beqz */
13416 case 1:
13417 return 73; /* bnez */
13418 case 2:
13419 return 75; /* bltz */
13420 case 3:
13421 return 74; /* bgez */
13423 break;
13424 case 2:
13425 switch (Field_m_Slot_inst_get (insn))
13427 case 0:
13428 return 52; /* beqi */
13429 case 1:
13430 return 53; /* bnei */
13431 case 2:
13432 return 55; /* blti */
13433 case 3:
13434 return 54; /* bgei */
13436 break;
13437 case 3:
13438 switch (Field_m_Slot_inst_get (insn))
13440 case 0:
13441 return 11; /* entry */
13442 case 1:
13443 switch (Field_r_Slot_inst_get (insn))
13445 case 8:
13446 return 87; /* loop */
13447 case 9:
13448 return 88; /* loopnez */
13449 case 10:
13450 return 89; /* loopgtz */
13452 break;
13453 case 2:
13454 return 59; /* bltui */
13455 case 3:
13456 return 58; /* bgeui */
13458 break;
13460 break;
13461 case 7:
13462 switch (Field_r_Slot_inst_get (insn))
13464 case 0:
13465 return 67; /* bnone */
13466 case 1:
13467 return 60; /* beq */
13468 case 2:
13469 return 63; /* blt */
13470 case 3:
13471 return 65; /* bltu */
13472 case 4:
13473 return 68; /* ball */
13474 case 5:
13475 return 70; /* bbc */
13476 case 6:
13477 case 7:
13478 return 56; /* bbci */
13479 case 8:
13480 return 66; /* bany */
13481 case 9:
13482 return 61; /* bne */
13483 case 10:
13484 return 62; /* bge */
13485 case 11:
13486 return 64; /* bgeu */
13487 case 12:
13488 return 69; /* bnall */
13489 case 13:
13490 return 71; /* bbs */
13491 case 14:
13492 case 15:
13493 return 57; /* bbsi */
13495 break;
13497 return XTENSA_UNDEFINED;
13500 static int
13501 Slot_inst16b_decode (const xtensa_insnbuf insn)
13503 switch (Field_op0_Slot_inst16b_get (insn))
13505 case 12:
13506 switch (Field_i_Slot_inst16b_get (insn))
13508 case 0:
13509 return 33; /* movi.n */
13510 case 1:
13511 switch (Field_z_Slot_inst16b_get (insn))
13513 case 0:
13514 return 28; /* beqz.n */
13515 case 1:
13516 return 29; /* bnez.n */
13518 break;
13520 break;
13521 case 13:
13522 switch (Field_r_Slot_inst16b_get (insn))
13524 case 0:
13525 return 32; /* mov.n */
13526 case 15:
13527 switch (Field_t_Slot_inst16b_get (insn))
13529 case 0:
13530 return 35; /* ret.n */
13531 case 1:
13532 return 15; /* retw.n */
13533 case 2:
13534 return 319; /* break.n */
13535 case 3:
13536 if (Field_s_Slot_inst16b_get (insn) == 0)
13537 return 34; /* nop.n */
13538 break;
13539 case 6:
13540 if (Field_s_Slot_inst16b_get (insn) == 0)
13541 return 30; /* ill.n */
13542 break;
13544 break;
13546 break;
13548 return XTENSA_UNDEFINED;
13551 static int
13552 Slot_inst16a_decode (const xtensa_insnbuf insn)
13554 switch (Field_op0_Slot_inst16a_get (insn))
13556 case 8:
13557 return 31; /* l32i.n */
13558 case 9:
13559 return 36; /* s32i.n */
13560 case 10:
13561 return 26; /* add.n */
13562 case 11:
13563 return 27; /* addi.n */
13565 return XTENSA_UNDEFINED;
13569 /* Instruction slots. */
13571 static void
13572 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
13573 xtensa_insnbuf slotbuf)
13575 slotbuf[0] = (insn[0] & 0xffffff);
13578 static void
13579 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
13580 const xtensa_insnbuf slotbuf)
13582 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
13585 static void
13586 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
13587 xtensa_insnbuf slotbuf)
13589 slotbuf[0] = (insn[0] & 0xffff);
13592 static void
13593 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
13594 const xtensa_insnbuf slotbuf)
13596 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13599 static void
13600 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
13601 xtensa_insnbuf slotbuf)
13603 slotbuf[0] = (insn[0] & 0xffff);
13606 static void
13607 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
13608 const xtensa_insnbuf slotbuf)
13610 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13613 static xtensa_get_field_fn
13614 Slot_inst_get_field_fns[] = {
13615 Field_t_Slot_inst_get,
13616 Field_bbi4_Slot_inst_get,
13617 Field_bbi_Slot_inst_get,
13618 Field_imm12_Slot_inst_get,
13619 Field_imm8_Slot_inst_get,
13620 Field_s_Slot_inst_get,
13621 Field_imm12b_Slot_inst_get,
13622 Field_imm16_Slot_inst_get,
13623 Field_m_Slot_inst_get,
13624 Field_n_Slot_inst_get,
13625 Field_offset_Slot_inst_get,
13626 Field_op0_Slot_inst_get,
13627 Field_op1_Slot_inst_get,
13628 Field_op2_Slot_inst_get,
13629 Field_r_Slot_inst_get,
13630 Field_sa4_Slot_inst_get,
13631 Field_sae4_Slot_inst_get,
13632 Field_sae_Slot_inst_get,
13633 Field_sal_Slot_inst_get,
13634 Field_sargt_Slot_inst_get,
13635 Field_sas4_Slot_inst_get,
13636 Field_sas_Slot_inst_get,
13637 Field_sr_Slot_inst_get,
13638 Field_st_Slot_inst_get,
13639 Field_thi3_Slot_inst_get,
13640 Field_imm4_Slot_inst_get,
13641 Field_mn_Slot_inst_get,
13650 Field_r3_Slot_inst_get,
13651 Field_rbit2_Slot_inst_get,
13652 Field_rhi_Slot_inst_get,
13653 Field_t3_Slot_inst_get,
13654 Field_tbit2_Slot_inst_get,
13655 Field_tlo_Slot_inst_get,
13656 Field_w_Slot_inst_get,
13657 Field_y_Slot_inst_get,
13658 Field_x_Slot_inst_get,
13659 Field_xt_wbr15_imm_Slot_inst_get,
13660 Field_xt_wbr18_imm_Slot_inst_get,
13661 Field_bitindex_Slot_inst_get,
13662 Field_s3to1_Slot_inst_get,
13663 Implicit_Field_ar0_get,
13664 Implicit_Field_ar4_get,
13665 Implicit_Field_ar8_get,
13666 Implicit_Field_ar12_get,
13667 Implicit_Field_mr0_get,
13668 Implicit_Field_mr1_get,
13669 Implicit_Field_mr2_get,
13670 Implicit_Field_mr3_get
13673 static xtensa_set_field_fn
13674 Slot_inst_set_field_fns[] = {
13675 Field_t_Slot_inst_set,
13676 Field_bbi4_Slot_inst_set,
13677 Field_bbi_Slot_inst_set,
13678 Field_imm12_Slot_inst_set,
13679 Field_imm8_Slot_inst_set,
13680 Field_s_Slot_inst_set,
13681 Field_imm12b_Slot_inst_set,
13682 Field_imm16_Slot_inst_set,
13683 Field_m_Slot_inst_set,
13684 Field_n_Slot_inst_set,
13685 Field_offset_Slot_inst_set,
13686 Field_op0_Slot_inst_set,
13687 Field_op1_Slot_inst_set,
13688 Field_op2_Slot_inst_set,
13689 Field_r_Slot_inst_set,
13690 Field_sa4_Slot_inst_set,
13691 Field_sae4_Slot_inst_set,
13692 Field_sae_Slot_inst_set,
13693 Field_sal_Slot_inst_set,
13694 Field_sargt_Slot_inst_set,
13695 Field_sas4_Slot_inst_set,
13696 Field_sas_Slot_inst_set,
13697 Field_sr_Slot_inst_set,
13698 Field_st_Slot_inst_set,
13699 Field_thi3_Slot_inst_set,
13700 Field_imm4_Slot_inst_set,
13701 Field_mn_Slot_inst_set,
13710 Field_r3_Slot_inst_set,
13711 Field_rbit2_Slot_inst_set,
13712 Field_rhi_Slot_inst_set,
13713 Field_t3_Slot_inst_set,
13714 Field_tbit2_Slot_inst_set,
13715 Field_tlo_Slot_inst_set,
13716 Field_w_Slot_inst_set,
13717 Field_y_Slot_inst_set,
13718 Field_x_Slot_inst_set,
13719 Field_xt_wbr15_imm_Slot_inst_set,
13720 Field_xt_wbr18_imm_Slot_inst_set,
13721 Field_bitindex_Slot_inst_set,
13722 Field_s3to1_Slot_inst_set,
13723 Implicit_Field_set,
13724 Implicit_Field_set,
13725 Implicit_Field_set,
13726 Implicit_Field_set,
13727 Implicit_Field_set,
13728 Implicit_Field_set,
13729 Implicit_Field_set,
13730 Implicit_Field_set
13733 static xtensa_get_field_fn
13734 Slot_inst16a_get_field_fns[] = {
13735 Field_t_Slot_inst16a_get,
13740 Field_s_Slot_inst16a_get,
13746 Field_op0_Slot_inst16a_get,
13749 Field_r_Slot_inst16a_get,
13757 Field_sr_Slot_inst16a_get,
13758 Field_st_Slot_inst16a_get,
13760 Field_imm4_Slot_inst16a_get,
13762 Field_i_Slot_inst16a_get,
13763 Field_imm6lo_Slot_inst16a_get,
13764 Field_imm6hi_Slot_inst16a_get,
13765 Field_imm7lo_Slot_inst16a_get,
13766 Field_imm7hi_Slot_inst16a_get,
13767 Field_z_Slot_inst16a_get,
13768 Field_imm6_Slot_inst16a_get,
13769 Field_imm7_Slot_inst16a_get,
13781 Field_bitindex_Slot_inst16a_get,
13782 Field_s3to1_Slot_inst16a_get,
13783 Implicit_Field_ar0_get,
13784 Implicit_Field_ar4_get,
13785 Implicit_Field_ar8_get,
13786 Implicit_Field_ar12_get,
13787 Implicit_Field_mr0_get,
13788 Implicit_Field_mr1_get,
13789 Implicit_Field_mr2_get,
13790 Implicit_Field_mr3_get
13793 static xtensa_set_field_fn
13794 Slot_inst16a_set_field_fns[] = {
13795 Field_t_Slot_inst16a_set,
13800 Field_s_Slot_inst16a_set,
13806 Field_op0_Slot_inst16a_set,
13809 Field_r_Slot_inst16a_set,
13817 Field_sr_Slot_inst16a_set,
13818 Field_st_Slot_inst16a_set,
13820 Field_imm4_Slot_inst16a_set,
13822 Field_i_Slot_inst16a_set,
13823 Field_imm6lo_Slot_inst16a_set,
13824 Field_imm6hi_Slot_inst16a_set,
13825 Field_imm7lo_Slot_inst16a_set,
13826 Field_imm7hi_Slot_inst16a_set,
13827 Field_z_Slot_inst16a_set,
13828 Field_imm6_Slot_inst16a_set,
13829 Field_imm7_Slot_inst16a_set,
13841 Field_bitindex_Slot_inst16a_set,
13842 Field_s3to1_Slot_inst16a_set,
13843 Implicit_Field_set,
13844 Implicit_Field_set,
13845 Implicit_Field_set,
13846 Implicit_Field_set,
13847 Implicit_Field_set,
13848 Implicit_Field_set,
13849 Implicit_Field_set,
13850 Implicit_Field_set
13853 static xtensa_get_field_fn
13854 Slot_inst16b_get_field_fns[] = {
13855 Field_t_Slot_inst16b_get,
13860 Field_s_Slot_inst16b_get,
13866 Field_op0_Slot_inst16b_get,
13869 Field_r_Slot_inst16b_get,
13877 Field_sr_Slot_inst16b_get,
13878 Field_st_Slot_inst16b_get,
13880 Field_imm4_Slot_inst16b_get,
13882 Field_i_Slot_inst16b_get,
13883 Field_imm6lo_Slot_inst16b_get,
13884 Field_imm6hi_Slot_inst16b_get,
13885 Field_imm7lo_Slot_inst16b_get,
13886 Field_imm7hi_Slot_inst16b_get,
13887 Field_z_Slot_inst16b_get,
13888 Field_imm6_Slot_inst16b_get,
13889 Field_imm7_Slot_inst16b_get,
13901 Field_bitindex_Slot_inst16b_get,
13902 Field_s3to1_Slot_inst16b_get,
13903 Implicit_Field_ar0_get,
13904 Implicit_Field_ar4_get,
13905 Implicit_Field_ar8_get,
13906 Implicit_Field_ar12_get,
13907 Implicit_Field_mr0_get,
13908 Implicit_Field_mr1_get,
13909 Implicit_Field_mr2_get,
13910 Implicit_Field_mr3_get
13913 static xtensa_set_field_fn
13914 Slot_inst16b_set_field_fns[] = {
13915 Field_t_Slot_inst16b_set,
13920 Field_s_Slot_inst16b_set,
13926 Field_op0_Slot_inst16b_set,
13929 Field_r_Slot_inst16b_set,
13937 Field_sr_Slot_inst16b_set,
13938 Field_st_Slot_inst16b_set,
13940 Field_imm4_Slot_inst16b_set,
13942 Field_i_Slot_inst16b_set,
13943 Field_imm6lo_Slot_inst16b_set,
13944 Field_imm6hi_Slot_inst16b_set,
13945 Field_imm7lo_Slot_inst16b_set,
13946 Field_imm7hi_Slot_inst16b_set,
13947 Field_z_Slot_inst16b_set,
13948 Field_imm6_Slot_inst16b_set,
13949 Field_imm7_Slot_inst16b_set,
13961 Field_bitindex_Slot_inst16b_set,
13962 Field_s3to1_Slot_inst16b_set,
13963 Implicit_Field_set,
13964 Implicit_Field_set,
13965 Implicit_Field_set,
13966 Implicit_Field_set,
13967 Implicit_Field_set,
13968 Implicit_Field_set,
13969 Implicit_Field_set,
13970 Implicit_Field_set
13973 static xtensa_slot_internal slots[] = {
13974 { "Inst", "x24", 0,
13975 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
13976 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
13977 Slot_inst_decode, "nop" },
13978 { "Inst16a", "x16a", 0,
13979 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
13980 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
13981 Slot_inst16a_decode, "" },
13982 { "Inst16b", "x16b", 0,
13983 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
13984 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
13985 Slot_inst16b_decode, "nop.n" }
13989 /* Instruction formats. */
13991 static void
13992 Format_x24_encode (xtensa_insnbuf insn)
13994 insn[0] = 0;
13997 static void
13998 Format_x16a_encode (xtensa_insnbuf insn)
14000 insn[0] = 0x8;
14003 static void
14004 Format_x16b_encode (xtensa_insnbuf insn)
14006 insn[0] = 0xc;
14009 static int Format_x24_slots[] = { 0 };
14011 static int Format_x16a_slots[] = { 1 };
14013 static int Format_x16b_slots[] = { 2 };
14015 static xtensa_format_internal formats[] = {
14016 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
14017 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
14018 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
14022 static int
14023 format_decoder (const xtensa_insnbuf insn)
14025 if ((insn[0] & 0x8) == 0)
14026 return 0; /* x24 */
14027 if ((insn[0] & 0xc) == 0x8)
14028 return 1; /* x16a */
14029 if ((insn[0] & 0xe) == 0xc)
14030 return 2; /* x16b */
14031 return -1;
14034 static int length_table[16] = {
14053 static int
14054 length_decoder (const unsigned char *insn)
14056 int op0 = insn[0] & 0xf;
14057 return length_table[op0];
14061 /* Top-level ISA structure. */
14063 xtensa_isa_internal xtensa_modules = {
14064 0 /* little-endian */,
14065 3 /* insn_size */, 0,
14066 3, formats, format_decoder, length_decoder,
14067 3, slots,
14068 56 /* num_fields */,
14069 93, operands,
14070 320, iclasses,
14071 446, opcodes, 0,
14072 2, regfiles,
14073 NUM_STATES, states, 0,
14074 NUM_SYSREGS, sysregs, 0,
14075 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
14076 1, interfaces, 0,
14077 0, funcUnits, 0