trace: switch position of headers to what Meson requires
[qemu/ar7.git] / target / riscv / insn_trans / trans_rva.inc.c
blobbe8a9f06dd198cec7e0fc6430fdc13e13aeaa8f8
1 /*
2 * RISC-V translation routines for the RV64A Standard Extension.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
23 TCGv src1 = tcg_temp_new();
24 /* Put addr in load_res, data in load_val. */
25 gen_get_gpr(src1, a->rs1);
26 if (a->rl) {
27 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
29 tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
30 if (a->aq) {
31 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
33 tcg_gen_mov_tl(load_res, src1);
34 gen_set_gpr(a->rd, load_val);
36 tcg_temp_free(src1);
37 return true;
40 static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
42 TCGv src1 = tcg_temp_new();
43 TCGv src2 = tcg_temp_new();
44 TCGv dat = tcg_temp_new();
45 TCGLabel *l1 = gen_new_label();
46 TCGLabel *l2 = gen_new_label();
48 gen_get_gpr(src1, a->rs1);
49 tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
51 gen_get_gpr(src2, a->rs2);
53 * Note that the TCG atomic primitives are SC,
54 * so we can ignore AQ/RL along this path.
56 tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
57 ctx->mem_idx, mop);
58 tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
59 gen_set_gpr(a->rd, dat);
60 tcg_gen_br(l2);
62 gen_set_label(l1);
64 * Address comparison failure. However, we still need to
65 * provide the memory barrier implied by AQ/RL.
67 tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
68 tcg_gen_movi_tl(dat, 1);
69 gen_set_gpr(a->rd, dat);
71 gen_set_label(l2);
73 * Clear the load reservation, since an SC must fail if there is
74 * an SC to any address, in between an LR and SC pair.
76 tcg_gen_movi_tl(load_res, -1);
78 tcg_temp_free(dat);
79 tcg_temp_free(src1);
80 tcg_temp_free(src2);
81 return true;
84 static bool gen_amo(DisasContext *ctx, arg_atomic *a,
85 void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
86 MemOp mop)
88 TCGv src1 = tcg_temp_new();
89 TCGv src2 = tcg_temp_new();
91 gen_get_gpr(src1, a->rs1);
92 gen_get_gpr(src2, a->rs2);
94 (*func)(src2, src1, src2, ctx->mem_idx, mop);
96 gen_set_gpr(a->rd, src2);
97 tcg_temp_free(src1);
98 tcg_temp_free(src2);
99 return true;
102 static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
104 REQUIRE_EXT(ctx, RVA);
105 return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
108 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
110 REQUIRE_EXT(ctx, RVA);
111 return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
114 static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
116 REQUIRE_EXT(ctx, RVA);
117 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
120 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
122 REQUIRE_EXT(ctx, RVA);
123 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
126 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
128 REQUIRE_EXT(ctx, RVA);
129 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
132 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
134 REQUIRE_EXT(ctx, RVA);
135 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
138 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
140 REQUIRE_EXT(ctx, RVA);
141 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
144 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
146 REQUIRE_EXT(ctx, RVA);
147 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
150 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
152 REQUIRE_EXT(ctx, RVA);
153 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
156 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
158 REQUIRE_EXT(ctx, RVA);
159 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
162 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
164 REQUIRE_EXT(ctx, RVA);
165 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
168 #ifdef TARGET_RISCV64
170 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
172 return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
175 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
177 return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
180 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
182 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
185 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
187 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
190 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
192 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
195 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
197 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
200 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
202 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
205 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
207 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
210 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
212 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
215 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
217 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
220 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
222 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
224 #endif