target/s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qemu/error-report.h"
  20 #include "exec/address-spaces.h"
  21 #include "cpu.h"
  22 #include "internal.h"
  23 #include "kvm_s390x.h"
  24 #include "sysemu/kvm.h"
  25 #include "sysemu/tcg.h"
  26 #include "exec/exec-all.h"
  27 #include "trace.h"
  28 #include "hw/hw.h"
  29 #include "hw/s390x/storage-keys.h"
  30
  31 /* #define DEBUG_S390 */
  32 /* #define DEBUG_S390_PTE */
  33 /* #define DEBUG_S390_STDOUT */
  34
  35 #ifdef DEBUG_S390
  36 #ifdef DEBUG_S390_STDOUT
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  39          if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...) \
  42     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  43 #endif
  44 #else
  45 #define DPRINTF(fmt, ...) \
  46     do { } while (0)
  47 #endif
  48
  49 #ifdef DEBUG_S390_PTE
  50 #define PTE_DPRINTF DPRINTF
  51 #else
  52 #define PTE_DPRINTF(fmt, ...) \
  53     do { } while (0)
  54 #endif
  55
  56 /* Fetch/store bits in the translation exception code: */
  57 #define FS_READ  0x800
  58 #define FS_WRITE 0x400
  59
  60 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
  61                                      uint32_t ilen, uint64_t tec)
  62 {
  63     S390CPU *cpu = env_archcpu(env);
  64
  65     if (kvm_enabled()) {
  66         kvm_s390_access_exception(cpu, type, tec);
  67     } else {
  68         CPUState *cs = env_cpu(env);
  69         if (type != PGM_ADDRESSING) {
  70             stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  71         }
  72         trigger_pgm_exception(env, type, ilen);
  73     }
  74 }
  75
  76 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  77                                uint64_t asc, int rw, bool exc)
  78 {
  79     uint64_t tec;
  80
  81     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
  82
  83     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
  84
  85     if (!exc) {
  86         return;
  87     }
  88
  89     trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec);
  90 }
  91
  92 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  93                                uint32_t type, uint64_t asc, int rw, bool exc)
  94 {
  95     int ilen = ILEN_AUTO;
  96     uint64_t tec;
  97
  98     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
  99
 100     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
 101
 102     if (!exc) {
 103         return;
 104     }
 105
 106     /* Code accesses have an undefined ilc.  */
 107     if (rw == MMU_INST_FETCH) {
 108         ilen = 2;
 109     }
 110
 111     trigger_access_exception(env, type, ilen, tec);
 112 }
 113
 114 /* check whether the address would be proteted by Low-Address Protection */
 115 static bool is_low_address(uint64_t addr)
 116 {
 117     return addr <= 511 || (addr >= 4096 && addr <= 4607);
 118 }
 119
 120 /* check whether Low-Address Protection is enabled for mmu_translate() */
 121 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
 122 {
 123     if (!(env->cregs[0] & CR0_LOWPROT)) {
 124         return false;
 125     }
 126     if (!(env->psw.mask & PSW_MASK_DAT)) {
 127         return true;
 128     }
 129
 130     /* Check the private-space control bit */
 131     switch (asc) {
 132     case PSW_ASC_PRIMARY:
 133         return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
 134     case PSW_ASC_SECONDARY:
 135         return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
 136     case PSW_ASC_HOME:
 137         return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
 138     default:
 139         /* We don't support access register mode */
 140         error_report("unsupported addressing mode");
 141         exit(1);
 142     }
 143 }
 144
 145 /**
 146  * Translate real address to absolute (= physical)
 147  * address by taking care of the prefix mapping.
 148  */
 149 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
 150 {
 151     if (raddr < 0x2000) {
 152         return raddr + env->psa;    /* Map the lowcore. */
 153     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 154         return raddr - env->psa;    /* Map the 0 page. */
 155     }
 156     return raddr;
 157 }
 158
 159 /* Decode page table entry (normal 4KB page) */
 160 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 161                              uint64_t asc, uint64_t pt_entry,
 162                              target_ulong *raddr, int *flags, int rw, bool exc)
 163 {
 164     if (pt_entry & PAGE_INVALID) {
 165         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
 166         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
 167         return -1;
 168     }
 169     if (pt_entry & PAGE_RES0) {
 170         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 171         return -1;
 172     }
 173     if (pt_entry & PAGE_RO) {
 174         *flags &= ~PAGE_WRITE;
 175     }
 176
 177     *raddr = pt_entry & ASCE_ORIGIN;
 178
 179     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
 180
 181     return 0;
 182 }
 183
 184 /* Decode segment table entry */
 185 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 186                                  uint64_t asc, uint64_t st_entry,
 187                                  target_ulong *raddr, int *flags, int rw,
 188                                  bool exc)
 189 {
 190     CPUState *cs = env_cpu(env);
 191     uint64_t origin, offs, pt_entry;
 192
 193     if (st_entry & SEGMENT_ENTRY_RO) {
 194         *flags &= ~PAGE_WRITE;
 195     }
 196
 197     if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 198         /* Decode EDAT1 segment frame absolute address (1MB page) */
 199         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 200         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 201         return 0;
 202     }
 203
 204     /* Look up 4KB page entry */
 205     origin = st_entry & SEGMENT_ENTRY_ORIGIN;
 206     offs  = (vaddr & VADDR_PX) >> 9;
 207     pt_entry = ldq_phys(cs->as, origin + offs);
 208     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 209                 __func__, origin, offs, pt_entry);
 210     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
 211 }
 212
 213 /* Decode region table entries */
 214 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 215                                 uint64_t asc, uint64_t entry, int level,
 216                                 target_ulong *raddr, int *flags, int rw,
 217                                 bool exc)
 218 {
 219     CPUState *cs = env_cpu(env);
 220     uint64_t origin, offs, new_entry;
 221     const int pchks[4] = {
 222         PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
 223         PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
 224     };
 225
 226     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 227
 228     origin = entry & REGION_ENTRY_ORIGIN;
 229     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 230
 231     new_entry = ldq_phys(cs->as, origin + offs);
 232     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 233                 __func__, origin, offs, new_entry);
 234
 235     if ((new_entry & REGION_ENTRY_INV) != 0) {
 236         DPRINTF("%s: invalid region\n", __func__);
 237         trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
 238         return -1;
 239     }
 240
 241     if ((new_entry & REGION_ENTRY_TYPE_MASK) != level) {
 242         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 243         return -1;
 244     }
 245
 246     if (level == ASCE_TYPE_SEGMENT) {
 247         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 248                                      rw, exc);
 249     }
 250
 251     /* Check region table offset and length */
 252     offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
 253     if (offs < ((new_entry & REGION_ENTRY_TF) >> 6)
 254         || offs > (new_entry & REGION_ENTRY_LENGTH)) {
 255         DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
 256         trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
 257         return -1;
 258     }
 259
 260     if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) {
 261         *flags &= ~PAGE_WRITE;
 262     }
 263
 264     /* yet another region */
 265     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 266                                 raddr, flags, rw, exc);
 267 }
 268
 269 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 270                               uint64_t asc, uint64_t asce, target_ulong *raddr,
 271                               int *flags, int rw, bool exc)
 272 {
 273     int level;
 274     int r;
 275
 276     if (asce & ASCE_REAL_SPACE) {
 277         /* direct mapping */
 278         *raddr = vaddr;
 279         return 0;
 280     }
 281
 282     level = asce & ASCE_TYPE_MASK;
 283     switch (level) {
 284     case ASCE_TYPE_REGION1:
 285         if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) {
 286             trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
 287             return -1;
 288         }
 289         break;
 290     case ASCE_TYPE_REGION2:
 291         if (vaddr & 0xffe0000000000000ULL) {
 292             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 293                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 294             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 295             return -1;
 296         }
 297         if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) {
 298             trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
 299             return -1;
 300         }
 301         break;
 302     case ASCE_TYPE_REGION3:
 303         if (vaddr & 0xfffffc0000000000ULL) {
 304             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 305                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 306             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 307             return -1;
 308         }
 309         if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) {
 310             trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
 311             return -1;
 312         }
 313         break;
 314     case ASCE_TYPE_SEGMENT:
 315         if (vaddr & 0xffffffff80000000ULL) {
 316             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 317                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 318             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 319             return -1;
 320         }
 321         if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) {
 322             trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 323             return -1;
 324         }
 325         break;
 326     }
 327
 328     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
 329                              exc);
 330     if (!r && rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
 331         trigger_prot_fault(env, vaddr, asc, rw, exc);
 332         return -1;
 333     }
 334
 335     return r;
 336 }
 337
 338 /**
 339  * Translate a virtual (logical) address into a physical (absolute) address.
 340  * @param vaddr  the virtual address
 341  * @param rw     0 = read, 1 = write, 2 = code fetch
 342  * @param asc    address space control (one of the PSW_ASC_* modes)
 343  * @param raddr  the translated address is stored to this pointer
 344  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 345  * @param exc    true = inject a program check if a fault occurred
 346  * @return       0 if the translation was successful, -1 if a fault occurred
 347  */
 348 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 349                   target_ulong *raddr, int *flags, bool exc)
 350 {
 351     static S390SKeysState *ss;
 352     static S390SKeysClass *skeyclass;
 353     int r = -1;
 354     uint8_t key;
 355
 356     if (unlikely(!ss)) {
 357         ss = s390_get_skeys_device();
 358         skeyclass = S390_SKEYS_GET_CLASS(ss);
 359     }
 360
 361     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 362     if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
 363         /*
 364          * If any part of this page is currently protected, make sure the
 365          * TLB entry will not be reused.
 366          *
 367          * As the protected range is always the first 512 bytes of the
 368          * two first pages, we are able to catch all writes to these areas
 369          * just by looking at the start address (triggering the tlb miss).
 370          */
 371         *flags |= PAGE_WRITE_INV;
 372         if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
 373             if (exc) {
 374                 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
 375             }
 376             return -EACCES;
 377         }
 378     }
 379
 380     vaddr &= TARGET_PAGE_MASK;
 381
 382     if (!(env->psw.mask & PSW_MASK_DAT)) {
 383         *raddr = vaddr;
 384         r = 0;
 385         goto out;
 386     }
 387
 388     switch (asc) {
 389     case PSW_ASC_PRIMARY:
 390         PTE_DPRINTF("%s: asc=primary\n", __func__);
 391         r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
 392                                rw, exc);
 393         break;
 394     case PSW_ASC_HOME:
 395         PTE_DPRINTF("%s: asc=home\n", __func__);
 396         r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
 397                                rw, exc);
 398         break;
 399     case PSW_ASC_SECONDARY:
 400         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 401         /*
 402          * Instruction: Primary
 403          * Data: Secondary
 404          */
 405         if (rw == MMU_INST_FETCH) {
 406             r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
 407                                    raddr, flags, rw, exc);
 408             *flags &= ~(PAGE_READ | PAGE_WRITE);
 409         } else {
 410             r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
 411                                    raddr, flags, rw, exc);
 412             *flags &= ~(PAGE_EXEC);
 413         }
 414         break;
 415     case PSW_ASC_ACCREG:
 416     default:
 417         hw_error("guest switched to unknown asc mode\n");
 418         break;
 419     }
 420
 421  out:
 422     /* Convert real address -> absolute address */
 423     *raddr = mmu_real2abs(env, *raddr);
 424
 425     if (r == 0 && *raddr < ram_size) {
 426         r = skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
 427         if (r) {
 428             trace_get_skeys_nonzero(r);
 429             return 0;
 430         }
 431
 432         if (*flags & PAGE_READ) {
 433             key |= SK_R;
 434         }
 435
 436         if (*flags & PAGE_WRITE) {
 437             key |= SK_C;
 438         }
 439
 440         r = skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
 441         if (r) {
 442             trace_set_skeys_nonzero(r);
 443             return 0;
 444         }
 445     }
 446
 447     return r;
 448 }
 449
 450 /**
 451  * translate_pages: Translate a set of consecutive logical page addresses
 452  * to absolute addresses. This function is used for TCG and old KVM without
 453  * the MEMOP interface.
 454  */
 455 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
 456                            target_ulong *pages, bool is_write)
 457 {
 458     uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
 459     CPUS390XState *env = &cpu->env;
 460     int ret, i, pflags;
 461
 462     for (i = 0; i < nr_pages; i++) {
 463         ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
 464         if (ret) {
 465             return ret;
 466         }
 467         if (!address_space_access_valid(&address_space_memory, pages[i],
 468                                         TARGET_PAGE_SIZE, is_write,
 469                                         MEMTXATTRS_UNSPECIFIED)) {
 470             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
 471             return -EFAULT;
 472         }
 473         addr += TARGET_PAGE_SIZE;
 474     }
 475
 476     return 0;
 477 }
 478
 479 /**
 480  * s390_cpu_virt_mem_rw:
 481  * @laddr:     the logical start address
 482  * @ar:        the access register number
 483  * @hostbuf:   buffer in host memory. NULL = do only checks w/o copying
 484  * @len:       length that should be transferred
 485  * @is_write:  true = write, false = read
 486  * Returns:    0 on success, non-zero if an exception occurred
 487  *
 488  * Copy from/to guest memory using logical addresses. Note that we inject a
 489  * program interrupt in case there is an error while accessing the memory.
 490  *
 491  * This function will always return (also for TCG), make sure to call
 492  * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
 493  */
 494 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 495                          int len, bool is_write)
 496 {
 497     int currlen, nr_pages, i;
 498     target_ulong *pages;
 499     int ret;
 500
 501     if (kvm_enabled()) {
 502         ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
 503         if (ret >= 0) {
 504             return ret;
 505         }
 506     }
 507
 508     nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
 509                + 1;
 510     pages = g_malloc(nr_pages * sizeof(*pages));
 511
 512     ret = translate_pages(cpu, laddr, nr_pages, pages, is_write);
 513     if (ret == 0 && hostbuf != NULL) {
 514         /* Copy data by stepping through the area page by page */
 515         for (i = 0; i < nr_pages; i++) {
 516             currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
 517             cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
 518                                    hostbuf, currlen, is_write);
 519             laddr += currlen;
 520             hostbuf += currlen;
 521             len -= currlen;
 522         }
 523     }
 524
 525     g_free(pages);
 526     return ret;
 527 }
 528
 529 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
 530 {
 531     /* KVM will handle the interrupt automatically, TCG has to exit the TB */
 532 #ifdef CONFIG_TCG
 533     if (tcg_enabled()) {
 534         cpu_loop_exit_restore(CPU(cpu), ra);
 535     }
 536 #endif
 537 }
 538
 539 /**
 540  * Translate a real address into a physical (absolute) address.
 541  * @param raddr  the real address
 542  * @param rw     0 = read, 1 = write, 2 = code fetch
 543  * @param addr   the translated address is stored to this pointer
 544  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 545  * @return       0 if the translation was successful, < 0 if a fault occurred
 546  */
 547 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
 548                        target_ulong *addr, int *flags)
 549 {
 550     const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
 551
 552     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 553     if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
 554         /* see comment in mmu_translate() how this works */
 555         *flags |= PAGE_WRITE_INV;
 556         if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
 557             trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
 558             return -EACCES;
 559         }
 560     }
 561
 562     *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
 563
 564     /* TODO: storage key handling */
 565     return 0;
 566 }